[deliverable/binutils-gdb.git] / gas / testsuite / gas / d10v / instruction_packing.d

#objdump: -Dr
#name: D10V instruction packing
#as: -W

.*: +file format elf32-d10v

Disassembly of section .text:

00000000 <main>:
   0:	2f 00 5e 00 	nop		||	nop	

00000004 <FM00_IU_MU>:
   4:	30 23 24 02 	ld	r2, @r3	||	sra	r0, r1
   8:	24 11 a4 02 	bra.s	94 <test_end>	||	sra	r0, r1

0000000c <FM00_MU_IU>:
   c:	30 23 24 02 	ld	r2, @r3	||	sra	r0, r1
  10:	24 10 a4 02 	bra.s	94 <test_end>	||	sra	r0, r1

00000014 <FM00_IM_MU>:
  14:	30 23 02 8a 	ld	r2, @r3	||	add	r4, r5
  18:	24 0f 82 8a 	bra.s	94 <test_end>	||	add	r4, r5

0000001c <FM00_IM_IU>:
  1c:	01 45 24 02 	add	r4, r5	||	sra	r0, r1
  20:	01 45 2c ce 	add	r4, r5	||	mulx	a0, r6, r7

00000024 <FM00_MU_IM>:
  24:	30 23 02 8a 	ld	r2, @r3	||	add	r4, r5
  28:	24 0d 82 8a 	bra.s	94 <test_end>	||	add	r4, r5

0000002c <FM00_IU_IM>:
  2c:	01 45 24 02 	add	r4, r5	||	sra	r0, r1
  30:	01 45 2c ce 	add	r4, r5	||	mulx	a0, r6, r7

00000034 <FM01_IU_MU>:
  34:	b0 23 24 02 	ld	r2, @r3	<-	sra	r0, r1
  38:	a4 0b a4 02 	bra.s	94 <test_end>	<-	sra	r0, r1

0000003c <FM01_MU_IU>:
  3c:	70 23 24 02 	ld	r2, @r3	->	sra	r0, r1
  40:	64 0a a4 02 	bra.s	94 <test_end>	->	sra	r0, r1

00000044 <FM01_IM_MU>:
  44:	41 45 60 46 	add	r4, r5	->	ld	r2, @r3
  48:	41 45 48 13 	add	r4, r5	->	bra.s	94 <test_end>

0000004c <FM01_IM_IU>:
  4c:	41 45 24 02 	add	r4, r5	->	sra	r0, r1
  50:	41 45 2c ce 	add	r4, r5	->	mulx	a0, r6, r7

00000054 <FM01_MU_IM>:
  54:	70 23 02 8a 	ld	r2, @r3	->	add	r4, r5
  58:	64 07 82 8a 	bra.s	94 <test_end>	->	add	r4, r5

0000005c <FM01_IU_IM>:
  5c:	81 45 24 02 	add	r4, r5	<-	sra	r0, r1
  60:	81 45 2c ce 	add	r4, r5	<-	mulx	a0, r6, r7

00000064 <FM10_IU_MU>:
  64:	70 23 24 02 	ld	r2, @r3	->	sra	r0, r1
  68:	64 05 a4 02 	bra.s	94 <test_end>	->	sra	r0, r1

0000006c <FM10_MU_IU>:
  6c:	b0 23 24 02 	ld	r2, @r3	<-	sra	r0, r1
  70:	a4 04 a4 02 	bra.s	94 <test_end>	<-	sra	r0, r1

00000074 <FM10_IM_MU>:
  74:	70 23 02 8a 	ld	r2, @r3	->	add	r4, r5
  78:	64 03 82 8a 	bra.s	94 <test_end>	->	add	r4, r5

0000007c <FM10_IM_IU>:
  7c:	81 45 24 02 	add	r4, r5	<-	sra	r0, r1
  80:	81 45 2c ce 	add	r4, r5	<-	mulx	a0, r6, r7

00000084 <FM10_MU_IM>:
  84:	b0 23 02 8a 	ld	r2, @r3	<-	add	r4, r5
  88:	a4 01 82 8a 	bra.s	94 <test_end>	<-	add	r4, r5

0000008c <FM10_IU_IM>:
  8c:	92 01 02 8a 	sra	r0, r1	<-	add	r4, r5
  90:	96 67 02 8a 	mulx	a0, r6, r7	<-	add	r4, r5

00000094 <test_end>:
  94:	26 0d 5e 00 	jmp	r13	||	nop
Commit	Line	Data
7f743288	1	#objdump: -Dr
9aff4b7a	2	#name: D10V instruction packing
7f743288 TR	3	#as: -W
	4
	5	.*: +file format elf32-d10v
	6
	7	Disassembly of section .text:
	8
	9	00000000 <main>:
	10	0: 2f 00 5e 00 nop \|\| nop
	11
	12	00000004 <FM00_IU_MU>:
	13	4: 30 23 24 02 ld r2, @r3 \|\| sra r0, r1
	14	8: 24 11 a4 02 bra.s 94 <test_end> \|\| sra r0, r1
	15
	16	0000000c <FM00_MU_IU>:
	17	c: 30 23 24 02 ld r2, @r3 \|\| sra r0, r1
	18	10: 24 10 a4 02 bra.s 94 <test_end> \|\| sra r0, r1
	19
	20	00000014 <FM00_IM_MU>:
	21	14: 30 23 02 8a ld r2, @r3 \|\| add r4, r5
	22	18: 24 0f 82 8a bra.s 94 <test_end> \|\| add r4, r5
	23
	24	0000001c <FM00_IM_IU>:
	25	1c: 01 45 24 02 add r4, r5 \|\| sra r0, r1
	26	20: 01 45 2c ce add r4, r5 \|\| mulx a0, r6, r7
	27
	28	00000024 <FM00_MU_IM>:
	29	24: 30 23 02 8a ld r2, @r3 \|\| add r4, r5
	30	28: 24 0d 82 8a bra.s 94 <test_end> \|\| add r4, r5
	31
	32	0000002c <FM00_IU_IM>:
	33	2c: 01 45 24 02 add r4, r5 \|\| sra r0, r1
	34	30: 01 45 2c ce add r4, r5 \|\| mulx a0, r6, r7
	35
	36	00000034 <FM01_IU_MU>:
	37	34: b0 23 24 02 ld r2, @r3 <- sra r0, r1
	38	38: a4 0b a4 02 bra.s 94 <test_end> <- sra r0, r1
	39
	40	0000003c <FM01_MU_IU>:
	41	3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1
	42	40: 64 0a a4 02 bra.s 94 <test_end> -> sra r0, r1
	43
	44	00000044 <FM01_IM_MU>:
	45	44: 41 45 60 46 add r4, r5 -> ld r2, @r3
	46	48: 41 45 48 13 add r4, r5 -> bra.s 94 <test_end>
	47
	48	0000004c <FM01_IM_IU>:
	49	4c: 41 45 24 02 add r4, r5 -> sra r0, r1
	50	50: 41 45 2c ce add r4, r5 -> mulx a0, r6, r7
	51
	52	00000054 <FM01_MU_IM>:
	53	54: 70 23 02 8a ld r2, @r3 -> add r4, r5
	54	58: 64 07 82 8a bra.s 94 <test_end> -> add r4, r5
	55
	56	0000005c <FM01_IU_IM>:
	57	5c: 81 45 24 02 add r4, r5 <- sra r0, r1
	58	60: 81 45 2c ce add r4, r5 <- mulx a0, r6, r7
	59
	60	00000064 <FM10_IU_MU>:
	61	64: 70 23 24 02 ld r2, @r3 -> sra r0, r1
	62	68: 64 05 a4 02 bra.s 94 <test_end> -> sra r0, r1
	63
	64	0000006c <FM10_MU_IU>:
	65	6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1
	66	70: a4 04 a4 02 bra.s 94 <test_end> <- sra r0, r1
67
68	00000074 <FM10_IM_MU>:
69	74: 70 23 02 8a ld r2, @r3 -> add r4, r5
70	78: 64 03 82 8a bra.s 94 <test_end> -> add r4, r5
71
72	0000007c <FM10_IM_IU>:
73	7c: 81 45 24 02 add r4, r5 <- sra r0, r1
74	80: 81 45 2c ce add r4, r5 <- mulx a0, r6, r7
75
76	00000084 <FM10_MU_IM>:
77	84: b0 23 02 8a ld r2, @r3 <- add r4, r5
78	88: a4 01 82 8a bra.s 94 <test_end> <- add r4, r5
79
80	0000008c <FM10_IU_IM>:
81	8c: 92 01 02 8a sra r0, r1 <- add r4, r5
82	90: 96 67 02 8a mulx a0, r6, r7 <- add r4, r5
83
84	00000094 <test_end>:
85	94: 26 0d 5e 00 jmp r13 \|\| nop