[AArch64] Warn on load pair to same register
[deliverable/binutils-gdb.git] / gas / testsuite / gas / d30v / bittest.s
CommitLineData
252b5132
RH
1# bittest.s
2#
3# Bit operation instructions (BCLR, BNOT, BSET, BTST) should not be placed in IU.
4# If the user specifically indicates they should be in the IU, GAS will
5# generate warnings. The reason why this is not an error is that those instructions
6# will fail in IU only occasionally. Thus GAS should pack them in MU for
7# safety, and it just needs to draw attention when a violation is given.
8
9
10 nop -> ldw R1, @(R2,R3)
11 nop || ldw R6, @(R5,R4)
12
13 nop -> BSET R1, R2, R3
14 nop <- BTST F1, R2, R3
15 nop || BCLR R1, R2, R3
16 nop -> BNOT R1, R2, R3
17 BNOT r1, r2, r3 -> nop
18
19 bset r1, r2, r3 || moddec r4, 5
20
21 bset r1, r2, r3
22 moddec r4, 5
23
24 bset r1, r2, r3
25 joinll r4, r5, r6
26
27 joinll r4, r5, r6
28 bset r1, r2, r3
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