Commit | Line | Data |
---|---|---|
47acf0bd IT |
1 | # Check 32bit AVX512{_4VNNIW,VL} instructions |
2 | ||
3 | .allow_index_reg | |
4 | .text | |
5 | _start: | |
6 | vp4dpwssd (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
7 | vp4dpwssd (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL} | |
8 | vp4dpwssd (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL} | |
9 | vp4dpwssd -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
10 | vp4dpwssd 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8 | |
11 | vp4dpwssd 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
12 | vp4dpwssd -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8 | |
13 | vp4dpwssd -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
14 | vp4dpwssd (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
15 | vp4dpwssd (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL} | |
16 | vp4dpwssd (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL} | |
17 | vp4dpwssd -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
18 | vp4dpwssd 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8 | |
19 | vp4dpwssd 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
20 | vp4dpwssd -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8 | |
21 | vp4dpwssd -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
22 | vp4dpwssds (%ecx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
23 | vp4dpwssds (%ecx), %xmm4, %xmm1{%k7} # AVX512{_4VNNIW,VL} | |
24 | vp4dpwssds (%ecx), %xmm4, %xmm1{%k7}{z} # AVX512{_4VNNIW,VL} | |
25 | vp4dpwssds -123456(%esp,%esi,8), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
26 | vp4dpwssds 4064(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8 | |
27 | vp4dpwssds 4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
28 | vp4dpwssds -4096(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} Disp8 | |
29 | vp4dpwssds -4128(%edx), %xmm4, %xmm1 # AVX512{_4VNNIW,VL} | |
30 | vp4dpwssds (%ecx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
31 | vp4dpwssds (%ecx), %ymm4, %ymm1{%k7} # AVX512{_4VNNIW,VL} | |
32 | vp4dpwssds (%ecx), %ymm4, %ymm1{%k7}{z} # AVX512{_4VNNIW,VL} | |
33 | vp4dpwssds -123456(%esp,%esi,8), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
34 | vp4dpwssds 4064(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8 | |
35 | vp4dpwssds 4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
36 | vp4dpwssds -4096(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} Disp8 | |
37 | vp4dpwssds -4128(%edx), %ymm4, %ymm1 # AVX512{_4VNNIW,VL} | |
38 | ||
39 | .intel_syntax noprefix | |
40 | vp4dpwssd xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL} | |
41 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
42 | vp4dpwssd xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
43 | vp4dpwssd xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
44 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL} | |
45 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8 | |
46 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL} | |
47 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8 | |
48 | vp4dpwssd xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL} | |
49 | vp4dpwssd ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL} | |
50 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
51 | vp4dpwssd ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
52 | vp4dpwssd ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
53 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL} | |
54 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8 | |
55 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL} | |
56 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8 | |
57 | vp4dpwssd ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL} | |
58 | vp4dpwssds xmm1, xmm4, [ecx] # AVX512{_4VNNIW,VL} | |
59 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
60 | vp4dpwssds xmm1{k7}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
61 | vp4dpwssds xmm1{k7}{z}, xmm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
62 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL} | |
63 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8 | |
64 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL} | |
65 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8 | |
66 | vp4dpwssds xmm1, xmm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL} | |
67 | vp4dpwssds ymm1, ymm4, [ecx] # AVX512{_4VNNIW,VL} | |
68 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
69 | vp4dpwssds ymm1{k7}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
70 | vp4dpwssds ymm1{k7}{z}, ymm4, XMMWORD PTR [ecx] # AVX512{_4VNNIW,VL} | |
71 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [esp+esi*8-123456] # AVX512{_4VNNIW,VL} | |
72 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4064] # AVX512{_4VNNIW,VL} Disp8 | |
73 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx+4096] # AVX512{_4VNNIW,VL} | |
74 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4096] # AVX512{_4VNNIW,VL} Disp8 | |
75 | vp4dpwssds ymm1, ymm4, XMMWORD PTR [edx-4128] # AVX512{_4VNNIW,VL} |