Commit | Line | Data |
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013468bc BE |
1 | ;; Test all instructions in the m88k instruction set. |
2 | ;; Copyright 2001 Free Software Foundation, Inc. | |
3 | ;; Contributed by Ben Elliston (bje at redhat.com). | |
4 | ||
5 | .text | |
6 | ;; integer add | |
7 | ||
8 | add r0, r1, r2 | |
9 | add.ci r1, r2, r3 | |
10 | add.co r2, r3, r4 | |
11 | add.cio r3, r4, r5 | |
12 | add r4, r5, 0 | |
13 | add r4, r5, 4096 | |
14 | ||
15 | ;; unsigned integer add | |
16 | ||
17 | addu r0, r1, r2 | |
18 | addu.ci r1, r2, r3 | |
19 | addu.co r2, r3, r4 | |
20 | addu.cio r3, r4, r5 | |
21 | addu r4, r5, 0 | |
22 | addu r4, r5, 4096 | |
23 | ||
24 | ;; logical and | |
25 | ||
26 | and r0, r1, r2 | |
27 | and.c r1, r2, r3 | |
28 | and r2, r3, 0 | |
29 | and r2, r3, 4096 | |
30 | and.u r2, r3, 0 | |
31 | and.u r2, r3, 4096 | |
32 | ||
33 | ;; branch on bit clear | |
34 | ||
35 | bb0 0, r1, 0 | |
36 | bb0 0, r1, -10 | |
37 | bb0 0, r1, 10 | |
38 | bb0 31, r1, 0 | |
39 | bb0 31, r1, -10 | |
40 | bb0 31, r1, 10 | |
41 | bb0.n 0, r1, 0 | |
42 | ||
43 | ;; branch on bit set | |
44 | ||
45 | bb1 0, r1, 0 | |
46 | bb1 0, r1, -10 | |
47 | bb1 0, r1, 10 | |
48 | bb1 31, r1, 0 | |
49 | bb1 31, r1, -10 | |
50 | bb1 31, r1, 10 | |
51 | bb1.n 0, r1, 0 | |
52 | ||
53 | ;; conditional branch | |
54 | ||
55 | bcnd eq0, r1, 0 | |
56 | bcnd eq0, r1, 10 | |
57 | bcnd eq0, r1, -10 | |
58 | bcnd.n eq0, r1, 0 | |
59 | bcnd.n eq0, r1, 10 | |
60 | bcnd.n eq0, r1, -10 | |
61 | bcnd ne0, r1, 0 | |
62 | bcnd ne0, r1, 10 | |
63 | bcnd ne0, r1, -10 | |
64 | bcnd.n ne0, r1, 0 | |
65 | bcnd.n ne0, r1, 10 | |
66 | bcnd.n ne0, r1, -10 | |
67 | bcnd gt0, r1, 0 | |
68 | bcnd gt0, r1, 10 | |
69 | bcnd gt0, r1, -10 | |
70 | bcnd.n gt0, r1, 0 | |
71 | bcnd.n gt0, r1, 10 | |
72 | bcnd.n gt0, r1, -10 | |
73 | bcnd lt0, r1, 0 | |
74 | bcnd lt0, r1, 10 | |
75 | bcnd lt0, r1, -10 | |
76 | bcnd.n lt0, r1, 0 | |
77 | bcnd.n lt0, r1, 10 | |
78 | bcnd.n lt0, r1, -10 | |
79 | bcnd ge0, r1, 0 | |
80 | bcnd ge0, r1, 10 | |
81 | bcnd ge0, r1, -10 | |
82 | bcnd.n ge0, r1, 0 | |
83 | bcnd.n ge0, r1, 10 | |
84 | bcnd.n ge0, r1, -10 | |
85 | bcnd le0, r1, 0 | |
86 | bcnd le0, r1, 10 | |
87 | bcnd le0, r1, -10 | |
88 | bcnd.n le0, r1, 0 | |
89 | bcnd.n le0, r1, 10 | |
90 | bcnd.n le0, r1, -10 | |
91 | ;; using m5 field | |
92 | bcnd 3, r1, 0 | |
93 | bcnd 3, r1, 10 | |
94 | bcnd 3, r1, -10 | |
95 | bcnd.n 3, r1, 0 | |
96 | bcnd.n 3, r1, 10 | |
97 | bcnd.n 3, r1, -10 | |
98 | ||
99 | ;; uncoditional branch | |
100 | ||
101 | br 0 | |
102 | br -10 | |
103 | br 10 | |
104 | br.n 0 | |
105 | br.n -10 | |
106 | br.n 10 | |
107 | ||
108 | ;; branch to subroutine | |
109 | ||
110 | bsr 0 | |
111 | bsr -10 | |
112 | bsr 10 | |
113 | bsr.n 0 | |
114 | bsr.n -10 | |
115 | bsr.n 10 | |
116 | ||
117 | ;; clear bit field | |
118 | ||
119 | clr r1, r2, 5<15> | |
120 | clr r1, r2, r3 | |
121 | clr r1, r2, 6 | |
122 | clr r1, r2, <6> | |
123 | ||
124 | ;; integer compare | |
125 | ||
126 | cmp r0, r1, r2 | |
127 | cmp r0, r2, 0 | |
128 | cmp r0, r2, 4096 | |
129 | ||
130 | ;; signed integer divide | |
131 | ||
132 | div r0, r1, r2 | |
133 | div r0, r1, 0 | |
134 | div r0, r1, 4096 | |
135 | ||
136 | ;; unsigned integer divide | |
137 | ||
138 | divu r0, r1, r2 | |
139 | divu r0, r1, 0 | |
140 | divu r0, r1, 10 | |
141 | ||
142 | ;; extract signed bit field | |
143 | ||
144 | ext r0, r1, 10<5> | |
145 | ext r1, r2, r3 | |
146 | ext r2, r3, 6 | |
147 | ext r2, r3, <6> | |
148 | ||
149 | ;; extract unsigned bit field | |
150 | ||
151 | extu r0, r1, 10<5> | |
152 | extu r1, r2, r3 | |
153 | extu r1, r2, 6 | |
154 | extu r1, r2, <6> | |
155 | ||
156 | ;; floating point add | |
157 | ||
158 | fadd.sss r0, r1, r2 | |
159 | fadd.ssd r0, r1, r2 | |
160 | fadd.sds r0, r1, r2 | |
161 | fadd.sdd r0, r1, r2 | |
162 | fadd.dss r0, r1, r2 | |
163 | fadd.dsd r0, r1, r2 | |
164 | fadd.dds r0, r1, r2 | |
165 | fadd.ddd r0, r1, r2 | |
166 | ||
167 | ;; floating point compare | |
168 | ||
169 | fcmp.sss r0, r1, r2 | |
170 | fcmp.ssd r0, r1, r2 | |
171 | fcmp.sds r0, r1, r2 | |
172 | fcmp.sdd r0, r1, r2 | |
173 | ||
174 | ;; floating point divide | |
175 | ||
176 | fdiv.sss r0, r1, r2 | |
177 | fdiv.ssd r0, r1, r2 | |
178 | fdiv.sds r0, r1, r2 | |
179 | fdiv.sdd r0, r1, r2 | |
180 | fdiv.dss r0, r1, r2 | |
181 | fdiv.dsd r0, r1, r2 | |
182 | fdiv.dds r0, r1, r2 | |
183 | fdiv.ddd r0, r1, r2 | |
184 | ||
185 | ;; find first bit clear | |
186 | ||
187 | ff0 r1, r7 | |
188 | ||
189 | ;; find first bit set | |
190 | ||
191 | ff1 r3, r8 | |
192 | ||
193 | ;; load from floating-point control register | |
194 | ||
195 | fldcr r0, fcr50 | |
196 | ||
197 | ;; convert integer to floating point | |
198 | ||
199 | flt.ss r0, r3 | |
200 | flt.ds r0, r10 | |
201 | ||
202 | ;; floating point multiply | |
203 | ||
204 | fmul.sss r0, r1, r2 | |
205 | fmul.ssd r0, r1, r2 | |
206 | fmul.sds r0, r1, r2 | |
207 | fmul.sdd r0, r1, r2 | |
208 | fmul.dss r0, r1, r2 | |
209 | fmul.dsd r0, r1, r2 | |
210 | fmul.dds r0, r1, r2 | |
211 | fmul.ddd r0, r1, r2 | |
212 | ||
213 | ;; store to floating point control register | |
214 | ||
215 | fstcr r0, fcr50 | |
216 | ||
217 | ;; floating point subtract | |
218 | ||
219 | fsub.sss r0, r1, r2 | |
220 | fsub.ssd r0, r1, r2 | |
221 | fsub.sds r0, r1, r2 | |
222 | fsub.sdd r0, r1, r2 | |
223 | fsub.dss r0, r1, r2 | |
224 | fsub.dsd r0, r1, r2 | |
225 | fsub.dds r0, r1, r2 | |
226 | fsub.ddd r0, r1, r2 | |
227 | ||
228 | ;; exchange floating point control register | |
229 | ||
230 | fxcr r0, r1, fcr50 | |
231 | ||
232 | ;; round floating point to integer | |
233 | ||
234 | int.ss r0, r1 | |
235 | int.sd r10, r2 | |
236 | ||
237 | ;; unconditional jump | |
238 | ||
239 | jmp r0 | |
240 | jmp.n r10 | |
241 | ||
242 | ;; jump to subroutine | |
243 | ||
244 | jsr r10 | |
245 | jsr.n r13 | |
246 | ||
247 | ;; load register from memory | |
248 | ||
249 | ;; unscaled | |
250 | ld.b r0, r1, 0 | |
251 | ld.b r0, r1, 4096 | |
252 | ld.bu r0, r1, 0 | |
253 | ld.bu r0, r1, 4096 | |
254 | ld.h r0, r1, 0 | |
255 | ld.h r0, r1, 4096 | |
256 | ld.hu r0, r1, 0 | |
257 | ld.hu r0, r1, 4096 | |
258 | ld r0, r1, 0 | |
259 | ld r0, r1, 4096 | |
260 | ld.d r0, r1, 0 | |
261 | ld.d r0, r1, 4096 | |
262 | ;; unscaled | |
263 | ld.b r0, r1, r2 | |
264 | ld.bu r1, r2, r3 | |
265 | ld.h r2, r3, r4 | |
266 | ld.hu r3, r4, r5 | |
267 | ld r4, r5, r6 | |
268 | ld.d r5, r6, r7 | |
269 | ld.b.usr r6, r7, r8 | |
270 | ld.bu.usr r7, r8, r9 | |
271 | ld.h.usr r8, r9, r1 | |
272 | ld.hu.usr r9, r1, r2 | |
273 | ld.usr r1, r2, r3 | |
274 | ld.d.usr r2, r3, r4 | |
275 | ;; scaled | |
276 | ld.b r0, r1[r2] | |
277 | ld.bu r1, r2[r3] | |
278 | ld.h r2, r3[r4] | |
279 | ld.hu r3, r4[r5] | |
280 | ld r4, r5[r6] | |
281 | ld.d r5, r6[r7] | |
282 | ld.b.usr r6, r7[r8] | |
283 | ld.bu.usr r7, r8[r9] | |
284 | ld.h.usr r8, r9[r1] | |
285 | ld.hu.usr r9, r1[r2] | |
286 | ld.usr r1, r2[r3] | |
287 | ld.d.usr r2, r3[r4] | |
288 | ||
289 | ;; load address | |
290 | ||
291 | lda.h r0, r1[r2] | |
292 | lda r1,r2[r3] | |
293 | lda.d r2,r3[r4] | |
294 | ||
295 | ;; load from control register | |
296 | ||
297 | ldcr r0, cr10 | |
298 | ||
299 | ;; make bit field | |
300 | ||
301 | mak r0, r1, 10<5> | |
302 | mak r0, r1, r2 | |
303 | mak r0, r1, 6 | |
304 | mak r0, r1, <6> | |
305 | ||
306 | ;; logical mask immediate | |
307 | ||
308 | mask r0, r1, 0 | |
309 | mask r0, r1, 4096 | |
310 | mask.u r0, r1, 0 | |
311 | mask.u r0, r1, 4096 | |
312 | ||
313 | ;; integer multiply | |
314 | ||
315 | mul r0, r1, r2 | |
316 | mul r0, r1, 0 | |
317 | mul r0, r1, 4096 | |
318 | ||
319 | ;; floating point round to nearest integer | |
320 | ||
321 | nint.ss r0, r10 | |
322 | nint.sd r10, r12 | |
323 | ||
324 | ;; logical or | |
325 | ||
326 | or r0, r1, r2 | |
327 | or.c r1, r7, r10 | |
328 | or r0, r4, 0 | |
329 | or r0, r4, 4096 | |
330 | or.u r0, r1, 0 | |
331 | or.u r2, r4, 4096 | |
332 | ||
333 | ;; rotate register | |
334 | ||
335 | rot r0, r1,<5> | |
336 | rot r2, r4, r6 | |
337 | ||
338 | ;; return from exception | |
339 | ||
340 | rte | |
341 | ||
342 | ;; set bit field | |
343 | ||
344 | set r0, r1, 10<5> | |
345 | set r2, r4, r6 | |
346 | set r3, r7, 6 | |
347 | set r3, r7, <6> | |
348 | ||
349 | ;; store register to memory | |
350 | ||
351 | ;; unscaled | |
352 | st.b r0, r1, 0 | |
353 | st.b r0, r1, 4096 | |
354 | st.h r0, r1, 0 | |
355 | st.h r0, r1, 4096 | |
356 | st r0, r1, 0 | |
357 | st r0, r1, 4096 | |
358 | st.d r0, r1, 0 | |
359 | st.d r0, r1, 4096 | |
360 | ;; unscaled | |
361 | st.b r0, r1, r2 | |
362 | st.h r2, r3, r4 | |
363 | st r4, r5, r6 | |
364 | st.d r5, r6, r7 | |
365 | st.b.usr r6, r7, r8 | |
366 | st.h.usr r8, r9, r1 | |
367 | st.usr r1, r2, r3 | |
368 | st.d.usr r2, r3, r4 | |
369 | ;; scaled | |
370 | st.b r0, r1[r2] | |
371 | st.h r2, r3[r4] | |
372 | st r4, r5[r6] | |
373 | st.d r5, r6[r7] | |
374 | st.b.usr r6, r7[r8] | |
375 | st.h.usr r8, r9[r1] | |
376 | st.usr r1, r2[r3] | |
377 | st.d.usr r2, r3[r4] | |
378 | ||
379 | ;; store to control register | |
380 | ||
381 | stcr r0, cr10 | |
382 | ||
383 | ;; integer subtract | |
384 | ||
385 | sub r0, r1, r2 | |
386 | sub.ci r1, r2, r3 | |
387 | sub.co r2, r3, r4 | |
388 | sub.cio r3, r4, r5 | |
389 | sub r4, r5, 0 | |
390 | sub r4, r5, 4096 | |
391 | ||
392 | ;; unsigned integer subtract | |
393 | ||
394 | subu r0, r1, r2 | |
395 | subu.ci r1, r2, r3 | |
396 | subu.co r3, r4, r5 | |
397 | subu.cio r4, r5, r6 | |
398 | subu r5, r6, 0 | |
399 | subu r5, r6, 4096 | |
400 | ||
401 | ;; trap on bit clear | |
402 | ||
403 | tb0 0, r10, 10 | |
404 | tb0 31, r11, 10 | |
405 | ||
406 | ;; trap on bit set | |
407 | ||
408 | tb1 0, r10, 10 | |
409 | tb1 31, r11, 10 | |
410 | ||
411 | ;; trap on bounds check | |
412 | ||
413 | tbnd r0, r1 | |
414 | tbnd r7, 0 | |
415 | tbnd r7, 4096 | |
416 | ||
417 | ;; conditional trap | |
418 | ||
419 | tcnd eq0, r10, 12 | |
420 | tcnd ne0, r9, 12 | |
421 | tcnd gt0, r8, 7 | |
422 | tcnd lt0, r7, 1 | |
423 | tcnd ge0, r6, 35 | |
424 | tcnd le0, r5, 33 | |
425 | tcnd 10, r4, 12 | |
426 | ||
427 | ;; truncate floating point to integer | |
428 | ||
429 | trnc.ss r0, r1 | |
430 | trnc.sd r1, r3 | |
431 | ||
432 | ;; exchange control register | |
433 | ||
434 | xcr r0, r3, cr10 | |
435 | ||
436 | ;; exchange register with memory | |
437 | ||
438 | ;; FIXME: these should assemble! | |
439 | ;; xmem.bu r0, r1, 0 | |
440 | ;; xmem.bu r0, r1, 10 | |
441 | ;; xmem r0, r1, 0 | |
442 | ;; xmem r1, r2, 4096 | |
443 | xmem.bu r0, r1, r2 | |
444 | xmem r1, r2, r3 | |
445 | xmem.bu.usr r4, r5, r6 | |
446 | xmem.usr r5, r6, r7 | |
447 | xmem.bu r2, r3[r4] | |
448 | xmem r3, r4[r5] | |
449 | xmem.bu.usr r4, r5[r9] | |
450 | xmem.usr r5, r6[r10] | |
451 | ||
452 | ;; logical exclusive or | |
453 | ||
454 | xor r0, r1, r2 | |
455 | xor.c r1, r2, r3 | |
456 | xor r2, r3, 0 | |
457 | xor r2, r4, 4096 | |
458 | xor.u r1, r2, 0 | |
459 | xor.u r2, r3, 4096 | |
460 |