* gdb.base/find.exp: Set newline variable
[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mips16-intermix.d
CommitLineData
b9d58d71 1#objdump: -t
08e8dfaf 2#as: -mips32r2 -32
b9d58d71
TS
3#name: MIPS16 intermix
4
5.*: +file format .*mips.*
6
7SYMBOL TABLE:
8#...
90+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_l
100+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_l
110+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_l
120+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_l
130+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_l
140+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_l
150+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_l
160+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_l
170+[0-9a-f]+ l d .mips16.fn.m16_d 0+[0-9a-f]+ .mips16.fn.m16_d
180+[0-9a-f]+ l F .mips16.fn.m16_d 0+[0-9a-f]+ __fn_stub_m16_d
190+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d
200+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d
210+[0-9a-f]+ l d .mips16.fn.m16_static_d 0+[0-9a-f]+ .mips16.fn.m16_static_d
220+[0-9a-f]+ l F .mips16.fn.m16_static_d 0+[0-9a-f]+ __fn_stub_m16_static_d
230+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d
240+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d
250+[0-9a-f]+ l d .mips16.fn.m16_static1_d 0+[0-9a-f]+ .mips16.fn.m16_static1_d
260+[0-9a-f]+ l F .mips16.fn.m16_static1_d 0+[0-9a-f]+ __fn_stub_m16_static1_d
270+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d
280+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d
290+[0-9a-f]+ l d .mips16.fn.m16_static32_d 0+[0-9a-f]+ .mips16.fn.m16_static32_d
300+[0-9a-f]+ l F .mips16.fn.m16_static32_d 0+[0-9a-f]+ __fn_stub_m16_static32_d
310+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d
320+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d
330+[0-9a-f]+ l d .mips16.fn.m16_static16_d 0+[0-9a-f]+ .mips16.fn.m16_static16_d
340+[0-9a-f]+ l F .mips16.fn.m16_static16_d 0+[0-9a-f]+ __fn_stub_m16_static16_d
350+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_ld
360+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_ld
370+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_ld
380+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_ld
390+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_ld
400+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_ld
410+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_ld
420+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_ld
430+[0-9a-f]+ l d .mips16.fn.m16_dl 0+[0-9a-f]+ .mips16.fn.m16_dl
440+[0-9a-f]+ l F .mips16.fn.m16_dl 0+[0-9a-f]+ __fn_stub_m16_dl
450+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_dl
460+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_dl
470+[0-9a-f]+ l d .mips16.fn.m16_static_dl 0+[0-9a-f]+ .mips16.fn.m16_static_dl
480+[0-9a-f]+ l F .mips16.fn.m16_static_dl 0+[0-9a-f]+ __fn_stub_m16_static_dl
490+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_dl
500+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dl
510+[0-9a-f]+ l d .mips16.fn.m16_static1_dl 0+[0-9a-f]+ .mips16.fn.m16_static1_dl
520+[0-9a-f]+ l F .mips16.fn.m16_static1_dl 0+[0-9a-f]+ __fn_stub_m16_static1_dl
530+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_dl
540+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dl
550+[0-9a-f]+ l d .mips16.fn.m16_static32_dl 0+[0-9a-f]+ .mips16.fn.m16_static32_dl
560+[0-9a-f]+ l F .mips16.fn.m16_static32_dl 0+[0-9a-f]+ __fn_stub_m16_static32_dl
570+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_dl
580+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dl
590+[0-9a-f]+ l d .mips16.fn.m16_static16_dl 0+[0-9a-f]+ .mips16.fn.m16_static16_dl
600+[0-9a-f]+ l F .mips16.fn.m16_static16_dl 0+[0-9a-f]+ __fn_stub_m16_static16_dl
610+[0-9a-f]+ l d .mips16.fn.m16_dlld 0+[0-9a-f]+ .mips16.fn.m16_dlld
620+[0-9a-f]+ l F .mips16.fn.m16_dlld 0+[0-9a-f]+ __fn_stub_m16_dlld
630+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_dlld
640+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_dlld
650+[0-9a-f]+ l d .mips16.fn.m16_static_dlld 0+[0-9a-f]+ .mips16.fn.m16_static_dlld
660+[0-9a-f]+ l F .mips16.fn.m16_static_dlld 0+[0-9a-f]+ __fn_stub_m16_static_dlld
670+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_dlld
680+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dlld
690+[0-9a-f]+ l d .mips16.fn.m16_static1_dlld 0+[0-9a-f]+ .mips16.fn.m16_static1_dlld
700+[0-9a-f]+ l F .mips16.fn.m16_static1_dlld 0+[0-9a-f]+ __fn_stub_m16_static1_dlld
710+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_dlld
720+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dlld
730+[0-9a-f]+ l d .mips16.fn.m16_static32_dlld 0+[0-9a-f]+ .mips16.fn.m16_static32_dlld
740+[0-9a-f]+ l F .mips16.fn.m16_static32_dlld 0+[0-9a-f]+ __fn_stub_m16_static32_dlld
750+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_dlld
760+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dlld
770+[0-9a-f]+ l d .mips16.fn.m16_static16_dlld 0+[0-9a-f]+ .mips16.fn.m16_static16_dlld
780+[0-9a-f]+ l F .mips16.fn.m16_static16_dlld 0+[0-9a-f]+ __fn_stub_m16_static16_dlld
790+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d_l
800+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_l
810+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d_l
820+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_l
830+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d_l
840+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_l
850+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d_l
860+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_l
870+[0-9a-f]+ l d .mips16.fn.m16_d_d 0+[0-9a-f]+ .mips16.fn.m16_d_d
880+[0-9a-f]+ l F .mips16.fn.m16_d_d 0+[0-9a-f]+ __fn_stub_m16_d_d
890+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d_d
900+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_d
910+[0-9a-f]+ l d .mips16.fn.m16_static_d_d 0+[0-9a-f]+ .mips16.fn.m16_static_d_d
920+[0-9a-f]+ l F .mips16.fn.m16_static_d_d 0+[0-9a-f]+ __fn_stub_m16_static_d_d
930+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d_d
940+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_d
950+[0-9a-f]+ l d .mips16.fn.m16_static1_d_d 0+[0-9a-f]+ .mips16.fn.m16_static1_d_d
960+[0-9a-f]+ l F .mips16.fn.m16_static1_d_d 0+[0-9a-f]+ __fn_stub_m16_static1_d_d
970+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d_d
980+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_d
990+[0-9a-f]+ l d .mips16.fn.m16_static32_d_d 0+[0-9a-f]+ .mips16.fn.m16_static32_d_d
1000+[0-9a-f]+ l F .mips16.fn.m16_static32_d_d 0+[0-9a-f]+ __fn_stub_m16_static32_d_d
1010+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d_d
1020+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_d
1030+[0-9a-f]+ l d .mips16.fn.m16_static16_d_d 0+[0-9a-f]+ .mips16.fn.m16_static16_d_d
1040+[0-9a-f]+ l F .mips16.fn.m16_static16_d_d 0+[0-9a-f]+ __fn_stub_m16_static16_d_d
1050+[0-9a-f]+ l d .mips16.call.m32_static1_d 0+[0-9a-f]+ .mips16.call.m32_static1_d
1060+[0-9a-f]+ l F .mips16.call.m32_static1_d 0+[0-9a-f]+ __call_stub_m32_static1_d
1070+[0-9a-f]+ l d .mips16.call.m16_static1_d 0+[0-9a-f]+ .mips16.call.m16_static1_d
1080+[0-9a-f]+ l F .mips16.call.m16_static1_d 0+[0-9a-f]+ __call_stub_m16_static1_d
1090+[0-9a-f]+ l d .mips16.call.m32_static1_dl 0+[0-9a-f]+ .mips16.call.m32_static1_dl
1100+[0-9a-f]+ l F .mips16.call.m32_static1_dl 0+[0-9a-f]+ __call_stub_m32_static1_dl
1110+[0-9a-f]+ l d .mips16.call.m16_static1_dl 0+[0-9a-f]+ .mips16.call.m16_static1_dl
1120+[0-9a-f]+ l F .mips16.call.m16_static1_dl 0+[0-9a-f]+ __call_stub_m16_static1_dl
1130+[0-9a-f]+ l d .mips16.call.m32_static1_dlld 0+[0-9a-f]+ .mips16.call.m32_static1_dlld
1140+[0-9a-f]+ l F .mips16.call.m32_static1_dlld 0+[0-9a-f]+ __call_stub_m32_static1_dlld
1150+[0-9a-f]+ l d .mips16.call.m16_static1_dlld 0+[0-9a-f]+ .mips16.call.m16_static1_dlld
1160+[0-9a-f]+ l F .mips16.call.m16_static1_dlld 0+[0-9a-f]+ __call_stub_m16_static1_dlld
1170+[0-9a-f]+ l d .mips16.call.fp.m32_static1_d_l 0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_l
1180+[0-9a-f]+ l F .mips16.call.fp.m32_static1_d_l 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l
1190+[0-9a-f]+ l d .mips16.call.fp.m16_static1_d_l 0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_l
1200+[0-9a-f]+ l F .mips16.call.fp.m16_static1_d_l 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l
1210+[0-9a-f]+ l d .mips16.call.fp.m32_static1_d_d 0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_d
1220+[0-9a-f]+ l F .mips16.call.fp.m32_static1_d_d 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d
1230+[0-9a-f]+ l d .mips16.call.fp.m16_static1_d_d 0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_d
1240+[0-9a-f]+ l F .mips16.call.fp.m16_static1_d_d 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d
1250+[0-9a-f]+ l d .mips16.call.m32_static16_d 0+[0-9a-f]+ .mips16.call.m32_static16_d
1260+[0-9a-f]+ l F .mips16.call.m32_static16_d 0+[0-9a-f]+ __call_stub_m32_static16_d
1270+[0-9a-f]+ l d .mips16.call.m16_static16_d 0+[0-9a-f]+ .mips16.call.m16_static16_d
1280+[0-9a-f]+ l F .mips16.call.m16_static16_d 0+[0-9a-f]+ __call_stub_m16_static16_d
1290+[0-9a-f]+ l d .mips16.call.m32_static16_dl 0+[0-9a-f]+ .mips16.call.m32_static16_dl
1300+[0-9a-f]+ l F .mips16.call.m32_static16_dl 0+[0-9a-f]+ __call_stub_m32_static16_dl
1310+[0-9a-f]+ l d .mips16.call.m16_static16_dl 0+[0-9a-f]+ .mips16.call.m16_static16_dl
1320+[0-9a-f]+ l F .mips16.call.m16_static16_dl 0+[0-9a-f]+ __call_stub_m16_static16_dl
1330+[0-9a-f]+ l d .mips16.call.m32_static16_dlld 0+[0-9a-f]+ .mips16.call.m32_static16_dlld
1340+[0-9a-f]+ l F .mips16.call.m32_static16_dlld 0+[0-9a-f]+ __call_stub_m32_static16_dlld
1350+[0-9a-f]+ l d .mips16.call.m16_static16_dlld 0+[0-9a-f]+ .mips16.call.m16_static16_dlld
1360+[0-9a-f]+ l F .mips16.call.m16_static16_dlld 0+[0-9a-f]+ __call_stub_m16_static16_dlld
1370+[0-9a-f]+ l d .mips16.call.fp.m32_static16_d_l 0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_l
1380+[0-9a-f]+ l F .mips16.call.fp.m32_static16_d_l 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l
1390+[0-9a-f]+ l d .mips16.call.fp.m16_static16_d_l 0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_l
1400+[0-9a-f]+ l F .mips16.call.fp.m16_static16_d_l 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l
1410+[0-9a-f]+ l d .mips16.call.fp.m32_static16_d_d 0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_d
1420+[0-9a-f]+ l F .mips16.call.fp.m32_static16_d_d 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d
1430+[0-9a-f]+ l d .mips16.call.fp.m16_static16_d_d 0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_d
1440+[0-9a-f]+ l F .mips16.call.fp.m16_static16_d_d 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d
145#...
1460+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_l
1470+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_l
1480+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d
1490+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d
150#...
1510+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_ld
1520+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_ld
1530+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_dl
1540+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_dl
1550+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_dlld
1560+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_dlld
1570+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d_l
1580+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d_l
159#...
1600+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d_d
1610+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d_d
1620+[0-9a-f]+ g F .text 0+[0-9a-f]+ f32
1630+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 f16
164#pass
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