Commit | Line | Data |
---|---|---|
8507b6e7 MR |
1 | #objdump: -dr --prefix-addresses --show-raw-insn |
2 | #name: MIPS16 PC-relative relocation with addend 8 (n64, sym32) | |
b32465c9 | 3 | #as: -64 -msym32 |
8507b6e7 MR |
4 | #source: mips16-pcrel-addend-8.s |
5 | ||
6 | .*: +file format .*mips.* | |
7 | ||
8 | Disassembly of section \.text: | |
9 | \.\.\. | |
10 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
11 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar | |
12 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
13 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
14 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
15 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 | |
16 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar | |
17 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
18 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
19 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
20 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar | |
21 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
22 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
23 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
24 | [0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\) | |
25 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar | |
26 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
27 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\* | |
28 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
29 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468 | |
30 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
31 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
32 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
33 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 | |
34 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468 | |
35 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
36 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
37 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
38 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468 | |
39 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
40 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
41 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
42 | [0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\) | |
43 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468 | |
44 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
45 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468 | |
46 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
47 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678 | |
48 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
49 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
50 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
51 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 | |
52 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678 | |
53 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
54 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
55 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
56 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678 | |
57 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
58 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
59 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
60 | [0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\) | |
61 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678 | |
62 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
63 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678 | |
64 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
65 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0 | |
66 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
67 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
68 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
69 | [0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0 | |
70 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0 | |
71 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
72 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
73 | [0-9a-f]+ <[^>]*> f000 6a00 li v0,0 | |
74 | [ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0 | |
75 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
76 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
77 | [0-9a-f]+ <[^>]*> f400 3240 sll v0,16 | |
78 | [0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\) | |
79 | [ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0 | |
80 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
81 | [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0 | |
82 | [0-9a-f]+ <[^>]*> 6500 nop | |
83 | \.\.\. |