Commit | Line | Data |
---|---|---|
e407c74b NC |
1 | .text |
2 | ||
3 | stuff: | |
4 | .ent stuff | |
5 | .set push | |
6 | .set noreorder | |
7 | .set noat | |
8 | ||
9 | add $0, $0, $31 | |
10 | add $1, $10, $3 | |
11 | add $31, $31, $0 | |
12 | ||
13 | addi $31, $0, 0 | |
14 | addi $1, $10, 3 | |
15 | addi $0, $31, -1 | |
16 | ||
17 | addiu $31, $0, 0 | |
18 | addiu $1, $10, 3 | |
19 | addiu $31, $0, 0xFFFF | |
20 | ||
21 | and $0, $0, $31 | |
22 | and $1, $10, $3 | |
23 | and $31, $31, $0 | |
24 | ||
25 | andi $31, $0, 0 | |
26 | andi $1, $10, 3 | |
27 | andi $0, $31, 0xFFFF | |
28 | ||
29 | nop | |
30 | ||
31 | # Test R5900 specific instructions: | |
32 | adda.s $f0, $f31 | |
33 | adda.s $f31, $f0 | |
34 | ||
35 | # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I. | |
36 | c.lt.s $f0, $f31 | |
37 | c.lt.s $f31, $f0 | |
38 | ||
39 | # The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I. | |
40 | c.le.s $f0, $f31 | |
41 | c.le.s $f31, $f0 | |
42 | ||
43 | c.eq.s $f0, $f31 | |
44 | c.eq.s $f31, $f0 | |
45 | ||
46 | c.f.s $f0, $f31 | |
47 | c.f.s $f31, $f0 | |
48 | ||
49 | # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I. | |
50 | # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU. | |
51 | # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s. | |
52 | # cvt.w.s should not be used on R5900. | |
53 | trunc.w.s $f0, $f31 | |
54 | trunc.w.s $f31, $f0 | |
55 | ||
56 | # Test ei/di, but not the R5900 has a bug. ei/di should not be used. | |
57 | di | |
58 | ei | |
59 | ||
60 | # Like div but result is written to lo1 and hi1 registers (pipeline 1). | |
61 | div1 $0, $1, $31 | |
62 | div1 $0, $31, $1 | |
63 | divu1 $0, $1, $31 | |
64 | divu1 $0, $31, $1 | |
65 | ||
66 | # 128 bit store instruction. | |
67 | sq $0, 0($0) | |
68 | sq $1, 0x7fff($1) | |
69 | sq $8, -0x8000($8) | |
70 | sq $31, -1($31) | |
71 | ||
72 | # 128 bit load instruction. | |
73 | lq $0, 0($0) | |
74 | lq $1, 0x7fff($1) | |
75 | lq $8, -0x8000($8) | |
76 | lq $31, -1($31) | |
77 | ||
78 | # Prefetch cache | |
79 | pref 0, 0($0) | |
80 | pref 1, 0x7fff($1) | |
81 | pref 8, -0x8000($8) | |
82 | pref 31, -1($31) | |
83 | ||
84 | # Floating point multiply-ADD | |
85 | madd.s $f0, $f31, $f0 | |
86 | madd.s $f31, $f0, $f31 | |
87 | ||
88 | # Like maddu, but pipeline 1 | |
89 | maddu1 $0, $31 | |
90 | maddu1 $31, $0 | |
91 | maddu1 $0, $0, $31 | |
92 | maddu1 $31, $31, $0 | |
93 | ||
94 | # Like madd, but pipeline 1 | |
95 | madd1 $0, $31 | |
96 | madd1 $31, $0 | |
97 | madd1 $0, $0, $31 | |
98 | madd1 $31, $31, $0 | |
99 | ||
100 | # Floating point multiply-ADD | |
101 | madda.s $f0, $f31 | |
102 | madda.s $f31, $f0 | |
103 | ||
104 | # Floating point maximum | |
105 | max.s $f0, $f31, $f0 | |
106 | max.s $f31, $f0, $f31 | |
107 | ||
108 | # Floating point minimum | |
109 | min.s $f0, $f31, $f0 | |
110 | min.s $f31, $f0, $f31 | |
111 | ||
112 | # Preformance counter registers | |
113 | mfpc $31, 0 | |
114 | mfpc $0, 1 | |
115 | mfps $0, 0 | |
116 | mfps $31, 0 | |
117 | mtpc $31, 0 | |
118 | mtpc $0, 1 | |
119 | mtps $0, 0 | |
120 | mtps $31, 0 | |
121 | ||
122 | # Brekpoint register | |
123 | mfbpc $0 | |
124 | mfbpc $31 | |
125 | mtbpc $0 | |
126 | mtbpc $31 | |
127 | mfdab $0 | |
128 | mfdab $31 | |
129 | mtdab $0 | |
130 | mtdab $31 | |
131 | mfdabm $0 | |
132 | mfdabm $31 | |
133 | mtdabm $0 | |
134 | mtdabm $31 | |
135 | mfdvb $0 | |
136 | mfdvb $31 | |
137 | mtdvb $0 | |
138 | mtdvb $31 | |
139 | mfdvbm $0 | |
140 | mfdvbm $31 | |
141 | mtdvbm $0 | |
142 | mtdvbm $31 | |
143 | mfiab $0 | |
144 | mfiab $31 | |
145 | mtiab $0 | |
146 | mtiab $31 | |
147 | mfiabm $0 | |
148 | mfiabm $31 | |
149 | mtiabm $0 | |
150 | mtiabm $31 | |
151 | ||
152 | # Pipeline1 | |
153 | mfhi1 $0 | |
154 | mfhi1 $31 | |
155 | mthi1 $0 | |
156 | mthi1 $31 | |
157 | mflo1 $0 | |
158 | mflo1 $31 | |
159 | mtlo1 $0 | |
160 | mtlo1 $31 | |
161 | ||
162 | # Shift amount register | |
163 | mfsa $0 | |
164 | mfsa $31 | |
165 | mtsa $0 | |
166 | mtsa $31 | |
167 | mtsab $0, -1 | |
168 | mtsab $8, 0x8000 | |
169 | mtsab $8, 0x7FFF | |
170 | mtsab $31, 0 | |
171 | mtsah $0, -1 | |
172 | mtsah $8, 0x8000 | |
173 | mtsah $8, 0x7FFF | |
174 | mtsah $31, 0 | |
175 | ||
176 | movn $0, $0, $31 | |
177 | movn $31, $31, $0 | |
178 | movz $0, $0, $31 | |
179 | movz $31, $31, $0 | |
180 | ||
181 | # Floating multiply and subtract | |
182 | msub.s $f0, $f31, $f0 | |
183 | msub.s $f31, $f0, $f31 | |
184 | ||
185 | # Floating multiply and subtract from accumulator | |
186 | msuba.s $f0, $f31 | |
187 | msuba.s $f31, $f0 | |
188 | ||
189 | # Floating point multiply to accumulator | |
190 | mula.s $f0, $f31 | |
191 | mula.s $f31, $f0 | |
192 | ||
193 | # Like mult but pipeline 1 | |
194 | mult1 $0, $0, $31 | |
195 | mult1 $31, $31, $0 | |
196 | mult1 $0, $31 | |
197 | mult1 $31, $0 | |
198 | ||
199 | # Like multu but pipeline 1 | |
200 | multu1 $0, $0, $31 | |
201 | multu1 $31, $31, $0 | |
202 | multu1 $0, $31 | |
203 | multu1 $31, $0 | |
204 | ||
205 | # Quadword funnel shift right variable | |
206 | qfsrv $0, $0, $31 | |
207 | qfsrv $31, $31, $0 | |
208 | ||
209 | # Floating point reciprocal squre root | |
210 | rsqrt.s $f0, $f31, $f0 | |
211 | rsqrt.s $f31, $f0, $f31 | |
212 | ||
213 | # FLoating point subtract to accumulator | |
214 | suba.s $f0, $f31 | |
215 | suba.s $f31, $f0 | |
216 | ||
217 | # Parallel instructions operating on 128 bit registers: | |
218 | pabsh $0, $31 | |
219 | pabsh $31, $0 | |
220 | pabsw $0, $31 | |
221 | pabsw $31, $0 | |
222 | paddb $0, $0, $31 | |
223 | paddb $31, $31, $0 | |
224 | paddh $0, $0, $31 | |
225 | paddh $31, $31, $0 | |
226 | paddsb $0, $0, $31 | |
227 | paddsb $31, $31, $0 | |
228 | paddsh $0, $0, $31 | |
229 | paddsh $31, $31, $0 | |
230 | paddsw $0, $0, $31 | |
231 | paddsw $31, $31, $0 | |
232 | paddub $0, $0, $31 | |
233 | paddub $31, $31, $0 | |
234 | padduh $0, $0, $31 | |
235 | padduh $31, $31, $0 | |
236 | padduw $0, $0, $31 | |
237 | padduw $31, $31, $0 | |
238 | paddw $0, $0, $31 | |
239 | paddw $31, $31, $0 | |
240 | padsbh $0, $0, $31 | |
241 | padsbh $31, $31, $0 | |
242 | pand $0, $0, $31 | |
243 | pand $31, $31, $0 | |
244 | pceqb $0, $0, $31 | |
245 | pceqb $31, $31, $0 | |
246 | pceqh $0, $0, $31 | |
247 | pceqh $31, $31, $0 | |
248 | pceqw $0, $0, $31 | |
249 | pcgtb $31, $31, $0 | |
250 | pceqw $0, $0, $31 | |
251 | pceqw $31, $31, $0 | |
252 | pcgtb $0, $0, $31 | |
253 | pcgtb $31, $31, $0 | |
254 | pcgth $0, $0, $31 | |
255 | pcgth $31, $31, $0 | |
256 | pcgtw $0, $0, $31 | |
257 | pcgtw $31, $31, $0 | |
258 | pcpyh $0, $31 | |
259 | pcpyh $31, $0 | |
260 | pcpyld $0, $0, $31 | |
261 | pcpyld $31, $31, $0 | |
262 | pcpyud $0, $0, $31 | |
263 | pcpyud $31, $31, $0 | |
264 | pdivbw $0, $31 | |
265 | pdivbw $31, $0 | |
266 | pdivuw $0, $31 | |
267 | pdivuw $31, $0 | |
268 | pdivw $0, $31 | |
269 | pdivw $31, $0 | |
270 | pexch $0, $31 | |
271 | pexch $31, $0 | |
272 | pexcw $0, $31 | |
273 | pexcw $31, $0 | |
274 | pexeh $0, $31 | |
275 | pexeh $31, $0 | |
276 | pexew $0, $31 | |
277 | pexew $31, $0 | |
278 | pext5 $0, $31 | |
279 | pext5 $31, $0 | |
280 | pextlb $0, $0, $31 | |
281 | pextlb $31, $31, $0 | |
282 | pextlh $0, $0, $31 | |
283 | pextlh $31, $31, $0 | |
284 | pextlw $0, $0, $31 | |
285 | pextlw $31, $31, $0 | |
286 | pextub $0, $0, $31 | |
287 | pextub $31, $31, $0 | |
288 | pextuh $0, $0, $31 | |
289 | pextuh $31, $31, $0 | |
290 | pextuw $0, $0, $31 | |
291 | pextuw $31, $31, $0 | |
292 | phmadh $0, $0, $31 | |
293 | phmadh $31, $31, $0 | |
294 | phmsbh $0, $0, $31 | |
295 | phmsbh $31, $31, $0 | |
296 | pinteh $0, $0, $31 | |
297 | pinteh $31, $31, $0 | |
298 | pinth $0, $0, $31 | |
299 | pinth $31, $31, $0 | |
300 | plzcw $0, $31 | |
301 | plzcw $31, $0 | |
302 | pmaddh $0, $0, $31 | |
303 | pmaddh $31, $31, $0 | |
304 | pmadduw $0, $0, $31 | |
305 | pmadduw $31, $31, $0 | |
306 | pmaddw $0, $0, $31 | |
307 | pmaddw $31, $31, $0 | |
308 | pmaxh $0, $0, $31 | |
309 | pmaxh $31, $31, $0 | |
310 | pmaxw $0, $0, $31 | |
311 | pmaxw $31, $31, $0 | |
312 | pmfhi $0 | |
313 | pmfhi $31 | |
314 | pmfhl.lh $0 | |
315 | pmfhl.lh $31 | |
316 | pmfhl.lw $0 | |
317 | pmfhl.lw $31 | |
318 | pmfhl.sh $0 | |
319 | pmfhl.sh $31 | |
320 | pmfhl.slw $0 | |
321 | pmfhl.slw $31 | |
322 | pmfhl.uw $0 | |
323 | pmfhl.uw $31 | |
324 | pmflo $0 | |
325 | pmflo $31 | |
326 | pminh $0, $0, $31 | |
327 | pminh $31, $31, $0 | |
328 | pminw $0, $0, $31 | |
329 | pminw $31, $31, $0 | |
330 | pmsubh $0, $0, $31 | |
331 | pmsubh $31, $31, $0 | |
332 | pmsubw $0, $0, $31 | |
333 | pmsubw $31, $31, $0 | |
334 | pmthi $0 | |
335 | pmthi $31 | |
336 | pmthl.lw $0 | |
337 | pmthl.lw $31 | |
338 | pmtlo $0 | |
339 | pmtlo $31 | |
340 | pmulth $0, $0, $31 | |
341 | pmulth $31, $31, $0 | |
342 | pmultuw $0, $0, $31 | |
343 | pmultuw $31, $31, $0 | |
344 | pmultw $0, $0, $31 | |
345 | pmultw $31, $31, $0 | |
346 | pmultw $0, $0, $31 | |
347 | pmultw $31, $31, $0 | |
348 | pnor $0, $0, $31 | |
349 | pnor $31, $31, $0 | |
350 | por $0, $0, $31 | |
351 | por $31, $31, $0 | |
352 | ppac5 $0, $31 | |
353 | ppac5 $31, $0 | |
354 | ppacb $0, $0, $31 | |
355 | ppacb $31, $31, $0 | |
356 | ppach $0, $0, $31 | |
357 | ppach $31, $31, $0 | |
358 | ppacw $0, $0, $31 | |
359 | ppacw $31, $31, $0 | |
360 | prevh $0, $31 | |
361 | prevh $31, $0 | |
362 | prot3w $0, $31 | |
363 | prot3w $31, $0 | |
364 | psllh $31, $0, 0 | |
365 | psllh $0, $31, 31 | |
366 | psllvw $0, $31, $0 | |
367 | psllvw $31, $0, $31 | |
368 | psllw $31, $0, 0 | |
369 | psllw $0, $31, 31 | |
370 | psrah $31, $0, 0 | |
371 | psrah $0, $31, 31 | |
372 | psravw $0, $31, $0 | |
373 | psravw $31, $0, $31 | |
374 | psraw $31, $0, 0 | |
375 | psraw $0, $31, 31 | |
376 | psrlh $31, $0, 0 | |
377 | psrlh $0, $31, 31 | |
378 | psrlvw $0, $31, $0 | |
379 | psrlvw $31, $0, $31 | |
380 | psrlw $31, $0, 0 | |
381 | psrlw $0, $31, 31 | |
382 | psubb $0, $0, $31 | |
383 | psubb $31, $31, $0 | |
384 | psubh $0, $0, $31 | |
385 | psubh $31, $31, $0 | |
386 | psubsb $0, $0, $31 | |
387 | psubsb $31, $31, $0 | |
388 | psubsh $0, $0, $31 | |
389 | psubsh $31, $31, $0 | |
390 | psubsw $0, $0, $31 | |
391 | psubsw $31, $31, $0 | |
392 | psubub $0, $0, $31 | |
393 | psubub $31, $31, $0 | |
394 | psubuh $0, $0, $31 | |
395 | psubuh $31, $31, $0 | |
396 | psubuw $0, $0, $31 | |
397 | psubuw $31, $31, $0 | |
398 | psubw $0, $0, $31 | |
399 | psubw $31, $31, $0 | |
400 | pxor $0, $0, $31 | |
401 | pxor $31, $31, $0 | |
402 | ||
403 | # G1 instructions | |
404 | mult $0, $0, $31 | |
405 | mult $31, $31, $0 | |
406 | multu $0, $0, $31 | |
407 | multu $31, $31, $0 | |
408 | mul $0, $0, $31 | |
409 | mul $31, $31, $0 | |
410 | madd $0, $0, $31 | |
411 | madd $31, $31, $0 | |
412 | madd $0, $31 | |
413 | madd $31, $0 | |
414 | maddu $0, $0, $31 | |
415 | maddu $31, $31, $0 | |
416 | maddu $0, $31 | |
417 | maddu $31, $0 | |
418 | sync | |
419 | ||
0aa27725 RS |
420 | # Enable sc/ll instructions by changing ISA level: |
421 | .set push | |
422 | .set mips2 | |
423 | ll $5, 0($6) | |
424 | sc $5, 0($6) | |
425 | .set pop | |
426 | ||
427 | # Enable scd/lld instructions by changing ISA level: | |
428 | .set push | |
429 | .set mips3 | |
430 | lld $5, 0($6) | |
431 | scd $5, 0($6) | |
432 | .set pop | |
433 | ||
e407c74b NC |
434 | .space 8 |
435 | .end stuff |