Commit | Line | Data |
---|---|---|
e407c74b NC |
1 | .text |
2 | ||
3 | stuff: | |
4 | .ent stuff | |
5 | .set push | |
6 | .set noreorder | |
7 | .set noat | |
8 | ||
9 | add $0, $0, $31 | |
10 | add $1, $10, $3 | |
11 | add $31, $31, $0 | |
12 | ||
13 | addi $31, $0, 0 | |
14 | addi $1, $10, 3 | |
15 | addi $0, $31, -1 | |
16 | ||
17 | addiu $31, $0, 0 | |
18 | addiu $1, $10, 3 | |
19 | addiu $31, $0, 0xFFFF | |
20 | ||
21 | and $0, $0, $31 | |
22 | and $1, $10, $3 | |
23 | and $31, $31, $0 | |
24 | ||
25 | andi $31, $0, 0 | |
26 | andi $1, $10, 3 | |
27 | andi $0, $31, 0xFFFF | |
28 | ||
29 | nop | |
30 | ||
31 | # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I. | |
32 | c.lt.s $f0, $f31 | |
33 | c.lt.s $f31, $f0 | |
34 | ||
35 | # The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I. | |
36 | c.le.s $f0, $f31 | |
37 | c.le.s $f31, $f0 | |
38 | ||
39 | c.eq.s $f0, $f31 | |
40 | c.eq.s $f31, $f0 | |
41 | ||
42 | c.f.s $f0, $f31 | |
43 | c.f.s $f31, $f0 | |
44 | ||
45 | # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I. | |
46 | # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU. | |
47 | # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s. | |
48 | # cvt.w.s should not be used on R5900. | |
49 | trunc.w.s $f0, $f31 | |
50 | trunc.w.s $f31, $f0 | |
51 | ||
52 | # 128 bit store instruction. | |
53 | sq $0, 0($0) | |
54 | sq $1, 0x7fff($1) | |
55 | sq $8, -0x8000($8) | |
56 | sq $31, -1($31) | |
57 | ||
58 | # 128 bit load instruction. | |
59 | lq $0, 0($0) | |
60 | lq $1, 0x7fff($1) | |
61 | lq $8, -0x8000($8) | |
62 | lq $31, -1($31) | |
63 | ||
64 | # Prefetch cache | |
65 | pref 0, 0($0) | |
66 | pref 1, 0x7fff($1) | |
67 | pref 8, -0x8000($8) | |
68 | pref 31, -1($31) | |
69 | ||
70 | # Preformance counter registers | |
71 | mfpc $31, 0 | |
72 | mfpc $0, 1 | |
73 | mfps $0, 0 | |
74 | mfps $31, 0 | |
75 | mtpc $31, 0 | |
76 | mtpc $0, 1 | |
77 | mtps $0, 0 | |
78 | mtps $31, 0 | |
79 | ||
80 | # Pipeline1 | |
81 | mfhi1 $0 | |
82 | mfhi1 $31 | |
83 | mthi1 $0 | |
84 | mthi1 $31 | |
85 | mflo1 $0 | |
86 | mflo1 $31 | |
87 | mtlo1 $0 | |
88 | mtlo1 $31 | |
89 | ||
90 | movn $0, $0, $31 | |
91 | movn $31, $31, $0 | |
92 | movz $0, $0, $31 | |
93 | movz $31, $31, $0 | |
94 | ||
95 | # Parallel instructions operating on 128 bit registers: | |
96 | pcpyld $0, $0, $31 | |
97 | pcpyld $31, $31, $0 | |
98 | pextlh $0, $0, $31 | |
99 | pextlh $31, $31, $0 | |
100 | pextlw $0, $0, $31 | |
101 | pextlw $31, $31, $0 | |
102 | ||
103 | # G1 instructions | |
104 | mult $0, $0, $31 | |
105 | mult $31, $31, $0 | |
106 | multu $0, $0, $31 | |
107 | multu $31, $31, $0 | |
108 | mul $0, $0, $31 | |
109 | mul $31, $31, $0 | |
110 | madd $0, $0, $31 | |
111 | madd $31, $31, $0 | |
112 | madd $0, $31 | |
113 | madd $31, $0 | |
114 | maddu $0, $0, $31 | |
115 | maddu $31, $31, $0 | |
116 | maddu $0, $31 | |
117 | maddu $31, $0 | |
118 | sync | |
119 | ||
120 | .set pop | |
121 | .set push | |
122 | .set reorder | |
123 | # Short loop fix. | |
124 | li $3, 300 | |
125 | short_loop1: | |
126 | addi $3, -1 | |
127 | addi $4, -1 | |
128 | # NOP should be inserted in branch delay. | |
129 | bne $3, $0, short_loop1 | |
130 | ||
131 | li $4, 3 | |
132 | .set pop | |
133 | ||
134 | .space 8 | |
135 | .end stuff |