Commit | Line | Data |
---|---|---|
5915a74a CD |
1 | #objdump: -dr --prefix-addresses |
2 | #name: MIPS macro rol/ror | |
21b99e26 | 3 | #as: -32 |
252b5132 RH |
4 | |
5 | # Test the rol and ror macros. | |
6 | ||
7 | .*: +file format .*mips.* | |
8 | ||
9 | Disassembly of section .text: | |
aa5f19f2 NC |
10 | 0+0000 <[^>]*> negu at,a1 |
11 | 0+0004 <[^>]*> srlv at,a0,at | |
12 | 0+0008 <[^>]*> sllv a0,a0,a1 | |
13 | 0+000c <[^>]*> or a0,a0,at | |
14 | 0+0010 <[^>]*> negu at,a2 | |
15 | 0+0014 <[^>]*> srlv at,a1,at | |
16 | 0+0018 <[^>]*> sllv a0,a1,a2 | |
17 | 0+001c <[^>]*> or a0,a0,at | |
18 | 0+0020 <[^>]*> sll at,a0,0x1 | |
19 | 0+0024 <[^>]*> srl a0,a0,0x1f | |
20 | 0+0028 <[^>]*> or a0,a0,at | |
21 | 0+002c <[^>]*> sll at,a1,0x1 | |
22 | 0+0030 <[^>]*> srl a0,a1,0x1f | |
23 | 0+0034 <[^>]*> or a0,a0,at | |
483fc7cd RS |
24 | 0+0038 <[^>]*> srl a0,a1,0x0 |
25 | 0+003c <[^>]*> negu at,a1 | |
26 | 0+0040 <[^>]*> sllv at,a0,at | |
27 | 0+0044 <[^>]*> srlv a0,a0,a1 | |
28 | 0+0048 <[^>]*> or a0,a0,at | |
29 | 0+004c <[^>]*> negu at,a2 | |
30 | 0+0050 <[^>]*> sllv at,a1,at | |
31 | 0+0054 <[^>]*> srlv a0,a1,a2 | |
32 | 0+0058 <[^>]*> or a0,a0,at | |
33 | 0+005c <[^>]*> srl at,a0,0x1 | |
34 | 0+0060 <[^>]*> sll a0,a0,0x1f | |
35 | 0+0064 <[^>]*> or a0,a0,at | |
36 | 0+0068 <[^>]*> srl at,a1,0x1 | |
37 | 0+006c <[^>]*> sll a0,a1,0x1f | |
38 | 0+0070 <[^>]*> or a0,a0,at | |
39 | 0+0074 <[^>]*> srl a0,a1,0x0 | |
82dd0097 CD |
40 | 0+0078 <[^>]*> srl a0,a1,0x0 |
41 | 0+007c <[^>]*> sll at,a1,0x1 | |
42 | 0+0080 <[^>]*> srl a0,a1,0x1f | |
43 | 0+0084 <[^>]*> or a0,a0,at | |
44 | 0+0088 <[^>]*> sll at,a1,0x1f | |
45 | 0+008c <[^>]*> srl a0,a1,0x1 | |
46 | 0+0090 <[^>]*> or a0,a0,at | |
47 | 0+0094 <[^>]*> srl a0,a1,0x0 | |
48 | 0+0098 <[^>]*> srl at,a1,0x1 | |
49 | 0+009c <[^>]*> sll a0,a1,0x1f | |
50 | 0+00a0 <[^>]*> or a0,a0,at | |
51 | 0+00a4 <[^>]*> srl at,a1,0x1f | |
52 | 0+00a8 <[^>]*> sll a0,a1,0x1 | |
53 | 0+00ac <[^>]*> or a0,a0,at | |
483fc7cd | 54 | ... |