projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 5915a74a CD |
1 | #objdump: -dr --prefix-addresses |
| 2 | #name: MIPS macro drol/dror | |
| 82dd0097 | 3 | #stderr: rol64.l |
| 771c7ce4 TS |
4 | |
| 5 | # Test the drol and dror macros. | |
| 6 | ||
| 7 | .*: +file format .*mips.* | |
| 8 | ||
| 9 | Disassembly of section .text: | |
| 10 | 0+0000 <[^>]*> dnegu at,a1 | |
| 11 | 0+0004 <[^>]*> dsrlv at,a0,at | |
| 12 | 0+0008 <[^>]*> dsllv a0,a0,a1 | |
| 13 | 0+000c <[^>]*> or a0,a0,at | |
| 14 | 0+0010 <[^>]*> dnegu at,a2 | |
| 15 | 0+0014 <[^>]*> dsrlv at,a1,at | |
| 16 | 0+0018 <[^>]*> dsllv a0,a1,a2 | |
| 17 | 0+001c <[^>]*> or a0,a0,at | |
| 18 | 0+0020 <[^>]*> dsll at,a0,0x1 | |
| 19 | 0+0024 <[^>]*> dsrl32 a0,a0,0x1f | |
| 20 | 0+0028 <[^>]*> or a0,a0,at | |
| 483fc7cd RS |
21 | 0+002c <[^>]*> dsrl a0,a1,0x0 |
| 22 | 0+0030 <[^>]*> dsll at,a1,0x1 | |
| 23 | 0+0034 <[^>]*> dsrl32 a0,a1,0x1f | |
| 24 | 0+0038 <[^>]*> or a0,a0,at | |
| 25 | 0+003c <[^>]*> dsll at,a1,0x1f | |
| 26 | 0+0040 <[^>]*> dsrl32 a0,a1,0x1 | |
| 27 | 0+0044 <[^>]*> or a0,a0,at | |
| 28 | 0+0048 <[^>]*> dsll32 at,a1,0x0 | |
| 29 | 0+004c <[^>]*> dsrl32 a0,a1,0x0 | |
| 30 | 0+0050 <[^>]*> or a0,a0,at | |
| 31 | 0+0054 <[^>]*> dsll32 at,a1,0x1 | |
| 32 | 0+0058 <[^>]*> dsrl a0,a1,0x1f | |
| 33 | 0+005c <[^>]*> or a0,a0,at | |
| 34 | 0+0060 <[^>]*> dsll32 at,a1,0x1f | |
| 35 | 0+0064 <[^>]*> dsrl a0,a1,0x1 | |
| 36 | 0+0068 <[^>]*> or a0,a0,at | |
| 37 | 0+006c <[^>]*> dsrl a0,a1,0x0 | |
| 38 | 0+0070 <[^>]*> dnegu at,a1 | |
| 39 | 0+0074 <[^>]*> dsllv at,a0,at | |
| 40 | 0+0078 <[^>]*> dsrlv a0,a0,a1 | |
| 41 | 0+007c <[^>]*> or a0,a0,at | |
| 42 | 0+0080 <[^>]*> dnegu at,a2 | |
| 43 | 0+0084 <[^>]*> dsllv at,a1,at | |
| 44 | 0+0088 <[^>]*> dsrlv a0,a1,a2 | |
| 45 | 0+008c <[^>]*> or a0,a0,at | |
| 46 | 0+0090 <[^>]*> dsrl at,a0,0x1 | |
| 47 | 0+0094 <[^>]*> dsll32 a0,a0,0x1f | |
| 48 | 0+0098 <[^>]*> or a0,a0,at | |
| 49 | 0+009c <[^>]*> dsrl a0,a1,0x0 | |
| 50 | 0+00a0 <[^>]*> dsrl at,a1,0x1 | |
| 51 | 0+00a4 <[^>]*> dsll32 a0,a1,0x1f | |
| 771c7ce4 | 52 | 0+00a8 <[^>]*> or a0,a0,at |
| 483fc7cd RS |
53 | 0+00ac <[^>]*> dsrl at,a1,0x1f |
| 54 | 0+00b0 <[^>]*> dsll32 a0,a1,0x1 | |
| 771c7ce4 | 55 | 0+00b4 <[^>]*> or a0,a0,at |
| 483fc7cd RS |
56 | 0+00b8 <[^>]*> dsrl32 at,a1,0x0 |
| 57 | 0+00bc <[^>]*> dsll32 a0,a1,0x0 | |
| 771c7ce4 | 58 | 0+00c0 <[^>]*> or a0,a0,at |
| 483fc7cd RS |
59 | 0+00c4 <[^>]*> dsrl32 at,a1,0x1 |
| 60 | 0+00c8 <[^>]*> dsll a0,a1,0x1f | |
| 771c7ce4 | 61 | 0+00cc <[^>]*> or a0,a0,at |
| 483fc7cd RS |
62 | 0+00d0 <[^>]*> dsrl32 at,a1,0x1f |
| 63 | 0+00d4 <[^>]*> dsll a0,a1,0x1 | |
| 64 | 0+00d8 <[^>]*> or a0,a0,at | |
| 65 | 0+00dc <[^>]*> dsrl a0,a1,0x0 | |
| 82dd0097 CD |
66 | 0+00e0 <[^>]*> dsll at,a1,0x1 |
| 67 | 0+00e4 <[^>]*> dsrl32 a0,a1,0x1f | |
| 68 | 0+00e8 <[^>]*> or a0,a0,at | |
| 69 | 0+00ec <[^>]*> dsll at,a1,0x1f | |
| 70 | 0+00f0 <[^>]*> dsrl32 a0,a1,0x1 | |
| 71 | 0+00f4 <[^>]*> or a0,a0,at | |
| 72 | 0+00f8 <[^>]*> dsll32 at,a1,0x0 | |
| 73 | 0+00fc <[^>]*> dsrl32 a0,a1,0x0 | |
| 74 | 0+0100 <[^>]*> or a0,a0,at | |
| 75 | 0+0104 <[^>]*> dsll32 at,a1,0x1 | |
| 76 | 0+0108 <[^>]*> dsrl a0,a1,0x1f | |
| 77 | 0+010c <[^>]*> or a0,a0,at | |
| 78 | 0+0110 <[^>]*> dsll32 at,a1,0x1f | |
| 79 | 0+0114 <[^>]*> dsrl a0,a1,0x1 | |
| 80 | 0+0118 <[^>]*> or a0,a0,at | |
| 81 | 0+011c <[^>]*> dsrl at,a1,0x1 | |
| 82 | 0+0120 <[^>]*> dsll32 a0,a1,0x1f | |
| 83 | 0+0124 <[^>]*> or a0,a0,at | |
| 84 | 0+0128 <[^>]*> dsrl at,a1,0x1f | |
| 85 | 0+012c <[^>]*> dsll32 a0,a1,0x1 | |
| 86 | 0+0130 <[^>]*> or a0,a0,at | |
| 87 | 0+0134 <[^>]*> dsrl32 at,a1,0x0 | |
| 88 | 0+0138 <[^>]*> dsll32 a0,a1,0x0 | |
| 89 | 0+013c <[^>]*> or a0,a0,at | |
| 90 | 0+0140 <[^>]*> dsrl32 at,a1,0x1 | |
| 91 | 0+0144 <[^>]*> dsll a0,a1,0x1f | |
| 92 | 0+0148 <[^>]*> or a0,a0,at | |
| 93 | 0+014c <[^>]*> dsrl32 at,a1,0x1f | |
| 94 | 0+0150 <[^>]*> dsll a0,a1,0x1 | |
| 95 | 0+0154 <[^>]*> or a0,a0,at | |
| 771c7ce4 | 96 | ... |