projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 983be668 ILT |
1 | #objdump: -dr |
| 2 | #name: MIPS ulh-svr4pic | |
| 3 | #as: -mips1 -KPIC | |
| 4 | #source: ulh-pic.s | |
| 5 | ||
| 6 | # Test the unaligned load and store macros with -KPIC. | |
| 7 | ||
| 8 | .*: +file format .*mips.* | |
| 9 | ||
| 10 | Disassembly of section .text: | |
| 11 | 0+0000 <[^>]*> lw \$at,0\(\$gp\) | |
| 12 | [ ]*RELOC: 0+0000 R_MIPS_GOT16 .data | |
| 13 | ... | |
| 14 | 0+0008 <[^>]*> addiu \$at,\$at,0 | |
| 15 | [ ]*RELOC: 0+0008 R_MIPS_LO16 .data | |
| 16 | 0+000c <[^>]*> lb \$a0,0\(\$at\) | |
| 17 | 0+0010 <[^>]*> lbu \$at,1\(\$at\) | |
| 18 | 0+0014 <[^>]*> sll \$a0,\$a0,0x8 | |
| 19 | 0+0018 <[^>]*> or \$a0,\$a0,\$at | |
| 20 | 0+001c <[^>]*> lw \$at,0\(\$gp\) | |
| 21 | [ ]*RELOC: 0+001c R_MIPS_GOT16 big_external_data_label | |
| 22 | ... | |
| 23 | 0+0024 <[^>]*> lbu \$a0,0\(\$at\) | |
| 24 | 0+0028 <[^>]*> lbu \$at,1\(\$at\) | |
| 25 | 0+002c <[^>]*> sll \$a0,\$a0,0x8 | |
| 26 | 0+0030 <[^>]*> or \$a0,\$a0,\$at | |
| 27 | 0+0034 <[^>]*> lw \$at,0\(\$gp\) | |
| 28 | [ ]*RELOC: 0+0034 R_MIPS_GOT16 small_external_data_label | |
| 29 | ... | |
| 30 | 0+003c <[^>]*> lwl \$a0,0\(\$at\) | |
| 31 | 0+0040 <[^>]*> lwr \$a0,3\(\$at\) | |
| 32 | 0+0044 <[^>]*> lw \$at,0\(\$gp\) | |
| 33 | [ ]*RELOC: 0+0044 R_MIPS_GOT16 big_external_common | |
| 34 | ... | |
| 35 | 0+004c <[^>]*> sb \$a0,1\(\$at\) | |
| 36 | 0+0050 <[^>]*> srl \$a0,\$a0,0x8 | |
| 37 | 0+0054 <[^>]*> sb \$a0,0\(\$at\) | |
| 38 | 0+0058 <[^>]*> lbu \$at,1\(\$at\) | |
| 39 | 0+005c <[^>]*> sll \$a0,\$a0,0x8 | |
| 40 | 0+0060 <[^>]*> or \$a0,\$a0,\$at | |
| 41 | 0+0064 <[^>]*> lw \$at,0\(\$gp\) | |
| 42 | [ ]*RELOC: 0+0064 R_MIPS_GOT16 small_external_common | |
| 43 | ... | |
| 44 | 0+006c <[^>]*> swl \$a0,0\(\$at\) | |
| 45 | 0+0070 <[^>]*> swr \$a0,3\(\$at\) | |
| 46 | 0+0074 <[^>]*> lw \$at,0\(\$gp\) | |
| 47 | [ ]*RELOC: 0+0074 R_MIPS_GOT16 .bss | |
| 48 | ... | |
| 49 | 0+007c <[^>]*> addiu \$at,\$at,0 | |
| 50 | [ ]*RELOC: 0+007c R_MIPS_LO16 .bss | |
| 51 | 0+0080 <[^>]*> lb \$a0,0\(\$at\) | |
| 52 | 0+0084 <[^>]*> lbu \$at,1\(\$at\) | |
| 53 | 0+0088 <[^>]*> sll \$a0,\$a0,0x8 | |
| 54 | 0+008c <[^>]*> or \$a0,\$a0,\$at | |
| 55 | 0+0090 <[^>]*> lw \$at,0\(\$gp\) | |
| 56 | [ ]*RELOC: 0+0090 R_MIPS_GOT16 .bss | |
| 57 | ... | |
| 58 | 0+0098 <[^>]*> addiu \$at,\$at,1000 | |
| 59 | [ ]*RELOC: 0+0098 R_MIPS_LO16 .bss | |
| 60 | 0+009c <[^>]*> lbu \$a0,0\(\$at\) | |
| 61 | 0+00a0 <[^>]*> lbu \$at,1\(\$at\) | |
| 62 | 0+00a4 <[^>]*> sll \$a0,\$a0,0x8 | |
| 63 | 0+00a8 <[^>]*> or \$a0,\$a0,\$at | |
| 64 | 0+00ac <[^>]*> lw \$at,0\(\$gp\) | |
| 65 | [ ]*RELOC: 0+00ac R_MIPS_GOT16 .data | |
| 66 | ... | |
| 67 | 0+00b4 <[^>]*> addiu \$at,\$at,1 | |
| 68 | [ ]*RELOC: 0+00b4 R_MIPS_LO16 .data | |
| 69 | 0+00b8 <[^>]*> lwl \$a0,0\(\$at\) | |
| 70 | 0+00bc <[^>]*> lwr \$a0,3\(\$at\) | |
| 71 | 0+00c0 <[^>]*> lw \$at,0\(\$gp\) | |
| 72 | [ ]*RELOC: 0+00c0 R_MIPS_GOT16 big_external_data_label | |
| 73 | ... | |
| 74 | 0+00c8 <[^>]*> sb \$a0,1\(\$at\) | |
| 75 | 0+00cc <[^>]*> srl \$a0,\$a0,0x8 | |
| 76 | 0+00d0 <[^>]*> sb \$a0,0\(\$at\) | |
| 77 | 0+00d4 <[^>]*> lbu \$at,1\(\$at\) | |
| 78 | 0+00d8 <[^>]*> sll \$a0,\$a0,0x8 | |
| 79 | 0+00dc <[^>]*> or \$a0,\$a0,\$at | |
| 80 | 0+00e0 <[^>]*> lw \$at,0\(\$gp\) | |
| 81 | [ ]*RELOC: 0+00e0 R_MIPS_GOT16 small_external_data_label | |
| 82 | ... | |
| 83 | 0+00e8 <[^>]*> swl \$a0,0\(\$at\) | |
| 84 | 0+00ec <[^>]*> swr \$a0,3\(\$at\) | |
| 85 | 0+00f0 <[^>]*> lw \$at,0\(\$gp\) | |
| 86 | [ ]*RELOC: 0+00f0 R_MIPS_GOT16 big_external_common | |
| 87 | ... | |
| 88 | 0+00f8 <[^>]*> lb \$a0,0\(\$at\) | |
| 89 | 0+00fc <[^>]*> lbu \$at,1\(\$at\) | |
| 90 | 0+0100 <[^>]*> sll \$a0,\$a0,0x8 | |
| 91 | 0+0104 <[^>]*> or \$a0,\$a0,\$at | |
| 92 | 0+0108 <[^>]*> lw \$at,0\(\$gp\) | |
| 93 | [ ]*RELOC: 0+0108 R_MIPS_GOT16 small_external_common | |
| 94 | ... | |
| 95 | 0+0110 <[^>]*> lbu \$a0,0\(\$at\) | |
| 96 | 0+0114 <[^>]*> lbu \$at,1\(\$at\) | |
| 97 | 0+0118 <[^>]*> sll \$a0,\$a0,0x8 | |
| 98 | 0+011c <[^>]*> or \$a0,\$a0,\$at | |
| 99 | 0+0120 <[^>]*> lw \$at,0\(\$gp\) | |
| 100 | [ ]*RELOC: 0+0120 R_MIPS_GOT16 .bss | |
| 101 | ... | |
| 102 | 0+0128 <[^>]*> addiu \$at,\$at,1 | |
| 103 | [ ]*RELOC: 0+0128 R_MIPS_LO16 .bss | |
| 104 | 0+012c <[^>]*> lwl \$a0,0\(\$at\) | |
| 105 | 0+0130 <[^>]*> lwr \$a0,3\(\$at\) | |
| 106 | 0+0134 <[^>]*> lw \$at,0\(\$gp\) | |
| 107 | [ ]*RELOC: 0+0134 R_MIPS_GOT16 .bss | |
| 108 | ... | |
| 109 | 0+013c <[^>]*> addiu \$at,\$at,1001 | |
| 110 | [ ]*RELOC: 0+013c R_MIPS_LO16 .bss | |
| 111 | 0+0140 <[^>]*> sb \$a0,1\(\$at\) | |
| 112 | 0+0144 <[^>]*> srl \$a0,\$a0,0x8 | |
| 113 | 0+0148 <[^>]*> sb \$a0,0\(\$at\) | |
| 114 | 0+014c <[^>]*> lbu \$at,1\(\$at\) | |
| 115 | 0+0150 <[^>]*> sll \$a0,\$a0,0x8 | |
| 116 | 0+0154 <[^>]*> or \$a0,\$a0,\$at | |
| 117 | ... |