projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 60b63b72 RS |
1 | .text |
| 2 | ||
| 3 | stuff: | |
| 4 | .ent stuff | |
| 5 | /* Integer instructions. */ | |
| 6 | ||
| 7 | mul $4,$5,$6 | |
| 8 | mulu $4,$5,$6 | |
| 9 | mulhi $4,$5,$6 | |
| 10 | mulhiu $4,$5,$6 | |
| 11 | muls $4,$5,$6 | |
| 12 | mulsu $4,$5,$6 | |
| 13 | mulshi $4,$5,$6 | |
| 14 | mulshiu $4,$5,$6 | |
| 15 | macc $4,$5,$6 | |
| 16 | maccu $4,$5,$6 | |
| 17 | macchi $4,$5,$6 | |
| 18 | macchiu $4,$5,$6 | |
| 19 | msac $4,$5,$6 | |
| 20 | msacu $4,$5,$6 | |
| 21 | msachi $4,$5,$6 | |
| 22 | msachiu $4,$5,$6 | |
| 23 | ||
| 24 | ror $4,$5,25 | |
| 25 | rorv $4,$5,$6 | |
| 26 | dror $4,$5,25 | |
| 27 | dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ | |
| 28 | dror32 $4,$5,25 | |
| 29 | drorv $4,$5,$6 | |
| 30 | ||
| 31 | /* Debug instructions. */ | |
| 32 | ||
| 33 | dbreak | |
| 34 | dret | |
| 35 | mfdr $3,$3 | |
| 36 | mtdr $3,$3 | |
| 37 | ||
| 38 | /* Coprocessor 0 instructions, minus standard ISA 3 ones. | |
| 39 | That leaves just the performance monitoring registers. */ | |
| 40 | ||
| 41 | mfpc $4,1 | |
| 42 | mfps $4,1 | |
| 43 | mtpc $4,1 | |
| 44 | mtps $4,1 | |
| 45 | ||
| 46 | /* Multimedia instructions. */ | |
| 47 | ||
| 48 | .macro nsel2 op | |
| 49 | /* Test each form of each vector opcode. */ | |
| 50 | \op $f0,$f2 | |
| b892b944 | 51 | \op $f4,$f6[2] |
| 60b63b72 RS |
52 | \op $f6,15 |
| 53 | .if 0 /* Which is right?? */ | |
| 54 | /* Test negative numbers in immediate-value slot. */ | |
| 55 | \op $f4,-3 | |
| 56 | .else | |
| 57 | /* Test that it's recognized as an unsigned field. */ | |
| b892b944 | 58 | \op $f4,31 |
| 60b63b72 RS |
59 | .endif |
| 60 | .endm | |
| 61 | ||
| 62 | .macro nsel3 op | |
| 63 | /* Test each form of each vector opcode. */ | |
| b892b944 TS |
64 | \op $f0,$f2,$f4 |
| 65 | \op $f2,$f4,$f6[2] | |
| 66 | \op $f6,$f4,15 | |
| 60b63b72 RS |
67 | .if 0 /* Which is right?? */ |
| 68 | /* Test negative numbers in immediate-value slot. */ | |
| 69 | \op $f4,$f6,-3 | |
| 70 | .else | |
| 71 | /* Test that it's recognized as an unsigned field. */ | |
| b892b944 | 72 | \op $f4,$f6,31 |
| 60b63b72 RS |
73 | .endif |
| 74 | .endm | |
| 75 | ||
| 76 | nsel3 add.ob | |
| 77 | nsel3 and.ob | |
| 78 | nsel2 c.eq.ob | |
| 79 | nsel2 c.le.ob | |
| 80 | nsel2 c.lt.ob | |
| 81 | nsel3 max.ob | |
| 82 | nsel3 min.ob | |
| 83 | nsel3 mul.ob | |
| 84 | nsel2 mula.ob | |
| 85 | nsel2 mull.ob | |
| 86 | nsel2 muls.ob | |
| 87 | nsel2 mulsl.ob | |
| 88 | nsel3 nor.ob | |
| 89 | nsel3 or.ob | |
| 90 | nsel3 pickf.ob | |
| 91 | nsel3 pickt.ob | |
| 92 | nsel3 sub.ob | |
| 93 | nsel3 xor.ob | |
| 94 | ||
| 95 | /* ALNI, SHFL: Vector only. */ | |
| b892b944 TS |
96 | alni.ob $f0,$f2,$f4,5 |
| 97 | shfl.mixh.ob $f0,$f2,$f4 | |
| 98 | shfl.mixl.ob $f0,$f2,$f4 | |
| 99 | shfl.pach.ob $f0,$f2,$f4 | |
| 100 | shfl.pacl.ob $f0,$f2,$f4 | |
| 60b63b72 RS |
101 | |
| 102 | /* SLL,SRL: Scalar or immediate. */ | |
| b892b944 TS |
103 | sll.ob $f2,$f4,$f6[3] |
| 104 | sll.ob $f4,$f6,14 | |
| 105 | srl.ob $f2,$f4,$f6[3] | |
| 106 | srl.ob $f4,$f6,14 | |
| 60b63b72 RS |
107 | |
| 108 | /* RZU: Immediate, must be 0, 8, or 16. */ | |
| 109 | rzu.ob $f2,13 | |
| 110 | ||
| 111 | /* No selector. */ | |
| 112 | rach.ob $f2 | |
| 113 | racl.ob $f2 | |
| 114 | racm.ob $f2 | |
| 115 | wach.ob $f2 | |
| b892b944 | 116 | wacl.ob $f2,$f4 |
| 60b63b72 RS |
117 | |
| 118 | ror $4,$5,$6 | |
| 119 | rol $4,$5,15 | |
| 120 | dror $4,$5,$6 | |
| 121 | drol $4,$5,31 | |
| 122 | drol $4,$5,62 | |
| 123 | ||
| 124 | .space 8 | |
| 125 | .end stuff |