[AArch64] Warn on load pair to same register
[deliverable/binutils-gdb.git] / gas / testsuite / gas / msp430 / bad.s
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1 .text
2 .cpu 430x
3
4;;; Test for the assembler detecting spurious size modifiers.
5
6 mov.z r1, r2
7 mov.abc r1, r2
8 mov.bcd r1, r2
9 mov.wcd r1, r2
10 mov. r1, r2
11 bis.a #8, r2
12
13;;; FIXME: Add more tests of assembler error detection here.
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14
15 ;; Changing interrupt states in two successive instructions
16 ;; might cause an interrupt to be missed. The assembler
17 ;; should warn about this, if the -mz command line option
18 ;; is used.
19 eint
20 dint
21 nop ;; No warning needed here.
22 dint
23 and #1, r11 ;; Any instruction will do, not just NOPs.
24 clr r2 ;; Aliases should trigger the warning too.
25 mov #1, r2
26 BIC #8, SR
27 BIS #8, SR
28 MOV.W #1, SR
29 ;; We will also get a warning if the last instruction in the file
30 ;; changes the interrupt state, since this file could be linked
31 ;; with another that starts with an interrupt change.
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