Commit | Line | Data |
---|---|---|
6b9d3259 KLC |
1 | #objdump: -d --prefix-addresses |
2 | #name: nds32 sys-reg instructions | |
3 | #as: | |
4 | ||
5 | # Test system register instructions | |
6 | ||
7 | .*: file format .* | |
8 | ||
9 | ||
10 | Disassembly of section .text: | |
11 | 0+0000 <[^>]*> mfsr \$r0, \$CPU_VER | |
12 | 0+0004 <[^>]*> mfsr \$r0, \$CORE_ID | |
13 | 0+0008 <[^>]*> mfsr \$r0, \$ICM_CFG | |
14 | 0+000c <[^>]*> mfsr \$r0, \$DCM_CFG | |
15 | 0+0010 <[^>]*> mfsr \$r0, \$MMU_CFG | |
16 | 0+0014 <[^>]*> mfsr \$r0, \$MSC_CFG | |
17 | 0+0018 <[^>]*> mfsr \$r0, \$PSW | |
18 | 0+001c <[^>]*> mfsr \$r0, \$IPSW | |
19 | 0+0020 <[^>]*> mfsr \$r0, \$P_IPSW | |
20 | 0+0024 <[^>]*> mfsr \$r0, \$IVB | |
21 | 0+0028 <[^>]*> mfsr \$r0, \$INT_CTRL | |
22 | 0+002c <[^>]*> mfsr \$r0, \$EVA | |
23 | 0+0030 <[^>]*> mfsr \$r0, \$P_EVA | |
24 | 0+0034 <[^>]*> mfsr \$r0, \$ITYPE | |
25 | 0+0038 <[^>]*> mfsr \$r0, \$P_ITYPE | |
26 | 0+003c <[^>]*> mfsr \$r0, \$MERR | |
27 | 0+0040 <[^>]*> mfsr \$r0, \$IPC | |
28 | 0+0044 <[^>]*> mfsr \$r0, \$P_IPC | |
29 | 0+0048 <[^>]*> mfsr \$r0, \$OIPC | |
30 | 0+004c <[^>]*> mfsr \$r0, \$P_P0 | |
31 | 0+0050 <[^>]*> mfsr \$r0, \$P_P1 | |
32 | 0+0054 <[^>]*> mfsr \$r0, \$INT_MASK | |
33 | 0+0058 <[^>]*> mfsr \$r0, \$INT_MASK2 | |
34 | 0+005c <[^>]*> mfsr \$r0, \$INT_PEND | |
35 | 0+0060 <[^>]*> mfsr \$r0, \$INT_PEND2 | |
36 | 0+0064 <[^>]*> mfsr \$r0, \$INT_TRIGGER | |
37 | 0+0068 <[^>]*> mfsr \$r0, \$SP_USR | |
38 | 0+006c <[^>]*> mfsr \$r0, \$SP_PRIV | |
39 | 0+0070 <[^>]*> mfsr \$r0, \$INT_PRI | |
40 | 0+0074 <[^>]*> mfsr \$r0, \$INT_PRI2 | |
41 | 0+0078 <[^>]*> mfsr \$r0, \$MMU_CTL | |
42 | 0+007c <[^>]*> mfsr \$r0, \$L1_PPTB | |
43 | 0+0080 <[^>]*> mfsr \$r0, \$TLB_VPN | |
44 | 0+0084 <[^>]*> mfsr \$r0, \$TLB_DATA | |
45 | 0+0088 <[^>]*> mfsr \$r0, \$TLB_MISC | |
46 | 0+008c <[^>]*> mfsr \$r0, \$VLPT_IDX | |
47 | 0+0090 <[^>]*> mfsr \$r0, \$ILMB | |
48 | 0+0094 <[^>]*> mfsr \$r0, \$DLMB | |
49 | 0+0098 <[^>]*> mfsr \$r0, \$CACHE_CTL | |
50 | 0+009c <[^>]*> mfsr \$r0, \$HSMP_SADDR | |
51 | 0+00a0 <[^>]*> mfsr \$r0, \$HSMP_EADDR | |
52 | 0+00a4 <[^>]*> mfsr \$r0, \$SDZ_CTL | |
53 | 0+00a8 <[^>]*> mfsr \$r0, \$MISC_CTL | |
54 | 0+00ac <[^>]*> mfsr \$r0, \$BPC0 | |
55 | 0+00b0 <[^>]*> mfsr \$r0, \$BPC1 | |
56 | 0+00b4 <[^>]*> mfsr \$r0, \$BPC2 | |
57 | 0+00b8 <[^>]*> mfsr \$r0, \$BPC3 | |
58 | 0+00bc <[^>]*> mfsr \$r0, \$BPC4 | |
59 | 0+00c0 <[^>]*> mfsr \$r0, \$BPC5 | |
60 | 0+00c4 <[^>]*> mfsr \$r0, \$BPC6 | |
61 | 0+00c8 <[^>]*> mfsr \$r0, \$BPC7 | |
62 | 0+00cc <[^>]*> mfsr \$r0, \$BPA0 | |
63 | 0+00d0 <[^>]*> mfsr \$r0, \$BPA1 | |
64 | 0+00d4 <[^>]*> mfsr \$r0, \$BPA2 | |
65 | 0+00d8 <[^>]*> mfsr \$r0, \$BPA3 | |
66 | 0+00dc <[^>]*> mfsr \$r0, \$BPA4 | |
67 | 0+00e0 <[^>]*> mfsr \$r0, \$BPA5 | |
68 | 0+00e4 <[^>]*> mfsr \$r0, \$BPA6 | |
69 | 0+00e8 <[^>]*> mfsr \$r0, \$BPA7 | |
70 | 0+00ec <[^>]*> mfsr \$r0, \$BPAM0 | |
71 | 0+00f0 <[^>]*> mfsr \$r0, \$BPAM1 | |
72 | 0+00f4 <[^>]*> mfsr \$r0, \$BPAM2 | |
73 | 0+00f8 <[^>]*> mfsr \$r0, \$BPAM3 | |
74 | 0+00fc <[^>]*> mfsr \$r0, \$BPAM4 | |
75 | 0+0100 <[^>]*> mfsr \$r0, \$BPAM5 | |
76 | 0+0104 <[^>]*> mfsr \$r0, \$BPAM6 | |
77 | 0+0108 <[^>]*> mfsr \$r0, \$BPAM7 | |
78 | 0+010c <[^>]*> mfsr \$r0, \$BPV0 | |
79 | 0+0110 <[^>]*> mfsr \$r0, \$BPV1 | |
80 | 0+0114 <[^>]*> mfsr \$r0, \$BPV2 | |
81 | 0+0118 <[^>]*> mfsr \$r0, \$BPV3 | |
82 | 0+011c <[^>]*> mfsr \$r0, \$BPV4 | |
83 | 0+0120 <[^>]*> mfsr \$r0, \$BPV5 | |
84 | 0+0124 <[^>]*> mfsr \$r0, \$BPV6 | |
85 | 0+0128 <[^>]*> mfsr \$r0, \$BPV7 | |
86 | 0+012c <[^>]*> mfsr \$r0, \$BPCID0 | |
87 | 0+0130 <[^>]*> mfsr \$r0, \$BPCID1 | |
88 | 0+0134 <[^>]*> mfsr \$r0, \$BPCID2 | |
89 | 0+0138 <[^>]*> mfsr \$r0, \$BPCID3 | |
90 | 0+013c <[^>]*> mfsr \$r0, \$BPCID4 | |
91 | 0+0140 <[^>]*> mfsr \$r0, \$BPCID5 | |
92 | 0+0144 <[^>]*> mfsr \$r0, \$BPCID6 | |
93 | 0+0148 <[^>]*> mfsr \$r0, \$BPCID7 | |
94 | 0+014c <[^>]*> mfsr \$r0, \$EDM_CFG | |
95 | 0+0150 <[^>]*> mfsr \$r0, \$EDMSW | |
96 | 0+0154 <[^>]*> mfsr \$r0, \$EDM_CTL | |
97 | 0+0158 <[^>]*> mfsr \$r0, \$EDM_DTR | |
98 | 0+015c <[^>]*> mfsr \$r0, \$BPMTC | |
99 | 0+0160 <[^>]*> mfsr \$r0, \$DIMBR | |
100 | 0+0164 <[^>]*> mfsr \$r0, \$TECR0 | |
101 | 0+0168 <[^>]*> mfsr \$r0, \$TECR1 | |
102 | 0+016c <[^>]*> mfsr \$r0, \$PFMC0 | |
103 | 0+0170 <[^>]*> mfsr \$r0, \$PFMC1 | |
104 | 0+0174 <[^>]*> mfsr \$r0, \$PFMC2 | |
105 | 0+0178 <[^>]*> mfsr \$r0, \$PFM_CTL | |
106 | 0+017c <[^>]*> mfsr \$r0, \$PRUSR_ACC_CTL | |
107 | 0+0180 <[^>]*> mfsr \$r0, \$FUCOP_CTL | |
108 | 0+0184 <[^>]*> mfsr \$r0, \$DMA_CFG | |
109 | 0+0188 <[^>]*> mfsr \$r0, \$DMA_GCSW | |
110 | 0+018c <[^>]*> mfsr \$r0, \$DMA_CHNSEL | |
111 | 0+0190 <[^>]*> mfsr \$r0, \$DMA_ACT | |
112 | 0+0194 <[^>]*> mfsr \$r0, \$DMA_SETUP | |
113 | 0+0198 <[^>]*> mfsr \$r0, \$DMA_ISADDR | |
114 | 0+019c <[^>]*> mfsr \$r0, \$DMA_ESADDR | |
115 | 0+01a0 <[^>]*> mfsr \$r0, \$DMA_TCNT | |
116 | 0+01a4 <[^>]*> mfsr \$r0, \$DMA_STATUS | |
117 | 0+01a8 <[^>]*> mfsr \$r0, \$DMA_2DSET | |
118 | 0+01ac <[^>]*> mfsr \$r0, \$DMA_2DSCTL |