Commit | Line | Data |
---|---|---|
aea77599 AM |
1 | #as: -mppc -me6500 |
2 | #objdump: -dr -Me6500 | |
3 | #name: Power E6500 tests | |
4 | ||
ab1f5dd1 | 5 | .* |
aea77599 AM |
6 | |
7 | Disassembly of section \.text: | |
8 | ||
9 | 0+00 <start>: | |
ab1f5dd1 AM |
10 | 0: (10 01 14 03|03 14 01 10) vabsdub v0,v1,v2 |
11 | 4: (10 01 14 43|43 14 01 10) vabsduh v0,v1,v2 | |
12 | 8: (10 01 14 83|83 14 01 10) vabsduw v0,v1,v2 | |
13 | c: (7c 01 10 dc|dc 10 01 7c) mvidsplt v0,r1,r2 | |
14 | 10: (7c 01 10 5c|5c 10 01 7c) mviwsplt v0,r1,r2 | |
15 | 14: (7c 00 12 0a|0a 12 00 7c) lvexbx v0,0,r2 | |
16 | 18: (7c 01 12 0a|0a 12 01 7c) lvexbx v0,r1,r2 | |
17 | 1c: (7c 00 12 4a|4a 12 00 7c) lvexhx v0,0,r2 | |
18 | 20: (7c 01 12 4a|4a 12 01 7c) lvexhx v0,r1,r2 | |
19 | 24: (7c 00 12 8a|8a 12 00 7c) lvexwx v0,0,r2 | |
20 | 28: (7c 01 12 8a|8a 12 01 7c) lvexwx v0,r1,r2 | |
21 | 2c: (7c 00 13 0a|0a 13 00 7c) stvexbx v0,0,r2 | |
22 | 30: (7c 01 13 0a|0a 13 01 7c) stvexbx v0,r1,r2 | |
23 | 34: (7c 00 13 4a|4a 13 00 7c) stvexhx v0,0,r2 | |
24 | 38: (7c 01 13 4a|4a 13 01 7c) stvexhx v0,r1,r2 | |
25 | 3c: (7c 00 13 8a|8a 13 00 7c) stvexwx v0,0,r2 | |
26 | 40: (7c 01 13 8a|8a 13 01 7c) stvexwx v0,r1,r2 | |
27 | 44: (7c 00 12 4e|4e 12 00 7c) lvepx v0,0,r2 | |
28 | 48: (7c 01 12 4e|4e 12 01 7c) lvepx v0,r1,r2 | |
29 | 4c: (7c 00 12 0e|0e 12 00 7c) lvepxl v0,0,r2 | |
30 | 50: (7c 01 12 0e|0e 12 01 7c) lvepxl v0,r1,r2 | |
31 | 54: (7c 00 16 4e|4e 16 00 7c) stvepx v0,0,r2 | |
32 | 58: (7c 01 16 4e|4e 16 01 7c) stvepx v0,r1,r2 | |
33 | 5c: (7c 00 16 0e|0e 16 00 7c) stvepxl v0,0,r2 | |
34 | 60: (7c 01 16 0e|0e 16 01 7c) stvepxl v0,r1,r2 | |
35 | 64: (7c 00 14 8a|8a 14 00 7c) lvtlx v0,0,r2 | |
36 | 68: (7c 01 14 8a|8a 14 01 7c) lvtlx v0,r1,r2 | |
37 | 6c: (7c 00 16 8a|8a 16 00 7c) lvtlxl v0,0,r2 | |
38 | 70: (7c 01 16 8a|8a 16 01 7c) lvtlxl v0,r1,r2 | |
39 | 74: (7c 00 14 4a|4a 14 00 7c) lvtrx v0,0,r2 | |
40 | 78: (7c 01 14 4a|4a 14 01 7c) lvtrx v0,r1,r2 | |
41 | 7c: (7c 00 16 4a|4a 16 00 7c) lvtrxl v0,0,r2 | |
42 | 80: (7c 01 16 4a|4a 16 01 7c) lvtrxl v0,r1,r2 | |
43 | 84: (7c 00 15 8a|8a 15 00 7c) stvflx v0,0,r2 | |
44 | 88: (7c 01 15 8a|8a 15 01 7c) stvflx v0,r1,r2 | |
45 | 8c: (7c 00 17 8a|8a 17 00 7c) stvflxl v0,0,r2 | |
46 | 90: (7c 01 17 8a|8a 17 01 7c) stvflxl v0,r1,r2 | |
47 | 94: (7c 00 15 4a|4a 15 00 7c) stvfrx v0,0,r2 | |
48 | 98: (7c 01 15 4a|4a 15 01 7c) stvfrx v0,r1,r2 | |
49 | 9c: (7c 00 17 4a|4a 17 00 7c) stvfrxl v0,0,r2 | |
50 | a0: (7c 01 17 4a|4a 17 01 7c) stvfrxl v0,r1,r2 | |
51 | a4: (7c 00 14 ca|ca 14 00 7c) lvswx v0,0,r2 | |
52 | a8: (7c 01 14 ca|ca 14 01 7c) lvswx v0,r1,r2 | |
53 | ac: (7c 00 16 ca|ca 16 00 7c) lvswxl v0,0,r2 | |
54 | b0: (7c 01 16 ca|ca 16 01 7c) lvswxl v0,r1,r2 | |
55 | b4: (7c 00 15 ca|ca 15 00 7c) stvswx v0,0,r2 | |
56 | b8: (7c 01 15 ca|ca 15 01 7c) stvswx v0,r1,r2 | |
57 | bc: (7c 00 17 ca|ca 17 00 7c) stvswxl v0,0,r2 | |
58 | c0: (7c 01 17 ca|ca 17 01 7c) stvswxl v0,r1,r2 | |
59 | c4: (7c 00 16 0a|0a 16 00 7c) lvsm v0,0,r2 | |
60 | c8: (7c 01 16 0a|0a 16 01 7c) lvsm v0,r1,r2 | |
61 | cc: (7f 5a d3 78|78 d3 5a 7f) miso | |
62 | d0: (7c 00 04 ac|ac 04 00 7c) sync | |
63 | d4: (7c 00 04 ac|ac 04 00 7c) sync | |
64 | d8: (7c 20 04 ac|ac 04 20 7c) lwsync | |
65 | dc: (7c 00 04 ac|ac 04 00 7c) sync | |
66 | e0: (7c 07 04 ac|ac 04 07 7c) sync 0,7 | |
67 | e4: (7c 28 04 ac|ac 04 28 7c) sync 1,8 | |
68 | e8: (7c 00 00 c3|c3 00 00 7c) dni 0,0 | |
69 | ec: (7f ff 00 c3|c3 00 ff 7f) dni 31,31 | |
70 | f0: (7c 40 0b 4d|4d 0b 40 7c) dcblq. 2,0,r1 | |
71 | f4: (7c 43 0b 4d|4d 0b 43 7c) dcblq. 2,r3,r1 | |
72 | f8: (7c 40 09 8d|8d 09 40 7c) icblq. 2,0,r1 | |
73 | fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1 | |
74 | 100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16 | |
75 | 104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0 |