Commit | Line | Data |
---|---|---|
ee1ee5b5 NC |
1 | /* |
2 | * test relax | |
3 | * br <-> br! : register number must be in 0-15 | |
4 | * brl <-> brl! : register number must be in 0-15 | |
5 | ||
6 | * Author: ligang | |
7 | */ | |
8 | ||
9 | /* This macro transform 32b instruction to 16b. */ | |
10 | .macro tran3216 insn32, insn16 | |
11 | .align 4 | |
12 | ||
13 | \insn32 r0 #32b -> 16b | |
14 | \insn16 r0 | |
15 | ||
16 | \insn32 r15 #32b -> 16b | |
17 | \insn16 r15 | |
18 | ||
19 | \insn32 r3 #32b -> 16b | |
20 | \insn32 r3 #32b -> 16b | |
21 | ||
22 | \insn16 r5 | |
23 | \insn32 r5 #32b -> 16b | |
24 | ||
25 | \insn32 r3 #No transform | |
26 | \insn32 r31 #No transform | |
27 | ||
28 | .endm | |
29 | ||
30 | /* This macro transform 16b instruction to 32b. */ | |
31 | .macro tran1632 insn32, insn16 | |
32 | .align 4 | |
33 | ||
34 | \insn16 r0 #16b -> 32b | |
35 | \insn32 r23 | |
36 | ||
37 | \insn16 r15 #16b -> 32b | |
38 | \insn32 r27 | |
39 | ||
40 | \insn16 r6 #No transform | |
41 | \insn32 r6 | |
42 | ||
43 | \insn16 r3 #No transform | |
44 | \insn16 r3 | |
45 | ||
46 | .endm | |
47 | ||
48 | tran3216 "br", "br!" | |
49 | tran3216 "brl", "brl!" | |
50 | ||
51 | tran1632 "br", "br!" | |
52 | tran1632 "brl", "brl!" | |
53 |