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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
42a4f53d | 3 | Copyright (C) 2011-2019 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
607685ec | 32 | #include "aarch32-linux-nat.h" |
db3cb7cb | 33 | #include "nat/aarch64-linux.h" |
554717a3 | 34 | #include "nat/aarch64-linux-hw-point.h" |
ba2d2bb2 | 35 | #include "nat/aarch64-sve-linux-ptrace.h" |
607685ec YQ |
36 | |
37 | #include "elf/external.h" | |
9d19df75 MS |
38 | #include "elf/common.h" |
39 | ||
5826e159 | 40 | #include "nat/gdb_ptrace.h" |
9d19df75 | 41 | #include <sys/utsname.h> |
036cd381 | 42 | #include <asm/ptrace.h> |
9d19df75 MS |
43 | |
44 | #include "gregset.h" | |
45 | ||
9d19df75 MS |
46 | /* Defines ps_err_e, struct ps_prochandle. */ |
47 | #include "gdb_proc_service.h" | |
48 | ||
49 | #ifndef TRAP_HWBKPT | |
50 | #define TRAP_HWBKPT 0x0004 | |
51 | #endif | |
52 | ||
f6ac5f3d PA |
53 | class aarch64_linux_nat_target final : public linux_nat_target |
54 | { | |
55 | public: | |
56 | /* Add our register access methods. */ | |
57 | void fetch_registers (struct regcache *, int) override; | |
58 | void store_registers (struct regcache *, int) override; | |
59 | ||
60 | const struct target_desc *read_description () override; | |
61 | ||
62 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
63 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
64 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
65 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
66 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
67 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
68 | struct expression *) override; | |
69 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
70 | struct expression *) override; | |
57810aa7 PA |
71 | bool stopped_by_watchpoint () override; |
72 | bool stopped_data_address (CORE_ADDR *) override; | |
73 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; | |
f6ac5f3d PA |
74 | |
75 | int can_do_single_step () override; | |
76 | ||
77 | /* Override the GNU/Linux inferior startup hook. */ | |
78 | void post_startup_inferior (ptid_t) override; | |
135340af | 79 | |
8363f9d5 RB |
80 | /* Override the GNU/Linux post attach hook. */ |
81 | void post_attach (int pid) override; | |
82 | ||
135340af PA |
83 | /* These three defer to common nat/ code. */ |
84 | void low_new_thread (struct lwp_info *lp) override | |
85 | { aarch64_linux_new_thread (lp); } | |
86 | void low_delete_thread (struct arch_lwp_info *lp) override | |
87 | { aarch64_linux_delete_thread (lp); } | |
88 | void low_prepare_to_resume (struct lwp_info *lp) override | |
89 | { aarch64_linux_prepare_to_resume (lp); } | |
90 | ||
91 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
92 | void low_forget_process (pid_t pid) override; | |
93 | ||
94 | /* Add our siginfo layout converter. */ | |
95 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
96 | override; | |
f6ac5f3d PA |
97 | }; |
98 | ||
99 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; | |
100 | ||
d6c44983 YZ |
101 | /* Per-process data. We don't bind this to a per-inferior registry |
102 | because of targets like x86 GNU/Linux that need to keep track of | |
103 | processes that aren't bound to any inferior (e.g., fork children, | |
104 | checkpoints). */ | |
9d19df75 | 105 | |
d6c44983 | 106 | struct aarch64_process_info |
9d19df75 | 107 | { |
d6c44983 YZ |
108 | /* Linked list. */ |
109 | struct aarch64_process_info *next; | |
9d19df75 | 110 | |
d6c44983 YZ |
111 | /* The process identifier. */ |
112 | pid_t pid; | |
9d19df75 | 113 | |
d6c44983 YZ |
114 | /* Copy of aarch64 hardware debug registers. */ |
115 | struct aarch64_debug_reg_state state; | |
116 | }; | |
117 | ||
118 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
119 | ||
120 | /* Find process data for process PID. */ | |
121 | ||
122 | static struct aarch64_process_info * | |
123 | aarch64_find_process_pid (pid_t pid) | |
124 | { | |
125 | struct aarch64_process_info *proc; | |
126 | ||
127 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
128 | if (proc->pid == pid) | |
129 | return proc; | |
130 | ||
131 | return NULL; | |
9d19df75 MS |
132 | } |
133 | ||
d6c44983 YZ |
134 | /* Add process data for process PID. Returns newly allocated info |
135 | object. */ | |
9d19df75 | 136 | |
d6c44983 YZ |
137 | static struct aarch64_process_info * |
138 | aarch64_add_process (pid_t pid) | |
9d19df75 | 139 | { |
d6c44983 | 140 | struct aarch64_process_info *proc; |
9d19df75 | 141 | |
8d749320 | 142 | proc = XCNEW (struct aarch64_process_info); |
d6c44983 | 143 | proc->pid = pid; |
9d19df75 | 144 | |
d6c44983 YZ |
145 | proc->next = aarch64_process_list; |
146 | aarch64_process_list = proc; | |
147 | ||
148 | return proc; | |
149 | } | |
150 | ||
151 | /* Get data specific info for process PID, creating it if necessary. | |
152 | Never returns NULL. */ | |
153 | ||
154 | static struct aarch64_process_info * | |
155 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 156 | { |
d6c44983 YZ |
157 | struct aarch64_process_info *proc; |
158 | ||
159 | proc = aarch64_find_process_pid (pid); | |
160 | if (proc == NULL) | |
161 | proc = aarch64_add_process (pid); | |
9d19df75 | 162 | |
d6c44983 | 163 | return proc; |
9d19df75 MS |
164 | } |
165 | ||
d6c44983 YZ |
166 | /* Called whenever GDB is no longer debugging process PID. It deletes |
167 | data structures that keep track of debug register state. */ | |
9d19df75 | 168 | |
135340af PA |
169 | void |
170 | aarch64_linux_nat_target::low_forget_process (pid_t pid) | |
9d19df75 | 171 | { |
d6c44983 | 172 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 173 | |
d6c44983 YZ |
174 | proc = aarch64_process_list; |
175 | proc_link = &aarch64_process_list; | |
176 | ||
177 | while (proc != NULL) | |
9d19df75 | 178 | { |
d6c44983 YZ |
179 | if (proc->pid == pid) |
180 | { | |
181 | *proc_link = proc->next; | |
9d19df75 | 182 | |
d6c44983 YZ |
183 | xfree (proc); |
184 | return; | |
185 | } | |
186 | ||
187 | proc_link = &proc->next; | |
188 | proc = *proc_link; | |
189 | } | |
9d19df75 MS |
190 | } |
191 | ||
d6c44983 | 192 | /* Get debug registers state for process PID. */ |
9d19df75 | 193 | |
db3cb7cb | 194 | struct aarch64_debug_reg_state * |
d6c44983 | 195 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 196 | { |
d6c44983 | 197 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
198 | } |
199 | ||
9d19df75 MS |
200 | /* Fill GDB's register array with the general-purpose register values |
201 | from the current thread. */ | |
202 | ||
203 | static void | |
204 | fetch_gregs_from_thread (struct regcache *regcache) | |
205 | { | |
607685ec | 206 | int ret, tid; |
ac7936df | 207 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 MS |
208 | elf_gregset_t regs; |
209 | struct iovec iovec; | |
210 | ||
607685ec YQ |
211 | /* Make sure REGS can hold all registers contents on both aarch64 |
212 | and arm. */ | |
213 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
214 | ||
e38504b3 | 215 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
216 | |
217 | iovec.iov_base = ®s; | |
607685ec YQ |
218 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
219 | iovec.iov_len = 18 * 4; | |
220 | else | |
221 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
222 | |
223 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
224 | if (ret < 0) | |
225 | perror_with_name (_("Unable to fetch general registers.")); | |
226 | ||
607685ec YQ |
227 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
228 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); | |
229 | else | |
230 | { | |
231 | int regno; | |
232 | ||
233 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
73e1c03f | 234 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 235 | } |
9d19df75 MS |
236 | } |
237 | ||
238 | /* Store to the current thread the valid general-purpose register | |
239 | values in the GDB's register array. */ | |
240 | ||
241 | static void | |
242 | store_gregs_to_thread (const struct regcache *regcache) | |
243 | { | |
607685ec | 244 | int ret, tid; |
9d19df75 MS |
245 | elf_gregset_t regs; |
246 | struct iovec iovec; | |
ac7936df | 247 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 248 | |
607685ec YQ |
249 | /* Make sure REGS can hold all registers contents on both aarch64 |
250 | and arm. */ | |
251 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
e38504b3 | 252 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
253 | |
254 | iovec.iov_base = ®s; | |
607685ec YQ |
255 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
256 | iovec.iov_len = 18 * 4; | |
257 | else | |
258 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
259 | |
260 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
261 | if (ret < 0) | |
262 | perror_with_name (_("Unable to fetch general registers.")); | |
263 | ||
607685ec YQ |
264 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
265 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); | |
266 | else | |
267 | { | |
268 | int regno; | |
269 | ||
270 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
0ec9f114 | 271 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 | 272 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 273 | } |
9d19df75 MS |
274 | |
275 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
276 | if (ret < 0) | |
277 | perror_with_name (_("Unable to store general registers.")); | |
278 | } | |
279 | ||
280 | /* Fill GDB's register array with the fp/simd register values | |
281 | from the current thread. */ | |
282 | ||
283 | static void | |
284 | fetch_fpregs_from_thread (struct regcache *regcache) | |
285 | { | |
607685ec | 286 | int ret, tid; |
9d19df75 MS |
287 | elf_fpregset_t regs; |
288 | struct iovec iovec; | |
ac7936df | 289 | struct gdbarch *gdbarch = regcache->arch (); |
607685ec YQ |
290 | |
291 | /* Make sure REGS can hold all VFP registers contents on both aarch64 | |
292 | and arm. */ | |
293 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
9d19df75 | 294 | |
e38504b3 | 295 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
296 | |
297 | iovec.iov_base = ®s; | |
9d19df75 | 298 | |
607685ec YQ |
299 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
300 | { | |
301 | iovec.iov_len = VFP_REGS_SIZE; | |
302 | ||
303 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); | |
304 | if (ret < 0) | |
305 | perror_with_name (_("Unable to fetch VFP registers.")); | |
306 | ||
307 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); | |
308 | } | |
309 | else | |
310 | { | |
311 | int regno; | |
312 | ||
313 | iovec.iov_len = sizeof (regs); | |
9d19df75 | 314 | |
607685ec YQ |
315 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
316 | if (ret < 0) | |
317 | perror_with_name (_("Unable to fetch vFP/SIMD registers.")); | |
9d19df75 | 318 | |
607685ec | 319 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
73e1c03f | 320 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
607685ec | 321 | |
73e1c03f SM |
322 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
323 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); | |
607685ec | 324 | } |
9d19df75 MS |
325 | } |
326 | ||
327 | /* Store to the current thread the valid fp/simd register | |
328 | values in the GDB's register array. */ | |
329 | ||
330 | static void | |
331 | store_fpregs_to_thread (const struct regcache *regcache) | |
332 | { | |
607685ec | 333 | int ret, tid; |
9d19df75 MS |
334 | elf_fpregset_t regs; |
335 | struct iovec iovec; | |
ac7936df | 336 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 337 | |
607685ec YQ |
338 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
339 | and arm. */ | |
340 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
e38504b3 | 341 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
342 | |
343 | iovec.iov_base = ®s; | |
9d19df75 | 344 | |
607685ec YQ |
345 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
346 | { | |
347 | iovec.iov_len = VFP_REGS_SIZE; | |
9d19df75 | 348 | |
607685ec YQ |
349 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
350 | if (ret < 0) | |
351 | perror_with_name (_("Unable to fetch VFP registers.")); | |
9d19df75 | 352 | |
607685ec YQ |
353 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
354 | } | |
355 | else | |
356 | { | |
357 | int regno; | |
9d19df75 | 358 | |
607685ec YQ |
359 | iovec.iov_len = sizeof (regs); |
360 | ||
361 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
362 | if (ret < 0) | |
363 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
364 | ||
365 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
0ec9f114 | 366 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 SM |
367 | regcache->raw_collect |
368 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
607685ec | 369 | |
0ec9f114 | 370 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
34a79281 | 371 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
0ec9f114 | 372 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
34a79281 | 373 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
607685ec YQ |
374 | } |
375 | ||
376 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
377 | { | |
378 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); | |
379 | if (ret < 0) | |
380 | perror_with_name (_("Unable to store VFP registers.")); | |
381 | } | |
382 | else | |
383 | { | |
384 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
385 | if (ret < 0) | |
386 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
387 | } | |
9d19df75 MS |
388 | } |
389 | ||
e9902bfc AH |
390 | /* Fill GDB's register array with the sve register values |
391 | from the current thread. */ | |
392 | ||
393 | static void | |
394 | fetch_sveregs_from_thread (struct regcache *regcache) | |
395 | { | |
396 | std::unique_ptr<gdb_byte[]> base | |
e38504b3 | 397 | = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); |
e9902bfc AH |
398 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); |
399 | } | |
400 | ||
401 | /* Store to the current thread the valid sve register | |
402 | values in the GDB's register array. */ | |
403 | ||
404 | static void | |
405 | store_sveregs_to_thread (struct regcache *regcache) | |
406 | { | |
407 | int ret; | |
408 | struct iovec iovec; | |
e38504b3 | 409 | int tid = regcache->ptid ().lwp (); |
e9902bfc AH |
410 | |
411 | /* Obtain a dump of SVE registers from ptrace. */ | |
412 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); | |
413 | ||
414 | /* Overwrite with regcache state. */ | |
415 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); | |
416 | ||
417 | /* Write back to the kernel. */ | |
418 | iovec.iov_base = base.get (); | |
419 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; | |
420 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); | |
421 | ||
422 | if (ret < 0) | |
423 | perror_with_name (_("Unable to store sve registers")); | |
424 | } | |
425 | ||
f6ac5f3d | 426 | /* Implement the "fetch_registers" target_ops method. */ |
9d19df75 | 427 | |
f6ac5f3d PA |
428 | void |
429 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, | |
430 | int regno) | |
9d19df75 | 431 | { |
e9902bfc AH |
432 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
433 | ||
9d19df75 MS |
434 | if (regno == -1) |
435 | { | |
436 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
437 | if (tdep->has_sve ()) |
438 | fetch_sveregs_from_thread (regcache); | |
439 | else | |
440 | fetch_fpregs_from_thread (regcache); | |
9d19df75 MS |
441 | } |
442 | else if (regno < AARCH64_V0_REGNUM) | |
443 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
444 | else if (tdep->has_sve ()) |
445 | fetch_sveregs_from_thread (regcache); | |
9d19df75 MS |
446 | else |
447 | fetch_fpregs_from_thread (regcache); | |
448 | } | |
449 | ||
f6ac5f3d | 450 | /* Implement the "store_registers" target_ops method. */ |
9d19df75 | 451 | |
f6ac5f3d PA |
452 | void |
453 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, | |
454 | int regno) | |
9d19df75 | 455 | { |
e9902bfc AH |
456 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
457 | ||
9d19df75 MS |
458 | if (regno == -1) |
459 | { | |
460 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
461 | if (tdep->has_sve ()) |
462 | store_sveregs_to_thread (regcache); | |
463 | else | |
464 | store_fpregs_to_thread (regcache); | |
9d19df75 MS |
465 | } |
466 | else if (regno < AARCH64_V0_REGNUM) | |
467 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
468 | else if (tdep->has_sve ()) |
469 | store_sveregs_to_thread (regcache); | |
9d19df75 MS |
470 | else |
471 | store_fpregs_to_thread (regcache); | |
472 | } | |
473 | ||
474 | /* Fill register REGNO (if it is a general-purpose register) in | |
475 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
476 | do this for all registers. */ | |
477 | ||
478 | void | |
479 | fill_gregset (const struct regcache *regcache, | |
480 | gdb_gregset_t *gregsetp, int regno) | |
481 | { | |
d4d793bf AA |
482 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
483 | regno, (gdb_byte *) gregsetp, | |
484 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
485 | } |
486 | ||
487 | /* Fill GDB's register array with the general-purpose register values | |
488 | in *GREGSETP. */ | |
489 | ||
490 | void | |
491 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
492 | { | |
d4d793bf AA |
493 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
494 | (const gdb_byte *) gregsetp, | |
495 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
496 | } |
497 | ||
498 | /* Fill register REGNO (if it is a floating-point register) in | |
499 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
500 | do this for all registers. */ | |
501 | ||
502 | void | |
503 | fill_fpregset (const struct regcache *regcache, | |
504 | gdb_fpregset_t *fpregsetp, int regno) | |
505 | { | |
d4d793bf AA |
506 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
507 | regno, (gdb_byte *) fpregsetp, | |
508 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
509 | } |
510 | ||
511 | /* Fill GDB's register array with the floating-point register values | |
512 | in *FPREGSETP. */ | |
513 | ||
514 | void | |
515 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
516 | { | |
d4d793bf AA |
517 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
518 | (const gdb_byte *) fpregsetp, | |
519 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
520 | } |
521 | ||
d6c44983 YZ |
522 | /* linux_nat_new_fork hook. */ |
523 | ||
135340af PA |
524 | void |
525 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
526 | pid_t child_pid) | |
d6c44983 YZ |
527 | { |
528 | pid_t parent_pid; | |
529 | struct aarch64_debug_reg_state *parent_state; | |
530 | struct aarch64_debug_reg_state *child_state; | |
531 | ||
532 | /* NULL means no watchpoint has ever been set in the parent. In | |
533 | that case, there's nothing to do. */ | |
534 | if (parent->arch_private == NULL) | |
535 | return; | |
536 | ||
537 | /* GDB core assumes the child inherits the watchpoints/hw | |
538 | breakpoints of the parent, and will remove them all from the | |
539 | forked off process. Copy the debug registers mirrors into the | |
540 | new process so that all breakpoints and watchpoints can be | |
541 | removed together. */ | |
542 | ||
e99b03dc | 543 | parent_pid = parent->ptid.pid (); |
d6c44983 YZ |
544 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
545 | child_state = aarch64_get_debug_reg_state (child_pid); | |
546 | *child_state = *parent_state; | |
547 | } | |
9d19df75 MS |
548 | \f |
549 | ||
550 | /* Called by libthread_db. Returns a pointer to the thread local | |
551 | storage (or its descriptor). */ | |
552 | ||
553 | ps_err_e | |
754653a7 | 554 | ps_get_thread_area (struct ps_prochandle *ph, |
9d19df75 MS |
555 | lwpid_t lwpid, int idx, void **base) |
556 | { | |
a0cc84cd YQ |
557 | int is_64bit_p |
558 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); | |
9d19df75 | 559 | |
a0cc84cd | 560 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
9d19df75 MS |
561 | } |
562 | \f | |
563 | ||
f6ac5f3d | 564 | /* Implement the "post_startup_inferior" target_ops method. */ |
9d19df75 | 565 | |
f6ac5f3d PA |
566 | void |
567 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) | |
9d19df75 | 568 | { |
e99b03dc TT |
569 | low_forget_process (ptid.pid ()); |
570 | aarch64_linux_get_debug_reg_capacity (ptid.pid ()); | |
f6ac5f3d | 571 | linux_nat_target::post_startup_inferior (ptid); |
9d19df75 MS |
572 | } |
573 | ||
8363f9d5 RB |
574 | /* Implement the "post_attach" target_ops method. */ |
575 | ||
576 | void | |
577 | aarch64_linux_nat_target::post_attach (int pid) | |
578 | { | |
579 | low_forget_process (pid); | |
580 | /* Set the hardware debug register capacity. If | |
581 | aarch64_linux_get_debug_reg_capacity is not called | |
582 | (as it is in aarch64_linux_child_post_startup_inferior) then | |
583 | software watchpoints will be used instead of hardware | |
584 | watchpoints when attaching to a target. */ | |
585 | aarch64_linux_get_debug_reg_capacity (pid); | |
586 | linux_nat_target::post_attach (pid); | |
587 | } | |
588 | ||
607685ec YQ |
589 | extern struct target_desc *tdesc_arm_with_neon; |
590 | ||
f6ac5f3d | 591 | /* Implement the "read_description" target_ops method. */ |
9d19df75 | 592 | |
f6ac5f3d PA |
593 | const struct target_desc * |
594 | aarch64_linux_nat_target::read_description () | |
9d19df75 | 595 | { |
6f67973b YQ |
596 | int ret, tid; |
597 | gdb_byte regbuf[VFP_REGS_SIZE]; | |
598 | struct iovec iovec; | |
607685ec | 599 | |
e38504b3 | 600 | tid = inferior_ptid.lwp (); |
607685ec | 601 | |
6f67973b YQ |
602 | iovec.iov_base = regbuf; |
603 | iovec.iov_len = VFP_REGS_SIZE; | |
607685ec | 604 | |
6f67973b YQ |
605 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
606 | if (ret == 0) | |
607 | return tdesc_arm_with_neon; | |
608 | else | |
ba2d2bb2 | 609 | return aarch64_read_description (aarch64_sve_get_vq (tid)); |
9d19df75 MS |
610 | } |
611 | ||
ade90bde YQ |
612 | /* Convert a native/host siginfo object, into/from the siginfo in the |
613 | layout of the inferiors' architecture. Returns true if any | |
614 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
615 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
616 | INF. */ | |
617 | ||
135340af PA |
618 | bool |
619 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, | |
620 | int direction) | |
ade90bde YQ |
621 | { |
622 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); | |
623 | ||
624 | /* Is the inferior 32-bit? If so, then do fixup the siginfo | |
625 | object. */ | |
626 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
627 | { | |
628 | if (direction == 0) | |
629 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, | |
630 | native); | |
631 | else | |
632 | aarch64_siginfo_from_compat_siginfo (native, | |
633 | (struct compat_siginfo *) inf); | |
634 | ||
135340af | 635 | return true; |
ade90bde YQ |
636 | } |
637 | ||
135340af | 638 | return false; |
ade90bde YQ |
639 | } |
640 | ||
9d19df75 MS |
641 | /* Returns the number of hardware watchpoints of type TYPE that we can |
642 | set. Value is positive if we can set CNT watchpoints, zero if | |
643 | setting watchpoints of type TYPE is not supported, and negative if | |
644 | CNT is more than the maximum number of watchpoints of type TYPE | |
645 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
646 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
647 | CNT is the number of such watchpoints used so far (including this | |
648 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
c2fbdc59 | 649 | currently enabled. */ |
9d19df75 | 650 | |
f6ac5f3d PA |
651 | int |
652 | aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
653 | int cnt, int othertype) | |
9d19df75 | 654 | { |
c2fbdc59 YQ |
655 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
656 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
657 | { | |
658 | if (aarch64_num_wp_regs == 0) | |
659 | return 0; | |
660 | } | |
661 | else if (type == bp_hardware_breakpoint) | |
662 | { | |
663 | if (aarch64_num_bp_regs == 0) | |
664 | return 0; | |
665 | } | |
666 | else | |
667 | gdb_assert_not_reached ("unexpected breakpoint type"); | |
668 | ||
669 | /* We always return 1 here because we don't have enough information | |
670 | about possible overlap of addresses that they want to watch. As an | |
671 | extreme example, consider the case where all the watchpoints watch | |
672 | the same address and the same region length: then we can handle a | |
673 | virtually unlimited number of watchpoints, due to debug register | |
674 | sharing implemented via reference counts. */ | |
9d19df75 MS |
675 | return 1; |
676 | } | |
677 | ||
0d5ed153 | 678 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
9d19df75 MS |
679 | Return 0 on success, -1 on failure. */ |
680 | ||
f6ac5f3d PA |
681 | int |
682 | aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
683 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
684 | { |
685 | int ret; | |
0d5ed153 | 686 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
8d689ee5 | 687 | int len; |
2ecd81c2 | 688 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 689 | struct aarch64_debug_reg_state *state |
e99b03dc | 690 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 691 | |
8d689ee5 YQ |
692 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
693 | ||
c5e92cca | 694 | if (show_debug_regs) |
9d19df75 MS |
695 | fprintf_unfiltered |
696 | (gdb_stdlog, | |
697 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
698 | (unsigned long) addr, len); | |
699 | ||
c67ca4de | 700 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 701 | |
c5e92cca | 702 | if (show_debug_regs) |
d6c44983 | 703 | { |
d6c44983 | 704 | aarch64_show_debug_reg_state (state, |
2fd0f80d | 705 | "insert_hw_breakpoint", addr, len, type); |
d6c44983 | 706 | } |
9d19df75 MS |
707 | |
708 | return ret; | |
709 | } | |
710 | ||
711 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
712 | Return 0 on success, -1 on failure. */ | |
713 | ||
f6ac5f3d PA |
714 | int |
715 | aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
716 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
717 | { |
718 | int ret; | |
719 | CORE_ADDR addr = bp_tgt->placed_address; | |
8d689ee5 | 720 | int len = 4; |
2ecd81c2 | 721 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 722 | struct aarch64_debug_reg_state *state |
e99b03dc | 723 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 724 | |
8d689ee5 YQ |
725 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
726 | ||
c5e92cca | 727 | if (show_debug_regs) |
9d19df75 MS |
728 | fprintf_unfiltered |
729 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
730 | (unsigned long) addr, len); | |
731 | ||
c67ca4de | 732 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 733 | |
c5e92cca | 734 | if (show_debug_regs) |
d6c44983 | 735 | { |
d6c44983 YZ |
736 | aarch64_show_debug_reg_state (state, |
737 | "remove_hw_watchpoint", addr, len, type); | |
738 | } | |
9d19df75 MS |
739 | |
740 | return ret; | |
741 | } | |
742 | ||
f6ac5f3d | 743 | /* Implement the "insert_watchpoint" target_ops method. |
9d19df75 MS |
744 | |
745 | Insert a watchpoint to watch a memory region which starts at | |
746 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
747 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
748 | ||
f6ac5f3d PA |
749 | int |
750 | aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
751 | enum target_hw_bp_type type, | |
752 | struct expression *cond) | |
9d19df75 MS |
753 | { |
754 | int ret; | |
c67ca4de | 755 | struct aarch64_debug_reg_state *state |
e99b03dc | 756 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 757 | |
c5e92cca | 758 | if (show_debug_regs) |
9d19df75 MS |
759 | fprintf_unfiltered (gdb_stdlog, |
760 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
761 | (unsigned long) addr, len); | |
762 | ||
763 | gdb_assert (type != hw_execute); | |
764 | ||
c67ca4de | 765 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 766 | |
c5e92cca | 767 | if (show_debug_regs) |
d6c44983 | 768 | { |
d6c44983 YZ |
769 | aarch64_show_debug_reg_state (state, |
770 | "insert_watchpoint", addr, len, type); | |
771 | } | |
9d19df75 MS |
772 | |
773 | return ret; | |
774 | } | |
775 | ||
f6ac5f3d | 776 | /* Implement the "remove_watchpoint" target_ops method. |
9d19df75 MS |
777 | Remove a watchpoint that watched the memory region which starts at |
778 | address ADDR, whose length is LEN bytes, and for accesses of the | |
779 | type TYPE. Return 0 on success, -1 on failure. */ | |
780 | ||
f6ac5f3d PA |
781 | int |
782 | aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
783 | enum target_hw_bp_type type, | |
784 | struct expression *cond) | |
9d19df75 MS |
785 | { |
786 | int ret; | |
c67ca4de | 787 | struct aarch64_debug_reg_state *state |
e99b03dc | 788 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 789 | |
c5e92cca | 790 | if (show_debug_regs) |
9d19df75 MS |
791 | fprintf_unfiltered (gdb_stdlog, |
792 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
793 | (unsigned long) addr, len); | |
794 | ||
795 | gdb_assert (type != hw_execute); | |
796 | ||
c67ca4de | 797 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 798 | |
c5e92cca | 799 | if (show_debug_regs) |
d6c44983 | 800 | { |
d6c44983 YZ |
801 | aarch64_show_debug_reg_state (state, |
802 | "remove_watchpoint", addr, len, type); | |
803 | } | |
9d19df75 MS |
804 | |
805 | return ret; | |
806 | } | |
807 | ||
f6ac5f3d | 808 | /* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ |
9d19df75 | 809 | |
f6ac5f3d PA |
810 | int |
811 | aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
9d19df75 | 812 | { |
39edd165 | 813 | return aarch64_linux_region_ok_for_watchpoint (addr, len); |
9d19df75 MS |
814 | } |
815 | ||
f6ac5f3d | 816 | /* Implement the "stopped_data_address" target_ops method. */ |
9d19df75 | 817 | |
57810aa7 | 818 | bool |
f6ac5f3d | 819 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
9d19df75 MS |
820 | { |
821 | siginfo_t siginfo; | |
cf4088a9 | 822 | int i; |
9d19df75 MS |
823 | struct aarch64_debug_reg_state *state; |
824 | ||
825 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 826 | return false; |
9d19df75 MS |
827 | |
828 | /* This must be a hardware breakpoint. */ | |
829 | if (siginfo.si_signo != SIGTRAP | |
830 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
57810aa7 | 831 | return false; |
9d19df75 MS |
832 | |
833 | /* Check if the address matches any watched address. */ | |
e99b03dc | 834 | state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 MS |
835 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
836 | { | |
a3b60e45 JK |
837 | const unsigned int offset |
838 | = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); | |
9d19df75 MS |
839 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
840 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
a3b60e45 JK |
841 | const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; |
842 | const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); | |
843 | const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; | |
9d19df75 MS |
844 | |
845 | if (state->dr_ref_count_wp[i] | |
846 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
a3b60e45 | 847 | && addr_trap >= addr_watch_aligned |
9d19df75 MS |
848 | && addr_trap < addr_watch + len) |
849 | { | |
a3b60e45 JK |
850 | /* ADDR_TRAP reports the first address of the memory range |
851 | accessed by the CPU, regardless of what was the memory | |
852 | range watched. Thus, a large CPU access that straddles | |
853 | the ADDR_WATCH..ADDR_WATCH+LEN range may result in an | |
854 | ADDR_TRAP that is lower than the | |
855 | ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: | |
856 | ||
857 | addr: | 4 | 5 | 6 | 7 | 8 | | |
858 | |---- range watched ----| | |
859 | |----------- range accessed ------------| | |
860 | ||
861 | In this case, ADDR_TRAP will be 4. | |
862 | ||
863 | To match a watchpoint known to GDB core, we must never | |
864 | report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN | |
865 | range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false | |
866 | positive on kernels older than 4.10. See PR | |
867 | external/20207. */ | |
868 | *addr_p = addr_orig; | |
57810aa7 | 869 | return true; |
9d19df75 MS |
870 | } |
871 | } | |
872 | ||
57810aa7 | 873 | return false; |
9d19df75 MS |
874 | } |
875 | ||
f6ac5f3d | 876 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
9d19df75 | 877 | |
57810aa7 | 878 | bool |
f6ac5f3d | 879 | aarch64_linux_nat_target::stopped_by_watchpoint () |
9d19df75 MS |
880 | { |
881 | CORE_ADDR addr; | |
882 | ||
f6ac5f3d | 883 | return stopped_data_address (&addr); |
9d19df75 MS |
884 | } |
885 | ||
f6ac5f3d | 886 | /* Implement the "watchpoint_addr_within_range" target_ops method. */ |
9d19df75 | 887 | |
57810aa7 | 888 | bool |
f6ac5f3d PA |
889 | aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
890 | CORE_ADDR start, int length) | |
9d19df75 MS |
891 | { |
892 | return start <= addr && start + length - 1 >= addr; | |
893 | } | |
894 | ||
f6ac5f3d | 895 | /* Implement the "can_do_single_step" target_ops method. */ |
750ce8d1 | 896 | |
f6ac5f3d PA |
897 | int |
898 | aarch64_linux_nat_target::can_do_single_step () | |
750ce8d1 YQ |
899 | { |
900 | return 1; | |
901 | } | |
902 | ||
9d19df75 MS |
903 | /* Define AArch64 maintenance commands. */ |
904 | ||
905 | static void | |
906 | add_show_debug_regs_command (void) | |
907 | { | |
908 | /* A maintenance command to enable printing the internal DRi mirror | |
909 | variables. */ | |
910 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
c5e92cca | 911 | &show_debug_regs, _("\ |
9d19df75 MS |
912 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
913 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
914 | Use \"on\" to enable, \"off\" to disable.\n\ | |
915 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
916 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
917 | triggers a breakpoint or watchpoint."), | |
918 | NULL, | |
919 | NULL, | |
920 | &maintenance_set_cmdlist, | |
921 | &maintenance_show_cmdlist); | |
922 | } | |
923 | ||
9d19df75 MS |
924 | void |
925 | _initialize_aarch64_linux_nat (void) | |
926 | { | |
9d19df75 MS |
927 | add_show_debug_regs_command (); |
928 | ||
9d19df75 | 929 | /* Register the target. */ |
f6ac5f3d | 930 | linux_target = &the_aarch64_linux_nat_target; |
d9f719f1 | 931 | add_inf_child_target (&the_aarch64_linux_nat_target); |
9d19df75 | 932 | } |