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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
3 | Copyright (C) 2011-2013 Free Software Foundation, Inc. | |
4 | Contributed by ARM Ltd. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
32 | #include "elf/common.h" | |
33 | ||
34 | #include <sys/ptrace.h> | |
35 | #include <sys/utsname.h> | |
36 | ||
37 | #include "gregset.h" | |
38 | ||
39 | #include "features/aarch64.c" | |
40 | ||
41 | /* Defines ps_err_e, struct ps_prochandle. */ | |
42 | #include "gdb_proc_service.h" | |
43 | ||
44 | #ifndef TRAP_HWBKPT | |
45 | #define TRAP_HWBKPT 0x0004 | |
46 | #endif | |
47 | ||
48 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which | |
49 | case we may be tracing more than one process at a time. In that | |
50 | case, inferior_ptid will contain the main process ID and the | |
51 | individual thread (process) ID. get_thread_id () is used to get | |
52 | the thread id if it's available, and the process id otherwise. */ | |
53 | ||
54 | static int | |
55 | get_thread_id (ptid_t ptid) | |
56 | { | |
57 | int tid = TIDGET (ptid); | |
58 | ||
59 | if (0 == tid) | |
60 | tid = PIDGET (ptid); | |
61 | return tid; | |
62 | } | |
63 | ||
64 | /* Macro definitions, data structures, and code for the hardware | |
65 | breakpoint and hardware watchpoint support follow. We use the | |
66 | following abbreviations throughout the code: | |
67 | ||
68 | hw - hardware | |
69 | bp - breakpoint | |
70 | wp - watchpoint */ | |
71 | ||
72 | /* Maximum number of hardware breakpoint and watchpoint registers. | |
73 | Neither of these values may exceed the width of dr_changed_t | |
74 | measured in bits. */ | |
75 | ||
76 | #define AARCH64_HBP_MAX_NUM 16 | |
77 | #define AARCH64_HWP_MAX_NUM 16 | |
78 | ||
79 | /* Alignment requirement in bytes for addresses written to | |
80 | hardware breakpoint and watchpoint value registers. | |
81 | ||
82 | A ptrace call attempting to set an address that does not meet the | |
83 | alignment criteria will fail. Limited support has been provided in | |
84 | this port for unaligned watchpoints, such that from a GDB user | |
85 | perspective, an unaligned watchpoint may be requested. | |
86 | ||
87 | This is achieved by minimally enlarging the watched area to meet the | |
88 | alignment requirement, and if necessary, splitting the watchpoint | |
89 | over several hardware watchpoint registers. */ | |
90 | ||
91 | #define AARCH64_HBP_ALIGNMENT 4 | |
92 | #define AARCH64_HWP_ALIGNMENT 8 | |
93 | ||
94 | /* The maximum length of a memory region that can be watched by one | |
95 | hardware watchpoint register. */ | |
96 | ||
97 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 | |
98 | ||
99 | /* ptrace hardware breakpoint resource info is formatted as follows: | |
100 | ||
101 | 31 24 16 8 0 | |
102 | +---------------+--------------+---------------+---------------+ | |
103 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | | |
104 | +---------------+--------------+---------------+---------------+ */ | |
105 | ||
106 | ||
107 | /* Macros to extract fields from the hardware debug information word. */ | |
108 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) | |
109 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) | |
110 | ||
111 | /* Macro for the expected version of the ARMv8-A debug architecture. */ | |
112 | #define AARCH64_DEBUG_ARCH_V8 0x6 | |
113 | ||
114 | /* Number of hardware breakpoints/watchpoints the target supports. | |
115 | They are initialized with values obtained via the ptrace calls | |
116 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ | |
117 | ||
118 | static int aarch64_num_bp_regs; | |
119 | static int aarch64_num_wp_regs; | |
120 | ||
121 | /* Debugging of hardware breakpoint/watchpoint support. */ | |
122 | ||
123 | static int debug_hw_points; | |
124 | ||
125 | /* Each bit of a variable of this type is used to indicate whether a | |
126 | hardware breakpoint or watchpoint setting has been changed since | |
127 | the last update. | |
128 | ||
129 | Bit N corresponds to the Nth hardware breakpoint or watchpoint | |
130 | setting which is managed in aarch64_debug_reg_state, where N is | |
131 | valid between 0 and the total number of the hardware breakpoint or | |
132 | watchpoint debug registers minus 1. | |
133 | ||
134 | When bit N is 1, the corresponding breakpoint or watchpoint setting | |
135 | has changed, and therefore the corresponding hardware debug | |
136 | register needs to be updated via the ptrace interface. | |
137 | ||
138 | In the per-thread arch-specific data area, we define two such | |
139 | variables for per-thread hardware breakpoint and watchpoint | |
140 | settings respectively. | |
141 | ||
142 | This type is part of the mechanism which helps reduce the number of | |
143 | ptrace calls to the kernel, i.e. avoid asking the kernel to write | |
144 | to the debug registers with unchanged values. */ | |
145 | ||
6eb04473 | 146 | typedef unsigned LONGEST dr_changed_t; |
9d19df75 MS |
147 | |
148 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ | |
149 | ||
150 | #define DR_MARK_ALL_CHANGED(x, m) \ | |
151 | do \ | |
152 | { \ | |
153 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ | |
154 | (x) = (((dr_changed_t)1 << (m)) - 1); \ | |
155 | } while (0) | |
156 | ||
157 | #define DR_MARK_N_CHANGED(x, n) \ | |
158 | do \ | |
159 | { \ | |
160 | (x) |= ((dr_changed_t)1 << (n)); \ | |
161 | } while (0) | |
162 | ||
163 | #define DR_CLEAR_CHANGED(x) \ | |
164 | do \ | |
165 | { \ | |
166 | (x) = 0; \ | |
167 | } while (0) | |
168 | ||
169 | #define DR_HAS_CHANGED(x) ((x) != 0) | |
170 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) | |
171 | ||
172 | /* Structure for managing the hardware breakpoint/watchpoint resources. | |
173 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register | |
174 | content, and DR_REF_COUNT_* counts the numbers of references to the | |
175 | corresponding bp/wp, by which way the limited hardware resources | |
176 | are not wasted on duplicated bp/wp settings (though so far gdb has | |
177 | done a good job by not sending duplicated bp/wp requests). */ | |
178 | ||
179 | struct aarch64_debug_reg_state | |
180 | { | |
181 | /* hardware breakpoint */ | |
182 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; | |
183 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; | |
184 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; | |
185 | ||
186 | /* hardware watchpoint */ | |
187 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; | |
188 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; | |
189 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; | |
190 | }; | |
191 | ||
d6c44983 YZ |
192 | /* Per-process data. We don't bind this to a per-inferior registry |
193 | because of targets like x86 GNU/Linux that need to keep track of | |
194 | processes that aren't bound to any inferior (e.g., fork children, | |
195 | checkpoints). */ | |
9d19df75 | 196 | |
d6c44983 | 197 | struct aarch64_process_info |
9d19df75 | 198 | { |
d6c44983 YZ |
199 | /* Linked list. */ |
200 | struct aarch64_process_info *next; | |
9d19df75 | 201 | |
d6c44983 YZ |
202 | /* The process identifier. */ |
203 | pid_t pid; | |
9d19df75 | 204 | |
d6c44983 YZ |
205 | /* Copy of aarch64 hardware debug registers. */ |
206 | struct aarch64_debug_reg_state state; | |
207 | }; | |
208 | ||
209 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
210 | ||
211 | /* Find process data for process PID. */ | |
212 | ||
213 | static struct aarch64_process_info * | |
214 | aarch64_find_process_pid (pid_t pid) | |
215 | { | |
216 | struct aarch64_process_info *proc; | |
217 | ||
218 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
219 | if (proc->pid == pid) | |
220 | return proc; | |
221 | ||
222 | return NULL; | |
9d19df75 MS |
223 | } |
224 | ||
d6c44983 YZ |
225 | /* Add process data for process PID. Returns newly allocated info |
226 | object. */ | |
9d19df75 | 227 | |
d6c44983 YZ |
228 | static struct aarch64_process_info * |
229 | aarch64_add_process (pid_t pid) | |
9d19df75 | 230 | { |
d6c44983 | 231 | struct aarch64_process_info *proc; |
9d19df75 | 232 | |
d6c44983 YZ |
233 | proc = xcalloc (1, sizeof (*proc)); |
234 | proc->pid = pid; | |
9d19df75 | 235 | |
d6c44983 YZ |
236 | proc->next = aarch64_process_list; |
237 | aarch64_process_list = proc; | |
238 | ||
239 | return proc; | |
240 | } | |
241 | ||
242 | /* Get data specific info for process PID, creating it if necessary. | |
243 | Never returns NULL. */ | |
244 | ||
245 | static struct aarch64_process_info * | |
246 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 247 | { |
d6c44983 YZ |
248 | struct aarch64_process_info *proc; |
249 | ||
250 | proc = aarch64_find_process_pid (pid); | |
251 | if (proc == NULL) | |
252 | proc = aarch64_add_process (pid); | |
9d19df75 | 253 | |
d6c44983 | 254 | return proc; |
9d19df75 MS |
255 | } |
256 | ||
d6c44983 YZ |
257 | /* Called whenever GDB is no longer debugging process PID. It deletes |
258 | data structures that keep track of debug register state. */ | |
9d19df75 | 259 | |
d6c44983 YZ |
260 | static void |
261 | aarch64_forget_process (pid_t pid) | |
9d19df75 | 262 | { |
d6c44983 | 263 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 264 | |
d6c44983 YZ |
265 | proc = aarch64_process_list; |
266 | proc_link = &aarch64_process_list; | |
267 | ||
268 | while (proc != NULL) | |
9d19df75 | 269 | { |
d6c44983 YZ |
270 | if (proc->pid == pid) |
271 | { | |
272 | *proc_link = proc->next; | |
9d19df75 | 273 | |
d6c44983 YZ |
274 | xfree (proc); |
275 | return; | |
276 | } | |
277 | ||
278 | proc_link = &proc->next; | |
279 | proc = *proc_link; | |
280 | } | |
9d19df75 MS |
281 | } |
282 | ||
d6c44983 | 283 | /* Get debug registers state for process PID. */ |
9d19df75 MS |
284 | |
285 | static struct aarch64_debug_reg_state * | |
d6c44983 | 286 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 287 | { |
d6c44983 | 288 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
289 | } |
290 | ||
291 | /* Per-thread arch-specific data we want to keep. */ | |
292 | ||
293 | struct arch_lwp_info | |
294 | { | |
295 | /* When bit N is 1, it indicates the Nth hardware breakpoint or | |
296 | watchpoint register pair needs to be updated when the thread is | |
297 | resumed; see aarch64_linux_prepare_to_resume. */ | |
298 | dr_changed_t dr_changed_bp; | |
299 | dr_changed_t dr_changed_wp; | |
300 | }; | |
301 | ||
302 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint | |
303 | registers with data from *STATE. */ | |
304 | ||
305 | static void | |
306 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, | |
307 | int tid, int watchpoint) | |
308 | { | |
309 | int i, count; | |
310 | struct iovec iov; | |
311 | struct user_hwdebug_state regs; | |
312 | const CORE_ADDR *addr; | |
313 | const unsigned int *ctrl; | |
314 | ||
315 | iov.iov_base = ®s; | |
316 | iov.iov_len = sizeof (regs); | |
317 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; | |
318 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; | |
319 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; | |
320 | ||
321 | for (i = 0; i < count; i++) | |
322 | { | |
323 | regs.dbg_regs[i].addr = addr[i]; | |
324 | regs.dbg_regs[i].ctrl = ctrl[i]; | |
325 | } | |
326 | ||
327 | if (ptrace (PTRACE_SETREGSET, tid, | |
328 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, | |
329 | (void *) &iov)) | |
330 | error (_("Unexpected error setting hardware debug registers")); | |
331 | } | |
332 | ||
333 | struct aarch64_dr_update_callback_param | |
334 | { | |
335 | int is_watchpoint; | |
336 | unsigned int idx; | |
337 | }; | |
338 | ||
d6c44983 | 339 | /* Callback for iterate_over_lwps. Records the |
9d19df75 MS |
340 | information about the change of one hardware breakpoint/watchpoint |
341 | setting for the thread LWP. | |
342 | The information is passed in via PTR. | |
343 | N.B. The actual updating of hardware debug registers is not | |
344 | carried out until the moment the thread is resumed. */ | |
345 | ||
346 | static int | |
347 | debug_reg_change_callback (struct lwp_info *lwp, void *ptr) | |
348 | { | |
349 | struct aarch64_dr_update_callback_param *param_p | |
350 | = (struct aarch64_dr_update_callback_param *) ptr; | |
351 | int pid = get_thread_id (lwp->ptid); | |
352 | int idx = param_p->idx; | |
353 | int is_watchpoint = param_p->is_watchpoint; | |
354 | struct arch_lwp_info *info = lwp->arch_private; | |
355 | dr_changed_t *dr_changed_ptr; | |
356 | dr_changed_t dr_changed; | |
357 | ||
358 | if (info == NULL) | |
359 | info = lwp->arch_private = XCNEW (struct arch_lwp_info); | |
360 | ||
361 | if (debug_hw_points) | |
362 | { | |
363 | fprintf_unfiltered (gdb_stdlog, | |
364 | "debug_reg_change_callback: \n\tOn entry:\n"); | |
365 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
366 | "\tpid%d, dr_changed_bp=0x%s, " |
367 | "dr_changed_wp=0x%s\n", | |
368 | pid, phex (info->dr_changed_bp, 8), | |
369 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
370 | } |
371 | ||
372 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp | |
373 | : &info->dr_changed_bp; | |
374 | dr_changed = *dr_changed_ptr; | |
375 | ||
376 | gdb_assert (idx >= 0 | |
377 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs | |
378 | : aarch64_num_bp_regs))); | |
379 | ||
380 | /* The actual update is done later just before resuming the lwp, | |
381 | we just mark that one register pair needs updating. */ | |
382 | DR_MARK_N_CHANGED (dr_changed, idx); | |
383 | *dr_changed_ptr = dr_changed; | |
384 | ||
385 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
386 | we can update its debug registers. */ | |
387 | if (!lwp->stopped) | |
388 | linux_stop_lwp (lwp); | |
389 | ||
390 | if (debug_hw_points) | |
391 | { | |
392 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
393 | "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, " |
394 | "dr_changed_wp=0x%s\n", | |
395 | pid, phex (info->dr_changed_bp, 8), | |
396 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
397 | } |
398 | ||
399 | /* Continue the iteration. */ | |
400 | return 0; | |
401 | } | |
402 | ||
403 | /* Notify each thread that their IDXth breakpoint/watchpoint register | |
404 | pair needs to be updated. The message will be recorded in each | |
405 | thread's arch-specific data area, the actual updating will be done | |
406 | when the thread is resumed. */ | |
407 | ||
408 | static void | |
409 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, | |
410 | int is_watchpoint, unsigned int idx) | |
411 | { | |
412 | struct aarch64_dr_update_callback_param param; | |
d6c44983 | 413 | ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
414 | |
415 | param.is_watchpoint = is_watchpoint; | |
416 | param.idx = idx; | |
417 | ||
d6c44983 | 418 | iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m); |
9d19df75 MS |
419 | } |
420 | ||
421 | /* Print the values of the cached breakpoint/watchpoint registers. */ | |
422 | ||
423 | static void | |
424 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, | |
425 | const char *func, CORE_ADDR addr, | |
426 | int len, int type) | |
427 | { | |
428 | int i; | |
429 | ||
430 | fprintf_unfiltered (gdb_stdlog, "%s", func); | |
431 | if (addr || len) | |
432 | fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)", | |
433 | (unsigned long) addr, len, | |
434 | type == hw_write ? "hw-write-watchpoint" | |
435 | : (type == hw_read ? "hw-read-watchpoint" | |
436 | : (type == hw_access ? "hw-access-watchpoint" | |
437 | : (type == hw_execute ? "hw-breakpoint" | |
438 | : "??unknown??")))); | |
439 | fprintf_unfiltered (gdb_stdlog, ":\n"); | |
440 | ||
441 | fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n"); | |
442 | for (i = 0; i < aarch64_num_bp_regs; i++) | |
443 | fprintf_unfiltered (gdb_stdlog, | |
444 | "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
445 | i, state->dr_addr_bp[i], | |
446 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); | |
447 | ||
448 | fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n"); | |
449 | for (i = 0; i < aarch64_num_wp_regs; i++) | |
450 | fprintf_unfiltered (gdb_stdlog, | |
451 | "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
452 | i, state->dr_addr_wp[i], | |
453 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); | |
454 | } | |
455 | ||
456 | /* Fill GDB's register array with the general-purpose register values | |
457 | from the current thread. */ | |
458 | ||
459 | static void | |
460 | fetch_gregs_from_thread (struct regcache *regcache) | |
461 | { | |
462 | int ret, regno, tid; | |
463 | elf_gregset_t regs; | |
464 | struct iovec iovec; | |
465 | ||
466 | tid = get_thread_id (inferior_ptid); | |
467 | ||
468 | iovec.iov_base = ®s; | |
469 | iovec.iov_len = sizeof (regs); | |
470 | ||
471 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
472 | if (ret < 0) | |
473 | perror_with_name (_("Unable to fetch general registers.")); | |
474 | ||
475 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
476 | regcache_raw_supply (regcache, regno, | |
477 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
478 | } | |
479 | ||
480 | /* Store to the current thread the valid general-purpose register | |
481 | values in the GDB's register array. */ | |
482 | ||
483 | static void | |
484 | store_gregs_to_thread (const struct regcache *regcache) | |
485 | { | |
486 | int ret, regno, tid; | |
487 | elf_gregset_t regs; | |
488 | struct iovec iovec; | |
489 | ||
490 | tid = get_thread_id (inferior_ptid); | |
491 | ||
492 | iovec.iov_base = ®s; | |
493 | iovec.iov_len = sizeof (regs); | |
494 | ||
495 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
496 | if (ret < 0) | |
497 | perror_with_name (_("Unable to fetch general registers.")); | |
498 | ||
499 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
500 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
501 | regcache_raw_collect (regcache, regno, | |
502 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
503 | ||
504 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
505 | if (ret < 0) | |
506 | perror_with_name (_("Unable to store general registers.")); | |
507 | } | |
508 | ||
509 | /* Fill GDB's register array with the fp/simd register values | |
510 | from the current thread. */ | |
511 | ||
512 | static void | |
513 | fetch_fpregs_from_thread (struct regcache *regcache) | |
514 | { | |
515 | int ret, regno, tid; | |
516 | elf_fpregset_t regs; | |
517 | struct iovec iovec; | |
518 | ||
519 | tid = get_thread_id (inferior_ptid); | |
520 | ||
521 | iovec.iov_base = ®s; | |
522 | iovec.iov_len = sizeof (regs); | |
523 | ||
524 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
525 | if (ret < 0) | |
526 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
527 | ||
528 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
529 | regcache_raw_supply (regcache, regno, | |
530 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
531 | ||
532 | regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
533 | regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
534 | } | |
535 | ||
536 | /* Store to the current thread the valid fp/simd register | |
537 | values in the GDB's register array. */ | |
538 | ||
539 | static void | |
540 | store_fpregs_to_thread (const struct regcache *regcache) | |
541 | { | |
542 | int ret, regno, tid; | |
543 | elf_fpregset_t regs; | |
544 | struct iovec iovec; | |
545 | ||
546 | tid = get_thread_id (inferior_ptid); | |
547 | ||
548 | iovec.iov_base = ®s; | |
549 | iovec.iov_len = sizeof (regs); | |
550 | ||
551 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
552 | if (ret < 0) | |
553 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
554 | ||
555 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
556 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
557 | regcache_raw_collect (regcache, regno, | |
558 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
559 | ||
560 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM)) | |
561 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
562 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM)) | |
563 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
564 | ||
565 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
566 | if (ret < 0) | |
567 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
568 | } | |
569 | ||
570 | /* Implement the "to_fetch_register" target_ops method. */ | |
571 | ||
572 | static void | |
573 | aarch64_linux_fetch_inferior_registers (struct target_ops *ops, | |
574 | struct regcache *regcache, | |
575 | int regno) | |
576 | { | |
577 | if (regno == -1) | |
578 | { | |
579 | fetch_gregs_from_thread (regcache); | |
580 | fetch_fpregs_from_thread (regcache); | |
581 | } | |
582 | else if (regno < AARCH64_V0_REGNUM) | |
583 | fetch_gregs_from_thread (regcache); | |
584 | else | |
585 | fetch_fpregs_from_thread (regcache); | |
586 | } | |
587 | ||
588 | /* Implement the "to_store_register" target_ops method. */ | |
589 | ||
590 | static void | |
591 | aarch64_linux_store_inferior_registers (struct target_ops *ops, | |
592 | struct regcache *regcache, | |
593 | int regno) | |
594 | { | |
595 | if (regno == -1) | |
596 | { | |
597 | store_gregs_to_thread (regcache); | |
598 | store_fpregs_to_thread (regcache); | |
599 | } | |
600 | else if (regno < AARCH64_V0_REGNUM) | |
601 | store_gregs_to_thread (regcache); | |
602 | else | |
603 | store_fpregs_to_thread (regcache); | |
604 | } | |
605 | ||
606 | /* Fill register REGNO (if it is a general-purpose register) in | |
607 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
608 | do this for all registers. */ | |
609 | ||
610 | void | |
611 | fill_gregset (const struct regcache *regcache, | |
612 | gdb_gregset_t *gregsetp, int regno) | |
613 | { | |
614 | gdb_byte *gregs_buf = (gdb_byte *) gregsetp; | |
615 | int i; | |
616 | ||
617 | for (i = AARCH64_X0_REGNUM; i <= AARCH64_CPSR_REGNUM; i++) | |
618 | if (regno == -1 || regno == i) | |
619 | regcache_raw_collect (regcache, i, | |
620 | gregs_buf + X_REGISTER_SIZE | |
621 | * (i - AARCH64_X0_REGNUM)); | |
622 | } | |
623 | ||
624 | /* Fill GDB's register array with the general-purpose register values | |
625 | in *GREGSETP. */ | |
626 | ||
627 | void | |
628 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
629 | { | |
630 | aarch64_linux_supply_gregset (regcache, (const gdb_byte *) gregsetp); | |
631 | } | |
632 | ||
633 | /* Fill register REGNO (if it is a floating-point register) in | |
634 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
635 | do this for all registers. */ | |
636 | ||
637 | void | |
638 | fill_fpregset (const struct regcache *regcache, | |
639 | gdb_fpregset_t *fpregsetp, int regno) | |
640 | { | |
641 | gdb_byte *fpregs_buf = (gdb_byte *) fpregsetp; | |
642 | int i; | |
643 | ||
644 | for (i = AARCH64_V0_REGNUM; i <= AARCH64_V31_REGNUM; i++) | |
645 | if (regno == -1 || regno == i) | |
646 | regcache_raw_collect (regcache, i, | |
647 | fpregs_buf + V_REGISTER_SIZE | |
648 | * (i - AARCH64_V0_REGNUM)); | |
649 | ||
650 | if (regno == -1 || regno == AARCH64_FPSR_REGNUM) | |
651 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, | |
652 | fpregs_buf + V_REGISTER_SIZE * 32); | |
653 | ||
654 | if (regno == -1 || regno == AARCH64_FPCR_REGNUM) | |
655 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, | |
656 | fpregs_buf + V_REGISTER_SIZE * 32 + 4); | |
657 | } | |
658 | ||
659 | /* Fill GDB's register array with the floating-point register values | |
660 | in *FPREGSETP. */ | |
661 | ||
662 | void | |
663 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
664 | { | |
665 | aarch64_linux_supply_fpregset (regcache, (const gdb_byte *) fpregsetp); | |
666 | } | |
667 | ||
668 | /* Called when resuming a thread. | |
669 | The hardware debug registers are updated when there is any change. */ | |
670 | ||
671 | static void | |
672 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) | |
673 | { | |
674 | struct arch_lwp_info *info = lwp->arch_private; | |
675 | ||
676 | /* NULL means this is the main thread still going through the shell, | |
677 | or, no watchpoint has been set yet. In that case, there's | |
678 | nothing to do. */ | |
679 | if (info == NULL) | |
680 | return; | |
681 | ||
682 | if (DR_HAS_CHANGED (info->dr_changed_bp) | |
683 | || DR_HAS_CHANGED (info->dr_changed_wp)) | |
684 | { | |
685 | int tid = GET_LWP (lwp->ptid); | |
d6c44983 YZ |
686 | struct aarch64_debug_reg_state *state |
687 | = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid)); | |
9d19df75 MS |
688 | |
689 | if (debug_hw_points) | |
690 | fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid); | |
691 | ||
692 | /* Watchpoints. */ | |
693 | if (DR_HAS_CHANGED (info->dr_changed_wp)) | |
694 | { | |
695 | aarch64_linux_set_debug_regs (state, tid, 1); | |
696 | DR_CLEAR_CHANGED (info->dr_changed_wp); | |
697 | } | |
698 | ||
699 | /* Breakpoints. */ | |
700 | if (DR_HAS_CHANGED (info->dr_changed_bp)) | |
701 | { | |
702 | aarch64_linux_set_debug_regs (state, tid, 0); | |
703 | DR_CLEAR_CHANGED (info->dr_changed_bp); | |
704 | } | |
705 | } | |
706 | } | |
707 | ||
708 | static void | |
709 | aarch64_linux_new_thread (struct lwp_info *lp) | |
710 | { | |
711 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
712 | ||
713 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
714 | for this thread need to be initialized. */ | |
715 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); | |
716 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); | |
717 | ||
718 | lp->arch_private = info; | |
719 | } | |
d6c44983 YZ |
720 | |
721 | /* linux_nat_new_fork hook. */ | |
722 | ||
723 | static void | |
724 | aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
725 | { | |
726 | pid_t parent_pid; | |
727 | struct aarch64_debug_reg_state *parent_state; | |
728 | struct aarch64_debug_reg_state *child_state; | |
729 | ||
730 | /* NULL means no watchpoint has ever been set in the parent. In | |
731 | that case, there's nothing to do. */ | |
732 | if (parent->arch_private == NULL) | |
733 | return; | |
734 | ||
735 | /* GDB core assumes the child inherits the watchpoints/hw | |
736 | breakpoints of the parent, and will remove them all from the | |
737 | forked off process. Copy the debug registers mirrors into the | |
738 | new process so that all breakpoints and watchpoints can be | |
739 | removed together. */ | |
740 | ||
741 | parent_pid = ptid_get_pid (parent->ptid); | |
742 | parent_state = aarch64_get_debug_reg_state (parent_pid); | |
743 | child_state = aarch64_get_debug_reg_state (child_pid); | |
744 | *child_state = *parent_state; | |
745 | } | |
9d19df75 MS |
746 | \f |
747 | ||
748 | /* Called by libthread_db. Returns a pointer to the thread local | |
749 | storage (or its descriptor). */ | |
750 | ||
751 | ps_err_e | |
752 | ps_get_thread_area (const struct ps_prochandle *ph, | |
753 | lwpid_t lwpid, int idx, void **base) | |
754 | { | |
755 | struct iovec iovec; | |
756 | uint64_t reg; | |
757 | ||
758 | iovec.iov_base = ® | |
759 | iovec.iov_len = sizeof (reg); | |
760 | ||
761 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) | |
762 | return PS_ERR; | |
763 | ||
764 | /* IDX is the bias from the thread pointer to the beginning of the | |
765 | thread descriptor. It has to be subtracted due to implementation | |
766 | quirks in libthread_db. */ | |
767 | *base = (void *) (reg - idx); | |
768 | ||
769 | return PS_OK; | |
770 | } | |
771 | \f | |
772 | ||
773 | /* Get the hardware debug register capacity information. */ | |
774 | ||
775 | static void | |
776 | aarch64_linux_get_debug_reg_capacity (void) | |
777 | { | |
778 | int tid; | |
779 | struct iovec iov; | |
780 | struct user_hwdebug_state dreg_state; | |
781 | ||
782 | tid = get_thread_id (inferior_ptid); | |
783 | iov.iov_base = &dreg_state; | |
784 | iov.iov_len = sizeof (dreg_state); | |
785 | ||
786 | /* Get hardware watchpoint register info. */ | |
787 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 | |
788 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
789 | { | |
790 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
791 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) | |
792 | { | |
1d3ffd6b MS |
793 | warning (_("Unexpected number of hardware watchpoint registers" |
794 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
795 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
796 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; | |
797 | } | |
798 | } | |
799 | else | |
800 | { | |
1d3ffd6b MS |
801 | warning (_("Unable to determine the number of hardware watchpoints" |
802 | " available.")); | |
9d19df75 MS |
803 | aarch64_num_wp_regs = 0; |
804 | } | |
805 | ||
806 | /* Get hardware breakpoint register info. */ | |
807 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 | |
808 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
809 | { | |
810 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
811 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) | |
812 | { | |
1d3ffd6b MS |
813 | warning (_("Unexpected number of hardware breakpoint registers" |
814 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
815 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
816 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; | |
817 | } | |
818 | } | |
819 | else | |
820 | { | |
1d3ffd6b MS |
821 | warning (_("Unable to determine the number of hardware breakpoints" |
822 | " available.")); | |
9d19df75 MS |
823 | aarch64_num_bp_regs = 0; |
824 | } | |
825 | } | |
826 | ||
827 | static void (*super_post_startup_inferior) (ptid_t ptid); | |
828 | ||
829 | /* Implement the "to_post_startup_inferior" target_ops method. */ | |
830 | ||
831 | static void | |
832 | aarch64_linux_child_post_startup_inferior (ptid_t ptid) | |
833 | { | |
d6c44983 | 834 | aarch64_forget_process (ptid_get_pid (ptid)); |
9d19df75 MS |
835 | aarch64_linux_get_debug_reg_capacity (); |
836 | super_post_startup_inferior (ptid); | |
837 | } | |
838 | ||
839 | /* Implement the "to_read_description" target_ops method. */ | |
840 | ||
841 | static const struct target_desc * | |
842 | aarch64_linux_read_description (struct target_ops *ops) | |
843 | { | |
844 | initialize_tdesc_aarch64 (); | |
845 | return tdesc_aarch64; | |
846 | } | |
847 | ||
848 | /* Given the (potentially unaligned) watchpoint address in ADDR and | |
849 | length in LEN, return the aligned address and aligned length in | |
850 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned | |
851 | aligned address and length will be valid values to write to the | |
852 | hardware watchpoint value and control registers. | |
853 | ||
854 | The given watchpoint may get truncated if more than one hardware | |
855 | register is needed to cover the watched region. *NEXT_ADDR_P | |
856 | and *NEXT_LEN_P, if non-NULL, will return the address and length | |
857 | of the remaining part of the watchpoint (which can be processed | |
858 | by calling this routine again to generate another aligned address | |
859 | and length pair. | |
860 | ||
861 | See the comment above the function of the same name in | |
862 | gdbserver/linux-aarch64-low.c for more information. */ | |
863 | ||
864 | static void | |
865 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, | |
866 | int *aligned_len_p, CORE_ADDR *next_addr_p, | |
867 | int *next_len_p) | |
868 | { | |
869 | int aligned_len; | |
870 | unsigned int offset; | |
871 | CORE_ADDR aligned_addr; | |
872 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; | |
873 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; | |
874 | ||
875 | /* As assumed by the algorithm. */ | |
876 | gdb_assert (alignment == max_wp_len); | |
877 | ||
878 | if (len <= 0) | |
879 | return; | |
880 | ||
881 | /* Address to be put into the hardware watchpoint value register | |
882 | must be aligned. */ | |
883 | offset = addr & (alignment - 1); | |
884 | aligned_addr = addr - offset; | |
885 | ||
886 | gdb_assert (offset >= 0 && offset < alignment); | |
887 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); | |
888 | gdb_assert (offset + len > 0); | |
889 | ||
890 | if (offset + len >= max_wp_len) | |
891 | { | |
892 | /* Need more than one watchpoint registers; truncate it at the | |
893 | alignment boundary. */ | |
894 | aligned_len = max_wp_len; | |
895 | len -= (max_wp_len - offset); | |
896 | addr += (max_wp_len - offset); | |
897 | gdb_assert ((addr & (alignment - 1)) == 0); | |
898 | } | |
899 | else | |
900 | { | |
901 | /* Find the smallest valid length that is large enough to | |
902 | accommodate this watchpoint. */ | |
903 | static const unsigned char | |
904 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = | |
905 | { 1, 2, 4, 4, 8, 8, 8, 8 }; | |
906 | ||
907 | aligned_len = aligned_len_array[offset + len - 1]; | |
908 | addr += len; | |
909 | len = 0; | |
910 | } | |
911 | ||
912 | if (aligned_addr_p) | |
913 | *aligned_addr_p = aligned_addr; | |
914 | if (aligned_len_p) | |
915 | *aligned_len_p = aligned_len; | |
916 | if (next_addr_p) | |
917 | *next_addr_p = addr; | |
918 | if (next_len_p) | |
919 | *next_len_p = len; | |
920 | } | |
921 | ||
922 | /* Returns the number of hardware watchpoints of type TYPE that we can | |
923 | set. Value is positive if we can set CNT watchpoints, zero if | |
924 | setting watchpoints of type TYPE is not supported, and negative if | |
925 | CNT is more than the maximum number of watchpoints of type TYPE | |
926 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
927 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
928 | CNT is the number of such watchpoints used so far (including this | |
929 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
930 | currently enabled. | |
931 | ||
932 | We always return 1 here because we don't have enough information | |
933 | about possible overlap of addresses that they want to watch. As an | |
934 | extreme example, consider the case where all the watchpoints watch | |
935 | the same address and the same region length: then we can handle a | |
936 | virtually unlimited number of watchpoints, due to debug register | |
937 | sharing implemented via reference counts. */ | |
938 | ||
939 | static int | |
940 | aarch64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
941 | { | |
942 | return 1; | |
943 | } | |
944 | ||
945 | /* ptrace expects control registers to be formatted as follows: | |
946 | ||
947 | 31 13 5 3 1 0 | |
948 | +--------------------------------+----------+------+------+----+ | |
949 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | | |
950 | +--------------------------------+----------+------+------+----+ | |
951 | ||
952 | The TYPE field is ignored for breakpoints. */ | |
953 | ||
954 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) | |
955 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) | |
956 | ||
957 | /* Utility function that returns the length in bytes of a watchpoint | |
958 | according to the content of a hardware debug control register CTRL. | |
959 | Note that the kernel currently only supports the following Byte | |
960 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means | |
961 | that for a hardware watchpoint, its valid length can only be 1 | |
962 | byte, 2 bytes, 4 bytes or 8 bytes. */ | |
963 | ||
964 | static inline unsigned int | |
965 | aarch64_watchpoint_length (unsigned int ctrl) | |
966 | { | |
967 | switch (DR_CONTROL_LENGTH (ctrl)) | |
968 | { | |
969 | case 0x01: | |
970 | return 1; | |
971 | case 0x03: | |
972 | return 2; | |
973 | case 0x0f: | |
974 | return 4; | |
975 | case 0xff: | |
976 | return 8; | |
977 | default: | |
978 | return 0; | |
979 | } | |
980 | } | |
981 | ||
982 | /* Given the hardware breakpoint or watchpoint type TYPE and its | |
983 | length LEN, return the expected encoding for a hardware | |
984 | breakpoint/watchpoint control register. */ | |
985 | ||
986 | static unsigned int | |
987 | aarch64_point_encode_ctrl_reg (int type, int len) | |
988 | { | |
989 | unsigned int ctrl, ttype; | |
990 | ||
991 | /* type */ | |
992 | switch (type) | |
993 | { | |
994 | case hw_write: | |
995 | ttype = 2; | |
996 | break; | |
997 | case hw_read: | |
998 | ttype = 1; | |
999 | break; | |
1000 | case hw_access: | |
1001 | ttype = 3; | |
1002 | break; | |
1003 | case hw_execute: | |
1004 | ttype = 0; | |
1005 | break; | |
1006 | default: | |
1007 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); | |
1008 | } | |
1009 | ctrl = ttype << 3; | |
1010 | ||
1011 | /* length bitmask */ | |
1012 | ctrl |= ((1 << len) - 1) << 5; | |
1013 | /* enabled at el0 */ | |
1014 | ctrl |= (2 << 1) | 1; | |
1015 | ||
1016 | return ctrl; | |
1017 | } | |
1018 | ||
1019 | /* Addresses to be written to the hardware breakpoint and watchpoint | |
1020 | value registers need to be aligned; the alignment is 4-byte and | |
1021 | 8-type respectively. Linux kernel rejects any non-aligned address | |
1022 | it receives from the related ptrace call. Furthermore, the kernel | |
1023 | currently only supports the following Byte Address Select (BAS) | |
1024 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware | |
1025 | watchpoint to be accepted by the kernel (via ptrace call), its | |
1026 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. | |
1027 | Despite these limitations, the unaligned watchpoint is supported in | |
1028 | this port. | |
1029 | ||
1030 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ | |
1031 | ||
1032 | static int | |
1033 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) | |
1034 | { | |
1035 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT | |
1036 | : AARCH64_HBP_ALIGNMENT; | |
1037 | ||
1038 | if (addr & (alignment - 1)) | |
1039 | return 0; | |
1040 | ||
1041 | if (len != 8 && len != 4 && len != 2 && len != 1) | |
1042 | return 0; | |
1043 | ||
1044 | return 1; | |
1045 | } | |
1046 | ||
1047 | /* Record the insertion of one breakpoint/watchpoint, as represented | |
1048 | by ADDR and CTRL, in the cached debug register state area *STATE. */ | |
1049 | ||
1050 | static int | |
1051 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, | |
1052 | int type, CORE_ADDR addr, int len) | |
1053 | { | |
1054 | int i, idx, num_regs, is_watchpoint; | |
1055 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1056 | CORE_ADDR *dr_addr_p; | |
1057 | ||
1058 | /* Set up state pointers. */ | |
1059 | is_watchpoint = (type != hw_execute); | |
1060 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1061 | if (is_watchpoint) | |
1062 | { | |
1063 | num_regs = aarch64_num_wp_regs; | |
1064 | dr_addr_p = state->dr_addr_wp; | |
1065 | dr_ctrl_p = state->dr_ctrl_wp; | |
1066 | dr_ref_count = state->dr_ref_count_wp; | |
1067 | } | |
1068 | else | |
1069 | { | |
1070 | num_regs = aarch64_num_bp_regs; | |
1071 | dr_addr_p = state->dr_addr_bp; | |
1072 | dr_ctrl_p = state->dr_ctrl_bp; | |
1073 | dr_ref_count = state->dr_ref_count_bp; | |
1074 | } | |
1075 | ||
1076 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1077 | ||
1078 | /* Find an existing or free register in our cache. */ | |
1079 | idx = -1; | |
1080 | for (i = 0; i < num_regs; ++i) | |
1081 | { | |
1082 | if ((dr_ctrl_p[i] & 1) == 0) | |
1083 | { | |
1084 | gdb_assert (dr_ref_count[i] == 0); | |
1085 | idx = i; | |
1086 | /* no break; continue hunting for an existing one. */ | |
1087 | } | |
1088 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1089 | { | |
1090 | gdb_assert (dr_ref_count[i] != 0); | |
1091 | idx = i; | |
1092 | break; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | /* No space. */ | |
1097 | if (idx == -1) | |
1098 | return -1; | |
1099 | ||
1100 | /* Update our cache. */ | |
1101 | if ((dr_ctrl_p[idx] & 1) == 0) | |
1102 | { | |
1103 | /* new entry */ | |
1104 | dr_addr_p[idx] = addr; | |
1105 | dr_ctrl_p[idx] = ctrl; | |
1106 | dr_ref_count[idx] = 1; | |
1107 | /* Notify the change. */ | |
1108 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); | |
1109 | } | |
1110 | else | |
1111 | { | |
1112 | /* existing entry */ | |
1113 | dr_ref_count[idx]++; | |
1114 | } | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | /* Record the removal of one breakpoint/watchpoint, as represented by | |
1120 | ADDR and CTRL, in the cached debug register state area *STATE. */ | |
1121 | ||
1122 | static int | |
1123 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, | |
1124 | int type, CORE_ADDR addr, int len) | |
1125 | { | |
1126 | int i, num_regs, is_watchpoint; | |
1127 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1128 | CORE_ADDR *dr_addr_p; | |
1129 | ||
1130 | /* Set up state pointers. */ | |
1131 | is_watchpoint = (type != hw_execute); | |
1132 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1133 | if (is_watchpoint) | |
1134 | { | |
1135 | num_regs = aarch64_num_wp_regs; | |
1136 | dr_addr_p = state->dr_addr_wp; | |
1137 | dr_ctrl_p = state->dr_ctrl_wp; | |
1138 | dr_ref_count = state->dr_ref_count_wp; | |
1139 | } | |
1140 | else | |
1141 | { | |
1142 | num_regs = aarch64_num_bp_regs; | |
1143 | dr_addr_p = state->dr_addr_bp; | |
1144 | dr_ctrl_p = state->dr_ctrl_bp; | |
1145 | dr_ref_count = state->dr_ref_count_bp; | |
1146 | } | |
1147 | ||
1148 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1149 | ||
1150 | /* Find the entry that matches the ADDR and CTRL. */ | |
1151 | for (i = 0; i < num_regs; ++i) | |
1152 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1153 | { | |
1154 | gdb_assert (dr_ref_count[i] != 0); | |
1155 | break; | |
1156 | } | |
1157 | ||
1158 | /* Not found. */ | |
1159 | if (i == num_regs) | |
1160 | return -1; | |
1161 | ||
1162 | /* Clear our cache. */ | |
1163 | if (--dr_ref_count[i] == 0) | |
1164 | { | |
1165 | /* Clear the enable bit. */ | |
1166 | ctrl &= ~1; | |
1167 | dr_addr_p[i] = 0; | |
1168 | dr_ctrl_p[i] = ctrl; | |
1169 | /* Notify the change. */ | |
1170 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); | |
1171 | } | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | /* Implement insertion and removal of a single breakpoint. */ | |
1177 | ||
1178 | static int | |
1179 | aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1180 | { | |
1181 | struct aarch64_debug_reg_state *state; | |
1182 | ||
1183 | /* The hardware breakpoint on AArch64 should always be 4-byte | |
1184 | aligned. */ | |
1185 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) | |
1186 | return -1; | |
1187 | ||
d6c44983 | 1188 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
1189 | |
1190 | if (is_insert) | |
1191 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1192 | else | |
1193 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1194 | } | |
1195 | ||
1196 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. | |
1197 | Return 0 on success, -1 on failure. */ | |
1198 | ||
1199 | static int | |
1200 | aarch64_linux_insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1201 | struct bp_target_info *bp_tgt) | |
1202 | { | |
1203 | int ret; | |
1204 | CORE_ADDR addr = bp_tgt->placed_address; | |
1205 | const int len = 4; | |
1206 | const int type = hw_execute; | |
1207 | ||
1208 | if (debug_hw_points) | |
1209 | fprintf_unfiltered | |
1210 | (gdb_stdlog, | |
1211 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1212 | (unsigned long) addr, len); | |
1213 | ||
1214 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */); | |
1215 | ||
1216 | if (debug_hw_points > 1) | |
d6c44983 YZ |
1217 | { |
1218 | struct aarch64_debug_reg_state *state | |
1219 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1220 | ||
1221 | aarch64_show_debug_reg_state (state, | |
1222 | "insert_hw_watchpoint", addr, len, type); | |
1223 | } | |
9d19df75 MS |
1224 | |
1225 | return ret; | |
1226 | } | |
1227 | ||
1228 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
1229 | Return 0 on success, -1 on failure. */ | |
1230 | ||
1231 | static int | |
1232 | aarch64_linux_remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1233 | struct bp_target_info *bp_tgt) | |
1234 | { | |
1235 | int ret; | |
1236 | CORE_ADDR addr = bp_tgt->placed_address; | |
1237 | const int len = 4; | |
1238 | const int type = hw_execute; | |
1239 | ||
1240 | if (debug_hw_points) | |
1241 | fprintf_unfiltered | |
1242 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1243 | (unsigned long) addr, len); | |
1244 | ||
1245 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */); | |
1246 | ||
1247 | if (debug_hw_points > 1) | |
d6c44983 YZ |
1248 | { |
1249 | struct aarch64_debug_reg_state *state | |
1250 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1251 | ||
1252 | aarch64_show_debug_reg_state (state, | |
1253 | "remove_hw_watchpoint", addr, len, type); | |
1254 | } | |
9d19df75 MS |
1255 | |
1256 | return ret; | |
1257 | } | |
1258 | ||
1259 | /* This is essentially the same as aarch64_handle_breakpoint, apart | |
1260 | from that it is an aligned watchpoint to be handled. */ | |
1261 | ||
1262 | static int | |
1263 | aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1264 | int is_insert) | |
1265 | { | |
d6c44983 YZ |
1266 | struct aarch64_debug_reg_state *state |
1267 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 MS |
1268 | |
1269 | if (is_insert) | |
1270 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1271 | else | |
1272 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1273 | } | |
1274 | ||
1275 | /* Insert/remove unaligned watchpoint by calling | |
1276 | aarch64_align_watchpoint repeatedly until the whole watched region, | |
1277 | as represented by ADDR and LEN, has been properly aligned and ready | |
1278 | to be written to one or more hardware watchpoint registers. | |
1279 | IS_INSERT indicates whether this is an insertion or a deletion. | |
1280 | Return 0 if succeed. */ | |
1281 | ||
1282 | static int | |
1283 | aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1284 | int is_insert) | |
1285 | { | |
d6c44983 YZ |
1286 | struct aarch64_debug_reg_state *state |
1287 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 MS |
1288 | |
1289 | while (len > 0) | |
1290 | { | |
1291 | CORE_ADDR aligned_addr; | |
1292 | int aligned_len, ret; | |
1293 | ||
1294 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, | |
1295 | &addr, &len); | |
1296 | ||
1297 | if (is_insert) | |
1298 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, | |
1299 | aligned_len); | |
1300 | else | |
1301 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, | |
1302 | aligned_len); | |
1303 | ||
1304 | if (debug_hw_points) | |
1305 | fprintf_unfiltered (gdb_stdlog, | |
1306 | "handle_unaligned_watchpoint: is_insert: %d\n" | |
1307 | " aligned_addr: 0x%08lx, aligned_len: %d\n" | |
1308 | " next_addr: 0x%08lx, next_len: %d\n", | |
1309 | is_insert, aligned_addr, aligned_len, addr, len); | |
1310 | ||
1311 | if (ret != 0) | |
1312 | return ret; | |
1313 | } | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* Implements insertion and removal of a single watchpoint. */ | |
1319 | ||
1320 | static int | |
1321 | aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1322 | { | |
1323 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) | |
1324 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); | |
1325 | else | |
1326 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); | |
1327 | } | |
1328 | ||
1329 | /* Implement the "to_insert_watchpoint" target_ops method. | |
1330 | ||
1331 | Insert a watchpoint to watch a memory region which starts at | |
1332 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
1333 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
1334 | ||
1335 | static int | |
1336 | aarch64_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, | |
1337 | struct expression *cond) | |
1338 | { | |
1339 | int ret; | |
1340 | ||
1341 | if (debug_hw_points) | |
1342 | fprintf_unfiltered (gdb_stdlog, | |
1343 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1344 | (unsigned long) addr, len); | |
1345 | ||
1346 | gdb_assert (type != hw_execute); | |
1347 | ||
1348 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */); | |
1349 | ||
1350 | if (debug_hw_points > 1) | |
d6c44983 YZ |
1351 | { |
1352 | struct aarch64_debug_reg_state *state | |
1353 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1354 | ||
1355 | aarch64_show_debug_reg_state (state, | |
1356 | "insert_watchpoint", addr, len, type); | |
1357 | } | |
9d19df75 MS |
1358 | |
1359 | return ret; | |
1360 | } | |
1361 | ||
1362 | /* Implement the "to_remove_watchpoint" target_ops method. | |
1363 | Remove a watchpoint that watched the memory region which starts at | |
1364 | address ADDR, whose length is LEN bytes, and for accesses of the | |
1365 | type TYPE. Return 0 on success, -1 on failure. */ | |
1366 | ||
1367 | static int | |
1368 | aarch64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, | |
1369 | struct expression *cond) | |
1370 | { | |
1371 | int ret; | |
1372 | ||
1373 | if (debug_hw_points) | |
1374 | fprintf_unfiltered (gdb_stdlog, | |
1375 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1376 | (unsigned long) addr, len); | |
1377 | ||
1378 | gdb_assert (type != hw_execute); | |
1379 | ||
1380 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */); | |
1381 | ||
1382 | if (debug_hw_points > 1) | |
d6c44983 YZ |
1383 | { |
1384 | struct aarch64_debug_reg_state *state | |
1385 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1386 | ||
1387 | aarch64_show_debug_reg_state (state, | |
1388 | "remove_watchpoint", addr, len, type); | |
1389 | } | |
9d19df75 MS |
1390 | |
1391 | return ret; | |
1392 | } | |
1393 | ||
1394 | /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */ | |
1395 | ||
1396 | static int | |
1397 | aarch64_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
1398 | { | |
1399 | CORE_ADDR aligned_addr; | |
1400 | ||
1401 | /* Can not set watchpoints for zero or negative lengths. */ | |
1402 | if (len <= 0) | |
1403 | return 0; | |
1404 | ||
1405 | /* Must have hardware watchpoint debug register(s). */ | |
1406 | if (aarch64_num_wp_regs == 0) | |
1407 | return 0; | |
1408 | ||
1409 | /* We support unaligned watchpoint address and arbitrary length, | |
1410 | as long as the size of the whole watched area after alignment | |
1411 | doesn't exceed size of the total area that all watchpoint debug | |
1412 | registers can watch cooperatively. | |
1413 | ||
1414 | This is a very relaxed rule, but unfortunately there are | |
1415 | limitations, e.g. false-positive hits, due to limited support of | |
1416 | hardware debug registers in the kernel. See comment above | |
1417 | aarch64_align_watchpoint for more information. */ | |
1418 | ||
1419 | aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1); | |
1420 | if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG | |
1421 | < addr + len) | |
1422 | return 0; | |
1423 | ||
1424 | /* All tests passed so we are likely to be able to set the watchpoint. | |
1425 | The reason that it is 'likely' rather than 'must' is because | |
1426 | we don't check the current usage of the watchpoint registers, and | |
1427 | there may not be enough registers available for this watchpoint. | |
1428 | Ideally we should check the cached debug register state, however | |
1429 | the checking is costly. */ | |
1430 | return 1; | |
1431 | } | |
1432 | ||
1433 | /* Implement the "to_stopped_data_address" target_ops method. */ | |
1434 | ||
1435 | static int | |
1436 | aarch64_linux_stopped_data_address (struct target_ops *target, | |
1437 | CORE_ADDR *addr_p) | |
1438 | { | |
1439 | siginfo_t siginfo; | |
1440 | int i, tid; | |
1441 | struct aarch64_debug_reg_state *state; | |
1442 | ||
1443 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1444 | return 0; | |
1445 | ||
1446 | /* This must be a hardware breakpoint. */ | |
1447 | if (siginfo.si_signo != SIGTRAP | |
1448 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
1449 | return 0; | |
1450 | ||
1451 | /* Check if the address matches any watched address. */ | |
d6c44983 | 1452 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
1453 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
1454 | { | |
1455 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); | |
1456 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
1457 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; | |
1458 | ||
1459 | if (state->dr_ref_count_wp[i] | |
1460 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
1461 | && addr_trap >= addr_watch | |
1462 | && addr_trap < addr_watch + len) | |
1463 | { | |
1464 | *addr_p = addr_trap; | |
1465 | return 1; | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | /* Implement the "to_stopped_by_watchpoint" target_ops method. */ | |
1473 | ||
1474 | static int | |
1475 | aarch64_linux_stopped_by_watchpoint (void) | |
1476 | { | |
1477 | CORE_ADDR addr; | |
1478 | ||
1479 | return aarch64_linux_stopped_data_address (¤t_target, &addr); | |
1480 | } | |
1481 | ||
1482 | /* Implement the "to_watchpoint_addr_within_range" target_ops method. */ | |
1483 | ||
1484 | static int | |
1485 | aarch64_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1486 | CORE_ADDR addr, | |
1487 | CORE_ADDR start, int length) | |
1488 | { | |
1489 | return start <= addr && start + length - 1 >= addr; | |
1490 | } | |
1491 | ||
1492 | /* Define AArch64 maintenance commands. */ | |
1493 | ||
1494 | static void | |
1495 | add_show_debug_regs_command (void) | |
1496 | { | |
1497 | /* A maintenance command to enable printing the internal DRi mirror | |
1498 | variables. */ | |
1499 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
1500 | &debug_hw_points, _("\ | |
1501 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ | |
1502 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
1503 | Use \"on\" to enable, \"off\" to disable.\n\ | |
1504 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1505 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1506 | triggers a breakpoint or watchpoint."), | |
1507 | NULL, | |
1508 | NULL, | |
1509 | &maintenance_set_cmdlist, | |
1510 | &maintenance_show_cmdlist); | |
1511 | } | |
1512 | ||
1513 | /* -Wmissing-prototypes. */ | |
1514 | void _initialize_aarch64_linux_nat (void); | |
1515 | ||
1516 | void | |
1517 | _initialize_aarch64_linux_nat (void) | |
1518 | { | |
1519 | struct target_ops *t; | |
1520 | ||
1521 | /* Fill in the generic GNU/Linux methods. */ | |
1522 | t = linux_target (); | |
1523 | ||
1524 | add_show_debug_regs_command (); | |
1525 | ||
1526 | /* Add our register access methods. */ | |
1527 | t->to_fetch_registers = aarch64_linux_fetch_inferior_registers; | |
1528 | t->to_store_registers = aarch64_linux_store_inferior_registers; | |
1529 | ||
1530 | t->to_read_description = aarch64_linux_read_description; | |
1531 | ||
1532 | t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint; | |
1533 | t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint; | |
1534 | t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint; | |
1535 | t->to_region_ok_for_hw_watchpoint = | |
1536 | aarch64_linux_region_ok_for_hw_watchpoint; | |
1537 | t->to_insert_watchpoint = aarch64_linux_insert_watchpoint; | |
1538 | t->to_remove_watchpoint = aarch64_linux_remove_watchpoint; | |
1539 | t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint; | |
1540 | t->to_stopped_data_address = aarch64_linux_stopped_data_address; | |
1541 | t->to_watchpoint_addr_within_range = | |
1542 | aarch64_linux_watchpoint_addr_within_range; | |
9d19df75 MS |
1543 | |
1544 | /* Override the GNU/Linux inferior startup hook. */ | |
1545 | super_post_startup_inferior = t->to_post_startup_inferior; | |
1546 | t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior; | |
1547 | ||
1548 | /* Register the target. */ | |
1549 | linux_nat_add_target (t); | |
1550 | linux_nat_set_new_thread (t, aarch64_linux_new_thread); | |
d6c44983 YZ |
1551 | linux_nat_set_new_fork (t, aarch64_linux_new_fork); |
1552 | linux_nat_set_forget_process (t, aarch64_forget_process); | |
9d19df75 MS |
1553 | linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume); |
1554 | } |