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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
32d0add0 | 3 | Copyright (C) 2011-2015 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
32 | #include "elf/common.h" | |
33 | ||
34 | #include <sys/ptrace.h> | |
35 | #include <sys/utsname.h> | |
036cd381 | 36 | #include <asm/ptrace.h> |
9d19df75 MS |
37 | |
38 | #include "gregset.h" | |
39 | ||
9d19df75 MS |
40 | /* Defines ps_err_e, struct ps_prochandle. */ |
41 | #include "gdb_proc_service.h" | |
42 | ||
43 | #ifndef TRAP_HWBKPT | |
44 | #define TRAP_HWBKPT 0x0004 | |
45 | #endif | |
46 | ||
47 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which | |
48 | case we may be tracing more than one process at a time. In that | |
49 | case, inferior_ptid will contain the main process ID and the | |
50 | individual thread (process) ID. get_thread_id () is used to get | |
51 | the thread id if it's available, and the process id otherwise. */ | |
52 | ||
53 | static int | |
54 | get_thread_id (ptid_t ptid) | |
55 | { | |
dfd4cc63 | 56 | int tid = ptid_get_lwp (ptid); |
9d19df75 MS |
57 | |
58 | if (0 == tid) | |
dfd4cc63 | 59 | tid = ptid_get_pid (ptid); |
9d19df75 MS |
60 | return tid; |
61 | } | |
62 | ||
63 | /* Macro definitions, data structures, and code for the hardware | |
64 | breakpoint and hardware watchpoint support follow. We use the | |
65 | following abbreviations throughout the code: | |
66 | ||
67 | hw - hardware | |
68 | bp - breakpoint | |
69 | wp - watchpoint */ | |
70 | ||
71 | /* Maximum number of hardware breakpoint and watchpoint registers. | |
72 | Neither of these values may exceed the width of dr_changed_t | |
73 | measured in bits. */ | |
74 | ||
75 | #define AARCH64_HBP_MAX_NUM 16 | |
76 | #define AARCH64_HWP_MAX_NUM 16 | |
77 | ||
78 | /* Alignment requirement in bytes for addresses written to | |
79 | hardware breakpoint and watchpoint value registers. | |
80 | ||
81 | A ptrace call attempting to set an address that does not meet the | |
82 | alignment criteria will fail. Limited support has been provided in | |
83 | this port for unaligned watchpoints, such that from a GDB user | |
84 | perspective, an unaligned watchpoint may be requested. | |
85 | ||
86 | This is achieved by minimally enlarging the watched area to meet the | |
87 | alignment requirement, and if necessary, splitting the watchpoint | |
88 | over several hardware watchpoint registers. */ | |
89 | ||
90 | #define AARCH64_HBP_ALIGNMENT 4 | |
91 | #define AARCH64_HWP_ALIGNMENT 8 | |
92 | ||
93 | /* The maximum length of a memory region that can be watched by one | |
94 | hardware watchpoint register. */ | |
95 | ||
96 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 | |
97 | ||
98 | /* ptrace hardware breakpoint resource info is formatted as follows: | |
99 | ||
100 | 31 24 16 8 0 | |
101 | +---------------+--------------+---------------+---------------+ | |
102 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | | |
103 | +---------------+--------------+---------------+---------------+ */ | |
104 | ||
105 | ||
106 | /* Macros to extract fields from the hardware debug information word. */ | |
107 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) | |
108 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) | |
109 | ||
110 | /* Macro for the expected version of the ARMv8-A debug architecture. */ | |
111 | #define AARCH64_DEBUG_ARCH_V8 0x6 | |
112 | ||
113 | /* Number of hardware breakpoints/watchpoints the target supports. | |
114 | They are initialized with values obtained via the ptrace calls | |
115 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ | |
116 | ||
117 | static int aarch64_num_bp_regs; | |
118 | static int aarch64_num_wp_regs; | |
119 | ||
9d19df75 MS |
120 | /* Each bit of a variable of this type is used to indicate whether a |
121 | hardware breakpoint or watchpoint setting has been changed since | |
122 | the last update. | |
123 | ||
124 | Bit N corresponds to the Nth hardware breakpoint or watchpoint | |
125 | setting which is managed in aarch64_debug_reg_state, where N is | |
126 | valid between 0 and the total number of the hardware breakpoint or | |
127 | watchpoint debug registers minus 1. | |
128 | ||
129 | When bit N is 1, the corresponding breakpoint or watchpoint setting | |
130 | has changed, and therefore the corresponding hardware debug | |
131 | register needs to be updated via the ptrace interface. | |
132 | ||
133 | In the per-thread arch-specific data area, we define two such | |
134 | variables for per-thread hardware breakpoint and watchpoint | |
135 | settings respectively. | |
136 | ||
137 | This type is part of the mechanism which helps reduce the number of | |
138 | ptrace calls to the kernel, i.e. avoid asking the kernel to write | |
139 | to the debug registers with unchanged values. */ | |
140 | ||
de589d04 | 141 | typedef ULONGEST dr_changed_t; |
9d19df75 MS |
142 | |
143 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ | |
144 | ||
145 | #define DR_MARK_ALL_CHANGED(x, m) \ | |
146 | do \ | |
147 | { \ | |
148 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ | |
149 | (x) = (((dr_changed_t)1 << (m)) - 1); \ | |
150 | } while (0) | |
151 | ||
152 | #define DR_MARK_N_CHANGED(x, n) \ | |
153 | do \ | |
154 | { \ | |
155 | (x) |= ((dr_changed_t)1 << (n)); \ | |
156 | } while (0) | |
157 | ||
158 | #define DR_CLEAR_CHANGED(x) \ | |
159 | do \ | |
160 | { \ | |
161 | (x) = 0; \ | |
162 | } while (0) | |
163 | ||
164 | #define DR_HAS_CHANGED(x) ((x) != 0) | |
165 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) | |
166 | ||
167 | /* Structure for managing the hardware breakpoint/watchpoint resources. | |
168 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register | |
169 | content, and DR_REF_COUNT_* counts the numbers of references to the | |
170 | corresponding bp/wp, by which way the limited hardware resources | |
171 | are not wasted on duplicated bp/wp settings (though so far gdb has | |
172 | done a good job by not sending duplicated bp/wp requests). */ | |
173 | ||
174 | struct aarch64_debug_reg_state | |
175 | { | |
176 | /* hardware breakpoint */ | |
177 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; | |
178 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; | |
179 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; | |
180 | ||
181 | /* hardware watchpoint */ | |
182 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; | |
183 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; | |
184 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; | |
185 | }; | |
186 | ||
d6c44983 YZ |
187 | /* Per-process data. We don't bind this to a per-inferior registry |
188 | because of targets like x86 GNU/Linux that need to keep track of | |
189 | processes that aren't bound to any inferior (e.g., fork children, | |
190 | checkpoints). */ | |
9d19df75 | 191 | |
d6c44983 | 192 | struct aarch64_process_info |
9d19df75 | 193 | { |
d6c44983 YZ |
194 | /* Linked list. */ |
195 | struct aarch64_process_info *next; | |
9d19df75 | 196 | |
d6c44983 YZ |
197 | /* The process identifier. */ |
198 | pid_t pid; | |
9d19df75 | 199 | |
d6c44983 YZ |
200 | /* Copy of aarch64 hardware debug registers. */ |
201 | struct aarch64_debug_reg_state state; | |
202 | }; | |
203 | ||
204 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
205 | ||
206 | /* Find process data for process PID. */ | |
207 | ||
208 | static struct aarch64_process_info * | |
209 | aarch64_find_process_pid (pid_t pid) | |
210 | { | |
211 | struct aarch64_process_info *proc; | |
212 | ||
213 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
214 | if (proc->pid == pid) | |
215 | return proc; | |
216 | ||
217 | return NULL; | |
9d19df75 MS |
218 | } |
219 | ||
d6c44983 YZ |
220 | /* Add process data for process PID. Returns newly allocated info |
221 | object. */ | |
9d19df75 | 222 | |
d6c44983 YZ |
223 | static struct aarch64_process_info * |
224 | aarch64_add_process (pid_t pid) | |
9d19df75 | 225 | { |
d6c44983 | 226 | struct aarch64_process_info *proc; |
9d19df75 | 227 | |
d6c44983 YZ |
228 | proc = xcalloc (1, sizeof (*proc)); |
229 | proc->pid = pid; | |
9d19df75 | 230 | |
d6c44983 YZ |
231 | proc->next = aarch64_process_list; |
232 | aarch64_process_list = proc; | |
233 | ||
234 | return proc; | |
235 | } | |
236 | ||
237 | /* Get data specific info for process PID, creating it if necessary. | |
238 | Never returns NULL. */ | |
239 | ||
240 | static struct aarch64_process_info * | |
241 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 242 | { |
d6c44983 YZ |
243 | struct aarch64_process_info *proc; |
244 | ||
245 | proc = aarch64_find_process_pid (pid); | |
246 | if (proc == NULL) | |
247 | proc = aarch64_add_process (pid); | |
9d19df75 | 248 | |
d6c44983 | 249 | return proc; |
9d19df75 MS |
250 | } |
251 | ||
d6c44983 YZ |
252 | /* Called whenever GDB is no longer debugging process PID. It deletes |
253 | data structures that keep track of debug register state. */ | |
9d19df75 | 254 | |
d6c44983 YZ |
255 | static void |
256 | aarch64_forget_process (pid_t pid) | |
9d19df75 | 257 | { |
d6c44983 | 258 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 259 | |
d6c44983 YZ |
260 | proc = aarch64_process_list; |
261 | proc_link = &aarch64_process_list; | |
262 | ||
263 | while (proc != NULL) | |
9d19df75 | 264 | { |
d6c44983 YZ |
265 | if (proc->pid == pid) |
266 | { | |
267 | *proc_link = proc->next; | |
9d19df75 | 268 | |
d6c44983 YZ |
269 | xfree (proc); |
270 | return; | |
271 | } | |
272 | ||
273 | proc_link = &proc->next; | |
274 | proc = *proc_link; | |
275 | } | |
9d19df75 MS |
276 | } |
277 | ||
d6c44983 | 278 | /* Get debug registers state for process PID. */ |
9d19df75 MS |
279 | |
280 | static struct aarch64_debug_reg_state * | |
d6c44983 | 281 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 282 | { |
d6c44983 | 283 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
284 | } |
285 | ||
286 | /* Per-thread arch-specific data we want to keep. */ | |
287 | ||
288 | struct arch_lwp_info | |
289 | { | |
290 | /* When bit N is 1, it indicates the Nth hardware breakpoint or | |
291 | watchpoint register pair needs to be updated when the thread is | |
292 | resumed; see aarch64_linux_prepare_to_resume. */ | |
293 | dr_changed_t dr_changed_bp; | |
294 | dr_changed_t dr_changed_wp; | |
295 | }; | |
296 | ||
297 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint | |
298 | registers with data from *STATE. */ | |
299 | ||
300 | static void | |
301 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, | |
302 | int tid, int watchpoint) | |
303 | { | |
304 | int i, count; | |
305 | struct iovec iov; | |
306 | struct user_hwdebug_state regs; | |
307 | const CORE_ADDR *addr; | |
308 | const unsigned int *ctrl; | |
309 | ||
1aa4cd77 | 310 | memset (®s, 0, sizeof (regs)); |
9d19df75 | 311 | iov.iov_base = ®s; |
9d19df75 MS |
312 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; |
313 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; | |
314 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; | |
f45c82da YZ |
315 | if (count == 0) |
316 | return; | |
317 | iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) | |
318 | + sizeof (regs.dbg_regs [count - 1])); | |
9d19df75 MS |
319 | |
320 | for (i = 0; i < count; i++) | |
321 | { | |
322 | regs.dbg_regs[i].addr = addr[i]; | |
323 | regs.dbg_regs[i].ctrl = ctrl[i]; | |
324 | } | |
325 | ||
326 | if (ptrace (PTRACE_SETREGSET, tid, | |
327 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, | |
328 | (void *) &iov)) | |
329 | error (_("Unexpected error setting hardware debug registers")); | |
330 | } | |
331 | ||
332 | struct aarch64_dr_update_callback_param | |
333 | { | |
334 | int is_watchpoint; | |
335 | unsigned int idx; | |
336 | }; | |
337 | ||
d6c44983 | 338 | /* Callback for iterate_over_lwps. Records the |
9d19df75 MS |
339 | information about the change of one hardware breakpoint/watchpoint |
340 | setting for the thread LWP. | |
341 | The information is passed in via PTR. | |
342 | N.B. The actual updating of hardware debug registers is not | |
343 | carried out until the moment the thread is resumed. */ | |
344 | ||
345 | static int | |
346 | debug_reg_change_callback (struct lwp_info *lwp, void *ptr) | |
347 | { | |
348 | struct aarch64_dr_update_callback_param *param_p | |
349 | = (struct aarch64_dr_update_callback_param *) ptr; | |
350 | int pid = get_thread_id (lwp->ptid); | |
351 | int idx = param_p->idx; | |
352 | int is_watchpoint = param_p->is_watchpoint; | |
353 | struct arch_lwp_info *info = lwp->arch_private; | |
354 | dr_changed_t *dr_changed_ptr; | |
355 | dr_changed_t dr_changed; | |
356 | ||
357 | if (info == NULL) | |
358 | info = lwp->arch_private = XCNEW (struct arch_lwp_info); | |
359 | ||
c5e92cca | 360 | if (show_debug_regs) |
9d19df75 MS |
361 | { |
362 | fprintf_unfiltered (gdb_stdlog, | |
363 | "debug_reg_change_callback: \n\tOn entry:\n"); | |
364 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
365 | "\tpid%d, dr_changed_bp=0x%s, " |
366 | "dr_changed_wp=0x%s\n", | |
367 | pid, phex (info->dr_changed_bp, 8), | |
368 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
369 | } |
370 | ||
371 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp | |
372 | : &info->dr_changed_bp; | |
373 | dr_changed = *dr_changed_ptr; | |
374 | ||
375 | gdb_assert (idx >= 0 | |
376 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs | |
377 | : aarch64_num_bp_regs))); | |
378 | ||
379 | /* The actual update is done later just before resuming the lwp, | |
380 | we just mark that one register pair needs updating. */ | |
381 | DR_MARK_N_CHANGED (dr_changed, idx); | |
382 | *dr_changed_ptr = dr_changed; | |
383 | ||
384 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
385 | we can update its debug registers. */ | |
386 | if (!lwp->stopped) | |
387 | linux_stop_lwp (lwp); | |
388 | ||
c5e92cca | 389 | if (show_debug_regs) |
9d19df75 MS |
390 | { |
391 | fprintf_unfiltered (gdb_stdlog, | |
1d3ffd6b MS |
392 | "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, " |
393 | "dr_changed_wp=0x%s\n", | |
394 | pid, phex (info->dr_changed_bp, 8), | |
395 | phex (info->dr_changed_wp, 8)); | |
9d19df75 MS |
396 | } |
397 | ||
398 | /* Continue the iteration. */ | |
399 | return 0; | |
400 | } | |
401 | ||
402 | /* Notify each thread that their IDXth breakpoint/watchpoint register | |
403 | pair needs to be updated. The message will be recorded in each | |
404 | thread's arch-specific data area, the actual updating will be done | |
405 | when the thread is resumed. */ | |
406 | ||
407 | static void | |
408 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, | |
409 | int is_watchpoint, unsigned int idx) | |
410 | { | |
411 | struct aarch64_dr_update_callback_param param; | |
d6c44983 | 412 | ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
413 | |
414 | param.is_watchpoint = is_watchpoint; | |
415 | param.idx = idx; | |
416 | ||
d6c44983 | 417 | iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m); |
9d19df75 MS |
418 | } |
419 | ||
420 | /* Print the values of the cached breakpoint/watchpoint registers. */ | |
421 | ||
422 | static void | |
423 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, | |
424 | const char *func, CORE_ADDR addr, | |
425 | int len, int type) | |
426 | { | |
427 | int i; | |
428 | ||
429 | fprintf_unfiltered (gdb_stdlog, "%s", func); | |
430 | if (addr || len) | |
431 | fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)", | |
432 | (unsigned long) addr, len, | |
433 | type == hw_write ? "hw-write-watchpoint" | |
434 | : (type == hw_read ? "hw-read-watchpoint" | |
435 | : (type == hw_access ? "hw-access-watchpoint" | |
436 | : (type == hw_execute ? "hw-breakpoint" | |
437 | : "??unknown??")))); | |
438 | fprintf_unfiltered (gdb_stdlog, ":\n"); | |
439 | ||
440 | fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n"); | |
441 | for (i = 0; i < aarch64_num_bp_regs; i++) | |
442 | fprintf_unfiltered (gdb_stdlog, | |
443 | "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
444 | i, state->dr_addr_bp[i], | |
445 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); | |
446 | ||
447 | fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n"); | |
448 | for (i = 0; i < aarch64_num_wp_regs; i++) | |
449 | fprintf_unfiltered (gdb_stdlog, | |
450 | "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", | |
451 | i, state->dr_addr_wp[i], | |
452 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); | |
453 | } | |
454 | ||
455 | /* Fill GDB's register array with the general-purpose register values | |
456 | from the current thread. */ | |
457 | ||
458 | static void | |
459 | fetch_gregs_from_thread (struct regcache *regcache) | |
460 | { | |
461 | int ret, regno, tid; | |
462 | elf_gregset_t regs; | |
463 | struct iovec iovec; | |
464 | ||
465 | tid = get_thread_id (inferior_ptid); | |
466 | ||
467 | iovec.iov_base = ®s; | |
468 | iovec.iov_len = sizeof (regs); | |
469 | ||
470 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
471 | if (ret < 0) | |
472 | perror_with_name (_("Unable to fetch general registers.")); | |
473 | ||
474 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
475 | regcache_raw_supply (regcache, regno, | |
476 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
477 | } | |
478 | ||
479 | /* Store to the current thread the valid general-purpose register | |
480 | values in the GDB's register array. */ | |
481 | ||
482 | static void | |
483 | store_gregs_to_thread (const struct regcache *regcache) | |
484 | { | |
485 | int ret, regno, tid; | |
486 | elf_gregset_t regs; | |
487 | struct iovec iovec; | |
488 | ||
489 | tid = get_thread_id (inferior_ptid); | |
490 | ||
491 | iovec.iov_base = ®s; | |
492 | iovec.iov_len = sizeof (regs); | |
493 | ||
494 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
495 | if (ret < 0) | |
496 | perror_with_name (_("Unable to fetch general registers.")); | |
497 | ||
498 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
499 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
500 | regcache_raw_collect (regcache, regno, | |
501 | (char *) ®s[regno - AARCH64_X0_REGNUM]); | |
502 | ||
503 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
504 | if (ret < 0) | |
505 | perror_with_name (_("Unable to store general registers.")); | |
506 | } | |
507 | ||
508 | /* Fill GDB's register array with the fp/simd register values | |
509 | from the current thread. */ | |
510 | ||
511 | static void | |
512 | fetch_fpregs_from_thread (struct regcache *regcache) | |
513 | { | |
514 | int ret, regno, tid; | |
515 | elf_fpregset_t regs; | |
516 | struct iovec iovec; | |
517 | ||
518 | tid = get_thread_id (inferior_ptid); | |
519 | ||
520 | iovec.iov_base = ®s; | |
521 | iovec.iov_len = sizeof (regs); | |
522 | ||
523 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
524 | if (ret < 0) | |
525 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
526 | ||
527 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
528 | regcache_raw_supply (regcache, regno, | |
529 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
530 | ||
531 | regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
532 | regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
533 | } | |
534 | ||
535 | /* Store to the current thread the valid fp/simd register | |
536 | values in the GDB's register array. */ | |
537 | ||
538 | static void | |
539 | store_fpregs_to_thread (const struct regcache *regcache) | |
540 | { | |
541 | int ret, regno, tid; | |
542 | elf_fpregset_t regs; | |
543 | struct iovec iovec; | |
544 | ||
545 | tid = get_thread_id (inferior_ptid); | |
546 | ||
547 | iovec.iov_base = ®s; | |
548 | iovec.iov_len = sizeof (regs); | |
549 | ||
550 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
551 | if (ret < 0) | |
552 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
553 | ||
554 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
555 | if (REG_VALID == regcache_register_status (regcache, regno)) | |
556 | regcache_raw_collect (regcache, regno, | |
557 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
558 | ||
559 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM)) | |
560 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); | |
561 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM)) | |
562 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); | |
563 | ||
564 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
565 | if (ret < 0) | |
566 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
567 | } | |
568 | ||
569 | /* Implement the "to_fetch_register" target_ops method. */ | |
570 | ||
571 | static void | |
572 | aarch64_linux_fetch_inferior_registers (struct target_ops *ops, | |
573 | struct regcache *regcache, | |
574 | int regno) | |
575 | { | |
576 | if (regno == -1) | |
577 | { | |
578 | fetch_gregs_from_thread (regcache); | |
579 | fetch_fpregs_from_thread (regcache); | |
580 | } | |
581 | else if (regno < AARCH64_V0_REGNUM) | |
582 | fetch_gregs_from_thread (regcache); | |
583 | else | |
584 | fetch_fpregs_from_thread (regcache); | |
585 | } | |
586 | ||
587 | /* Implement the "to_store_register" target_ops method. */ | |
588 | ||
589 | static void | |
590 | aarch64_linux_store_inferior_registers (struct target_ops *ops, | |
591 | struct regcache *regcache, | |
592 | int regno) | |
593 | { | |
594 | if (regno == -1) | |
595 | { | |
596 | store_gregs_to_thread (regcache); | |
597 | store_fpregs_to_thread (regcache); | |
598 | } | |
599 | else if (regno < AARCH64_V0_REGNUM) | |
600 | store_gregs_to_thread (regcache); | |
601 | else | |
602 | store_fpregs_to_thread (regcache); | |
603 | } | |
604 | ||
605 | /* Fill register REGNO (if it is a general-purpose register) in | |
606 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
607 | do this for all registers. */ | |
608 | ||
609 | void | |
610 | fill_gregset (const struct regcache *regcache, | |
611 | gdb_gregset_t *gregsetp, int regno) | |
612 | { | |
d4d793bf AA |
613 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
614 | regno, (gdb_byte *) gregsetp, | |
615 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
616 | } |
617 | ||
618 | /* Fill GDB's register array with the general-purpose register values | |
619 | in *GREGSETP. */ | |
620 | ||
621 | void | |
622 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
623 | { | |
d4d793bf AA |
624 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
625 | (const gdb_byte *) gregsetp, | |
626 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
627 | } |
628 | ||
629 | /* Fill register REGNO (if it is a floating-point register) in | |
630 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
631 | do this for all registers. */ | |
632 | ||
633 | void | |
634 | fill_fpregset (const struct regcache *regcache, | |
635 | gdb_fpregset_t *fpregsetp, int regno) | |
636 | { | |
d4d793bf AA |
637 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
638 | regno, (gdb_byte *) fpregsetp, | |
639 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
640 | } |
641 | ||
642 | /* Fill GDB's register array with the floating-point register values | |
643 | in *FPREGSETP. */ | |
644 | ||
645 | void | |
646 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
647 | { | |
d4d793bf AA |
648 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
649 | (const gdb_byte *) fpregsetp, | |
650 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
651 | } |
652 | ||
653 | /* Called when resuming a thread. | |
654 | The hardware debug registers are updated when there is any change. */ | |
655 | ||
656 | static void | |
657 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) | |
658 | { | |
659 | struct arch_lwp_info *info = lwp->arch_private; | |
660 | ||
661 | /* NULL means this is the main thread still going through the shell, | |
662 | or, no watchpoint has been set yet. In that case, there's | |
663 | nothing to do. */ | |
664 | if (info == NULL) | |
665 | return; | |
666 | ||
667 | if (DR_HAS_CHANGED (info->dr_changed_bp) | |
668 | || DR_HAS_CHANGED (info->dr_changed_wp)) | |
669 | { | |
dfd4cc63 | 670 | int tid = ptid_get_lwp (lwp->ptid); |
d6c44983 YZ |
671 | struct aarch64_debug_reg_state *state |
672 | = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid)); | |
9d19df75 | 673 | |
c5e92cca | 674 | if (show_debug_regs) |
9d19df75 MS |
675 | fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid); |
676 | ||
677 | /* Watchpoints. */ | |
678 | if (DR_HAS_CHANGED (info->dr_changed_wp)) | |
679 | { | |
680 | aarch64_linux_set_debug_regs (state, tid, 1); | |
681 | DR_CLEAR_CHANGED (info->dr_changed_wp); | |
682 | } | |
683 | ||
684 | /* Breakpoints. */ | |
685 | if (DR_HAS_CHANGED (info->dr_changed_bp)) | |
686 | { | |
687 | aarch64_linux_set_debug_regs (state, tid, 0); | |
688 | DR_CLEAR_CHANGED (info->dr_changed_bp); | |
689 | } | |
690 | } | |
691 | } | |
692 | ||
693 | static void | |
694 | aarch64_linux_new_thread (struct lwp_info *lp) | |
695 | { | |
696 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
697 | ||
698 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
699 | for this thread need to be initialized. */ | |
700 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); | |
701 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); | |
702 | ||
703 | lp->arch_private = info; | |
704 | } | |
d6c44983 YZ |
705 | |
706 | /* linux_nat_new_fork hook. */ | |
707 | ||
708 | static void | |
709 | aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
710 | { | |
711 | pid_t parent_pid; | |
712 | struct aarch64_debug_reg_state *parent_state; | |
713 | struct aarch64_debug_reg_state *child_state; | |
714 | ||
715 | /* NULL means no watchpoint has ever been set in the parent. In | |
716 | that case, there's nothing to do. */ | |
717 | if (parent->arch_private == NULL) | |
718 | return; | |
719 | ||
720 | /* GDB core assumes the child inherits the watchpoints/hw | |
721 | breakpoints of the parent, and will remove them all from the | |
722 | forked off process. Copy the debug registers mirrors into the | |
723 | new process so that all breakpoints and watchpoints can be | |
724 | removed together. */ | |
725 | ||
726 | parent_pid = ptid_get_pid (parent->ptid); | |
727 | parent_state = aarch64_get_debug_reg_state (parent_pid); | |
728 | child_state = aarch64_get_debug_reg_state (child_pid); | |
729 | *child_state = *parent_state; | |
730 | } | |
9d19df75 MS |
731 | \f |
732 | ||
733 | /* Called by libthread_db. Returns a pointer to the thread local | |
734 | storage (or its descriptor). */ | |
735 | ||
736 | ps_err_e | |
737 | ps_get_thread_area (const struct ps_prochandle *ph, | |
738 | lwpid_t lwpid, int idx, void **base) | |
739 | { | |
740 | struct iovec iovec; | |
741 | uint64_t reg; | |
742 | ||
743 | iovec.iov_base = ® | |
744 | iovec.iov_len = sizeof (reg); | |
745 | ||
746 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) | |
747 | return PS_ERR; | |
748 | ||
749 | /* IDX is the bias from the thread pointer to the beginning of the | |
750 | thread descriptor. It has to be subtracted due to implementation | |
751 | quirks in libthread_db. */ | |
752 | *base = (void *) (reg - idx); | |
753 | ||
754 | return PS_OK; | |
755 | } | |
756 | \f | |
757 | ||
758 | /* Get the hardware debug register capacity information. */ | |
759 | ||
760 | static void | |
761 | aarch64_linux_get_debug_reg_capacity (void) | |
762 | { | |
763 | int tid; | |
764 | struct iovec iov; | |
765 | struct user_hwdebug_state dreg_state; | |
766 | ||
767 | tid = get_thread_id (inferior_ptid); | |
768 | iov.iov_base = &dreg_state; | |
769 | iov.iov_len = sizeof (dreg_state); | |
770 | ||
771 | /* Get hardware watchpoint register info. */ | |
772 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 | |
773 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
774 | { | |
775 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
776 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) | |
777 | { | |
1d3ffd6b MS |
778 | warning (_("Unexpected number of hardware watchpoint registers" |
779 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
780 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
781 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; | |
782 | } | |
783 | } | |
784 | else | |
785 | { | |
1d3ffd6b MS |
786 | warning (_("Unable to determine the number of hardware watchpoints" |
787 | " available.")); | |
9d19df75 MS |
788 | aarch64_num_wp_regs = 0; |
789 | } | |
790 | ||
791 | /* Get hardware breakpoint register info. */ | |
792 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 | |
793 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
794 | { | |
795 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
796 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) | |
797 | { | |
1d3ffd6b MS |
798 | warning (_("Unexpected number of hardware breakpoint registers" |
799 | " reported by ptrace, got %d, expected %d."), | |
9d19df75 MS |
800 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
801 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; | |
802 | } | |
803 | } | |
804 | else | |
805 | { | |
1d3ffd6b MS |
806 | warning (_("Unable to determine the number of hardware breakpoints" |
807 | " available.")); | |
9d19df75 MS |
808 | aarch64_num_bp_regs = 0; |
809 | } | |
810 | } | |
811 | ||
2e97a79e TT |
812 | static void (*super_post_startup_inferior) (struct target_ops *self, |
813 | ptid_t ptid); | |
9d19df75 MS |
814 | |
815 | /* Implement the "to_post_startup_inferior" target_ops method. */ | |
816 | ||
817 | static void | |
2e97a79e TT |
818 | aarch64_linux_child_post_startup_inferior (struct target_ops *self, |
819 | ptid_t ptid) | |
9d19df75 | 820 | { |
d6c44983 | 821 | aarch64_forget_process (ptid_get_pid (ptid)); |
9d19df75 | 822 | aarch64_linux_get_debug_reg_capacity (); |
2e97a79e | 823 | super_post_startup_inferior (self, ptid); |
9d19df75 MS |
824 | } |
825 | ||
826 | /* Implement the "to_read_description" target_ops method. */ | |
827 | ||
828 | static const struct target_desc * | |
829 | aarch64_linux_read_description (struct target_ops *ops) | |
830 | { | |
9d19df75 MS |
831 | return tdesc_aarch64; |
832 | } | |
833 | ||
834 | /* Given the (potentially unaligned) watchpoint address in ADDR and | |
835 | length in LEN, return the aligned address and aligned length in | |
836 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned | |
837 | aligned address and length will be valid values to write to the | |
838 | hardware watchpoint value and control registers. | |
839 | ||
840 | The given watchpoint may get truncated if more than one hardware | |
841 | register is needed to cover the watched region. *NEXT_ADDR_P | |
842 | and *NEXT_LEN_P, if non-NULL, will return the address and length | |
843 | of the remaining part of the watchpoint (which can be processed | |
844 | by calling this routine again to generate another aligned address | |
845 | and length pair. | |
846 | ||
847 | See the comment above the function of the same name in | |
848 | gdbserver/linux-aarch64-low.c for more information. */ | |
849 | ||
850 | static void | |
851 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, | |
852 | int *aligned_len_p, CORE_ADDR *next_addr_p, | |
853 | int *next_len_p) | |
854 | { | |
855 | int aligned_len; | |
856 | unsigned int offset; | |
857 | CORE_ADDR aligned_addr; | |
858 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; | |
859 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; | |
860 | ||
861 | /* As assumed by the algorithm. */ | |
862 | gdb_assert (alignment == max_wp_len); | |
863 | ||
864 | if (len <= 0) | |
865 | return; | |
866 | ||
867 | /* Address to be put into the hardware watchpoint value register | |
868 | must be aligned. */ | |
869 | offset = addr & (alignment - 1); | |
870 | aligned_addr = addr - offset; | |
871 | ||
872 | gdb_assert (offset >= 0 && offset < alignment); | |
873 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); | |
874 | gdb_assert (offset + len > 0); | |
875 | ||
876 | if (offset + len >= max_wp_len) | |
877 | { | |
878 | /* Need more than one watchpoint registers; truncate it at the | |
879 | alignment boundary. */ | |
880 | aligned_len = max_wp_len; | |
881 | len -= (max_wp_len - offset); | |
882 | addr += (max_wp_len - offset); | |
883 | gdb_assert ((addr & (alignment - 1)) == 0); | |
884 | } | |
885 | else | |
886 | { | |
887 | /* Find the smallest valid length that is large enough to | |
888 | accommodate this watchpoint. */ | |
889 | static const unsigned char | |
890 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = | |
891 | { 1, 2, 4, 4, 8, 8, 8, 8 }; | |
892 | ||
893 | aligned_len = aligned_len_array[offset + len - 1]; | |
894 | addr += len; | |
895 | len = 0; | |
896 | } | |
897 | ||
898 | if (aligned_addr_p) | |
899 | *aligned_addr_p = aligned_addr; | |
900 | if (aligned_len_p) | |
901 | *aligned_len_p = aligned_len; | |
902 | if (next_addr_p) | |
903 | *next_addr_p = addr; | |
904 | if (next_len_p) | |
905 | *next_len_p = len; | |
906 | } | |
907 | ||
908 | /* Returns the number of hardware watchpoints of type TYPE that we can | |
909 | set. Value is positive if we can set CNT watchpoints, zero if | |
910 | setting watchpoints of type TYPE is not supported, and negative if | |
911 | CNT is more than the maximum number of watchpoints of type TYPE | |
912 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
913 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
914 | CNT is the number of such watchpoints used so far (including this | |
915 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
916 | currently enabled. | |
917 | ||
918 | We always return 1 here because we don't have enough information | |
919 | about possible overlap of addresses that they want to watch. As an | |
920 | extreme example, consider the case where all the watchpoints watch | |
921 | the same address and the same region length: then we can handle a | |
922 | virtually unlimited number of watchpoints, due to debug register | |
923 | sharing implemented via reference counts. */ | |
924 | ||
925 | static int | |
5461485a TT |
926 | aarch64_linux_can_use_hw_breakpoint (struct target_ops *self, |
927 | int type, int cnt, int othertype) | |
9d19df75 MS |
928 | { |
929 | return 1; | |
930 | } | |
931 | ||
932 | /* ptrace expects control registers to be formatted as follows: | |
933 | ||
934 | 31 13 5 3 1 0 | |
935 | +--------------------------------+----------+------+------+----+ | |
936 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | | |
937 | +--------------------------------+----------+------+------+----+ | |
938 | ||
939 | The TYPE field is ignored for breakpoints. */ | |
940 | ||
941 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) | |
942 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) | |
943 | ||
944 | /* Utility function that returns the length in bytes of a watchpoint | |
945 | according to the content of a hardware debug control register CTRL. | |
946 | Note that the kernel currently only supports the following Byte | |
947 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means | |
948 | that for a hardware watchpoint, its valid length can only be 1 | |
949 | byte, 2 bytes, 4 bytes or 8 bytes. */ | |
950 | ||
951 | static inline unsigned int | |
952 | aarch64_watchpoint_length (unsigned int ctrl) | |
953 | { | |
954 | switch (DR_CONTROL_LENGTH (ctrl)) | |
955 | { | |
956 | case 0x01: | |
957 | return 1; | |
958 | case 0x03: | |
959 | return 2; | |
960 | case 0x0f: | |
961 | return 4; | |
962 | case 0xff: | |
963 | return 8; | |
964 | default: | |
965 | return 0; | |
966 | } | |
967 | } | |
968 | ||
969 | /* Given the hardware breakpoint or watchpoint type TYPE and its | |
970 | length LEN, return the expected encoding for a hardware | |
971 | breakpoint/watchpoint control register. */ | |
972 | ||
973 | static unsigned int | |
974 | aarch64_point_encode_ctrl_reg (int type, int len) | |
975 | { | |
976 | unsigned int ctrl, ttype; | |
977 | ||
978 | /* type */ | |
979 | switch (type) | |
980 | { | |
981 | case hw_write: | |
982 | ttype = 2; | |
983 | break; | |
984 | case hw_read: | |
985 | ttype = 1; | |
986 | break; | |
987 | case hw_access: | |
988 | ttype = 3; | |
989 | break; | |
990 | case hw_execute: | |
991 | ttype = 0; | |
992 | break; | |
993 | default: | |
994 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); | |
995 | } | |
996 | ctrl = ttype << 3; | |
997 | ||
998 | /* length bitmask */ | |
999 | ctrl |= ((1 << len) - 1) << 5; | |
1000 | /* enabled at el0 */ | |
1001 | ctrl |= (2 << 1) | 1; | |
1002 | ||
1003 | return ctrl; | |
1004 | } | |
1005 | ||
1006 | /* Addresses to be written to the hardware breakpoint and watchpoint | |
1007 | value registers need to be aligned; the alignment is 4-byte and | |
1008 | 8-type respectively. Linux kernel rejects any non-aligned address | |
1009 | it receives from the related ptrace call. Furthermore, the kernel | |
1010 | currently only supports the following Byte Address Select (BAS) | |
1011 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware | |
1012 | watchpoint to be accepted by the kernel (via ptrace call), its | |
1013 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. | |
1014 | Despite these limitations, the unaligned watchpoint is supported in | |
1015 | this port. | |
1016 | ||
1017 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ | |
1018 | ||
1019 | static int | |
1020 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) | |
1021 | { | |
1022 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT | |
1023 | : AARCH64_HBP_ALIGNMENT; | |
1024 | ||
1025 | if (addr & (alignment - 1)) | |
1026 | return 0; | |
1027 | ||
1028 | if (len != 8 && len != 4 && len != 2 && len != 1) | |
1029 | return 0; | |
1030 | ||
1031 | return 1; | |
1032 | } | |
1033 | ||
1034 | /* Record the insertion of one breakpoint/watchpoint, as represented | |
1035 | by ADDR and CTRL, in the cached debug register state area *STATE. */ | |
1036 | ||
1037 | static int | |
1038 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, | |
1039 | int type, CORE_ADDR addr, int len) | |
1040 | { | |
1041 | int i, idx, num_regs, is_watchpoint; | |
1042 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1043 | CORE_ADDR *dr_addr_p; | |
1044 | ||
1045 | /* Set up state pointers. */ | |
1046 | is_watchpoint = (type != hw_execute); | |
1047 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1048 | if (is_watchpoint) | |
1049 | { | |
1050 | num_regs = aarch64_num_wp_regs; | |
1051 | dr_addr_p = state->dr_addr_wp; | |
1052 | dr_ctrl_p = state->dr_ctrl_wp; | |
1053 | dr_ref_count = state->dr_ref_count_wp; | |
1054 | } | |
1055 | else | |
1056 | { | |
1057 | num_regs = aarch64_num_bp_regs; | |
1058 | dr_addr_p = state->dr_addr_bp; | |
1059 | dr_ctrl_p = state->dr_ctrl_bp; | |
1060 | dr_ref_count = state->dr_ref_count_bp; | |
1061 | } | |
1062 | ||
1063 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1064 | ||
1065 | /* Find an existing or free register in our cache. */ | |
1066 | idx = -1; | |
1067 | for (i = 0; i < num_regs; ++i) | |
1068 | { | |
1069 | if ((dr_ctrl_p[i] & 1) == 0) | |
1070 | { | |
1071 | gdb_assert (dr_ref_count[i] == 0); | |
1072 | idx = i; | |
1073 | /* no break; continue hunting for an existing one. */ | |
1074 | } | |
1075 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1076 | { | |
1077 | gdb_assert (dr_ref_count[i] != 0); | |
1078 | idx = i; | |
1079 | break; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | /* No space. */ | |
1084 | if (idx == -1) | |
1085 | return -1; | |
1086 | ||
1087 | /* Update our cache. */ | |
1088 | if ((dr_ctrl_p[idx] & 1) == 0) | |
1089 | { | |
1090 | /* new entry */ | |
1091 | dr_addr_p[idx] = addr; | |
1092 | dr_ctrl_p[idx] = ctrl; | |
1093 | dr_ref_count[idx] = 1; | |
1094 | /* Notify the change. */ | |
1095 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); | |
1096 | } | |
1097 | else | |
1098 | { | |
1099 | /* existing entry */ | |
1100 | dr_ref_count[idx]++; | |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | /* Record the removal of one breakpoint/watchpoint, as represented by | |
1107 | ADDR and CTRL, in the cached debug register state area *STATE. */ | |
1108 | ||
1109 | static int | |
1110 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, | |
1111 | int type, CORE_ADDR addr, int len) | |
1112 | { | |
1113 | int i, num_regs, is_watchpoint; | |
1114 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
1115 | CORE_ADDR *dr_addr_p; | |
1116 | ||
1117 | /* Set up state pointers. */ | |
1118 | is_watchpoint = (type != hw_execute); | |
1119 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
1120 | if (is_watchpoint) | |
1121 | { | |
1122 | num_regs = aarch64_num_wp_regs; | |
1123 | dr_addr_p = state->dr_addr_wp; | |
1124 | dr_ctrl_p = state->dr_ctrl_wp; | |
1125 | dr_ref_count = state->dr_ref_count_wp; | |
1126 | } | |
1127 | else | |
1128 | { | |
1129 | num_regs = aarch64_num_bp_regs; | |
1130 | dr_addr_p = state->dr_addr_bp; | |
1131 | dr_ctrl_p = state->dr_ctrl_bp; | |
1132 | dr_ref_count = state->dr_ref_count_bp; | |
1133 | } | |
1134 | ||
1135 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
1136 | ||
1137 | /* Find the entry that matches the ADDR and CTRL. */ | |
1138 | for (i = 0; i < num_regs; ++i) | |
1139 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
1140 | { | |
1141 | gdb_assert (dr_ref_count[i] != 0); | |
1142 | break; | |
1143 | } | |
1144 | ||
1145 | /* Not found. */ | |
1146 | if (i == num_regs) | |
1147 | return -1; | |
1148 | ||
1149 | /* Clear our cache. */ | |
1150 | if (--dr_ref_count[i] == 0) | |
1151 | { | |
1152 | /* Clear the enable bit. */ | |
1153 | ctrl &= ~1; | |
1154 | dr_addr_p[i] = 0; | |
1155 | dr_ctrl_p[i] = ctrl; | |
1156 | /* Notify the change. */ | |
1157 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); | |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | /* Implement insertion and removal of a single breakpoint. */ | |
1164 | ||
1165 | static int | |
1166 | aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1167 | { | |
1168 | struct aarch64_debug_reg_state *state; | |
1169 | ||
1170 | /* The hardware breakpoint on AArch64 should always be 4-byte | |
1171 | aligned. */ | |
1172 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) | |
1173 | return -1; | |
1174 | ||
d6c44983 | 1175 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
1176 | |
1177 | if (is_insert) | |
1178 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1179 | else | |
1180 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1181 | } | |
1182 | ||
0d5ed153 | 1183 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
9d19df75 MS |
1184 | Return 0 on success, -1 on failure. */ |
1185 | ||
1186 | static int | |
23a26771 TT |
1187 | aarch64_linux_insert_hw_breakpoint (struct target_ops *self, |
1188 | struct gdbarch *gdbarch, | |
9d19df75 MS |
1189 | struct bp_target_info *bp_tgt) |
1190 | { | |
1191 | int ret; | |
0d5ed153 | 1192 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
9d19df75 MS |
1193 | const int len = 4; |
1194 | const int type = hw_execute; | |
1195 | ||
c5e92cca | 1196 | if (show_debug_regs) |
9d19df75 MS |
1197 | fprintf_unfiltered |
1198 | (gdb_stdlog, | |
1199 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1200 | (unsigned long) addr, len); | |
1201 | ||
1202 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */); | |
1203 | ||
c5e92cca | 1204 | if (show_debug_regs) |
d6c44983 YZ |
1205 | { |
1206 | struct aarch64_debug_reg_state *state | |
1207 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1208 | ||
1209 | aarch64_show_debug_reg_state (state, | |
1210 | "insert_hw_watchpoint", addr, len, type); | |
1211 | } | |
9d19df75 MS |
1212 | |
1213 | return ret; | |
1214 | } | |
1215 | ||
1216 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
1217 | Return 0 on success, -1 on failure. */ | |
1218 | ||
1219 | static int | |
a64dc96c TT |
1220 | aarch64_linux_remove_hw_breakpoint (struct target_ops *self, |
1221 | struct gdbarch *gdbarch, | |
9d19df75 MS |
1222 | struct bp_target_info *bp_tgt) |
1223 | { | |
1224 | int ret; | |
1225 | CORE_ADDR addr = bp_tgt->placed_address; | |
1226 | const int len = 4; | |
1227 | const int type = hw_execute; | |
1228 | ||
c5e92cca | 1229 | if (show_debug_regs) |
9d19df75 MS |
1230 | fprintf_unfiltered |
1231 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
1232 | (unsigned long) addr, len); | |
1233 | ||
1234 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */); | |
1235 | ||
c5e92cca | 1236 | if (show_debug_regs) |
d6c44983 YZ |
1237 | { |
1238 | struct aarch64_debug_reg_state *state | |
1239 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1240 | ||
1241 | aarch64_show_debug_reg_state (state, | |
1242 | "remove_hw_watchpoint", addr, len, type); | |
1243 | } | |
9d19df75 MS |
1244 | |
1245 | return ret; | |
1246 | } | |
1247 | ||
1248 | /* This is essentially the same as aarch64_handle_breakpoint, apart | |
1249 | from that it is an aligned watchpoint to be handled. */ | |
1250 | ||
1251 | static int | |
1252 | aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1253 | int is_insert) | |
1254 | { | |
d6c44983 YZ |
1255 | struct aarch64_debug_reg_state *state |
1256 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 MS |
1257 | |
1258 | if (is_insert) | |
1259 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
1260 | else | |
1261 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
1262 | } | |
1263 | ||
1264 | /* Insert/remove unaligned watchpoint by calling | |
1265 | aarch64_align_watchpoint repeatedly until the whole watched region, | |
1266 | as represented by ADDR and LEN, has been properly aligned and ready | |
1267 | to be written to one or more hardware watchpoint registers. | |
1268 | IS_INSERT indicates whether this is an insertion or a deletion. | |
1269 | Return 0 if succeed. */ | |
1270 | ||
1271 | static int | |
1272 | aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len, | |
1273 | int is_insert) | |
1274 | { | |
d6c44983 YZ |
1275 | struct aarch64_debug_reg_state *state |
1276 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 MS |
1277 | |
1278 | while (len > 0) | |
1279 | { | |
1280 | CORE_ADDR aligned_addr; | |
1281 | int aligned_len, ret; | |
1282 | ||
1283 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, | |
1284 | &addr, &len); | |
1285 | ||
1286 | if (is_insert) | |
1287 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, | |
1288 | aligned_len); | |
1289 | else | |
1290 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, | |
1291 | aligned_len); | |
1292 | ||
c5e92cca | 1293 | if (show_debug_regs) |
9d19df75 MS |
1294 | fprintf_unfiltered (gdb_stdlog, |
1295 | "handle_unaligned_watchpoint: is_insert: %d\n" | |
1296 | " aligned_addr: 0x%08lx, aligned_len: %d\n" | |
1297 | " next_addr: 0x%08lx, next_len: %d\n", | |
1298 | is_insert, aligned_addr, aligned_len, addr, len); | |
1299 | ||
1300 | if (ret != 0) | |
1301 | return ret; | |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | /* Implements insertion and removal of a single watchpoint. */ | |
1308 | ||
1309 | static int | |
1310 | aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert) | |
1311 | { | |
1312 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) | |
1313 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); | |
1314 | else | |
1315 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); | |
1316 | } | |
1317 | ||
1318 | /* Implement the "to_insert_watchpoint" target_ops method. | |
1319 | ||
1320 | Insert a watchpoint to watch a memory region which starts at | |
1321 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
1322 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
1323 | ||
1324 | static int | |
7bb99c53 TT |
1325 | aarch64_linux_insert_watchpoint (struct target_ops *self, |
1326 | CORE_ADDR addr, int len, int type, | |
9d19df75 MS |
1327 | struct expression *cond) |
1328 | { | |
1329 | int ret; | |
1330 | ||
c5e92cca | 1331 | if (show_debug_regs) |
9d19df75 MS |
1332 | fprintf_unfiltered (gdb_stdlog, |
1333 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1334 | (unsigned long) addr, len); | |
1335 | ||
1336 | gdb_assert (type != hw_execute); | |
1337 | ||
1338 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */); | |
1339 | ||
c5e92cca | 1340 | if (show_debug_regs) |
d6c44983 YZ |
1341 | { |
1342 | struct aarch64_debug_reg_state *state | |
1343 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1344 | ||
1345 | aarch64_show_debug_reg_state (state, | |
1346 | "insert_watchpoint", addr, len, type); | |
1347 | } | |
9d19df75 MS |
1348 | |
1349 | return ret; | |
1350 | } | |
1351 | ||
1352 | /* Implement the "to_remove_watchpoint" target_ops method. | |
1353 | Remove a watchpoint that watched the memory region which starts at | |
1354 | address ADDR, whose length is LEN bytes, and for accesses of the | |
1355 | type TYPE. Return 0 on success, -1 on failure. */ | |
1356 | ||
1357 | static int | |
11b5219a TT |
1358 | aarch64_linux_remove_watchpoint (struct target_ops *self, |
1359 | CORE_ADDR addr, int len, int type, | |
9d19df75 MS |
1360 | struct expression *cond) |
1361 | { | |
1362 | int ret; | |
1363 | ||
c5e92cca | 1364 | if (show_debug_regs) |
9d19df75 MS |
1365 | fprintf_unfiltered (gdb_stdlog, |
1366 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
1367 | (unsigned long) addr, len); | |
1368 | ||
1369 | gdb_assert (type != hw_execute); | |
1370 | ||
1371 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */); | |
1372 | ||
c5e92cca | 1373 | if (show_debug_regs) |
d6c44983 YZ |
1374 | { |
1375 | struct aarch64_debug_reg_state *state | |
1376 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1377 | ||
1378 | aarch64_show_debug_reg_state (state, | |
1379 | "remove_watchpoint", addr, len, type); | |
1380 | } | |
9d19df75 MS |
1381 | |
1382 | return ret; | |
1383 | } | |
1384 | ||
1385 | /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */ | |
1386 | ||
1387 | static int | |
31568a15 TT |
1388 | aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1389 | CORE_ADDR addr, int len) | |
9d19df75 MS |
1390 | { |
1391 | CORE_ADDR aligned_addr; | |
1392 | ||
1393 | /* Can not set watchpoints for zero or negative lengths. */ | |
1394 | if (len <= 0) | |
1395 | return 0; | |
1396 | ||
1397 | /* Must have hardware watchpoint debug register(s). */ | |
1398 | if (aarch64_num_wp_regs == 0) | |
1399 | return 0; | |
1400 | ||
1401 | /* We support unaligned watchpoint address and arbitrary length, | |
1402 | as long as the size of the whole watched area after alignment | |
1403 | doesn't exceed size of the total area that all watchpoint debug | |
1404 | registers can watch cooperatively. | |
1405 | ||
1406 | This is a very relaxed rule, but unfortunately there are | |
1407 | limitations, e.g. false-positive hits, due to limited support of | |
1408 | hardware debug registers in the kernel. See comment above | |
1409 | aarch64_align_watchpoint for more information. */ | |
1410 | ||
1411 | aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1); | |
1412 | if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG | |
1413 | < addr + len) | |
1414 | return 0; | |
1415 | ||
1416 | /* All tests passed so we are likely to be able to set the watchpoint. | |
1417 | The reason that it is 'likely' rather than 'must' is because | |
1418 | we don't check the current usage of the watchpoint registers, and | |
1419 | there may not be enough registers available for this watchpoint. | |
1420 | Ideally we should check the cached debug register state, however | |
1421 | the checking is costly. */ | |
1422 | return 1; | |
1423 | } | |
1424 | ||
1425 | /* Implement the "to_stopped_data_address" target_ops method. */ | |
1426 | ||
1427 | static int | |
1428 | aarch64_linux_stopped_data_address (struct target_ops *target, | |
1429 | CORE_ADDR *addr_p) | |
1430 | { | |
1431 | siginfo_t siginfo; | |
1432 | int i, tid; | |
1433 | struct aarch64_debug_reg_state *state; | |
1434 | ||
1435 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1436 | return 0; | |
1437 | ||
1438 | /* This must be a hardware breakpoint. */ | |
1439 | if (siginfo.si_signo != SIGTRAP | |
1440 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
1441 | return 0; | |
1442 | ||
1443 | /* Check if the address matches any watched address. */ | |
d6c44983 | 1444 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
1445 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
1446 | { | |
1447 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); | |
1448 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
1449 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; | |
1450 | ||
1451 | if (state->dr_ref_count_wp[i] | |
1452 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
1453 | && addr_trap >= addr_watch | |
1454 | && addr_trap < addr_watch + len) | |
1455 | { | |
1456 | *addr_p = addr_trap; | |
1457 | return 1; | |
1458 | } | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | /* Implement the "to_stopped_by_watchpoint" target_ops method. */ | |
1465 | ||
1466 | static int | |
6a109b6b | 1467 | aarch64_linux_stopped_by_watchpoint (struct target_ops *ops) |
9d19df75 MS |
1468 | { |
1469 | CORE_ADDR addr; | |
1470 | ||
6a109b6b | 1471 | return aarch64_linux_stopped_data_address (ops, &addr); |
9d19df75 MS |
1472 | } |
1473 | ||
1474 | /* Implement the "to_watchpoint_addr_within_range" target_ops method. */ | |
1475 | ||
1476 | static int | |
1477 | aarch64_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1478 | CORE_ADDR addr, | |
1479 | CORE_ADDR start, int length) | |
1480 | { | |
1481 | return start <= addr && start + length - 1 >= addr; | |
1482 | } | |
1483 | ||
1484 | /* Define AArch64 maintenance commands. */ | |
1485 | ||
1486 | static void | |
1487 | add_show_debug_regs_command (void) | |
1488 | { | |
1489 | /* A maintenance command to enable printing the internal DRi mirror | |
1490 | variables. */ | |
1491 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
c5e92cca | 1492 | &show_debug_regs, _("\ |
9d19df75 MS |
1493 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
1494 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
1495 | Use \"on\" to enable, \"off\" to disable.\n\ | |
1496 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1497 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1498 | triggers a breakpoint or watchpoint."), | |
1499 | NULL, | |
1500 | NULL, | |
1501 | &maintenance_set_cmdlist, | |
1502 | &maintenance_show_cmdlist); | |
1503 | } | |
1504 | ||
1505 | /* -Wmissing-prototypes. */ | |
1506 | void _initialize_aarch64_linux_nat (void); | |
1507 | ||
1508 | void | |
1509 | _initialize_aarch64_linux_nat (void) | |
1510 | { | |
1511 | struct target_ops *t; | |
1512 | ||
1513 | /* Fill in the generic GNU/Linux methods. */ | |
1514 | t = linux_target (); | |
1515 | ||
1516 | add_show_debug_regs_command (); | |
1517 | ||
1518 | /* Add our register access methods. */ | |
1519 | t->to_fetch_registers = aarch64_linux_fetch_inferior_registers; | |
1520 | t->to_store_registers = aarch64_linux_store_inferior_registers; | |
1521 | ||
1522 | t->to_read_description = aarch64_linux_read_description; | |
1523 | ||
1524 | t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint; | |
1525 | t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint; | |
1526 | t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint; | |
1527 | t->to_region_ok_for_hw_watchpoint = | |
1528 | aarch64_linux_region_ok_for_hw_watchpoint; | |
1529 | t->to_insert_watchpoint = aarch64_linux_insert_watchpoint; | |
1530 | t->to_remove_watchpoint = aarch64_linux_remove_watchpoint; | |
1531 | t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint; | |
1532 | t->to_stopped_data_address = aarch64_linux_stopped_data_address; | |
1533 | t->to_watchpoint_addr_within_range = | |
1534 | aarch64_linux_watchpoint_addr_within_range; | |
9d19df75 MS |
1535 | |
1536 | /* Override the GNU/Linux inferior startup hook. */ | |
1537 | super_post_startup_inferior = t->to_post_startup_inferior; | |
1538 | t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior; | |
1539 | ||
1540 | /* Register the target. */ | |
1541 | linux_nat_add_target (t); | |
1542 | linux_nat_set_new_thread (t, aarch64_linux_new_thread); | |
d6c44983 YZ |
1543 | linux_nat_set_new_fork (t, aarch64_linux_new_fork); |
1544 | linux_nat_set_forget_process (t, aarch64_forget_process); | |
9d19df75 MS |
1545 | linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume); |
1546 | } |