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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
42a4f53d | 3 | Copyright (C) 2011-2019 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
607685ec | 32 | #include "aarch32-linux-nat.h" |
db3cb7cb | 33 | #include "nat/aarch64-linux.h" |
554717a3 | 34 | #include "nat/aarch64-linux-hw-point.h" |
ba2d2bb2 | 35 | #include "nat/aarch64-sve-linux-ptrace.h" |
607685ec YQ |
36 | |
37 | #include "elf/external.h" | |
9d19df75 MS |
38 | #include "elf/common.h" |
39 | ||
5826e159 | 40 | #include "nat/gdb_ptrace.h" |
9d19df75 | 41 | #include <sys/utsname.h> |
036cd381 | 42 | #include <asm/ptrace.h> |
9d19df75 MS |
43 | |
44 | #include "gregset.h" | |
0f83012e | 45 | #include "linux-tdep.h" |
9d19df75 | 46 | |
9d19df75 MS |
47 | /* Defines ps_err_e, struct ps_prochandle. */ |
48 | #include "gdb_proc_service.h" | |
49 | ||
50 | #ifndef TRAP_HWBKPT | |
51 | #define TRAP_HWBKPT 0x0004 | |
52 | #endif | |
53 | ||
f6ac5f3d PA |
54 | class aarch64_linux_nat_target final : public linux_nat_target |
55 | { | |
56 | public: | |
57 | /* Add our register access methods. */ | |
58 | void fetch_registers (struct regcache *, int) override; | |
59 | void store_registers (struct regcache *, int) override; | |
60 | ||
61 | const struct target_desc *read_description () override; | |
62 | ||
63 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
64 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
65 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
66 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
67 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
68 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
69 | struct expression *) override; | |
70 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
71 | struct expression *) override; | |
57810aa7 PA |
72 | bool stopped_by_watchpoint () override; |
73 | bool stopped_data_address (CORE_ADDR *) override; | |
74 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; | |
f6ac5f3d PA |
75 | |
76 | int can_do_single_step () override; | |
77 | ||
78 | /* Override the GNU/Linux inferior startup hook. */ | |
79 | void post_startup_inferior (ptid_t) override; | |
135340af | 80 | |
8363f9d5 RB |
81 | /* Override the GNU/Linux post attach hook. */ |
82 | void post_attach (int pid) override; | |
83 | ||
135340af PA |
84 | /* These three defer to common nat/ code. */ |
85 | void low_new_thread (struct lwp_info *lp) override | |
86 | { aarch64_linux_new_thread (lp); } | |
87 | void low_delete_thread (struct arch_lwp_info *lp) override | |
88 | { aarch64_linux_delete_thread (lp); } | |
89 | void low_prepare_to_resume (struct lwp_info *lp) override | |
90 | { aarch64_linux_prepare_to_resume (lp); } | |
91 | ||
92 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
93 | void low_forget_process (pid_t pid) override; | |
94 | ||
95 | /* Add our siginfo layout converter. */ | |
96 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
97 | override; | |
f6ac5f3d PA |
98 | }; |
99 | ||
100 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; | |
101 | ||
d6c44983 YZ |
102 | /* Per-process data. We don't bind this to a per-inferior registry |
103 | because of targets like x86 GNU/Linux that need to keep track of | |
104 | processes that aren't bound to any inferior (e.g., fork children, | |
105 | checkpoints). */ | |
9d19df75 | 106 | |
d6c44983 | 107 | struct aarch64_process_info |
9d19df75 | 108 | { |
d6c44983 YZ |
109 | /* Linked list. */ |
110 | struct aarch64_process_info *next; | |
9d19df75 | 111 | |
d6c44983 YZ |
112 | /* The process identifier. */ |
113 | pid_t pid; | |
9d19df75 | 114 | |
d6c44983 YZ |
115 | /* Copy of aarch64 hardware debug registers. */ |
116 | struct aarch64_debug_reg_state state; | |
117 | }; | |
118 | ||
119 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
120 | ||
121 | /* Find process data for process PID. */ | |
122 | ||
123 | static struct aarch64_process_info * | |
124 | aarch64_find_process_pid (pid_t pid) | |
125 | { | |
126 | struct aarch64_process_info *proc; | |
127 | ||
128 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
129 | if (proc->pid == pid) | |
130 | return proc; | |
131 | ||
132 | return NULL; | |
9d19df75 MS |
133 | } |
134 | ||
d6c44983 YZ |
135 | /* Add process data for process PID. Returns newly allocated info |
136 | object. */ | |
9d19df75 | 137 | |
d6c44983 YZ |
138 | static struct aarch64_process_info * |
139 | aarch64_add_process (pid_t pid) | |
9d19df75 | 140 | { |
d6c44983 | 141 | struct aarch64_process_info *proc; |
9d19df75 | 142 | |
8d749320 | 143 | proc = XCNEW (struct aarch64_process_info); |
d6c44983 | 144 | proc->pid = pid; |
9d19df75 | 145 | |
d6c44983 YZ |
146 | proc->next = aarch64_process_list; |
147 | aarch64_process_list = proc; | |
148 | ||
149 | return proc; | |
150 | } | |
151 | ||
152 | /* Get data specific info for process PID, creating it if necessary. | |
153 | Never returns NULL. */ | |
154 | ||
155 | static struct aarch64_process_info * | |
156 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 157 | { |
d6c44983 YZ |
158 | struct aarch64_process_info *proc; |
159 | ||
160 | proc = aarch64_find_process_pid (pid); | |
161 | if (proc == NULL) | |
162 | proc = aarch64_add_process (pid); | |
9d19df75 | 163 | |
d6c44983 | 164 | return proc; |
9d19df75 MS |
165 | } |
166 | ||
d6c44983 YZ |
167 | /* Called whenever GDB is no longer debugging process PID. It deletes |
168 | data structures that keep track of debug register state. */ | |
9d19df75 | 169 | |
135340af PA |
170 | void |
171 | aarch64_linux_nat_target::low_forget_process (pid_t pid) | |
9d19df75 | 172 | { |
d6c44983 | 173 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 174 | |
d6c44983 YZ |
175 | proc = aarch64_process_list; |
176 | proc_link = &aarch64_process_list; | |
177 | ||
178 | while (proc != NULL) | |
9d19df75 | 179 | { |
d6c44983 YZ |
180 | if (proc->pid == pid) |
181 | { | |
182 | *proc_link = proc->next; | |
9d19df75 | 183 | |
d6c44983 YZ |
184 | xfree (proc); |
185 | return; | |
186 | } | |
187 | ||
188 | proc_link = &proc->next; | |
189 | proc = *proc_link; | |
190 | } | |
9d19df75 MS |
191 | } |
192 | ||
d6c44983 | 193 | /* Get debug registers state for process PID. */ |
9d19df75 | 194 | |
db3cb7cb | 195 | struct aarch64_debug_reg_state * |
d6c44983 | 196 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 197 | { |
d6c44983 | 198 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
199 | } |
200 | ||
9d19df75 MS |
201 | /* Fill GDB's register array with the general-purpose register values |
202 | from the current thread. */ | |
203 | ||
204 | static void | |
205 | fetch_gregs_from_thread (struct regcache *regcache) | |
206 | { | |
607685ec | 207 | int ret, tid; |
ac7936df | 208 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 MS |
209 | elf_gregset_t regs; |
210 | struct iovec iovec; | |
211 | ||
607685ec YQ |
212 | /* Make sure REGS can hold all registers contents on both aarch64 |
213 | and arm. */ | |
214 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
215 | ||
e38504b3 | 216 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
217 | |
218 | iovec.iov_base = ®s; | |
607685ec YQ |
219 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
220 | iovec.iov_len = 18 * 4; | |
221 | else | |
222 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
223 | |
224 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
225 | if (ret < 0) | |
226 | perror_with_name (_("Unable to fetch general registers.")); | |
227 | ||
607685ec YQ |
228 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
229 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); | |
230 | else | |
231 | { | |
232 | int regno; | |
233 | ||
234 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
73e1c03f | 235 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 236 | } |
9d19df75 MS |
237 | } |
238 | ||
239 | /* Store to the current thread the valid general-purpose register | |
240 | values in the GDB's register array. */ | |
241 | ||
242 | static void | |
243 | store_gregs_to_thread (const struct regcache *regcache) | |
244 | { | |
607685ec | 245 | int ret, tid; |
9d19df75 MS |
246 | elf_gregset_t regs; |
247 | struct iovec iovec; | |
ac7936df | 248 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 249 | |
607685ec YQ |
250 | /* Make sure REGS can hold all registers contents on both aarch64 |
251 | and arm. */ | |
252 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
e38504b3 | 253 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
254 | |
255 | iovec.iov_base = ®s; | |
607685ec YQ |
256 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
257 | iovec.iov_len = 18 * 4; | |
258 | else | |
259 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
260 | |
261 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
262 | if (ret < 0) | |
263 | perror_with_name (_("Unable to fetch general registers.")); | |
264 | ||
607685ec YQ |
265 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
266 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); | |
267 | else | |
268 | { | |
269 | int regno; | |
270 | ||
271 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
0ec9f114 | 272 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 | 273 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 274 | } |
9d19df75 MS |
275 | |
276 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
277 | if (ret < 0) | |
278 | perror_with_name (_("Unable to store general registers.")); | |
279 | } | |
280 | ||
281 | /* Fill GDB's register array with the fp/simd register values | |
282 | from the current thread. */ | |
283 | ||
284 | static void | |
285 | fetch_fpregs_from_thread (struct regcache *regcache) | |
286 | { | |
607685ec | 287 | int ret, tid; |
9d19df75 MS |
288 | elf_fpregset_t regs; |
289 | struct iovec iovec; | |
ac7936df | 290 | struct gdbarch *gdbarch = regcache->arch (); |
607685ec YQ |
291 | |
292 | /* Make sure REGS can hold all VFP registers contents on both aarch64 | |
293 | and arm. */ | |
294 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
9d19df75 | 295 | |
e38504b3 | 296 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
297 | |
298 | iovec.iov_base = ®s; | |
9d19df75 | 299 | |
607685ec YQ |
300 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
301 | { | |
302 | iovec.iov_len = VFP_REGS_SIZE; | |
303 | ||
304 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); | |
305 | if (ret < 0) | |
306 | perror_with_name (_("Unable to fetch VFP registers.")); | |
307 | ||
308 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); | |
309 | } | |
310 | else | |
311 | { | |
312 | int regno; | |
313 | ||
314 | iovec.iov_len = sizeof (regs); | |
9d19df75 | 315 | |
607685ec YQ |
316 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
317 | if (ret < 0) | |
318 | perror_with_name (_("Unable to fetch vFP/SIMD registers.")); | |
9d19df75 | 319 | |
607685ec | 320 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
73e1c03f | 321 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
607685ec | 322 | |
73e1c03f SM |
323 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
324 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); | |
607685ec | 325 | } |
9d19df75 MS |
326 | } |
327 | ||
328 | /* Store to the current thread the valid fp/simd register | |
329 | values in the GDB's register array. */ | |
330 | ||
331 | static void | |
332 | store_fpregs_to_thread (const struct regcache *regcache) | |
333 | { | |
607685ec | 334 | int ret, tid; |
9d19df75 MS |
335 | elf_fpregset_t regs; |
336 | struct iovec iovec; | |
ac7936df | 337 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 338 | |
607685ec YQ |
339 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
340 | and arm. */ | |
341 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
e38504b3 | 342 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
343 | |
344 | iovec.iov_base = ®s; | |
9d19df75 | 345 | |
607685ec YQ |
346 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
347 | { | |
348 | iovec.iov_len = VFP_REGS_SIZE; | |
9d19df75 | 349 | |
607685ec YQ |
350 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
351 | if (ret < 0) | |
352 | perror_with_name (_("Unable to fetch VFP registers.")); | |
9d19df75 | 353 | |
607685ec YQ |
354 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
355 | } | |
356 | else | |
357 | { | |
358 | int regno; | |
9d19df75 | 359 | |
607685ec YQ |
360 | iovec.iov_len = sizeof (regs); |
361 | ||
362 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
363 | if (ret < 0) | |
364 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
365 | ||
366 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
0ec9f114 | 367 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 SM |
368 | regcache->raw_collect |
369 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
607685ec | 370 | |
0ec9f114 | 371 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
34a79281 | 372 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
0ec9f114 | 373 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
34a79281 | 374 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
607685ec YQ |
375 | } |
376 | ||
377 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
378 | { | |
379 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); | |
380 | if (ret < 0) | |
381 | perror_with_name (_("Unable to store VFP registers.")); | |
382 | } | |
383 | else | |
384 | { | |
385 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
386 | if (ret < 0) | |
387 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
388 | } | |
9d19df75 MS |
389 | } |
390 | ||
e9902bfc AH |
391 | /* Fill GDB's register array with the sve register values |
392 | from the current thread. */ | |
393 | ||
394 | static void | |
395 | fetch_sveregs_from_thread (struct regcache *regcache) | |
396 | { | |
397 | std::unique_ptr<gdb_byte[]> base | |
e38504b3 | 398 | = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); |
e9902bfc AH |
399 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); |
400 | } | |
401 | ||
402 | /* Store to the current thread the valid sve register | |
403 | values in the GDB's register array. */ | |
404 | ||
405 | static void | |
406 | store_sveregs_to_thread (struct regcache *regcache) | |
407 | { | |
408 | int ret; | |
409 | struct iovec iovec; | |
e38504b3 | 410 | int tid = regcache->ptid ().lwp (); |
e9902bfc AH |
411 | |
412 | /* Obtain a dump of SVE registers from ptrace. */ | |
413 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); | |
414 | ||
415 | /* Overwrite with regcache state. */ | |
416 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); | |
417 | ||
418 | /* Write back to the kernel. */ | |
419 | iovec.iov_base = base.get (); | |
420 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; | |
421 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); | |
422 | ||
423 | if (ret < 0) | |
424 | perror_with_name (_("Unable to store sve registers")); | |
425 | } | |
426 | ||
76bed0fd AH |
427 | /* Fill GDB's register array with the pointer authentication mask values from |
428 | the current thread. */ | |
429 | ||
430 | static void | |
431 | fetch_pauth_masks_from_thread (struct regcache *regcache) | |
432 | { | |
433 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); | |
434 | int ret; | |
435 | struct iovec iovec; | |
436 | uint64_t pauth_regset[2] = {0, 0}; | |
437 | int tid = regcache->ptid ().lwp (); | |
438 | ||
439 | iovec.iov_base = &pauth_regset; | |
440 | iovec.iov_len = sizeof (pauth_regset); | |
441 | ||
442 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec); | |
443 | if (ret != 0) | |
444 | perror_with_name (_("unable to fetch pauth registers.")); | |
445 | ||
446 | regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), | |
447 | &pauth_regset[0]); | |
448 | regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base), | |
449 | &pauth_regset[1]); | |
450 | } | |
451 | ||
f6ac5f3d | 452 | /* Implement the "fetch_registers" target_ops method. */ |
9d19df75 | 453 | |
f6ac5f3d PA |
454 | void |
455 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, | |
456 | int regno) | |
9d19df75 | 457 | { |
e9902bfc AH |
458 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
459 | ||
9d19df75 MS |
460 | if (regno == -1) |
461 | { | |
462 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
463 | if (tdep->has_sve ()) |
464 | fetch_sveregs_from_thread (regcache); | |
465 | else | |
466 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
467 | |
468 | if (tdep->has_pauth ()) | |
469 | fetch_pauth_masks_from_thread (regcache); | |
9d19df75 MS |
470 | } |
471 | else if (regno < AARCH64_V0_REGNUM) | |
472 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
473 | else if (tdep->has_sve ()) |
474 | fetch_sveregs_from_thread (regcache); | |
9d19df75 MS |
475 | else |
476 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
477 | |
478 | if (tdep->has_pauth ()) | |
479 | { | |
480 | if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) | |
481 | || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) | |
482 | fetch_pauth_masks_from_thread (regcache); | |
483 | } | |
9d19df75 MS |
484 | } |
485 | ||
f6ac5f3d | 486 | /* Implement the "store_registers" target_ops method. */ |
9d19df75 | 487 | |
f6ac5f3d PA |
488 | void |
489 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, | |
490 | int regno) | |
9d19df75 | 491 | { |
e9902bfc AH |
492 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
493 | ||
9d19df75 MS |
494 | if (regno == -1) |
495 | { | |
496 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
497 | if (tdep->has_sve ()) |
498 | store_sveregs_to_thread (regcache); | |
499 | else | |
500 | store_fpregs_to_thread (regcache); | |
9d19df75 MS |
501 | } |
502 | else if (regno < AARCH64_V0_REGNUM) | |
503 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
504 | else if (tdep->has_sve ()) |
505 | store_sveregs_to_thread (regcache); | |
9d19df75 MS |
506 | else |
507 | store_fpregs_to_thread (regcache); | |
508 | } | |
509 | ||
510 | /* Fill register REGNO (if it is a general-purpose register) in | |
511 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
512 | do this for all registers. */ | |
513 | ||
514 | void | |
515 | fill_gregset (const struct regcache *regcache, | |
516 | gdb_gregset_t *gregsetp, int regno) | |
517 | { | |
d4d793bf AA |
518 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
519 | regno, (gdb_byte *) gregsetp, | |
520 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
521 | } |
522 | ||
523 | /* Fill GDB's register array with the general-purpose register values | |
524 | in *GREGSETP. */ | |
525 | ||
526 | void | |
527 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
528 | { | |
d4d793bf AA |
529 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
530 | (const gdb_byte *) gregsetp, | |
531 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
532 | } |
533 | ||
534 | /* Fill register REGNO (if it is a floating-point register) in | |
535 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
536 | do this for all registers. */ | |
537 | ||
538 | void | |
539 | fill_fpregset (const struct regcache *regcache, | |
540 | gdb_fpregset_t *fpregsetp, int regno) | |
541 | { | |
d4d793bf AA |
542 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
543 | regno, (gdb_byte *) fpregsetp, | |
544 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
545 | } |
546 | ||
547 | /* Fill GDB's register array with the floating-point register values | |
548 | in *FPREGSETP. */ | |
549 | ||
550 | void | |
551 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
552 | { | |
d4d793bf AA |
553 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
554 | (const gdb_byte *) fpregsetp, | |
555 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
556 | } |
557 | ||
d6c44983 YZ |
558 | /* linux_nat_new_fork hook. */ |
559 | ||
135340af PA |
560 | void |
561 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
562 | pid_t child_pid) | |
d6c44983 YZ |
563 | { |
564 | pid_t parent_pid; | |
565 | struct aarch64_debug_reg_state *parent_state; | |
566 | struct aarch64_debug_reg_state *child_state; | |
567 | ||
568 | /* NULL means no watchpoint has ever been set in the parent. In | |
569 | that case, there's nothing to do. */ | |
570 | if (parent->arch_private == NULL) | |
571 | return; | |
572 | ||
573 | /* GDB core assumes the child inherits the watchpoints/hw | |
574 | breakpoints of the parent, and will remove them all from the | |
575 | forked off process. Copy the debug registers mirrors into the | |
576 | new process so that all breakpoints and watchpoints can be | |
577 | removed together. */ | |
578 | ||
e99b03dc | 579 | parent_pid = parent->ptid.pid (); |
d6c44983 YZ |
580 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
581 | child_state = aarch64_get_debug_reg_state (child_pid); | |
582 | *child_state = *parent_state; | |
583 | } | |
9d19df75 MS |
584 | \f |
585 | ||
586 | /* Called by libthread_db. Returns a pointer to the thread local | |
587 | storage (or its descriptor). */ | |
588 | ||
589 | ps_err_e | |
754653a7 | 590 | ps_get_thread_area (struct ps_prochandle *ph, |
9d19df75 MS |
591 | lwpid_t lwpid, int idx, void **base) |
592 | { | |
a0cc84cd YQ |
593 | int is_64bit_p |
594 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); | |
9d19df75 | 595 | |
a0cc84cd | 596 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
9d19df75 MS |
597 | } |
598 | \f | |
599 | ||
f6ac5f3d | 600 | /* Implement the "post_startup_inferior" target_ops method. */ |
9d19df75 | 601 | |
f6ac5f3d PA |
602 | void |
603 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) | |
9d19df75 | 604 | { |
e99b03dc TT |
605 | low_forget_process (ptid.pid ()); |
606 | aarch64_linux_get_debug_reg_capacity (ptid.pid ()); | |
f6ac5f3d | 607 | linux_nat_target::post_startup_inferior (ptid); |
9d19df75 MS |
608 | } |
609 | ||
8363f9d5 RB |
610 | /* Implement the "post_attach" target_ops method. */ |
611 | ||
612 | void | |
613 | aarch64_linux_nat_target::post_attach (int pid) | |
614 | { | |
615 | low_forget_process (pid); | |
616 | /* Set the hardware debug register capacity. If | |
617 | aarch64_linux_get_debug_reg_capacity is not called | |
618 | (as it is in aarch64_linux_child_post_startup_inferior) then | |
619 | software watchpoints will be used instead of hardware | |
620 | watchpoints when attaching to a target. */ | |
621 | aarch64_linux_get_debug_reg_capacity (pid); | |
622 | linux_nat_target::post_attach (pid); | |
623 | } | |
624 | ||
607685ec YQ |
625 | extern struct target_desc *tdesc_arm_with_neon; |
626 | ||
f6ac5f3d | 627 | /* Implement the "read_description" target_ops method. */ |
9d19df75 | 628 | |
f6ac5f3d PA |
629 | const struct target_desc * |
630 | aarch64_linux_nat_target::read_description () | |
9d19df75 | 631 | { |
6f67973b YQ |
632 | int ret, tid; |
633 | gdb_byte regbuf[VFP_REGS_SIZE]; | |
634 | struct iovec iovec; | |
607685ec | 635 | |
e38504b3 | 636 | tid = inferior_ptid.lwp (); |
607685ec | 637 | |
6f67973b YQ |
638 | iovec.iov_base = regbuf; |
639 | iovec.iov_len = VFP_REGS_SIZE; | |
607685ec | 640 | |
6f67973b YQ |
641 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
642 | if (ret == 0) | |
643 | return tdesc_arm_with_neon; | |
6dc0ebde | 644 | |
0f83012e | 645 | CORE_ADDR hwcap = linux_get_hwcap (this); |
ee4fbcfa | 646 | |
0f83012e AH |
647 | return aarch64_read_description (aarch64_sve_get_vq (tid), |
648 | hwcap & AARCH64_HWCAP_PACA); | |
9d19df75 MS |
649 | } |
650 | ||
ade90bde YQ |
651 | /* Convert a native/host siginfo object, into/from the siginfo in the |
652 | layout of the inferiors' architecture. Returns true if any | |
653 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
654 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
655 | INF. */ | |
656 | ||
135340af PA |
657 | bool |
658 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, | |
659 | int direction) | |
ade90bde YQ |
660 | { |
661 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); | |
662 | ||
663 | /* Is the inferior 32-bit? If so, then do fixup the siginfo | |
664 | object. */ | |
665 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
666 | { | |
667 | if (direction == 0) | |
668 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, | |
669 | native); | |
670 | else | |
671 | aarch64_siginfo_from_compat_siginfo (native, | |
672 | (struct compat_siginfo *) inf); | |
673 | ||
135340af | 674 | return true; |
ade90bde YQ |
675 | } |
676 | ||
135340af | 677 | return false; |
ade90bde YQ |
678 | } |
679 | ||
9d19df75 MS |
680 | /* Returns the number of hardware watchpoints of type TYPE that we can |
681 | set. Value is positive if we can set CNT watchpoints, zero if | |
682 | setting watchpoints of type TYPE is not supported, and negative if | |
683 | CNT is more than the maximum number of watchpoints of type TYPE | |
684 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
685 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
686 | CNT is the number of such watchpoints used so far (including this | |
687 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
c2fbdc59 | 688 | currently enabled. */ |
9d19df75 | 689 | |
f6ac5f3d PA |
690 | int |
691 | aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
692 | int cnt, int othertype) | |
9d19df75 | 693 | { |
c2fbdc59 YQ |
694 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
695 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
696 | { | |
697 | if (aarch64_num_wp_regs == 0) | |
698 | return 0; | |
699 | } | |
700 | else if (type == bp_hardware_breakpoint) | |
701 | { | |
702 | if (aarch64_num_bp_regs == 0) | |
703 | return 0; | |
704 | } | |
705 | else | |
706 | gdb_assert_not_reached ("unexpected breakpoint type"); | |
707 | ||
708 | /* We always return 1 here because we don't have enough information | |
709 | about possible overlap of addresses that they want to watch. As an | |
710 | extreme example, consider the case where all the watchpoints watch | |
711 | the same address and the same region length: then we can handle a | |
712 | virtually unlimited number of watchpoints, due to debug register | |
713 | sharing implemented via reference counts. */ | |
9d19df75 MS |
714 | return 1; |
715 | } | |
716 | ||
0d5ed153 | 717 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
9d19df75 MS |
718 | Return 0 on success, -1 on failure. */ |
719 | ||
f6ac5f3d PA |
720 | int |
721 | aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
722 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
723 | { |
724 | int ret; | |
0d5ed153 | 725 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
8d689ee5 | 726 | int len; |
2ecd81c2 | 727 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 728 | struct aarch64_debug_reg_state *state |
e99b03dc | 729 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 730 | |
8d689ee5 YQ |
731 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
732 | ||
c5e92cca | 733 | if (show_debug_regs) |
9d19df75 MS |
734 | fprintf_unfiltered |
735 | (gdb_stdlog, | |
736 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
737 | (unsigned long) addr, len); | |
738 | ||
c67ca4de | 739 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 740 | |
c5e92cca | 741 | if (show_debug_regs) |
d6c44983 | 742 | { |
d6c44983 | 743 | aarch64_show_debug_reg_state (state, |
2fd0f80d | 744 | "insert_hw_breakpoint", addr, len, type); |
d6c44983 | 745 | } |
9d19df75 MS |
746 | |
747 | return ret; | |
748 | } | |
749 | ||
750 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
751 | Return 0 on success, -1 on failure. */ | |
752 | ||
f6ac5f3d PA |
753 | int |
754 | aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
755 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
756 | { |
757 | int ret; | |
758 | CORE_ADDR addr = bp_tgt->placed_address; | |
8d689ee5 | 759 | int len = 4; |
2ecd81c2 | 760 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de | 761 | struct aarch64_debug_reg_state *state |
e99b03dc | 762 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 763 | |
8d689ee5 YQ |
764 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
765 | ||
c5e92cca | 766 | if (show_debug_regs) |
9d19df75 MS |
767 | fprintf_unfiltered |
768 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
769 | (unsigned long) addr, len); | |
770 | ||
c67ca4de | 771 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 772 | |
c5e92cca | 773 | if (show_debug_regs) |
d6c44983 | 774 | { |
d6c44983 YZ |
775 | aarch64_show_debug_reg_state (state, |
776 | "remove_hw_watchpoint", addr, len, type); | |
777 | } | |
9d19df75 MS |
778 | |
779 | return ret; | |
780 | } | |
781 | ||
f6ac5f3d | 782 | /* Implement the "insert_watchpoint" target_ops method. |
9d19df75 MS |
783 | |
784 | Insert a watchpoint to watch a memory region which starts at | |
785 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
786 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
787 | ||
f6ac5f3d PA |
788 | int |
789 | aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
790 | enum target_hw_bp_type type, | |
791 | struct expression *cond) | |
9d19df75 MS |
792 | { |
793 | int ret; | |
c67ca4de | 794 | struct aarch64_debug_reg_state *state |
e99b03dc | 795 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 796 | |
c5e92cca | 797 | if (show_debug_regs) |
9d19df75 MS |
798 | fprintf_unfiltered (gdb_stdlog, |
799 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
800 | (unsigned long) addr, len); | |
801 | ||
802 | gdb_assert (type != hw_execute); | |
803 | ||
c67ca4de | 804 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 805 | |
c5e92cca | 806 | if (show_debug_regs) |
d6c44983 | 807 | { |
d6c44983 YZ |
808 | aarch64_show_debug_reg_state (state, |
809 | "insert_watchpoint", addr, len, type); | |
810 | } | |
9d19df75 MS |
811 | |
812 | return ret; | |
813 | } | |
814 | ||
f6ac5f3d | 815 | /* Implement the "remove_watchpoint" target_ops method. |
9d19df75 MS |
816 | Remove a watchpoint that watched the memory region which starts at |
817 | address ADDR, whose length is LEN bytes, and for accesses of the | |
818 | type TYPE. Return 0 on success, -1 on failure. */ | |
819 | ||
f6ac5f3d PA |
820 | int |
821 | aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
822 | enum target_hw_bp_type type, | |
823 | struct expression *cond) | |
9d19df75 MS |
824 | { |
825 | int ret; | |
c67ca4de | 826 | struct aarch64_debug_reg_state *state |
e99b03dc | 827 | = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 | 828 | |
c5e92cca | 829 | if (show_debug_regs) |
9d19df75 MS |
830 | fprintf_unfiltered (gdb_stdlog, |
831 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
832 | (unsigned long) addr, len); | |
833 | ||
834 | gdb_assert (type != hw_execute); | |
835 | ||
c67ca4de | 836 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 837 | |
c5e92cca | 838 | if (show_debug_regs) |
d6c44983 | 839 | { |
d6c44983 YZ |
840 | aarch64_show_debug_reg_state (state, |
841 | "remove_watchpoint", addr, len, type); | |
842 | } | |
9d19df75 MS |
843 | |
844 | return ret; | |
845 | } | |
846 | ||
f6ac5f3d | 847 | /* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ |
9d19df75 | 848 | |
f6ac5f3d PA |
849 | int |
850 | aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
9d19df75 | 851 | { |
39edd165 | 852 | return aarch64_linux_region_ok_for_watchpoint (addr, len); |
9d19df75 MS |
853 | } |
854 | ||
f6ac5f3d | 855 | /* Implement the "stopped_data_address" target_ops method. */ |
9d19df75 | 856 | |
57810aa7 | 857 | bool |
f6ac5f3d | 858 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
9d19df75 MS |
859 | { |
860 | siginfo_t siginfo; | |
cf4088a9 | 861 | int i; |
9d19df75 MS |
862 | struct aarch64_debug_reg_state *state; |
863 | ||
864 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 865 | return false; |
9d19df75 MS |
866 | |
867 | /* This must be a hardware breakpoint. */ | |
868 | if (siginfo.si_signo != SIGTRAP | |
869 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
57810aa7 | 870 | return false; |
9d19df75 MS |
871 | |
872 | /* Check if the address matches any watched address. */ | |
e99b03dc | 873 | state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
9d19df75 MS |
874 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
875 | { | |
a3b60e45 JK |
876 | const unsigned int offset |
877 | = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); | |
9d19df75 MS |
878 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
879 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
a3b60e45 JK |
880 | const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; |
881 | const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); | |
882 | const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; | |
9d19df75 MS |
883 | |
884 | if (state->dr_ref_count_wp[i] | |
885 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
a3b60e45 | 886 | && addr_trap >= addr_watch_aligned |
9d19df75 MS |
887 | && addr_trap < addr_watch + len) |
888 | { | |
a3b60e45 JK |
889 | /* ADDR_TRAP reports the first address of the memory range |
890 | accessed by the CPU, regardless of what was the memory | |
891 | range watched. Thus, a large CPU access that straddles | |
892 | the ADDR_WATCH..ADDR_WATCH+LEN range may result in an | |
893 | ADDR_TRAP that is lower than the | |
894 | ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: | |
895 | ||
896 | addr: | 4 | 5 | 6 | 7 | 8 | | |
897 | |---- range watched ----| | |
898 | |----------- range accessed ------------| | |
899 | ||
900 | In this case, ADDR_TRAP will be 4. | |
901 | ||
902 | To match a watchpoint known to GDB core, we must never | |
903 | report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN | |
904 | range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false | |
905 | positive on kernels older than 4.10. See PR | |
906 | external/20207. */ | |
907 | *addr_p = addr_orig; | |
57810aa7 | 908 | return true; |
9d19df75 MS |
909 | } |
910 | } | |
911 | ||
57810aa7 | 912 | return false; |
9d19df75 MS |
913 | } |
914 | ||
f6ac5f3d | 915 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
9d19df75 | 916 | |
57810aa7 | 917 | bool |
f6ac5f3d | 918 | aarch64_linux_nat_target::stopped_by_watchpoint () |
9d19df75 MS |
919 | { |
920 | CORE_ADDR addr; | |
921 | ||
f6ac5f3d | 922 | return stopped_data_address (&addr); |
9d19df75 MS |
923 | } |
924 | ||
f6ac5f3d | 925 | /* Implement the "watchpoint_addr_within_range" target_ops method. */ |
9d19df75 | 926 | |
57810aa7 | 927 | bool |
f6ac5f3d PA |
928 | aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
929 | CORE_ADDR start, int length) | |
9d19df75 MS |
930 | { |
931 | return start <= addr && start + length - 1 >= addr; | |
932 | } | |
933 | ||
f6ac5f3d | 934 | /* Implement the "can_do_single_step" target_ops method. */ |
750ce8d1 | 935 | |
f6ac5f3d PA |
936 | int |
937 | aarch64_linux_nat_target::can_do_single_step () | |
750ce8d1 YQ |
938 | { |
939 | return 1; | |
940 | } | |
941 | ||
9d19df75 MS |
942 | /* Define AArch64 maintenance commands. */ |
943 | ||
944 | static void | |
945 | add_show_debug_regs_command (void) | |
946 | { | |
947 | /* A maintenance command to enable printing the internal DRi mirror | |
948 | variables. */ | |
949 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
c5e92cca | 950 | &show_debug_regs, _("\ |
9d19df75 MS |
951 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
952 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
953 | Use \"on\" to enable, \"off\" to disable.\n\ | |
954 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
955 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
956 | triggers a breakpoint or watchpoint."), | |
957 | NULL, | |
958 | NULL, | |
959 | &maintenance_set_cmdlist, | |
960 | &maintenance_show_cmdlist); | |
961 | } | |
962 | ||
9d19df75 MS |
963 | void |
964 | _initialize_aarch64_linux_nat (void) | |
965 | { | |
9d19df75 MS |
966 | add_show_debug_regs_command (); |
967 | ||
9d19df75 | 968 | /* Register the target. */ |
f6ac5f3d | 969 | linux_target = &the_aarch64_linux_nat_target; |
d9f719f1 | 970 | add_inf_child_target (&the_aarch64_linux_nat_target); |
9d19df75 | 971 | } |