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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
e2882c85 | 3 | Copyright (C) 2009-2018 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
07b287a0 MS |
27 | #include "dis-asm.h" |
28 | #include "regcache.h" | |
29 | #include "reggroups.h" | |
07b287a0 MS |
30 | #include "value.h" |
31 | #include "arch-utils.h" | |
32 | #include "osabi.h" | |
33 | #include "frame-unwind.h" | |
34 | #include "frame-base.h" | |
35 | #include "trad-frame.h" | |
36 | #include "objfiles.h" | |
37 | #include "dwarf2-frame.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "prologue-value.h" | |
40 | #include "target-descriptions.h" | |
41 | #include "user-regs.h" | |
42 | #include "language.h" | |
43 | #include "infcall.h" | |
ea873d8e PL |
44 | #include "ax.h" |
45 | #include "ax-gdb.h" | |
4d9a9006 | 46 | #include "selftest.h" |
07b287a0 MS |
47 | |
48 | #include "aarch64-tdep.h" | |
49 | ||
50 | #include "elf-bfd.h" | |
51 | #include "elf/aarch64.h" | |
52 | ||
07b287a0 MS |
53 | #include "vec.h" |
54 | ||
99afc88b OJ |
55 | #include "record.h" |
56 | #include "record-full.h" | |
787749ea PL |
57 | #include "arch/aarch64-insn.h" |
58 | ||
f77ee802 | 59 | #include "opcode/aarch64.h" |
325fac50 | 60 | #include <algorithm> |
f77ee802 YQ |
61 | |
62 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
63 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
64 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
65 | ||
07b287a0 MS |
66 | /* Pseudo register base numbers. */ |
67 | #define AARCH64_Q0_REGNUM 0 | |
187f5d00 | 68 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT) |
07b287a0 MS |
69 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) |
70 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
71 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
63bad7b6 | 72 | #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32) |
07b287a0 | 73 | |
95228a0d AH |
74 | /* All possible aarch64 target descriptors. */ |
75 | struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1]; | |
76 | ||
07b287a0 MS |
77 | /* The standard register names, and all the valid aliases for them. */ |
78 | static const struct | |
79 | { | |
80 | const char *const name; | |
81 | int regnum; | |
82 | } aarch64_register_aliases[] = | |
83 | { | |
84 | /* 64-bit register names. */ | |
85 | {"fp", AARCH64_FP_REGNUM}, | |
86 | {"lr", AARCH64_LR_REGNUM}, | |
87 | {"sp", AARCH64_SP_REGNUM}, | |
88 | ||
89 | /* 32-bit register names. */ | |
90 | {"w0", AARCH64_X0_REGNUM + 0}, | |
91 | {"w1", AARCH64_X0_REGNUM + 1}, | |
92 | {"w2", AARCH64_X0_REGNUM + 2}, | |
93 | {"w3", AARCH64_X0_REGNUM + 3}, | |
94 | {"w4", AARCH64_X0_REGNUM + 4}, | |
95 | {"w5", AARCH64_X0_REGNUM + 5}, | |
96 | {"w6", AARCH64_X0_REGNUM + 6}, | |
97 | {"w7", AARCH64_X0_REGNUM + 7}, | |
98 | {"w8", AARCH64_X0_REGNUM + 8}, | |
99 | {"w9", AARCH64_X0_REGNUM + 9}, | |
100 | {"w10", AARCH64_X0_REGNUM + 10}, | |
101 | {"w11", AARCH64_X0_REGNUM + 11}, | |
102 | {"w12", AARCH64_X0_REGNUM + 12}, | |
103 | {"w13", AARCH64_X0_REGNUM + 13}, | |
104 | {"w14", AARCH64_X0_REGNUM + 14}, | |
105 | {"w15", AARCH64_X0_REGNUM + 15}, | |
106 | {"w16", AARCH64_X0_REGNUM + 16}, | |
107 | {"w17", AARCH64_X0_REGNUM + 17}, | |
108 | {"w18", AARCH64_X0_REGNUM + 18}, | |
109 | {"w19", AARCH64_X0_REGNUM + 19}, | |
110 | {"w20", AARCH64_X0_REGNUM + 20}, | |
111 | {"w21", AARCH64_X0_REGNUM + 21}, | |
112 | {"w22", AARCH64_X0_REGNUM + 22}, | |
113 | {"w23", AARCH64_X0_REGNUM + 23}, | |
114 | {"w24", AARCH64_X0_REGNUM + 24}, | |
115 | {"w25", AARCH64_X0_REGNUM + 25}, | |
116 | {"w26", AARCH64_X0_REGNUM + 26}, | |
117 | {"w27", AARCH64_X0_REGNUM + 27}, | |
118 | {"w28", AARCH64_X0_REGNUM + 28}, | |
119 | {"w29", AARCH64_X0_REGNUM + 29}, | |
120 | {"w30", AARCH64_X0_REGNUM + 30}, | |
121 | ||
122 | /* specials */ | |
123 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
124 | {"ip1", AARCH64_X0_REGNUM + 17} | |
125 | }; | |
126 | ||
127 | /* The required core 'R' registers. */ | |
128 | static const char *const aarch64_r_register_names[] = | |
129 | { | |
130 | /* These registers must appear in consecutive RAW register number | |
131 | order and they must begin with AARCH64_X0_REGNUM! */ | |
132 | "x0", "x1", "x2", "x3", | |
133 | "x4", "x5", "x6", "x7", | |
134 | "x8", "x9", "x10", "x11", | |
135 | "x12", "x13", "x14", "x15", | |
136 | "x16", "x17", "x18", "x19", | |
137 | "x20", "x21", "x22", "x23", | |
138 | "x24", "x25", "x26", "x27", | |
139 | "x28", "x29", "x30", "sp", | |
140 | "pc", "cpsr" | |
141 | }; | |
142 | ||
143 | /* The FP/SIMD 'V' registers. */ | |
144 | static const char *const aarch64_v_register_names[] = | |
145 | { | |
146 | /* These registers must appear in consecutive RAW register number | |
147 | order and they must begin with AARCH64_V0_REGNUM! */ | |
148 | "v0", "v1", "v2", "v3", | |
149 | "v4", "v5", "v6", "v7", | |
150 | "v8", "v9", "v10", "v11", | |
151 | "v12", "v13", "v14", "v15", | |
152 | "v16", "v17", "v18", "v19", | |
153 | "v20", "v21", "v22", "v23", | |
154 | "v24", "v25", "v26", "v27", | |
155 | "v28", "v29", "v30", "v31", | |
156 | "fpsr", | |
157 | "fpcr" | |
158 | }; | |
159 | ||
739e8682 AH |
160 | /* The SVE 'Z' and 'P' registers. */ |
161 | static const char *const aarch64_sve_register_names[] = | |
162 | { | |
163 | /* These registers must appear in consecutive RAW register number | |
164 | order and they must begin with AARCH64_SVE_Z0_REGNUM! */ | |
165 | "z0", "z1", "z2", "z3", | |
166 | "z4", "z5", "z6", "z7", | |
167 | "z8", "z9", "z10", "z11", | |
168 | "z12", "z13", "z14", "z15", | |
169 | "z16", "z17", "z18", "z19", | |
170 | "z20", "z21", "z22", "z23", | |
171 | "z24", "z25", "z26", "z27", | |
172 | "z28", "z29", "z30", "z31", | |
173 | "fpsr", "fpcr", | |
174 | "p0", "p1", "p2", "p3", | |
175 | "p4", "p5", "p6", "p7", | |
176 | "p8", "p9", "p10", "p11", | |
177 | "p12", "p13", "p14", "p15", | |
178 | "ffr", "vg" | |
179 | }; | |
180 | ||
07b287a0 MS |
181 | /* AArch64 prologue cache structure. */ |
182 | struct aarch64_prologue_cache | |
183 | { | |
db634143 PL |
184 | /* The program counter at the start of the function. It is used to |
185 | identify this frame as a prologue frame. */ | |
186 | CORE_ADDR func; | |
187 | ||
188 | /* The program counter at the time this frame was created; i.e. where | |
189 | this function was called from. It is used to identify this frame as a | |
190 | stub frame. */ | |
191 | CORE_ADDR prev_pc; | |
192 | ||
07b287a0 MS |
193 | /* The stack pointer at the time this frame was created; i.e. the |
194 | caller's stack pointer when this function was called. It is used | |
195 | to identify this frame. */ | |
196 | CORE_ADDR prev_sp; | |
197 | ||
7dfa3edc PL |
198 | /* Is the target available to read from? */ |
199 | int available_p; | |
200 | ||
07b287a0 MS |
201 | /* The frame base for this frame is just prev_sp - frame size. |
202 | FRAMESIZE is the distance from the frame pointer to the | |
203 | initial stack pointer. */ | |
204 | int framesize; | |
205 | ||
206 | /* The register used to hold the frame pointer for this frame. */ | |
207 | int framereg; | |
208 | ||
209 | /* Saved register offsets. */ | |
210 | struct trad_frame_saved_reg *saved_regs; | |
211 | }; | |
212 | ||
07b287a0 MS |
213 | static void |
214 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
215 | struct cmd_list_element *c, const char *value) | |
216 | { | |
217 | fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value); | |
218 | } | |
219 | ||
ffdbe864 YQ |
220 | namespace { |
221 | ||
4d9a9006 YQ |
222 | /* Abstract instruction reader. */ |
223 | ||
224 | class abstract_instruction_reader | |
225 | { | |
226 | public: | |
227 | /* Read in one instruction. */ | |
228 | virtual ULONGEST read (CORE_ADDR memaddr, int len, | |
229 | enum bfd_endian byte_order) = 0; | |
230 | }; | |
231 | ||
232 | /* Instruction reader from real target. */ | |
233 | ||
234 | class instruction_reader : public abstract_instruction_reader | |
235 | { | |
236 | public: | |
237 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 238 | override |
4d9a9006 | 239 | { |
fc2f703e | 240 | return read_code_unsigned_integer (memaddr, len, byte_order); |
4d9a9006 YQ |
241 | } |
242 | }; | |
243 | ||
ffdbe864 YQ |
244 | } // namespace |
245 | ||
07b287a0 MS |
246 | /* Analyze a prologue, looking for a recognizable stack frame |
247 | and frame pointer. Scan until we encounter a store that could | |
248 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
249 | ||
250 | static CORE_ADDR | |
251 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
252 | CORE_ADDR start, CORE_ADDR limit, | |
4d9a9006 YQ |
253 | struct aarch64_prologue_cache *cache, |
254 | abstract_instruction_reader& reader) | |
07b287a0 MS |
255 | { |
256 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
257 | int i; | |
187f5d00 YQ |
258 | /* Track X registers and D registers in prologue. */ |
259 | pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT]; | |
07b287a0 | 260 | |
187f5d00 | 261 | for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++) |
07b287a0 | 262 | regs[i] = pv_register (i, 0); |
f7b7ed97 | 263 | pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
07b287a0 MS |
264 | |
265 | for (; start < limit; start += 4) | |
266 | { | |
267 | uint32_t insn; | |
d9ebcbce | 268 | aarch64_inst inst; |
07b287a0 | 269 | |
4d9a9006 | 270 | insn = reader.read (start, 4, byte_order_for_code); |
07b287a0 | 271 | |
561a72d4 | 272 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
d9ebcbce YQ |
273 | break; |
274 | ||
275 | if (inst.opcode->iclass == addsub_imm | |
276 | && (inst.opcode->op == OP_ADD | |
277 | || strcmp ("sub", inst.opcode->name) == 0)) | |
07b287a0 | 278 | { |
d9ebcbce YQ |
279 | unsigned rd = inst.operands[0].reg.regno; |
280 | unsigned rn = inst.operands[1].reg.regno; | |
281 | ||
282 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
283 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
284 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
285 | gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM); | |
286 | ||
287 | if (inst.opcode->op == OP_ADD) | |
288 | { | |
289 | regs[rd] = pv_add_constant (regs[rn], | |
290 | inst.operands[2].imm.value); | |
291 | } | |
292 | else | |
293 | { | |
294 | regs[rd] = pv_add_constant (regs[rn], | |
295 | -inst.operands[2].imm.value); | |
296 | } | |
297 | } | |
298 | else if (inst.opcode->iclass == pcreladdr | |
299 | && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP) | |
300 | { | |
301 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
302 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
303 | ||
304 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
07b287a0 | 305 | } |
d9ebcbce | 306 | else if (inst.opcode->iclass == branch_imm) |
07b287a0 MS |
307 | { |
308 | /* Stop analysis on branch. */ | |
309 | break; | |
310 | } | |
d9ebcbce | 311 | else if (inst.opcode->iclass == condbranch) |
07b287a0 MS |
312 | { |
313 | /* Stop analysis on branch. */ | |
314 | break; | |
315 | } | |
d9ebcbce | 316 | else if (inst.opcode->iclass == branch_reg) |
07b287a0 MS |
317 | { |
318 | /* Stop analysis on branch. */ | |
319 | break; | |
320 | } | |
d9ebcbce | 321 | else if (inst.opcode->iclass == compbranch) |
07b287a0 MS |
322 | { |
323 | /* Stop analysis on branch. */ | |
324 | break; | |
325 | } | |
d9ebcbce YQ |
326 | else if (inst.opcode->op == OP_MOVZ) |
327 | { | |
328 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
329 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
330 | } | |
331 | else if (inst.opcode->iclass == log_shift | |
332 | && strcmp (inst.opcode->name, "orr") == 0) | |
07b287a0 | 333 | { |
d9ebcbce YQ |
334 | unsigned rd = inst.operands[0].reg.regno; |
335 | unsigned rn = inst.operands[1].reg.regno; | |
336 | unsigned rm = inst.operands[2].reg.regno; | |
337 | ||
338 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
339 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn); | |
340 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT); | |
341 | ||
342 | if (inst.operands[2].shifter.amount == 0 | |
343 | && rn == AARCH64_SP_REGNUM) | |
07b287a0 MS |
344 | regs[rd] = regs[rm]; |
345 | else | |
346 | { | |
347 | if (aarch64_debug) | |
b277c936 PL |
348 | { |
349 | debug_printf ("aarch64: prologue analysis gave up " | |
0a0da556 | 350 | "addr=%s opcode=0x%x (orr x register)\n", |
b277c936 PL |
351 | core_addr_to_string_nz (start), insn); |
352 | } | |
07b287a0 MS |
353 | break; |
354 | } | |
355 | } | |
d9ebcbce | 356 | else if (inst.opcode->op == OP_STUR) |
07b287a0 | 357 | { |
d9ebcbce YQ |
358 | unsigned rt = inst.operands[0].reg.regno; |
359 | unsigned rn = inst.operands[1].addr.base_regno; | |
360 | int is64 | |
361 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
362 | ||
363 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
364 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); | |
365 | gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); | |
366 | gdb_assert (!inst.operands[1].addr.offset.is_reg); | |
367 | ||
f7b7ed97 TT |
368 | stack.store (pv_add_constant (regs[rn], |
369 | inst.operands[1].addr.offset.imm), | |
370 | is64 ? 8 : 4, regs[rt]); | |
07b287a0 | 371 | } |
d9ebcbce | 372 | else if ((inst.opcode->iclass == ldstpair_off |
03bcd739 YQ |
373 | || (inst.opcode->iclass == ldstpair_indexed |
374 | && inst.operands[2].addr.preind)) | |
d9ebcbce | 375 | && strcmp ("stp", inst.opcode->name) == 0) |
07b287a0 | 376 | { |
03bcd739 | 377 | /* STP with addressing mode Pre-indexed and Base register. */ |
187f5d00 YQ |
378 | unsigned rt1; |
379 | unsigned rt2; | |
d9ebcbce YQ |
380 | unsigned rn = inst.operands[2].addr.base_regno; |
381 | int32_t imm = inst.operands[2].addr.offset.imm; | |
382 | ||
187f5d00 YQ |
383 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
384 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
385 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2 | |
386 | || inst.operands[1].type == AARCH64_OPND_Ft2); | |
d9ebcbce YQ |
387 | gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7); |
388 | gdb_assert (!inst.operands[2].addr.offset.is_reg); | |
389 | ||
07b287a0 MS |
390 | /* If recording this store would invalidate the store area |
391 | (perhaps because rn is not known) then we should abandon | |
392 | further prologue analysis. */ | |
f7b7ed97 | 393 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm))) |
07b287a0 MS |
394 | break; |
395 | ||
f7b7ed97 | 396 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8))) |
07b287a0 MS |
397 | break; |
398 | ||
187f5d00 YQ |
399 | rt1 = inst.operands[0].reg.regno; |
400 | rt2 = inst.operands[1].reg.regno; | |
401 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
402 | { | |
403 | /* Only bottom 64-bit of each V register (D register) need | |
404 | to be preserved. */ | |
405 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
406 | rt1 += AARCH64_X_REGISTER_COUNT; | |
407 | rt2 += AARCH64_X_REGISTER_COUNT; | |
408 | } | |
409 | ||
f7b7ed97 TT |
410 | stack.store (pv_add_constant (regs[rn], imm), 8, |
411 | regs[rt1]); | |
412 | stack.store (pv_add_constant (regs[rn], imm + 8), 8, | |
413 | regs[rt2]); | |
14ac654f | 414 | |
d9ebcbce | 415 | if (inst.operands[2].addr.writeback) |
93d96012 | 416 | regs[rn] = pv_add_constant (regs[rn], imm); |
07b287a0 | 417 | |
07b287a0 | 418 | } |
432ec081 YQ |
419 | else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ |
420 | || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ | |
421 | && (inst.opcode->op == OP_STR_POS | |
422 | || inst.opcode->op == OP_STRF_POS))) | |
423 | && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM | |
424 | && strcmp ("str", inst.opcode->name) == 0) | |
425 | { | |
426 | /* STR (immediate) */ | |
427 | unsigned int rt = inst.operands[0].reg.regno; | |
428 | int32_t imm = inst.operands[1].addr.offset.imm; | |
429 | unsigned int rn = inst.operands[1].addr.base_regno; | |
430 | bool is64 | |
431 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
432 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt | |
433 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
434 | ||
435 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
436 | { | |
437 | /* Only bottom 64-bit of each V register (D register) need | |
438 | to be preserved. */ | |
439 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
440 | rt += AARCH64_X_REGISTER_COUNT; | |
441 | } | |
442 | ||
f7b7ed97 TT |
443 | stack.store (pv_add_constant (regs[rn], imm), |
444 | is64 ? 8 : 4, regs[rt]); | |
432ec081 YQ |
445 | if (inst.operands[1].addr.writeback) |
446 | regs[rn] = pv_add_constant (regs[rn], imm); | |
447 | } | |
d9ebcbce | 448 | else if (inst.opcode->iclass == testbranch) |
07b287a0 MS |
449 | { |
450 | /* Stop analysis on branch. */ | |
451 | break; | |
452 | } | |
453 | else | |
454 | { | |
455 | if (aarch64_debug) | |
b277c936 | 456 | { |
0a0da556 | 457 | debug_printf ("aarch64: prologue analysis gave up addr=%s" |
b277c936 PL |
458 | " opcode=0x%x\n", |
459 | core_addr_to_string_nz (start), insn); | |
460 | } | |
07b287a0 MS |
461 | break; |
462 | } | |
463 | } | |
464 | ||
465 | if (cache == NULL) | |
f7b7ed97 | 466 | return start; |
07b287a0 MS |
467 | |
468 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
469 | { | |
470 | /* Frame pointer is fp. Frame size is constant. */ | |
471 | cache->framereg = AARCH64_FP_REGNUM; | |
472 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
473 | } | |
474 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
475 | { | |
476 | /* Try the stack pointer. */ | |
477 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
478 | cache->framereg = AARCH64_SP_REGNUM; | |
479 | } | |
480 | else | |
481 | { | |
482 | /* We're just out of luck. We don't know where the frame is. */ | |
483 | cache->framereg = -1; | |
484 | cache->framesize = 0; | |
485 | } | |
486 | ||
487 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
488 | { | |
489 | CORE_ADDR offset; | |
490 | ||
f7b7ed97 | 491 | if (stack.find_reg (gdbarch, i, &offset)) |
07b287a0 MS |
492 | cache->saved_regs[i].addr = offset; |
493 | } | |
494 | ||
187f5d00 YQ |
495 | for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++) |
496 | { | |
497 | int regnum = gdbarch_num_regs (gdbarch); | |
498 | CORE_ADDR offset; | |
499 | ||
f7b7ed97 TT |
500 | if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT, |
501 | &offset)) | |
187f5d00 YQ |
502 | cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset; |
503 | } | |
504 | ||
07b287a0 MS |
505 | return start; |
506 | } | |
507 | ||
4d9a9006 YQ |
508 | static CORE_ADDR |
509 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
510 | CORE_ADDR start, CORE_ADDR limit, | |
511 | struct aarch64_prologue_cache *cache) | |
512 | { | |
513 | instruction_reader reader; | |
514 | ||
515 | return aarch64_analyze_prologue (gdbarch, start, limit, cache, | |
516 | reader); | |
517 | } | |
518 | ||
519 | #if GDB_SELF_TEST | |
520 | ||
521 | namespace selftests { | |
522 | ||
523 | /* Instruction reader from manually cooked instruction sequences. */ | |
524 | ||
525 | class instruction_reader_test : public abstract_instruction_reader | |
526 | { | |
527 | public: | |
528 | template<size_t SIZE> | |
529 | explicit instruction_reader_test (const uint32_t (&insns)[SIZE]) | |
530 | : m_insns (insns), m_insns_size (SIZE) | |
531 | {} | |
532 | ||
533 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 534 | override |
4d9a9006 YQ |
535 | { |
536 | SELF_CHECK (len == 4); | |
537 | SELF_CHECK (memaddr % 4 == 0); | |
538 | SELF_CHECK (memaddr / 4 < m_insns_size); | |
539 | ||
540 | return m_insns[memaddr / 4]; | |
541 | } | |
542 | ||
543 | private: | |
544 | const uint32_t *m_insns; | |
545 | size_t m_insns_size; | |
546 | }; | |
547 | ||
548 | static void | |
549 | aarch64_analyze_prologue_test (void) | |
550 | { | |
551 | struct gdbarch_info info; | |
552 | ||
553 | gdbarch_info_init (&info); | |
554 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
555 | ||
556 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
557 | SELF_CHECK (gdbarch != NULL); | |
558 | ||
559 | /* Test the simple prologue in which frame pointer is used. */ | |
560 | { | |
561 | struct aarch64_prologue_cache cache; | |
562 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
563 | ||
564 | static const uint32_t insns[] = { | |
565 | 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */ | |
566 | 0x910003fd, /* mov x29, sp */ | |
567 | 0x97ffffe6, /* bl 0x400580 */ | |
568 | }; | |
569 | instruction_reader_test reader (insns); | |
570 | ||
571 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
572 | SELF_CHECK (end == 4 * 2); | |
573 | ||
574 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
575 | SELF_CHECK (cache.framesize == 272); | |
576 | ||
577 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
578 | { | |
579 | if (i == AARCH64_FP_REGNUM) | |
580 | SELF_CHECK (cache.saved_regs[i].addr == -272); | |
581 | else if (i == AARCH64_LR_REGNUM) | |
582 | SELF_CHECK (cache.saved_regs[i].addr == -264); | |
583 | else | |
584 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
585 | } | |
586 | ||
587 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
588 | { | |
589 | int regnum = gdbarch_num_regs (gdbarch); | |
590 | ||
591 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
592 | == -1); | |
593 | } | |
594 | } | |
432ec081 YQ |
595 | |
596 | /* Test a prologue in which STR is used and frame pointer is not | |
597 | used. */ | |
598 | { | |
599 | struct aarch64_prologue_cache cache; | |
600 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
601 | ||
602 | static const uint32_t insns[] = { | |
603 | 0xf81d0ff3, /* str x19, [sp, #-48]! */ | |
604 | 0xb9002fe0, /* str w0, [sp, #44] */ | |
605 | 0xf90013e1, /* str x1, [sp, #32]*/ | |
606 | 0xfd000fe0, /* str d0, [sp, #24] */ | |
607 | 0xaa0203f3, /* mov x19, x2 */ | |
608 | 0xf94013e0, /* ldr x0, [sp, #32] */ | |
609 | }; | |
610 | instruction_reader_test reader (insns); | |
611 | ||
612 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
613 | ||
614 | SELF_CHECK (end == 4 * 5); | |
615 | ||
616 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
617 | SELF_CHECK (cache.framesize == 48); | |
618 | ||
619 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
620 | { | |
621 | if (i == 1) | |
622 | SELF_CHECK (cache.saved_regs[i].addr == -16); | |
623 | else if (i == 19) | |
624 | SELF_CHECK (cache.saved_regs[i].addr == -48); | |
625 | else | |
626 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
627 | } | |
628 | ||
629 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
630 | { | |
631 | int regnum = gdbarch_num_regs (gdbarch); | |
632 | ||
633 | if (i == 0) | |
634 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
635 | == -24); | |
636 | else | |
637 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
638 | == -1); | |
639 | } | |
640 | } | |
4d9a9006 YQ |
641 | } |
642 | } // namespace selftests | |
643 | #endif /* GDB_SELF_TEST */ | |
644 | ||
07b287a0 MS |
645 | /* Implement the "skip_prologue" gdbarch method. */ |
646 | ||
647 | static CORE_ADDR | |
648 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
649 | { | |
07b287a0 | 650 | CORE_ADDR func_addr, limit_pc; |
07b287a0 MS |
651 | |
652 | /* See if we can determine the end of the prologue via the symbol | |
653 | table. If so, then return either PC, or the PC after the | |
654 | prologue, whichever is greater. */ | |
655 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
656 | { | |
657 | CORE_ADDR post_prologue_pc | |
658 | = skip_prologue_using_sal (gdbarch, func_addr); | |
659 | ||
660 | if (post_prologue_pc != 0) | |
325fac50 | 661 | return std::max (pc, post_prologue_pc); |
07b287a0 MS |
662 | } |
663 | ||
664 | /* Can't determine prologue from the symbol table, need to examine | |
665 | instructions. */ | |
666 | ||
667 | /* Find an upper limit on the function prologue using the debug | |
668 | information. If the debug information could not be used to | |
669 | provide that bound, then use an arbitrary large number as the | |
670 | upper bound. */ | |
671 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
672 | if (limit_pc == 0) | |
673 | limit_pc = pc + 128; /* Magic. */ | |
674 | ||
675 | /* Try disassembling prologue. */ | |
676 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
677 | } | |
678 | ||
679 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
680 | cache CACHE. */ | |
681 | ||
682 | static void | |
683 | aarch64_scan_prologue (struct frame_info *this_frame, | |
684 | struct aarch64_prologue_cache *cache) | |
685 | { | |
686 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
687 | CORE_ADDR prologue_start; | |
688 | CORE_ADDR prologue_end; | |
689 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
690 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
691 | ||
db634143 PL |
692 | cache->prev_pc = prev_pc; |
693 | ||
07b287a0 MS |
694 | /* Assume we do not find a frame. */ |
695 | cache->framereg = -1; | |
696 | cache->framesize = 0; | |
697 | ||
698 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
699 | &prologue_end)) | |
700 | { | |
701 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
702 | ||
703 | if (sal.line == 0) | |
704 | { | |
705 | /* No line info so use the current PC. */ | |
706 | prologue_end = prev_pc; | |
707 | } | |
708 | else if (sal.end < prologue_end) | |
709 | { | |
710 | /* The next line begins after the function end. */ | |
711 | prologue_end = sal.end; | |
712 | } | |
713 | ||
325fac50 | 714 | prologue_end = std::min (prologue_end, prev_pc); |
07b287a0 MS |
715 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
716 | } | |
717 | else | |
718 | { | |
719 | CORE_ADDR frame_loc; | |
07b287a0 MS |
720 | |
721 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
722 | if (frame_loc == 0) | |
723 | return; | |
724 | ||
725 | cache->framereg = AARCH64_FP_REGNUM; | |
726 | cache->framesize = 16; | |
727 | cache->saved_regs[29].addr = 0; | |
728 | cache->saved_regs[30].addr = 8; | |
729 | } | |
730 | } | |
731 | ||
7dfa3edc PL |
732 | /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This |
733 | function may throw an exception if the inferior's registers or memory is | |
734 | not available. */ | |
07b287a0 | 735 | |
7dfa3edc PL |
736 | static void |
737 | aarch64_make_prologue_cache_1 (struct frame_info *this_frame, | |
738 | struct aarch64_prologue_cache *cache) | |
07b287a0 | 739 | { |
07b287a0 MS |
740 | CORE_ADDR unwound_fp; |
741 | int reg; | |
742 | ||
07b287a0 MS |
743 | aarch64_scan_prologue (this_frame, cache); |
744 | ||
745 | if (cache->framereg == -1) | |
7dfa3edc | 746 | return; |
07b287a0 MS |
747 | |
748 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
749 | if (unwound_fp == 0) | |
7dfa3edc | 750 | return; |
07b287a0 MS |
751 | |
752 | cache->prev_sp = unwound_fp + cache->framesize; | |
753 | ||
754 | /* Calculate actual addresses of saved registers using offsets | |
755 | determined by aarch64_analyze_prologue. */ | |
756 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
757 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
758 | cache->saved_regs[reg].addr += cache->prev_sp; | |
759 | ||
db634143 PL |
760 | cache->func = get_frame_func (this_frame); |
761 | ||
7dfa3edc PL |
762 | cache->available_p = 1; |
763 | } | |
764 | ||
765 | /* Allocate and fill in *THIS_CACHE with information about the prologue of | |
766 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
767 | Return a pointer to the current aarch64_prologue_cache in | |
768 | *THIS_CACHE. */ | |
769 | ||
770 | static struct aarch64_prologue_cache * | |
771 | aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache) | |
772 | { | |
773 | struct aarch64_prologue_cache *cache; | |
774 | ||
775 | if (*this_cache != NULL) | |
9a3c8263 | 776 | return (struct aarch64_prologue_cache *) *this_cache; |
7dfa3edc PL |
777 | |
778 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
779 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
780 | *this_cache = cache; | |
781 | ||
782 | TRY | |
783 | { | |
784 | aarch64_make_prologue_cache_1 (this_frame, cache); | |
785 | } | |
786 | CATCH (ex, RETURN_MASK_ERROR) | |
787 | { | |
788 | if (ex.error != NOT_AVAILABLE_ERROR) | |
789 | throw_exception (ex); | |
790 | } | |
791 | END_CATCH | |
792 | ||
07b287a0 MS |
793 | return cache; |
794 | } | |
795 | ||
7dfa3edc PL |
796 | /* Implement the "stop_reason" frame_unwind method. */ |
797 | ||
798 | static enum unwind_stop_reason | |
799 | aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
800 | void **this_cache) | |
801 | { | |
802 | struct aarch64_prologue_cache *cache | |
803 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
804 | ||
805 | if (!cache->available_p) | |
806 | return UNWIND_UNAVAILABLE; | |
807 | ||
808 | /* Halt the backtrace at "_start". */ | |
809 | if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
810 | return UNWIND_OUTERMOST; | |
811 | ||
812 | /* We've hit a wall, stop. */ | |
813 | if (cache->prev_sp == 0) | |
814 | return UNWIND_OUTERMOST; | |
815 | ||
816 | return UNWIND_NO_REASON; | |
817 | } | |
818 | ||
07b287a0 MS |
819 | /* Our frame ID for a normal frame is the current function's starting |
820 | PC and the caller's SP when we were called. */ | |
821 | ||
822 | static void | |
823 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
824 | void **this_cache, struct frame_id *this_id) | |
825 | { | |
7c8edfae PL |
826 | struct aarch64_prologue_cache *cache |
827 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 | 828 | |
7dfa3edc PL |
829 | if (!cache->available_p) |
830 | *this_id = frame_id_build_unavailable_stack (cache->func); | |
831 | else | |
832 | *this_id = frame_id_build (cache->prev_sp, cache->func); | |
07b287a0 MS |
833 | } |
834 | ||
835 | /* Implement the "prev_register" frame_unwind method. */ | |
836 | ||
837 | static struct value * | |
838 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
839 | void **this_cache, int prev_regnum) | |
840 | { | |
7c8edfae PL |
841 | struct aarch64_prologue_cache *cache |
842 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
843 | |
844 | /* If we are asked to unwind the PC, then we need to return the LR | |
845 | instead. The prologue may save PC, but it will point into this | |
846 | frame's prologue, not the next frame's resume location. */ | |
847 | if (prev_regnum == AARCH64_PC_REGNUM) | |
848 | { | |
849 | CORE_ADDR lr; | |
850 | ||
851 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
852 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); | |
853 | } | |
854 | ||
855 | /* SP is generally not saved to the stack, but this frame is | |
856 | identified by the next frame's stack pointer at the time of the | |
857 | call. The value was already reconstructed into PREV_SP. */ | |
858 | /* | |
859 | +----------+ ^ | |
860 | | saved lr | | | |
861 | +->| saved fp |--+ | |
862 | | | | | |
863 | | | | <- Previous SP | |
864 | | +----------+ | |
865 | | | saved lr | | |
866 | +--| saved fp |<- FP | |
867 | | | | |
868 | | |<- SP | |
869 | +----------+ */ | |
870 | if (prev_regnum == AARCH64_SP_REGNUM) | |
871 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
872 | cache->prev_sp); | |
873 | ||
874 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
875 | prev_regnum); | |
876 | } | |
877 | ||
878 | /* AArch64 prologue unwinder. */ | |
879 | struct frame_unwind aarch64_prologue_unwind = | |
880 | { | |
881 | NORMAL_FRAME, | |
7dfa3edc | 882 | aarch64_prologue_frame_unwind_stop_reason, |
07b287a0 MS |
883 | aarch64_prologue_this_id, |
884 | aarch64_prologue_prev_register, | |
885 | NULL, | |
886 | default_frame_sniffer | |
887 | }; | |
888 | ||
8b61f75d PL |
889 | /* Allocate and fill in *THIS_CACHE with information about the prologue of |
890 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
891 | Return a pointer to the current aarch64_prologue_cache in | |
892 | *THIS_CACHE. */ | |
07b287a0 MS |
893 | |
894 | static struct aarch64_prologue_cache * | |
8b61f75d | 895 | aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache) |
07b287a0 | 896 | { |
07b287a0 | 897 | struct aarch64_prologue_cache *cache; |
8b61f75d PL |
898 | |
899 | if (*this_cache != NULL) | |
9a3c8263 | 900 | return (struct aarch64_prologue_cache *) *this_cache; |
07b287a0 MS |
901 | |
902 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
903 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
8b61f75d | 904 | *this_cache = cache; |
07b287a0 | 905 | |
02a2a705 PL |
906 | TRY |
907 | { | |
908 | cache->prev_sp = get_frame_register_unsigned (this_frame, | |
909 | AARCH64_SP_REGNUM); | |
910 | cache->prev_pc = get_frame_pc (this_frame); | |
911 | cache->available_p = 1; | |
912 | } | |
913 | CATCH (ex, RETURN_MASK_ERROR) | |
914 | { | |
915 | if (ex.error != NOT_AVAILABLE_ERROR) | |
916 | throw_exception (ex); | |
917 | } | |
918 | END_CATCH | |
07b287a0 MS |
919 | |
920 | return cache; | |
921 | } | |
922 | ||
02a2a705 PL |
923 | /* Implement the "stop_reason" frame_unwind method. */ |
924 | ||
925 | static enum unwind_stop_reason | |
926 | aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame, | |
927 | void **this_cache) | |
928 | { | |
929 | struct aarch64_prologue_cache *cache | |
930 | = aarch64_make_stub_cache (this_frame, this_cache); | |
931 | ||
932 | if (!cache->available_p) | |
933 | return UNWIND_UNAVAILABLE; | |
934 | ||
935 | return UNWIND_NO_REASON; | |
936 | } | |
937 | ||
07b287a0 MS |
938 | /* Our frame ID for a stub frame is the current SP and LR. */ |
939 | ||
940 | static void | |
941 | aarch64_stub_this_id (struct frame_info *this_frame, | |
942 | void **this_cache, struct frame_id *this_id) | |
943 | { | |
8b61f75d PL |
944 | struct aarch64_prologue_cache *cache |
945 | = aarch64_make_stub_cache (this_frame, this_cache); | |
07b287a0 | 946 | |
02a2a705 PL |
947 | if (cache->available_p) |
948 | *this_id = frame_id_build (cache->prev_sp, cache->prev_pc); | |
949 | else | |
950 | *this_id = frame_id_build_unavailable_stack (cache->prev_pc); | |
07b287a0 MS |
951 | } |
952 | ||
953 | /* Implement the "sniffer" frame_unwind method. */ | |
954 | ||
955 | static int | |
956 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
957 | struct frame_info *this_frame, | |
958 | void **this_prologue_cache) | |
959 | { | |
960 | CORE_ADDR addr_in_block; | |
961 | gdb_byte dummy[4]; | |
962 | ||
963 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 964 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
965 | /* We also use the stub winder if the target memory is unreadable |
966 | to avoid having the prologue unwinder trying to read it. */ | |
967 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
968 | return 1; | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | /* AArch64 stub unwinder. */ | |
974 | struct frame_unwind aarch64_stub_unwind = | |
975 | { | |
976 | NORMAL_FRAME, | |
02a2a705 | 977 | aarch64_stub_frame_unwind_stop_reason, |
07b287a0 MS |
978 | aarch64_stub_this_id, |
979 | aarch64_prologue_prev_register, | |
980 | NULL, | |
981 | aarch64_stub_unwind_sniffer | |
982 | }; | |
983 | ||
984 | /* Return the frame base address of *THIS_FRAME. */ | |
985 | ||
986 | static CORE_ADDR | |
987 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
988 | { | |
7c8edfae PL |
989 | struct aarch64_prologue_cache *cache |
990 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
991 | |
992 | return cache->prev_sp - cache->framesize; | |
993 | } | |
994 | ||
995 | /* AArch64 default frame base information. */ | |
996 | struct frame_base aarch64_normal_base = | |
997 | { | |
998 | &aarch64_prologue_unwind, | |
999 | aarch64_normal_frame_base, | |
1000 | aarch64_normal_frame_base, | |
1001 | aarch64_normal_frame_base | |
1002 | }; | |
1003 | ||
1004 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that | |
1005 | dummy frame. The frame ID's base needs to match the TOS value | |
1006 | saved by save_dummy_frame_tos () and returned from | |
1007 | aarch64_push_dummy_call, and the PC needs to match the dummy | |
1008 | frame's breakpoint. */ | |
1009 | ||
1010 | static struct frame_id | |
1011 | aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1012 | { | |
1013 | return frame_id_build (get_frame_register_unsigned (this_frame, | |
1014 | AARCH64_SP_REGNUM), | |
1015 | get_frame_pc (this_frame)); | |
1016 | } | |
1017 | ||
1018 | /* Implement the "unwind_pc" gdbarch method. */ | |
1019 | ||
1020 | static CORE_ADDR | |
1021 | aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1022 | { | |
1023 | CORE_ADDR pc | |
1024 | = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM); | |
1025 | ||
1026 | return pc; | |
1027 | } | |
1028 | ||
1029 | /* Implement the "unwind_sp" gdbarch method. */ | |
1030 | ||
1031 | static CORE_ADDR | |
1032 | aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1033 | { | |
1034 | return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1035 | } | |
1036 | ||
1037 | /* Return the value of the REGNUM register in the previous frame of | |
1038 | *THIS_FRAME. */ | |
1039 | ||
1040 | static struct value * | |
1041 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1042 | void **this_cache, int regnum) | |
1043 | { | |
07b287a0 MS |
1044 | CORE_ADDR lr; |
1045 | ||
1046 | switch (regnum) | |
1047 | { | |
1048 | case AARCH64_PC_REGNUM: | |
1049 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1050 | return frame_unwind_got_constant (this_frame, regnum, lr); | |
1051 | ||
1052 | default: | |
1053 | internal_error (__FILE__, __LINE__, | |
1054 | _("Unexpected register %d"), regnum); | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | /* Implement the "init_reg" dwarf2_frame_ops method. */ | |
1059 | ||
1060 | static void | |
1061 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1062 | struct dwarf2_frame_state_reg *reg, | |
1063 | struct frame_info *this_frame) | |
1064 | { | |
1065 | switch (regnum) | |
1066 | { | |
1067 | case AARCH64_PC_REGNUM: | |
1068 | reg->how = DWARF2_FRAME_REG_FN; | |
1069 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
1070 | break; | |
1071 | case AARCH64_SP_REGNUM: | |
1072 | reg->how = DWARF2_FRAME_REG_CFA; | |
1073 | break; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | /* When arguments must be pushed onto the stack, they go on in reverse | |
1078 | order. The code below implements a FILO (stack) to do this. */ | |
1079 | ||
1080 | typedef struct | |
1081 | { | |
c3c87445 YQ |
1082 | /* Value to pass on stack. It can be NULL if this item is for stack |
1083 | padding. */ | |
7c543f7b | 1084 | const gdb_byte *data; |
07b287a0 MS |
1085 | |
1086 | /* Size in bytes of value to pass on stack. */ | |
1087 | int len; | |
1088 | } stack_item_t; | |
1089 | ||
1090 | DEF_VEC_O (stack_item_t); | |
1091 | ||
1092 | /* Return the alignment (in bytes) of the given type. */ | |
1093 | ||
1094 | static int | |
1095 | aarch64_type_align (struct type *t) | |
1096 | { | |
1097 | int n; | |
1098 | int align; | |
1099 | int falign; | |
1100 | ||
1101 | t = check_typedef (t); | |
1102 | switch (TYPE_CODE (t)) | |
1103 | { | |
1104 | default: | |
1105 | /* Should never happen. */ | |
1106 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1107 | return 4; | |
1108 | ||
1109 | case TYPE_CODE_PTR: | |
1110 | case TYPE_CODE_ENUM: | |
1111 | case TYPE_CODE_INT: | |
1112 | case TYPE_CODE_FLT: | |
1113 | case TYPE_CODE_SET: | |
1114 | case TYPE_CODE_RANGE: | |
1115 | case TYPE_CODE_BITSTRING: | |
1116 | case TYPE_CODE_REF: | |
aa006118 | 1117 | case TYPE_CODE_RVALUE_REF: |
07b287a0 MS |
1118 | case TYPE_CODE_CHAR: |
1119 | case TYPE_CODE_BOOL: | |
1120 | return TYPE_LENGTH (t); | |
1121 | ||
1122 | case TYPE_CODE_ARRAY: | |
238f2452 YQ |
1123 | if (TYPE_VECTOR (t)) |
1124 | { | |
1125 | /* Use the natural alignment for vector types (the same for | |
1126 | scalar type), but the maximum alignment is 128-bit. */ | |
1127 | if (TYPE_LENGTH (t) > 16) | |
1128 | return 16; | |
1129 | else | |
1130 | return TYPE_LENGTH (t); | |
1131 | } | |
1132 | else | |
1133 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
07b287a0 MS |
1134 | case TYPE_CODE_COMPLEX: |
1135 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
1136 | ||
1137 | case TYPE_CODE_STRUCT: | |
1138 | case TYPE_CODE_UNION: | |
1139 | align = 1; | |
1140 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1141 | { | |
1142 | falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n)); | |
1143 | if (falign > align) | |
1144 | align = falign; | |
1145 | } | |
1146 | return align; | |
1147 | } | |
1148 | } | |
1149 | ||
cd635f74 YQ |
1150 | /* Return 1 if *TY is a homogeneous floating-point aggregate or |
1151 | homogeneous short-vector aggregate as defined in the AAPCS64 ABI | |
1152 | document; otherwise return 0. */ | |
07b287a0 MS |
1153 | |
1154 | static int | |
cd635f74 | 1155 | is_hfa_or_hva (struct type *ty) |
07b287a0 MS |
1156 | { |
1157 | switch (TYPE_CODE (ty)) | |
1158 | { | |
1159 | case TYPE_CODE_ARRAY: | |
1160 | { | |
1161 | struct type *target_ty = TYPE_TARGET_TYPE (ty); | |
238f2452 YQ |
1162 | |
1163 | if (TYPE_VECTOR (ty)) | |
1164 | return 0; | |
1165 | ||
cd635f74 YQ |
1166 | if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */ |
1167 | && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */ | |
1168 | || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */ | |
1169 | && TYPE_VECTOR (target_ty)))) | |
07b287a0 MS |
1170 | return 1; |
1171 | break; | |
1172 | } | |
1173 | ||
1174 | case TYPE_CODE_UNION: | |
1175 | case TYPE_CODE_STRUCT: | |
1176 | { | |
cd635f74 | 1177 | /* HFA or HVA has at most four members. */ |
07b287a0 MS |
1178 | if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4) |
1179 | { | |
1180 | struct type *member0_type; | |
1181 | ||
1182 | member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0)); | |
cd635f74 YQ |
1183 | if (TYPE_CODE (member0_type) == TYPE_CODE_FLT |
1184 | || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY | |
1185 | && TYPE_VECTOR (member0_type))) | |
07b287a0 MS |
1186 | { |
1187 | int i; | |
1188 | ||
1189 | for (i = 0; i < TYPE_NFIELDS (ty); i++) | |
1190 | { | |
1191 | struct type *member1_type; | |
1192 | ||
1193 | member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i)); | |
1194 | if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type) | |
1195 | || (TYPE_LENGTH (member0_type) | |
1196 | != TYPE_LENGTH (member1_type))) | |
1197 | return 0; | |
1198 | } | |
1199 | return 1; | |
1200 | } | |
1201 | } | |
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | default: | |
1206 | break; | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | /* AArch64 function call information structure. */ | |
1213 | struct aarch64_call_info | |
1214 | { | |
1215 | /* the current argument number. */ | |
1216 | unsigned argnum; | |
1217 | ||
1218 | /* The next general purpose register number, equivalent to NGRN as | |
1219 | described in the AArch64 Procedure Call Standard. */ | |
1220 | unsigned ngrn; | |
1221 | ||
1222 | /* The next SIMD and floating point register number, equivalent to | |
1223 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
1224 | unsigned nsrn; | |
1225 | ||
1226 | /* The next stacked argument address, equivalent to NSAA as | |
1227 | described in the AArch64 Procedure Call Standard. */ | |
1228 | unsigned nsaa; | |
1229 | ||
1230 | /* Stack item vector. */ | |
1231 | VEC(stack_item_t) *si; | |
1232 | }; | |
1233 | ||
1234 | /* Pass a value in a sequence of consecutive X registers. The caller | |
1235 | is responsbile for ensuring sufficient registers are available. */ | |
1236 | ||
1237 | static void | |
1238 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1239 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1240 | struct value *arg) |
07b287a0 MS |
1241 | { |
1242 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1243 | int len = TYPE_LENGTH (type); | |
1244 | enum type_code typecode = TYPE_CODE (type); | |
1245 | int regnum = AARCH64_X0_REGNUM + info->ngrn; | |
8e80f9d1 | 1246 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1247 | |
1248 | info->argnum++; | |
1249 | ||
1250 | while (len > 0) | |
1251 | { | |
1252 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1253 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1254 | byte_order); | |
1255 | ||
1256 | ||
1257 | /* Adjust sub-word struct/union args when big-endian. */ | |
1258 | if (byte_order == BFD_ENDIAN_BIG | |
1259 | && partial_len < X_REGISTER_SIZE | |
1260 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1261 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1262 | ||
1263 | if (aarch64_debug) | |
b277c936 PL |
1264 | { |
1265 | debug_printf ("arg %d in %s = 0x%s\n", info->argnum, | |
1266 | gdbarch_register_name (gdbarch, regnum), | |
1267 | phex (regval, X_REGISTER_SIZE)); | |
1268 | } | |
07b287a0 MS |
1269 | regcache_cooked_write_unsigned (regcache, regnum, regval); |
1270 | len -= partial_len; | |
1271 | buf += partial_len; | |
1272 | regnum++; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | /* Attempt to marshall a value in a V register. Return 1 if | |
1277 | successful, or 0 if insufficient registers are available. This | |
1278 | function, unlike the equivalent pass_in_x() function does not | |
1279 | handle arguments spread across multiple registers. */ | |
1280 | ||
1281 | static int | |
1282 | pass_in_v (struct gdbarch *gdbarch, | |
1283 | struct regcache *regcache, | |
1284 | struct aarch64_call_info *info, | |
0735fddd | 1285 | int len, const bfd_byte *buf) |
07b287a0 MS |
1286 | { |
1287 | if (info->nsrn < 8) | |
1288 | { | |
07b287a0 | 1289 | int regnum = AARCH64_V0_REGNUM + info->nsrn; |
0735fddd | 1290 | gdb_byte reg[V_REGISTER_SIZE]; |
07b287a0 MS |
1291 | |
1292 | info->argnum++; | |
1293 | info->nsrn++; | |
1294 | ||
0735fddd YQ |
1295 | memset (reg, 0, sizeof (reg)); |
1296 | /* PCS C.1, the argument is allocated to the least significant | |
1297 | bits of V register. */ | |
1298 | memcpy (reg, buf, len); | |
b66f5587 | 1299 | regcache->cooked_write (regnum, reg); |
0735fddd | 1300 | |
07b287a0 | 1301 | if (aarch64_debug) |
b277c936 PL |
1302 | { |
1303 | debug_printf ("arg %d in %s\n", info->argnum, | |
1304 | gdbarch_register_name (gdbarch, regnum)); | |
1305 | } | |
07b287a0 MS |
1306 | return 1; |
1307 | } | |
1308 | info->nsrn = 8; | |
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | /* Marshall an argument onto the stack. */ | |
1313 | ||
1314 | static void | |
1315 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1316 | struct value *arg) |
07b287a0 | 1317 | { |
8e80f9d1 | 1318 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1319 | int len = TYPE_LENGTH (type); |
1320 | int align; | |
1321 | stack_item_t item; | |
1322 | ||
1323 | info->argnum++; | |
1324 | ||
1325 | align = aarch64_type_align (type); | |
1326 | ||
1327 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1328 | Natural alignment of the argument's type. */ | |
1329 | align = align_up (align, 8); | |
1330 | ||
1331 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1332 | if (align > 16) | |
1333 | align = 16; | |
1334 | ||
1335 | if (aarch64_debug) | |
b277c936 PL |
1336 | { |
1337 | debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len, | |
1338 | info->nsaa); | |
1339 | } | |
07b287a0 MS |
1340 | |
1341 | item.len = len; | |
1342 | item.data = buf; | |
1343 | VEC_safe_push (stack_item_t, info->si, &item); | |
1344 | ||
1345 | info->nsaa += len; | |
1346 | if (info->nsaa & (align - 1)) | |
1347 | { | |
1348 | /* Push stack alignment padding. */ | |
1349 | int pad = align - (info->nsaa & (align - 1)); | |
1350 | ||
1351 | item.len = pad; | |
c3c87445 | 1352 | item.data = NULL; |
07b287a0 MS |
1353 | |
1354 | VEC_safe_push (stack_item_t, info->si, &item); | |
1355 | info->nsaa += pad; | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | /* Marshall an argument into a sequence of one or more consecutive X | |
1360 | registers or, if insufficient X registers are available then onto | |
1361 | the stack. */ | |
1362 | ||
1363 | static void | |
1364 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1365 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1366 | struct value *arg) |
07b287a0 MS |
1367 | { |
1368 | int len = TYPE_LENGTH (type); | |
1369 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1370 | ||
1371 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1372 | if (info->ngrn + nregs <= 8) | |
1373 | { | |
8e80f9d1 | 1374 | pass_in_x (gdbarch, regcache, info, type, arg); |
07b287a0 MS |
1375 | info->ngrn += nregs; |
1376 | } | |
1377 | else | |
1378 | { | |
1379 | info->ngrn = 8; | |
8e80f9d1 | 1380 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1381 | } |
1382 | } | |
1383 | ||
1384 | /* Pass a value in a V register, or on the stack if insufficient are | |
1385 | available. */ | |
1386 | ||
1387 | static void | |
1388 | pass_in_v_or_stack (struct gdbarch *gdbarch, | |
1389 | struct regcache *regcache, | |
1390 | struct aarch64_call_info *info, | |
1391 | struct type *type, | |
8e80f9d1 | 1392 | struct value *arg) |
07b287a0 | 1393 | { |
0735fddd YQ |
1394 | if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type), |
1395 | value_contents (arg))) | |
8e80f9d1 | 1396 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1397 | } |
1398 | ||
1399 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1400 | ||
1401 | static CORE_ADDR | |
1402 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1403 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1404 | int nargs, | |
1405 | struct value **args, CORE_ADDR sp, int struct_return, | |
1406 | CORE_ADDR struct_addr) | |
1407 | { | |
07b287a0 | 1408 | int argnum; |
07b287a0 MS |
1409 | struct aarch64_call_info info; |
1410 | struct type *func_type; | |
1411 | struct type *return_type; | |
1412 | int lang_struct_return; | |
1413 | ||
1414 | memset (&info, 0, sizeof (info)); | |
1415 | ||
1416 | /* We need to know what the type of the called function is in order | |
1417 | to determine the number of named/anonymous arguments for the | |
1418 | actual argument placement, and the return type in order to handle | |
1419 | return value correctly. | |
1420 | ||
1421 | The generic code above us views the decision of return in memory | |
1422 | or return in registers as a two stage processes. The language | |
1423 | handler is consulted first and may decide to return in memory (eg | |
1424 | class with copy constructor returned by value), this will cause | |
1425 | the generic code to allocate space AND insert an initial leading | |
1426 | argument. | |
1427 | ||
1428 | If the language code does not decide to pass in memory then the | |
1429 | target code is consulted. | |
1430 | ||
1431 | If the language code decides to pass in memory we want to move | |
1432 | the pointer inserted as the initial argument from the argument | |
1433 | list and into X8, the conventional AArch64 struct return pointer | |
1434 | register. | |
1435 | ||
1436 | This is slightly awkward, ideally the flag "lang_struct_return" | |
1437 | would be passed to the targets implementation of push_dummy_call. | |
1438 | Rather that change the target interface we call the language code | |
1439 | directly ourselves. */ | |
1440 | ||
1441 | func_type = check_typedef (value_type (function)); | |
1442 | ||
1443 | /* Dereference function pointer types. */ | |
1444 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
1445 | func_type = TYPE_TARGET_TYPE (func_type); | |
1446 | ||
1447 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
1448 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
1449 | ||
1450 | /* If language_pass_by_reference () returned true we will have been | |
1451 | given an additional initial argument, a hidden pointer to the | |
1452 | return slot in memory. */ | |
1453 | return_type = TYPE_TARGET_TYPE (func_type); | |
1454 | lang_struct_return = language_pass_by_reference (return_type); | |
1455 | ||
1456 | /* Set the return address. For the AArch64, the return breakpoint | |
1457 | is always at BP_ADDR. */ | |
1458 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1459 | ||
1460 | /* If we were given an initial argument for the return slot because | |
1461 | lang_struct_return was true, lose it. */ | |
1462 | if (lang_struct_return) | |
1463 | { | |
1464 | args++; | |
1465 | nargs--; | |
1466 | } | |
1467 | ||
1468 | /* The struct_return pointer occupies X8. */ | |
1469 | if (struct_return || lang_struct_return) | |
1470 | { | |
1471 | if (aarch64_debug) | |
b277c936 PL |
1472 | { |
1473 | debug_printf ("struct return in %s = 0x%s\n", | |
1474 | gdbarch_register_name (gdbarch, | |
1475 | AARCH64_STRUCT_RETURN_REGNUM), | |
1476 | paddress (gdbarch, struct_addr)); | |
1477 | } | |
07b287a0 MS |
1478 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, |
1479 | struct_addr); | |
1480 | } | |
1481 | ||
1482 | for (argnum = 0; argnum < nargs; argnum++) | |
1483 | { | |
1484 | struct value *arg = args[argnum]; | |
1485 | struct type *arg_type; | |
1486 | int len; | |
1487 | ||
1488 | arg_type = check_typedef (value_type (arg)); | |
1489 | len = TYPE_LENGTH (arg_type); | |
1490 | ||
1491 | switch (TYPE_CODE (arg_type)) | |
1492 | { | |
1493 | case TYPE_CODE_INT: | |
1494 | case TYPE_CODE_BOOL: | |
1495 | case TYPE_CODE_CHAR: | |
1496 | case TYPE_CODE_RANGE: | |
1497 | case TYPE_CODE_ENUM: | |
1498 | if (len < 4) | |
1499 | { | |
1500 | /* Promote to 32 bit integer. */ | |
1501 | if (TYPE_UNSIGNED (arg_type)) | |
1502 | arg_type = builtin_type (gdbarch)->builtin_uint32; | |
1503 | else | |
1504 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1505 | arg = value_cast (arg_type, arg); | |
1506 | } | |
8e80f9d1 | 1507 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1508 | break; |
1509 | ||
1510 | case TYPE_CODE_COMPLEX: | |
1511 | if (info.nsrn <= 6) | |
1512 | { | |
1513 | const bfd_byte *buf = value_contents (arg); | |
1514 | struct type *target_type = | |
1515 | check_typedef (TYPE_TARGET_TYPE (arg_type)); | |
1516 | ||
07b287a0 | 1517 | pass_in_v (gdbarch, regcache, &info, |
0735fddd YQ |
1518 | TYPE_LENGTH (target_type), buf); |
1519 | pass_in_v (gdbarch, regcache, &info, | |
1520 | TYPE_LENGTH (target_type), | |
07b287a0 MS |
1521 | buf + TYPE_LENGTH (target_type)); |
1522 | } | |
1523 | else | |
1524 | { | |
1525 | info.nsrn = 8; | |
8e80f9d1 | 1526 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1527 | } |
1528 | break; | |
1529 | case TYPE_CODE_FLT: | |
8e80f9d1 | 1530 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1531 | break; |
1532 | ||
1533 | case TYPE_CODE_STRUCT: | |
1534 | case TYPE_CODE_ARRAY: | |
1535 | case TYPE_CODE_UNION: | |
cd635f74 | 1536 | if (is_hfa_or_hva (arg_type)) |
07b287a0 MS |
1537 | { |
1538 | int elements = TYPE_NFIELDS (arg_type); | |
1539 | ||
1540 | /* Homogeneous Aggregates */ | |
1541 | if (info.nsrn + elements < 8) | |
1542 | { | |
1543 | int i; | |
1544 | ||
1545 | for (i = 0; i < elements; i++) | |
1546 | { | |
1547 | /* We know that we have sufficient registers | |
1548 | available therefore this will never fallback | |
1549 | to the stack. */ | |
1550 | struct value *field = | |
1551 | value_primitive_field (arg, 0, i, arg_type); | |
1552 | struct type *field_type = | |
1553 | check_typedef (value_type (field)); | |
1554 | ||
8e80f9d1 YQ |
1555 | pass_in_v_or_stack (gdbarch, regcache, &info, |
1556 | field_type, field); | |
07b287a0 MS |
1557 | } |
1558 | } | |
1559 | else | |
1560 | { | |
1561 | info.nsrn = 8; | |
8e80f9d1 | 1562 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1563 | } |
1564 | } | |
238f2452 YQ |
1565 | else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY |
1566 | && TYPE_VECTOR (arg_type) && (len == 16 || len == 8)) | |
1567 | { | |
1568 | /* Short vector types are passed in V registers. */ | |
1569 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); | |
1570 | } | |
07b287a0 MS |
1571 | else if (len > 16) |
1572 | { | |
1573 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1574 | invisible reference. */ | |
1575 | ||
1576 | /* Allocate aligned storage. */ | |
1577 | sp = align_down (sp - len, 16); | |
1578 | ||
1579 | /* Write the real data into the stack. */ | |
1580 | write_memory (sp, value_contents (arg), len); | |
1581 | ||
1582 | /* Construct the indirection. */ | |
1583 | arg_type = lookup_pointer_type (arg_type); | |
1584 | arg = value_from_pointer (arg_type, sp); | |
8e80f9d1 | 1585 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1586 | } |
1587 | else | |
1588 | /* PCS C.15 / C.18 multiple values pass. */ | |
8e80f9d1 | 1589 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1590 | break; |
1591 | ||
1592 | default: | |
8e80f9d1 | 1593 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1594 | break; |
1595 | } | |
1596 | } | |
1597 | ||
1598 | /* Make sure stack retains 16 byte alignment. */ | |
1599 | if (info.nsaa & 15) | |
1600 | sp -= 16 - (info.nsaa & 15); | |
1601 | ||
1602 | while (!VEC_empty (stack_item_t, info.si)) | |
1603 | { | |
1604 | stack_item_t *si = VEC_last (stack_item_t, info.si); | |
1605 | ||
1606 | sp -= si->len; | |
c3c87445 YQ |
1607 | if (si->data != NULL) |
1608 | write_memory (sp, si->data, si->len); | |
07b287a0 MS |
1609 | VEC_pop (stack_item_t, info.si); |
1610 | } | |
1611 | ||
1612 | VEC_free (stack_item_t, info.si); | |
1613 | ||
1614 | /* Finally, update the SP register. */ | |
1615 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1616 | ||
1617 | return sp; | |
1618 | } | |
1619 | ||
1620 | /* Implement the "frame_align" gdbarch method. */ | |
1621 | ||
1622 | static CORE_ADDR | |
1623 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1624 | { | |
1625 | /* Align the stack to sixteen bytes. */ | |
1626 | return sp & ~(CORE_ADDR) 15; | |
1627 | } | |
1628 | ||
1629 | /* Return the type for an AdvSISD Q register. */ | |
1630 | ||
1631 | static struct type * | |
1632 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
1633 | { | |
1634 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1635 | ||
1636 | if (tdep->vnq_type == NULL) | |
1637 | { | |
1638 | struct type *t; | |
1639 | struct type *elem; | |
1640 | ||
1641 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
1642 | TYPE_CODE_UNION); | |
1643 | ||
1644 | elem = builtin_type (gdbarch)->builtin_uint128; | |
1645 | append_composite_type_field (t, "u", elem); | |
1646 | ||
1647 | elem = builtin_type (gdbarch)->builtin_int128; | |
1648 | append_composite_type_field (t, "s", elem); | |
1649 | ||
1650 | tdep->vnq_type = t; | |
1651 | } | |
1652 | ||
1653 | return tdep->vnq_type; | |
1654 | } | |
1655 | ||
1656 | /* Return the type for an AdvSISD D register. */ | |
1657 | ||
1658 | static struct type * | |
1659 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
1660 | { | |
1661 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1662 | ||
1663 | if (tdep->vnd_type == NULL) | |
1664 | { | |
1665 | struct type *t; | |
1666 | struct type *elem; | |
1667 | ||
1668 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
1669 | TYPE_CODE_UNION); | |
1670 | ||
1671 | elem = builtin_type (gdbarch)->builtin_double; | |
1672 | append_composite_type_field (t, "f", elem); | |
1673 | ||
1674 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1675 | append_composite_type_field (t, "u", elem); | |
1676 | ||
1677 | elem = builtin_type (gdbarch)->builtin_int64; | |
1678 | append_composite_type_field (t, "s", elem); | |
1679 | ||
1680 | tdep->vnd_type = t; | |
1681 | } | |
1682 | ||
1683 | return tdep->vnd_type; | |
1684 | } | |
1685 | ||
1686 | /* Return the type for an AdvSISD S register. */ | |
1687 | ||
1688 | static struct type * | |
1689 | aarch64_vns_type (struct gdbarch *gdbarch) | |
1690 | { | |
1691 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1692 | ||
1693 | if (tdep->vns_type == NULL) | |
1694 | { | |
1695 | struct type *t; | |
1696 | struct type *elem; | |
1697 | ||
1698 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
1699 | TYPE_CODE_UNION); | |
1700 | ||
1701 | elem = builtin_type (gdbarch)->builtin_float; | |
1702 | append_composite_type_field (t, "f", elem); | |
1703 | ||
1704 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1705 | append_composite_type_field (t, "u", elem); | |
1706 | ||
1707 | elem = builtin_type (gdbarch)->builtin_int32; | |
1708 | append_composite_type_field (t, "s", elem); | |
1709 | ||
1710 | tdep->vns_type = t; | |
1711 | } | |
1712 | ||
1713 | return tdep->vns_type; | |
1714 | } | |
1715 | ||
1716 | /* Return the type for an AdvSISD H register. */ | |
1717 | ||
1718 | static struct type * | |
1719 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
1720 | { | |
1721 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1722 | ||
1723 | if (tdep->vnh_type == NULL) | |
1724 | { | |
1725 | struct type *t; | |
1726 | struct type *elem; | |
1727 | ||
1728 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
1729 | TYPE_CODE_UNION); | |
1730 | ||
1731 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1732 | append_composite_type_field (t, "u", elem); | |
1733 | ||
1734 | elem = builtin_type (gdbarch)->builtin_int16; | |
1735 | append_composite_type_field (t, "s", elem); | |
1736 | ||
1737 | tdep->vnh_type = t; | |
1738 | } | |
1739 | ||
1740 | return tdep->vnh_type; | |
1741 | } | |
1742 | ||
1743 | /* Return the type for an AdvSISD B register. */ | |
1744 | ||
1745 | static struct type * | |
1746 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
1747 | { | |
1748 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1749 | ||
1750 | if (tdep->vnb_type == NULL) | |
1751 | { | |
1752 | struct type *t; | |
1753 | struct type *elem; | |
1754 | ||
1755 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
1756 | TYPE_CODE_UNION); | |
1757 | ||
1758 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1759 | append_composite_type_field (t, "u", elem); | |
1760 | ||
1761 | elem = builtin_type (gdbarch)->builtin_int8; | |
1762 | append_composite_type_field (t, "s", elem); | |
1763 | ||
1764 | tdep->vnb_type = t; | |
1765 | } | |
1766 | ||
1767 | return tdep->vnb_type; | |
1768 | } | |
1769 | ||
63bad7b6 AH |
1770 | /* Return the type for an AdvSISD V register. */ |
1771 | ||
1772 | static struct type * | |
1773 | aarch64_vnv_type (struct gdbarch *gdbarch) | |
1774 | { | |
1775 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1776 | ||
1777 | if (tdep->vnv_type == NULL) | |
1778 | { | |
1779 | struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv", | |
1780 | TYPE_CODE_UNION); | |
1781 | ||
1782 | append_composite_type_field (t, "d", aarch64_vnd_type (gdbarch)); | |
1783 | append_composite_type_field (t, "s", aarch64_vns_type (gdbarch)); | |
1784 | append_composite_type_field (t, "h", aarch64_vnh_type (gdbarch)); | |
1785 | append_composite_type_field (t, "b", aarch64_vnb_type (gdbarch)); | |
1786 | append_composite_type_field (t, "q", aarch64_vnq_type (gdbarch)); | |
1787 | ||
1788 | tdep->vnv_type = t; | |
1789 | } | |
1790 | ||
1791 | return tdep->vnv_type; | |
1792 | } | |
1793 | ||
07b287a0 MS |
1794 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
1795 | ||
1796 | static int | |
1797 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1798 | { | |
1799 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) | |
1800 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
1801 | ||
1802 | if (reg == AARCH64_DWARF_SP) | |
1803 | return AARCH64_SP_REGNUM; | |
1804 | ||
1805 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) | |
1806 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
1807 | ||
65d4cada AH |
1808 | if (reg == AARCH64_DWARF_SVE_VG) |
1809 | return AARCH64_SVE_VG_REGNUM; | |
1810 | ||
1811 | if (reg == AARCH64_DWARF_SVE_FFR) | |
1812 | return AARCH64_SVE_FFR_REGNUM; | |
1813 | ||
1814 | if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15) | |
1815 | return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0; | |
1816 | ||
1817 | if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15) | |
1818 | return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0; | |
1819 | ||
07b287a0 MS |
1820 | return -1; |
1821 | } | |
07b287a0 MS |
1822 | |
1823 | /* Implement the "print_insn" gdbarch method. */ | |
1824 | ||
1825 | static int | |
1826 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
1827 | { | |
1828 | info->symbols = NULL; | |
6394c606 | 1829 | return default_print_insn (memaddr, info); |
07b287a0 MS |
1830 | } |
1831 | ||
1832 | /* AArch64 BRK software debug mode instruction. | |
1833 | Note that AArch64 code is always little-endian. | |
1834 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
04180708 | 1835 | constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 | 1836 | |
04180708 | 1837 | typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint; |
07b287a0 MS |
1838 | |
1839 | /* Extract from an array REGS containing the (raw) register state a | |
1840 | function return value of type TYPE, and copy that, in virtual | |
1841 | format, into VALBUF. */ | |
1842 | ||
1843 | static void | |
1844 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
1845 | gdb_byte *valbuf) | |
1846 | { | |
ac7936df | 1847 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 MS |
1848 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1849 | ||
1850 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1851 | { | |
1852 | bfd_byte buf[V_REGISTER_SIZE]; | |
1853 | int len = TYPE_LENGTH (type); | |
1854 | ||
dca08e1f | 1855 | regs->cooked_read (AARCH64_V0_REGNUM, buf); |
07b287a0 MS |
1856 | memcpy (valbuf, buf, len); |
1857 | } | |
1858 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1859 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1860 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1861 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 1862 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
1863 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
1864 | { | |
1865 | /* If the the type is a plain integer, then the access is | |
1866 | straight-forward. Otherwise we have to play around a bit | |
1867 | more. */ | |
1868 | int len = TYPE_LENGTH (type); | |
1869 | int regno = AARCH64_X0_REGNUM; | |
1870 | ULONGEST tmp; | |
1871 | ||
1872 | while (len > 0) | |
1873 | { | |
1874 | /* By using store_unsigned_integer we avoid having to do | |
1875 | anything special for small big-endian values. */ | |
1876 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
1877 | store_unsigned_integer (valbuf, | |
1878 | (len > X_REGISTER_SIZE | |
1879 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
1880 | len -= X_REGISTER_SIZE; | |
1881 | valbuf += X_REGISTER_SIZE; | |
1882 | } | |
1883 | } | |
1884 | else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX) | |
1885 | { | |
1886 | int regno = AARCH64_V0_REGNUM; | |
1887 | bfd_byte buf[V_REGISTER_SIZE]; | |
1888 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1889 | int len = TYPE_LENGTH (target_type); | |
1890 | ||
dca08e1f | 1891 | regs->cooked_read (regno, buf); |
07b287a0 MS |
1892 | memcpy (valbuf, buf, len); |
1893 | valbuf += len; | |
dca08e1f | 1894 | regs->cooked_read (regno + 1, buf); |
07b287a0 MS |
1895 | memcpy (valbuf, buf, len); |
1896 | valbuf += len; | |
1897 | } | |
cd635f74 | 1898 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
1899 | { |
1900 | int elements = TYPE_NFIELDS (type); | |
1901 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1902 | int len = TYPE_LENGTH (member_type); | |
1903 | int i; | |
1904 | ||
1905 | for (i = 0; i < elements; i++) | |
1906 | { | |
1907 | int regno = AARCH64_V0_REGNUM + i; | |
db3516bb | 1908 | bfd_byte buf[V_REGISTER_SIZE]; |
07b287a0 MS |
1909 | |
1910 | if (aarch64_debug) | |
b277c936 | 1911 | { |
cd635f74 | 1912 | debug_printf ("read HFA or HVA return value element %d from %s\n", |
b277c936 PL |
1913 | i + 1, |
1914 | gdbarch_register_name (gdbarch, regno)); | |
1915 | } | |
dca08e1f | 1916 | regs->cooked_read (regno, buf); |
07b287a0 MS |
1917 | |
1918 | memcpy (valbuf, buf, len); | |
1919 | valbuf += len; | |
1920 | } | |
1921 | } | |
238f2452 YQ |
1922 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
1923 | && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8)) | |
1924 | { | |
1925 | /* Short vector is returned in V register. */ | |
1926 | gdb_byte buf[V_REGISTER_SIZE]; | |
1927 | ||
dca08e1f | 1928 | regs->cooked_read (AARCH64_V0_REGNUM, buf); |
238f2452 YQ |
1929 | memcpy (valbuf, buf, TYPE_LENGTH (type)); |
1930 | } | |
07b287a0 MS |
1931 | else |
1932 | { | |
1933 | /* For a structure or union the behaviour is as if the value had | |
1934 | been stored to word-aligned memory and then loaded into | |
1935 | registers with 64-bit load instruction(s). */ | |
1936 | int len = TYPE_LENGTH (type); | |
1937 | int regno = AARCH64_X0_REGNUM; | |
1938 | bfd_byte buf[X_REGISTER_SIZE]; | |
1939 | ||
1940 | while (len > 0) | |
1941 | { | |
dca08e1f | 1942 | regs->cooked_read (regno++, buf); |
07b287a0 MS |
1943 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); |
1944 | len -= X_REGISTER_SIZE; | |
1945 | valbuf += X_REGISTER_SIZE; | |
1946 | } | |
1947 | } | |
1948 | } | |
1949 | ||
1950 | ||
1951 | /* Will a function return an aggregate type in memory or in a | |
1952 | register? Return 0 if an aggregate type can be returned in a | |
1953 | register, 1 if it must be returned in memory. */ | |
1954 | ||
1955 | static int | |
1956 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
1957 | { | |
f168693b | 1958 | type = check_typedef (type); |
07b287a0 | 1959 | |
cd635f74 | 1960 | if (is_hfa_or_hva (type)) |
07b287a0 | 1961 | { |
cd635f74 YQ |
1962 | /* v0-v7 are used to return values and one register is allocated |
1963 | for one member. However, HFA or HVA has at most four members. */ | |
07b287a0 MS |
1964 | return 0; |
1965 | } | |
1966 | ||
1967 | if (TYPE_LENGTH (type) > 16) | |
1968 | { | |
1969 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
1970 | invisible reference. */ | |
1971 | ||
1972 | return 1; | |
1973 | } | |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | /* Write into appropriate registers a function return value of type | |
1979 | TYPE, given in virtual format. */ | |
1980 | ||
1981 | static void | |
1982 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
1983 | const gdb_byte *valbuf) | |
1984 | { | |
ac7936df | 1985 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 MS |
1986 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1987 | ||
1988 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1989 | { | |
1990 | bfd_byte buf[V_REGISTER_SIZE]; | |
1991 | int len = TYPE_LENGTH (type); | |
1992 | ||
1993 | memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
b66f5587 | 1994 | regs->cooked_write (AARCH64_V0_REGNUM, buf); |
07b287a0 MS |
1995 | } |
1996 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1997 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1998 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1999 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 2000 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
2001 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
2002 | { | |
2003 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
2004 | { | |
2005 | /* Values of one word or less are zero/sign-extended and | |
2006 | returned in r0. */ | |
2007 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2008 | LONGEST val = unpack_long (type, valbuf); | |
2009 | ||
2010 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
b66f5587 | 2011 | regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf); |
07b287a0 MS |
2012 | } |
2013 | else | |
2014 | { | |
2015 | /* Integral values greater than one word are stored in | |
2016 | consecutive registers starting with r0. This will always | |
2017 | be a multiple of the regiser size. */ | |
2018 | int len = TYPE_LENGTH (type); | |
2019 | int regno = AARCH64_X0_REGNUM; | |
2020 | ||
2021 | while (len > 0) | |
2022 | { | |
b66f5587 | 2023 | regs->cooked_write (regno++, valbuf); |
07b287a0 MS |
2024 | len -= X_REGISTER_SIZE; |
2025 | valbuf += X_REGISTER_SIZE; | |
2026 | } | |
2027 | } | |
2028 | } | |
cd635f74 | 2029 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
2030 | { |
2031 | int elements = TYPE_NFIELDS (type); | |
2032 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2033 | int len = TYPE_LENGTH (member_type); | |
2034 | int i; | |
2035 | ||
2036 | for (i = 0; i < elements; i++) | |
2037 | { | |
2038 | int regno = AARCH64_V0_REGNUM + i; | |
d1be909e | 2039 | bfd_byte tmpbuf[V_REGISTER_SIZE]; |
07b287a0 MS |
2040 | |
2041 | if (aarch64_debug) | |
b277c936 | 2042 | { |
cd635f74 | 2043 | debug_printf ("write HFA or HVA return value element %d to %s\n", |
b277c936 PL |
2044 | i + 1, |
2045 | gdbarch_register_name (gdbarch, regno)); | |
2046 | } | |
07b287a0 MS |
2047 | |
2048 | memcpy (tmpbuf, valbuf, len); | |
b66f5587 | 2049 | regs->cooked_write (regno, tmpbuf); |
07b287a0 MS |
2050 | valbuf += len; |
2051 | } | |
2052 | } | |
238f2452 YQ |
2053 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
2054 | && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16)) | |
2055 | { | |
2056 | /* Short vector. */ | |
2057 | gdb_byte buf[V_REGISTER_SIZE]; | |
2058 | ||
2059 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
b66f5587 | 2060 | regs->cooked_write (AARCH64_V0_REGNUM, buf); |
238f2452 | 2061 | } |
07b287a0 MS |
2062 | else |
2063 | { | |
2064 | /* For a structure or union the behaviour is as if the value had | |
2065 | been stored to word-aligned memory and then loaded into | |
2066 | registers with 64-bit load instruction(s). */ | |
2067 | int len = TYPE_LENGTH (type); | |
2068 | int regno = AARCH64_X0_REGNUM; | |
2069 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2070 | ||
2071 | while (len > 0) | |
2072 | { | |
2073 | memcpy (tmpbuf, valbuf, | |
2074 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
b66f5587 | 2075 | regs->cooked_write (regno++, tmpbuf); |
07b287a0 MS |
2076 | len -= X_REGISTER_SIZE; |
2077 | valbuf += X_REGISTER_SIZE; | |
2078 | } | |
2079 | } | |
2080 | } | |
2081 | ||
2082 | /* Implement the "return_value" gdbarch method. */ | |
2083 | ||
2084 | static enum return_value_convention | |
2085 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2086 | struct type *valtype, struct regcache *regcache, | |
2087 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2088 | { | |
07b287a0 MS |
2089 | |
2090 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2091 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2092 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2093 | { | |
2094 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2095 | { | |
2096 | if (aarch64_debug) | |
b277c936 | 2097 | debug_printf ("return value in memory\n"); |
07b287a0 MS |
2098 | return RETURN_VALUE_STRUCT_CONVENTION; |
2099 | } | |
2100 | } | |
2101 | ||
2102 | if (writebuf) | |
2103 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2104 | ||
2105 | if (readbuf) | |
2106 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2107 | ||
2108 | if (aarch64_debug) | |
b277c936 | 2109 | debug_printf ("return value in registers\n"); |
07b287a0 MS |
2110 | |
2111 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2112 | } | |
2113 | ||
2114 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2115 | ||
2116 | static int | |
2117 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2118 | { | |
2119 | CORE_ADDR jb_addr; | |
2120 | gdb_byte buf[X_REGISTER_SIZE]; | |
2121 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2122 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2123 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2124 | ||
2125 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2126 | ||
2127 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2128 | X_REGISTER_SIZE)) | |
2129 | return 0; | |
2130 | ||
2131 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2132 | return 1; | |
2133 | } | |
ea873d8e PL |
2134 | |
2135 | /* Implement the "gen_return_address" gdbarch method. */ | |
2136 | ||
2137 | static void | |
2138 | aarch64_gen_return_address (struct gdbarch *gdbarch, | |
2139 | struct agent_expr *ax, struct axs_value *value, | |
2140 | CORE_ADDR scope) | |
2141 | { | |
2142 | value->type = register_type (gdbarch, AARCH64_LR_REGNUM); | |
2143 | value->kind = axs_lvalue_register; | |
2144 | value->u.reg = AARCH64_LR_REGNUM; | |
2145 | } | |
07b287a0 MS |
2146 | \f |
2147 | ||
2148 | /* Return the pseudo register name corresponding to register regnum. */ | |
2149 | ||
2150 | static const char * | |
2151 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2152 | { | |
63bad7b6 AH |
2153 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2154 | ||
07b287a0 MS |
2155 | static const char *const q_name[] = |
2156 | { | |
2157 | "q0", "q1", "q2", "q3", | |
2158 | "q4", "q5", "q6", "q7", | |
2159 | "q8", "q9", "q10", "q11", | |
2160 | "q12", "q13", "q14", "q15", | |
2161 | "q16", "q17", "q18", "q19", | |
2162 | "q20", "q21", "q22", "q23", | |
2163 | "q24", "q25", "q26", "q27", | |
2164 | "q28", "q29", "q30", "q31", | |
2165 | }; | |
2166 | ||
2167 | static const char *const d_name[] = | |
2168 | { | |
2169 | "d0", "d1", "d2", "d3", | |
2170 | "d4", "d5", "d6", "d7", | |
2171 | "d8", "d9", "d10", "d11", | |
2172 | "d12", "d13", "d14", "d15", | |
2173 | "d16", "d17", "d18", "d19", | |
2174 | "d20", "d21", "d22", "d23", | |
2175 | "d24", "d25", "d26", "d27", | |
2176 | "d28", "d29", "d30", "d31", | |
2177 | }; | |
2178 | ||
2179 | static const char *const s_name[] = | |
2180 | { | |
2181 | "s0", "s1", "s2", "s3", | |
2182 | "s4", "s5", "s6", "s7", | |
2183 | "s8", "s9", "s10", "s11", | |
2184 | "s12", "s13", "s14", "s15", | |
2185 | "s16", "s17", "s18", "s19", | |
2186 | "s20", "s21", "s22", "s23", | |
2187 | "s24", "s25", "s26", "s27", | |
2188 | "s28", "s29", "s30", "s31", | |
2189 | }; | |
2190 | ||
2191 | static const char *const h_name[] = | |
2192 | { | |
2193 | "h0", "h1", "h2", "h3", | |
2194 | "h4", "h5", "h6", "h7", | |
2195 | "h8", "h9", "h10", "h11", | |
2196 | "h12", "h13", "h14", "h15", | |
2197 | "h16", "h17", "h18", "h19", | |
2198 | "h20", "h21", "h22", "h23", | |
2199 | "h24", "h25", "h26", "h27", | |
2200 | "h28", "h29", "h30", "h31", | |
2201 | }; | |
2202 | ||
2203 | static const char *const b_name[] = | |
2204 | { | |
2205 | "b0", "b1", "b2", "b3", | |
2206 | "b4", "b5", "b6", "b7", | |
2207 | "b8", "b9", "b10", "b11", | |
2208 | "b12", "b13", "b14", "b15", | |
2209 | "b16", "b17", "b18", "b19", | |
2210 | "b20", "b21", "b22", "b23", | |
2211 | "b24", "b25", "b26", "b27", | |
2212 | "b28", "b29", "b30", "b31", | |
2213 | }; | |
2214 | ||
2215 | regnum -= gdbarch_num_regs (gdbarch); | |
2216 | ||
2217 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2218 | return q_name[regnum - AARCH64_Q0_REGNUM]; | |
2219 | ||
2220 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2221 | return d_name[regnum - AARCH64_D0_REGNUM]; | |
2222 | ||
2223 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2224 | return s_name[regnum - AARCH64_S0_REGNUM]; | |
2225 | ||
2226 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2227 | return h_name[regnum - AARCH64_H0_REGNUM]; | |
2228 | ||
2229 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2230 | return b_name[regnum - AARCH64_B0_REGNUM]; | |
2231 | ||
63bad7b6 AH |
2232 | if (tdep->has_sve ()) |
2233 | { | |
2234 | static const char *const sve_v_name[] = | |
2235 | { | |
2236 | "v0", "v1", "v2", "v3", | |
2237 | "v4", "v5", "v6", "v7", | |
2238 | "v8", "v9", "v10", "v11", | |
2239 | "v12", "v13", "v14", "v15", | |
2240 | "v16", "v17", "v18", "v19", | |
2241 | "v20", "v21", "v22", "v23", | |
2242 | "v24", "v25", "v26", "v27", | |
2243 | "v28", "v29", "v30", "v31", | |
2244 | }; | |
2245 | ||
2246 | if (regnum >= AARCH64_SVE_V0_REGNUM | |
2247 | && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
2248 | return sve_v_name[regnum - AARCH64_SVE_V0_REGNUM]; | |
2249 | } | |
2250 | ||
07b287a0 MS |
2251 | internal_error (__FILE__, __LINE__, |
2252 | _("aarch64_pseudo_register_name: bad register number %d"), | |
2253 | regnum); | |
2254 | } | |
2255 | ||
2256 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2257 | ||
2258 | static struct type * | |
2259 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2260 | { | |
63bad7b6 AH |
2261 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2262 | ||
07b287a0 MS |
2263 | regnum -= gdbarch_num_regs (gdbarch); |
2264 | ||
2265 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2266 | return aarch64_vnq_type (gdbarch); | |
2267 | ||
2268 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2269 | return aarch64_vnd_type (gdbarch); | |
2270 | ||
2271 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2272 | return aarch64_vns_type (gdbarch); | |
2273 | ||
2274 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2275 | return aarch64_vnh_type (gdbarch); | |
2276 | ||
2277 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2278 | return aarch64_vnb_type (gdbarch); | |
2279 | ||
63bad7b6 AH |
2280 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM |
2281 | && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
2282 | return aarch64_vnv_type (gdbarch); | |
2283 | ||
07b287a0 MS |
2284 | internal_error (__FILE__, __LINE__, |
2285 | _("aarch64_pseudo_register_type: bad register number %d"), | |
2286 | regnum); | |
2287 | } | |
2288 | ||
2289 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2290 | ||
2291 | static int | |
2292 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2293 | struct reggroup *group) | |
2294 | { | |
63bad7b6 AH |
2295 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2296 | ||
07b287a0 MS |
2297 | regnum -= gdbarch_num_regs (gdbarch); |
2298 | ||
2299 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2300 | return group == all_reggroup || group == vector_reggroup; | |
2301 | else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2302 | return (group == all_reggroup || group == vector_reggroup | |
2303 | || group == float_reggroup); | |
2304 | else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2305 | return (group == all_reggroup || group == vector_reggroup | |
2306 | || group == float_reggroup); | |
2307 | else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2308 | return group == all_reggroup || group == vector_reggroup; | |
2309 | else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2310 | return group == all_reggroup || group == vector_reggroup; | |
63bad7b6 AH |
2311 | else if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM |
2312 | && regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
2313 | return group == all_reggroup || group == vector_reggroup; | |
07b287a0 MS |
2314 | |
2315 | return group == all_reggroup; | |
2316 | } | |
2317 | ||
3c5cd5c3 AH |
2318 | /* Helper for aarch64_pseudo_read_value. */ |
2319 | ||
2320 | static struct value * | |
63bad7b6 AH |
2321 | aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch, |
2322 | readable_regcache *regcache, int regnum_offset, | |
3c5cd5c3 AH |
2323 | int regsize, struct value *result_value) |
2324 | { | |
3c5cd5c3 AH |
2325 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
2326 | ||
63bad7b6 AH |
2327 | /* Enough space for a full vector register. */ |
2328 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2329 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2330 | ||
3c5cd5c3 AH |
2331 | if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID) |
2332 | mark_value_bytes_unavailable (result_value, 0, | |
2333 | TYPE_LENGTH (value_type (result_value))); | |
2334 | else | |
2335 | memcpy (value_contents_raw (result_value), reg_buf, regsize); | |
63bad7b6 | 2336 | |
3c5cd5c3 AH |
2337 | return result_value; |
2338 | } | |
2339 | ||
07b287a0 MS |
2340 | /* Implement the "pseudo_register_read_value" gdbarch method. */ |
2341 | ||
2342 | static struct value * | |
3c5cd5c3 | 2343 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache, |
07b287a0 MS |
2344 | int regnum) |
2345 | { | |
63bad7b6 | 2346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3c5cd5c3 | 2347 | struct value *result_value = allocate_value (register_type (gdbarch, regnum)); |
07b287a0 | 2348 | |
07b287a0 MS |
2349 | VALUE_LVAL (result_value) = lval_register; |
2350 | VALUE_REGNUM (result_value) = regnum; | |
07b287a0 MS |
2351 | |
2352 | regnum -= gdbarch_num_regs (gdbarch); | |
2353 | ||
2354 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2355 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2356 | regnum - AARCH64_Q0_REGNUM, | |
3c5cd5c3 | 2357 | Q_REGISTER_SIZE, result_value); |
07b287a0 MS |
2358 | |
2359 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2360 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2361 | regnum - AARCH64_D0_REGNUM, | |
3c5cd5c3 | 2362 | D_REGISTER_SIZE, result_value); |
07b287a0 MS |
2363 | |
2364 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2365 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2366 | regnum - AARCH64_S0_REGNUM, | |
3c5cd5c3 | 2367 | S_REGISTER_SIZE, result_value); |
07b287a0 MS |
2368 | |
2369 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2370 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2371 | regnum - AARCH64_H0_REGNUM, | |
3c5cd5c3 | 2372 | H_REGISTER_SIZE, result_value); |
07b287a0 MS |
2373 | |
2374 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2375 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2376 | regnum - AARCH64_B0_REGNUM, | |
3c5cd5c3 | 2377 | B_REGISTER_SIZE, result_value); |
07b287a0 | 2378 | |
63bad7b6 AH |
2379 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM |
2380 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2381 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, | |
2382 | regnum - AARCH64_SVE_V0_REGNUM, | |
2383 | V_REGISTER_SIZE, result_value); | |
2384 | ||
07b287a0 MS |
2385 | gdb_assert_not_reached ("regnum out of bound"); |
2386 | } | |
2387 | ||
3c5cd5c3 | 2388 | /* Helper for aarch64_pseudo_write. */ |
07b287a0 MS |
2389 | |
2390 | static void | |
63bad7b6 AH |
2391 | aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache, |
2392 | int regnum_offset, int regsize, const gdb_byte *buf) | |
07b287a0 | 2393 | { |
3c5cd5c3 | 2394 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
07b287a0 | 2395 | |
63bad7b6 AH |
2396 | /* Enough space for a full vector register. */ |
2397 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2398 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2399 | ||
07b287a0 MS |
2400 | /* Ensure the register buffer is zero, we want gdb writes of the |
2401 | various 'scalar' pseudo registers to behavior like architectural | |
2402 | writes, register width bytes are written the remainder are set to | |
2403 | zero. */ | |
63bad7b6 | 2404 | memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM)); |
07b287a0 | 2405 | |
3c5cd5c3 AH |
2406 | memcpy (reg_buf, buf, regsize); |
2407 | regcache->raw_write (v_regnum, reg_buf); | |
2408 | } | |
2409 | ||
2410 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2411 | ||
2412 | static void | |
2413 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2414 | int regnum, const gdb_byte *buf) | |
2415 | { | |
63bad7b6 | 2416 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
07b287a0 MS |
2417 | regnum -= gdbarch_num_regs (gdbarch); |
2418 | ||
2419 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2420 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2421 | regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE, | |
2422 | buf); | |
07b287a0 MS |
2423 | |
2424 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2425 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2426 | regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE, | |
2427 | buf); | |
07b287a0 MS |
2428 | |
2429 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2430 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2431 | regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE, | |
2432 | buf); | |
07b287a0 MS |
2433 | |
2434 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2435 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2436 | regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE, | |
2437 | buf); | |
07b287a0 MS |
2438 | |
2439 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2440 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2441 | regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE, | |
2442 | buf); | |
2443 | ||
2444 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM | |
2445 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2446 | return aarch64_pseudo_write_1 (gdbarch, regcache, | |
2447 | regnum - AARCH64_SVE_V0_REGNUM, | |
2448 | V_REGISTER_SIZE, buf); | |
07b287a0 MS |
2449 | |
2450 | gdb_assert_not_reached ("regnum out of bound"); | |
2451 | } | |
2452 | ||
07b287a0 MS |
2453 | /* Callback function for user_reg_add. */ |
2454 | ||
2455 | static struct value * | |
2456 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2457 | { | |
9a3c8263 | 2458 | const int *reg_p = (const int *) baton; |
07b287a0 MS |
2459 | |
2460 | return value_of_register (*reg_p, frame); | |
2461 | } | |
2462 | \f | |
2463 | ||
9404b58f KM |
2464 | /* Implement the "software_single_step" gdbarch method, needed to |
2465 | single step through atomic sequences on AArch64. */ | |
2466 | ||
a0ff9e1a | 2467 | static std::vector<CORE_ADDR> |
f5ea389a | 2468 | aarch64_software_single_step (struct regcache *regcache) |
9404b58f | 2469 | { |
ac7936df | 2470 | struct gdbarch *gdbarch = regcache->arch (); |
9404b58f KM |
2471 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2472 | const int insn_size = 4; | |
2473 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
0187a92f | 2474 | CORE_ADDR pc = regcache_read_pc (regcache); |
9404b58f KM |
2475 | CORE_ADDR breaks[2] = { -1, -1 }; |
2476 | CORE_ADDR loc = pc; | |
2477 | CORE_ADDR closing_insn = 0; | |
2478 | uint32_t insn = read_memory_unsigned_integer (loc, insn_size, | |
2479 | byte_order_for_code); | |
2480 | int index; | |
2481 | int insn_count; | |
2482 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2483 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
f77ee802 YQ |
2484 | aarch64_inst inst; |
2485 | ||
561a72d4 | 2486 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 2487 | return {}; |
9404b58f KM |
2488 | |
2489 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
f77ee802 | 2490 | if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) |
a0ff9e1a | 2491 | return {}; |
9404b58f KM |
2492 | |
2493 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2494 | { | |
9404b58f KM |
2495 | loc += insn_size; |
2496 | insn = read_memory_unsigned_integer (loc, insn_size, | |
2497 | byte_order_for_code); | |
2498 | ||
561a72d4 | 2499 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 2500 | return {}; |
9404b58f | 2501 | /* Check if the instruction is a conditional branch. */ |
f77ee802 | 2502 | if (inst.opcode->iclass == condbranch) |
9404b58f | 2503 | { |
f77ee802 YQ |
2504 | gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); |
2505 | ||
9404b58f | 2506 | if (bc_insn_count >= 1) |
a0ff9e1a | 2507 | return {}; |
9404b58f KM |
2508 | |
2509 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
f77ee802 | 2510 | breaks[1] = loc + inst.operands[0].imm.value; |
9404b58f KM |
2511 | |
2512 | bc_insn_count++; | |
2513 | last_breakpoint++; | |
2514 | } | |
2515 | ||
2516 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
f77ee802 | 2517 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) |
9404b58f KM |
2518 | { |
2519 | closing_insn = loc; | |
2520 | break; | |
2521 | } | |
2522 | } | |
2523 | ||
2524 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
2525 | if (!closing_insn) | |
a0ff9e1a | 2526 | return {}; |
9404b58f KM |
2527 | |
2528 | /* Insert breakpoint after the end of the atomic sequence. */ | |
2529 | breaks[0] = loc + insn_size; | |
2530 | ||
2531 | /* Check for duplicated breakpoints, and also check that the second | |
2532 | breakpoint is not within the atomic sequence. */ | |
2533 | if (last_breakpoint | |
2534 | && (breaks[1] == breaks[0] | |
2535 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
2536 | last_breakpoint = 0; | |
2537 | ||
a0ff9e1a SM |
2538 | std::vector<CORE_ADDR> next_pcs; |
2539 | ||
9404b58f KM |
2540 | /* Insert the breakpoint at the end of the sequence, and one at the |
2541 | destination of the conditional branch, if it exists. */ | |
2542 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 2543 | next_pcs.push_back (breaks[index]); |
9404b58f | 2544 | |
93f9a11f | 2545 | return next_pcs; |
9404b58f KM |
2546 | } |
2547 | ||
cfba9872 | 2548 | struct aarch64_displaced_step_closure : public displaced_step_closure |
b6542f81 YQ |
2549 | { |
2550 | /* It is true when condition instruction, such as B.CON, TBZ, etc, | |
2551 | is being displaced stepping. */ | |
cfba9872 | 2552 | int cond = 0; |
b6542f81 YQ |
2553 | |
2554 | /* PC adjustment offset after displaced stepping. */ | |
cfba9872 | 2555 | int32_t pc_adjust = 0; |
b6542f81 YQ |
2556 | }; |
2557 | ||
2558 | /* Data when visiting instructions for displaced stepping. */ | |
2559 | ||
2560 | struct aarch64_displaced_step_data | |
2561 | { | |
2562 | struct aarch64_insn_data base; | |
2563 | ||
2564 | /* The address where the instruction will be executed at. */ | |
2565 | CORE_ADDR new_addr; | |
2566 | /* Buffer of instructions to be copied to NEW_ADDR to execute. */ | |
2567 | uint32_t insn_buf[DISPLACED_MODIFIED_INSNS]; | |
2568 | /* Number of instructions in INSN_BUF. */ | |
2569 | unsigned insn_count; | |
2570 | /* Registers when doing displaced stepping. */ | |
2571 | struct regcache *regs; | |
2572 | ||
cfba9872 | 2573 | aarch64_displaced_step_closure *dsc; |
b6542f81 YQ |
2574 | }; |
2575 | ||
2576 | /* Implementation of aarch64_insn_visitor method "b". */ | |
2577 | ||
2578 | static void | |
2579 | aarch64_displaced_step_b (const int is_bl, const int32_t offset, | |
2580 | struct aarch64_insn_data *data) | |
2581 | { | |
2582 | struct aarch64_displaced_step_data *dsd | |
2583 | = (struct aarch64_displaced_step_data *) data; | |
2ac09a5b | 2584 | int64_t new_offset = data->insn_addr - dsd->new_addr + offset; |
b6542f81 YQ |
2585 | |
2586 | if (can_encode_int32 (new_offset, 28)) | |
2587 | { | |
2588 | /* Emit B rather than BL, because executing BL on a new address | |
2589 | will get the wrong address into LR. In order to avoid this, | |
2590 | we emit B, and update LR if the instruction is BL. */ | |
2591 | emit_b (dsd->insn_buf, 0, new_offset); | |
2592 | dsd->insn_count++; | |
2593 | } | |
2594 | else | |
2595 | { | |
2596 | /* Write NOP. */ | |
2597 | emit_nop (dsd->insn_buf); | |
2598 | dsd->insn_count++; | |
2599 | dsd->dsc->pc_adjust = offset; | |
2600 | } | |
2601 | ||
2602 | if (is_bl) | |
2603 | { | |
2604 | /* Update LR. */ | |
2605 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
2606 | data->insn_addr + 4); | |
2607 | } | |
2608 | } | |
2609 | ||
2610 | /* Implementation of aarch64_insn_visitor method "b_cond". */ | |
2611 | ||
2612 | static void | |
2613 | aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset, | |
2614 | struct aarch64_insn_data *data) | |
2615 | { | |
2616 | struct aarch64_displaced_step_data *dsd | |
2617 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2618 | |
2619 | /* GDB has to fix up PC after displaced step this instruction | |
2620 | differently according to the condition is true or false. Instead | |
2621 | of checking COND against conditional flags, we can use | |
2622 | the following instructions, and GDB can tell how to fix up PC | |
2623 | according to the PC value. | |
2624 | ||
2625 | B.COND TAKEN ; If cond is true, then jump to TAKEN. | |
2626 | INSN1 ; | |
2627 | TAKEN: | |
2628 | INSN2 | |
2629 | */ | |
2630 | ||
2631 | emit_bcond (dsd->insn_buf, cond, 8); | |
2632 | dsd->dsc->cond = 1; | |
2633 | dsd->dsc->pc_adjust = offset; | |
2634 | dsd->insn_count = 1; | |
2635 | } | |
2636 | ||
2637 | /* Dynamically allocate a new register. If we know the register | |
2638 | statically, we should make it a global as above instead of using this | |
2639 | helper function. */ | |
2640 | ||
2641 | static struct aarch64_register | |
2642 | aarch64_register (unsigned num, int is64) | |
2643 | { | |
2644 | return (struct aarch64_register) { num, is64 }; | |
2645 | } | |
2646 | ||
2647 | /* Implementation of aarch64_insn_visitor method "cb". */ | |
2648 | ||
2649 | static void | |
2650 | aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz, | |
2651 | const unsigned rn, int is64, | |
2652 | struct aarch64_insn_data *data) | |
2653 | { | |
2654 | struct aarch64_displaced_step_data *dsd | |
2655 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2656 | |
2657 | /* The offset is out of range for a compare and branch | |
2658 | instruction. We can use the following instructions instead: | |
2659 | ||
2660 | CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. | |
2661 | INSN1 ; | |
2662 | TAKEN: | |
2663 | INSN2 | |
2664 | */ | |
2665 | emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8); | |
2666 | dsd->insn_count = 1; | |
2667 | dsd->dsc->cond = 1; | |
2668 | dsd->dsc->pc_adjust = offset; | |
2669 | } | |
2670 | ||
2671 | /* Implementation of aarch64_insn_visitor method "tb". */ | |
2672 | ||
2673 | static void | |
2674 | aarch64_displaced_step_tb (const int32_t offset, int is_tbnz, | |
2675 | const unsigned rt, unsigned bit, | |
2676 | struct aarch64_insn_data *data) | |
2677 | { | |
2678 | struct aarch64_displaced_step_data *dsd | |
2679 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2680 | |
2681 | /* The offset is out of range for a test bit and branch | |
2682 | instruction We can use the following instructions instead: | |
2683 | ||
2684 | TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. | |
2685 | INSN1 ; | |
2686 | TAKEN: | |
2687 | INSN2 | |
2688 | ||
2689 | */ | |
2690 | emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8); | |
2691 | dsd->insn_count = 1; | |
2692 | dsd->dsc->cond = 1; | |
2693 | dsd->dsc->pc_adjust = offset; | |
2694 | } | |
2695 | ||
2696 | /* Implementation of aarch64_insn_visitor method "adr". */ | |
2697 | ||
2698 | static void | |
2699 | aarch64_displaced_step_adr (const int32_t offset, const unsigned rd, | |
2700 | const int is_adrp, struct aarch64_insn_data *data) | |
2701 | { | |
2702 | struct aarch64_displaced_step_data *dsd | |
2703 | = (struct aarch64_displaced_step_data *) data; | |
2704 | /* We know exactly the address the ADR{P,} instruction will compute. | |
2705 | We can just write it to the destination register. */ | |
2706 | CORE_ADDR address = data->insn_addr + offset; | |
2707 | ||
2708 | if (is_adrp) | |
2709 | { | |
2710 | /* Clear the lower 12 bits of the offset to get the 4K page. */ | |
2711 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2712 | address & ~0xfff); | |
2713 | } | |
2714 | else | |
2715 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2716 | address); | |
2717 | ||
2718 | dsd->dsc->pc_adjust = 4; | |
2719 | emit_nop (dsd->insn_buf); | |
2720 | dsd->insn_count = 1; | |
2721 | } | |
2722 | ||
2723 | /* Implementation of aarch64_insn_visitor method "ldr_literal". */ | |
2724 | ||
2725 | static void | |
2726 | aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw, | |
2727 | const unsigned rt, const int is64, | |
2728 | struct aarch64_insn_data *data) | |
2729 | { | |
2730 | struct aarch64_displaced_step_data *dsd | |
2731 | = (struct aarch64_displaced_step_data *) data; | |
2732 | CORE_ADDR address = data->insn_addr + offset; | |
2733 | struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 }; | |
2734 | ||
2735 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt, | |
2736 | address); | |
2737 | ||
2738 | if (is_sw) | |
2739 | dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1), | |
2740 | aarch64_register (rt, 1), zero); | |
2741 | else | |
2742 | dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64), | |
2743 | aarch64_register (rt, 1), zero); | |
2744 | ||
2745 | dsd->dsc->pc_adjust = 4; | |
2746 | } | |
2747 | ||
2748 | /* Implementation of aarch64_insn_visitor method "others". */ | |
2749 | ||
2750 | static void | |
2751 | aarch64_displaced_step_others (const uint32_t insn, | |
2752 | struct aarch64_insn_data *data) | |
2753 | { | |
2754 | struct aarch64_displaced_step_data *dsd | |
2755 | = (struct aarch64_displaced_step_data *) data; | |
2756 | ||
e1c587c3 | 2757 | aarch64_emit_insn (dsd->insn_buf, insn); |
b6542f81 YQ |
2758 | dsd->insn_count = 1; |
2759 | ||
2760 | if ((insn & 0xfffffc1f) == 0xd65f0000) | |
2761 | { | |
2762 | /* RET */ | |
2763 | dsd->dsc->pc_adjust = 0; | |
2764 | } | |
2765 | else | |
2766 | dsd->dsc->pc_adjust = 4; | |
2767 | } | |
2768 | ||
2769 | static const struct aarch64_insn_visitor visitor = | |
2770 | { | |
2771 | aarch64_displaced_step_b, | |
2772 | aarch64_displaced_step_b_cond, | |
2773 | aarch64_displaced_step_cb, | |
2774 | aarch64_displaced_step_tb, | |
2775 | aarch64_displaced_step_adr, | |
2776 | aarch64_displaced_step_ldr_literal, | |
2777 | aarch64_displaced_step_others, | |
2778 | }; | |
2779 | ||
2780 | /* Implement the "displaced_step_copy_insn" gdbarch method. */ | |
2781 | ||
2782 | struct displaced_step_closure * | |
2783 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
2784 | CORE_ADDR from, CORE_ADDR to, | |
2785 | struct regcache *regs) | |
2786 | { | |
b6542f81 YQ |
2787 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2788 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); | |
2789 | struct aarch64_displaced_step_data dsd; | |
c86a40c6 YQ |
2790 | aarch64_inst inst; |
2791 | ||
561a72d4 | 2792 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
c86a40c6 | 2793 | return NULL; |
b6542f81 YQ |
2794 | |
2795 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
c86a40c6 | 2796 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) |
b6542f81 YQ |
2797 | { |
2798 | /* We can't displaced step atomic sequences. */ | |
2799 | return NULL; | |
2800 | } | |
2801 | ||
cfba9872 SM |
2802 | std::unique_ptr<aarch64_displaced_step_closure> dsc |
2803 | (new aarch64_displaced_step_closure); | |
b6542f81 YQ |
2804 | dsd.base.insn_addr = from; |
2805 | dsd.new_addr = to; | |
2806 | dsd.regs = regs; | |
cfba9872 | 2807 | dsd.dsc = dsc.get (); |
034f1a81 | 2808 | dsd.insn_count = 0; |
b6542f81 YQ |
2809 | aarch64_relocate_instruction (insn, &visitor, |
2810 | (struct aarch64_insn_data *) &dsd); | |
2811 | gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS); | |
2812 | ||
2813 | if (dsd.insn_count != 0) | |
2814 | { | |
2815 | int i; | |
2816 | ||
2817 | /* Instruction can be relocated to scratch pad. Copy | |
2818 | relocated instruction(s) there. */ | |
2819 | for (i = 0; i < dsd.insn_count; i++) | |
2820 | { | |
2821 | if (debug_displaced) | |
2822 | { | |
2823 | debug_printf ("displaced: writing insn "); | |
2824 | debug_printf ("%.8x", dsd.insn_buf[i]); | |
2825 | debug_printf (" at %s\n", paddress (gdbarch, to + i * 4)); | |
2826 | } | |
2827 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, | |
2828 | (ULONGEST) dsd.insn_buf[i]); | |
2829 | } | |
2830 | } | |
2831 | else | |
2832 | { | |
b6542f81 YQ |
2833 | dsc = NULL; |
2834 | } | |
2835 | ||
cfba9872 | 2836 | return dsc.release (); |
b6542f81 YQ |
2837 | } |
2838 | ||
2839 | /* Implement the "displaced_step_fixup" gdbarch method. */ | |
2840 | ||
2841 | void | |
2842 | aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
cfba9872 | 2843 | struct displaced_step_closure *dsc_, |
b6542f81 YQ |
2844 | CORE_ADDR from, CORE_ADDR to, |
2845 | struct regcache *regs) | |
2846 | { | |
cfba9872 SM |
2847 | aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_; |
2848 | ||
b6542f81 YQ |
2849 | if (dsc->cond) |
2850 | { | |
2851 | ULONGEST pc; | |
2852 | ||
2853 | regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc); | |
2854 | if (pc - to == 8) | |
2855 | { | |
2856 | /* Condition is true. */ | |
2857 | } | |
2858 | else if (pc - to == 4) | |
2859 | { | |
2860 | /* Condition is false. */ | |
2861 | dsc->pc_adjust = 4; | |
2862 | } | |
2863 | else | |
2864 | gdb_assert_not_reached ("Unexpected PC value after displaced stepping"); | |
2865 | } | |
2866 | ||
2867 | if (dsc->pc_adjust != 0) | |
2868 | { | |
2869 | if (debug_displaced) | |
2870 | { | |
2871 | debug_printf ("displaced: fixup: set PC to %s:%d\n", | |
2872 | paddress (gdbarch, from), dsc->pc_adjust); | |
2873 | } | |
2874 | regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM, | |
2875 | from + dsc->pc_adjust); | |
2876 | } | |
2877 | } | |
2878 | ||
2879 | /* Implement the "displaced_step_hw_singlestep" gdbarch method. */ | |
2880 | ||
2881 | int | |
2882 | aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
2883 | struct displaced_step_closure *closure) | |
2884 | { | |
2885 | return 1; | |
2886 | } | |
2887 | ||
95228a0d AH |
2888 | /* Get the correct target description for the given VQ value. |
2889 | If VQ is zero then it is assumed SVE is not supported. | |
2890 | (It is not possible to set VQ to zero on an SVE system). */ | |
da434ccb AH |
2891 | |
2892 | const target_desc * | |
39bfb937 | 2893 | aarch64_read_description (uint64_t vq) |
da434ccb | 2894 | { |
95228a0d | 2895 | if (vq > AARCH64_MAX_SVE_VQ) |
39bfb937 | 2896 | error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq, |
95228a0d AH |
2897 | AARCH64_MAX_SVE_VQ); |
2898 | ||
2899 | struct target_desc *tdesc = tdesc_aarch64_list[vq]; | |
da434ccb | 2900 | |
95228a0d AH |
2901 | if (tdesc == NULL) |
2902 | { | |
2903 | tdesc = aarch64_create_target_description (vq); | |
2904 | tdesc_aarch64_list[vq] = tdesc; | |
2905 | } | |
da434ccb | 2906 | |
95228a0d | 2907 | return tdesc; |
da434ccb AH |
2908 | } |
2909 | ||
ba2d2bb2 AH |
2910 | /* Return the VQ used when creating the target description TDESC. */ |
2911 | ||
1332a140 | 2912 | static uint64_t |
ba2d2bb2 AH |
2913 | aarch64_get_tdesc_vq (const struct target_desc *tdesc) |
2914 | { | |
2915 | const struct tdesc_feature *feature_sve; | |
2916 | ||
2917 | if (!tdesc_has_registers (tdesc)) | |
2918 | return 0; | |
2919 | ||
2920 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
2921 | ||
2922 | if (feature_sve == nullptr) | |
2923 | return 0; | |
2924 | ||
1332a140 AH |
2925 | uint64_t vl = tdesc_register_size (feature_sve, |
2926 | aarch64_sve_register_names[0]); | |
ba2d2bb2 AH |
2927 | return sve_vq_from_vl (vl); |
2928 | } | |
2929 | ||
2930 | ||
07b287a0 MS |
2931 | /* Initialize the current architecture based on INFO. If possible, |
2932 | re-use an architecture from ARCHES, which is a list of | |
2933 | architectures already created during this debugging session. | |
2934 | ||
2935 | Called e.g. at program startup, when reading a core file, and when | |
2936 | reading a binary file. */ | |
2937 | ||
2938 | static struct gdbarch * | |
2939 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2940 | { | |
2941 | struct gdbarch_tdep *tdep; | |
2942 | struct gdbarch *gdbarch; | |
2943 | struct gdbarch_list *best_arch; | |
2944 | struct tdesc_arch_data *tdesc_data = NULL; | |
2945 | const struct target_desc *tdesc = info.target_desc; | |
2946 | int i; | |
07b287a0 | 2947 | int valid_p = 1; |
ba2d2bb2 AH |
2948 | const struct tdesc_feature *feature_core; |
2949 | const struct tdesc_feature *feature_fpu; | |
2950 | const struct tdesc_feature *feature_sve; | |
07b287a0 MS |
2951 | int num_regs = 0; |
2952 | int num_pseudo_regs = 0; | |
2953 | ||
ba2d2bb2 | 2954 | /* Ensure we always have a target description. */ |
07b287a0 | 2955 | if (!tdesc_has_registers (tdesc)) |
ba2d2bb2 | 2956 | tdesc = aarch64_read_description (0); |
07b287a0 MS |
2957 | gdb_assert (tdesc); |
2958 | ||
ba2d2bb2 AH |
2959 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core"); |
2960 | feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); | |
2961 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
07b287a0 | 2962 | |
ba2d2bb2 | 2963 | if (feature_core == NULL) |
07b287a0 MS |
2964 | return NULL; |
2965 | ||
2966 | tdesc_data = tdesc_data_alloc (); | |
2967 | ||
ba2d2bb2 | 2968 | /* Validate the description provides the mandatory core R registers |
07b287a0 MS |
2969 | and allocate their numbers. */ |
2970 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
ba2d2bb2 AH |
2971 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, |
2972 | AARCH64_X0_REGNUM + i, | |
2973 | aarch64_r_register_names[i]); | |
07b287a0 MS |
2974 | |
2975 | num_regs = AARCH64_X0_REGNUM + i; | |
2976 | ||
ba2d2bb2 AH |
2977 | /* Add the V registers. */ |
2978 | if (feature_fpu != NULL) | |
07b287a0 | 2979 | { |
ba2d2bb2 AH |
2980 | if (feature_sve != NULL) |
2981 | error (_("Program contains both fpu and SVE features.")); | |
2982 | ||
2983 | /* Validate the description provides the mandatory V registers | |
2984 | and allocate their numbers. */ | |
07b287a0 | 2985 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) |
ba2d2bb2 AH |
2986 | valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data, |
2987 | AARCH64_V0_REGNUM + i, | |
2988 | aarch64_v_register_names[i]); | |
07b287a0 MS |
2989 | |
2990 | num_regs = AARCH64_V0_REGNUM + i; | |
ba2d2bb2 | 2991 | } |
07b287a0 | 2992 | |
ba2d2bb2 AH |
2993 | /* Add the SVE registers. */ |
2994 | if (feature_sve != NULL) | |
2995 | { | |
2996 | /* Validate the description provides the mandatory SVE registers | |
2997 | and allocate their numbers. */ | |
2998 | for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++) | |
2999 | valid_p &= tdesc_numbered_register (feature_sve, tdesc_data, | |
3000 | AARCH64_SVE_Z0_REGNUM + i, | |
3001 | aarch64_sve_register_names[i]); | |
3002 | ||
3003 | num_regs = AARCH64_SVE_Z0_REGNUM + i; | |
3004 | num_pseudo_regs += 32; /* add the Vn register pseudos. */ | |
3005 | } | |
3006 | ||
3007 | if (feature_fpu != NULL || feature_sve != NULL) | |
3008 | { | |
07b287a0 MS |
3009 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ |
3010 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
3011 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
3012 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
3013 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
3014 | } | |
3015 | ||
3016 | if (!valid_p) | |
3017 | { | |
3018 | tdesc_data_cleanup (tdesc_data); | |
3019 | return NULL; | |
3020 | } | |
3021 | ||
3022 | /* AArch64 code is always little-endian. */ | |
3023 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
3024 | ||
3025 | /* If there is already a candidate, use it. */ | |
3026 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3027 | best_arch != NULL; | |
3028 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3029 | { | |
3030 | /* Found a match. */ | |
3031 | break; | |
3032 | } | |
3033 | ||
3034 | if (best_arch != NULL) | |
3035 | { | |
3036 | if (tdesc_data != NULL) | |
3037 | tdesc_data_cleanup (tdesc_data); | |
3038 | return best_arch->gdbarch; | |
3039 | } | |
3040 | ||
8d749320 | 3041 | tdep = XCNEW (struct gdbarch_tdep); |
07b287a0 MS |
3042 | gdbarch = gdbarch_alloc (&info, tdep); |
3043 | ||
3044 | /* This should be low enough for everything. */ | |
3045 | tdep->lowest_pc = 0x20; | |
3046 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
3047 | tdep->jb_elt_size = 8; | |
ba2d2bb2 | 3048 | tdep->vq = aarch64_get_tdesc_vq (tdesc); |
07b287a0 MS |
3049 | |
3050 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); | |
3051 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
3052 | ||
07b287a0 MS |
3053 | /* Frame handling. */ |
3054 | set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id); | |
3055 | set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc); | |
3056 | set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp); | |
3057 | ||
3058 | /* Advance PC across function entry code. */ | |
3059 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
3060 | ||
3061 | /* The stack grows downward. */ | |
3062 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3063 | ||
3064 | /* Breakpoint manipulation. */ | |
04180708 YQ |
3065 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3066 | aarch64_breakpoint::kind_from_pc); | |
3067 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3068 | aarch64_breakpoint::bp_from_kind); | |
07b287a0 | 3069 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 3070 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
3071 | |
3072 | /* Information about registers, etc. */ | |
3073 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
3074 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
3075 | set_gdbarch_num_regs (gdbarch, num_regs); | |
3076 | ||
3077 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
3078 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
3079 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
3080 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
3081 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
3082 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
3083 | aarch64_pseudo_register_reggroup_p); | |
3084 | ||
3085 | /* ABI */ | |
3086 | set_gdbarch_short_bit (gdbarch, 16); | |
3087 | set_gdbarch_int_bit (gdbarch, 32); | |
3088 | set_gdbarch_float_bit (gdbarch, 32); | |
3089 | set_gdbarch_double_bit (gdbarch, 64); | |
3090 | set_gdbarch_long_double_bit (gdbarch, 128); | |
3091 | set_gdbarch_long_bit (gdbarch, 64); | |
3092 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3093 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3094 | set_gdbarch_char_signed (gdbarch, 0); | |
53375380 | 3095 | set_gdbarch_wchar_signed (gdbarch, 0); |
07b287a0 MS |
3096 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
3097 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
3098 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
3099 | ||
3100 | /* Internal <-> external register number maps. */ | |
3101 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
3102 | ||
3103 | /* Returning results. */ | |
3104 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
3105 | ||
3106 | /* Disassembly. */ | |
3107 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
3108 | ||
3109 | /* Virtual tables. */ | |
3110 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3111 | ||
3112 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
3113 | info.target_desc = tdesc; | |
0dba2a6c | 3114 | info.tdesc_data = tdesc_data; |
07b287a0 MS |
3115 | gdbarch_init_osabi (info, gdbarch); |
3116 | ||
3117 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
3118 | ||
3119 | /* Add some default predicates. */ | |
3120 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
3121 | dwarf2_append_unwinders (gdbarch); | |
3122 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
3123 | ||
3124 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
3125 | ||
3126 | /* Now we have tuned the configuration, set a few final things, | |
3127 | based on what the OS ABI has told us. */ | |
3128 | ||
3129 | if (tdep->jb_pc >= 0) | |
3130 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
3131 | ||
ea873d8e PL |
3132 | set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address); |
3133 | ||
07b287a0 MS |
3134 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
3135 | ||
3136 | /* Add standard register aliases. */ | |
3137 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
3138 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
3139 | value_of_aarch64_user_reg, | |
3140 | &aarch64_register_aliases[i].regnum); | |
3141 | ||
3142 | return gdbarch; | |
3143 | } | |
3144 | ||
3145 | static void | |
3146 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3147 | { | |
3148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3149 | ||
3150 | if (tdep == NULL) | |
3151 | return; | |
3152 | ||
3153 | fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), | |
3154 | paddress (gdbarch, tdep->lowest_pc)); | |
3155 | } | |
3156 | ||
0d4c07af | 3157 | #if GDB_SELF_TEST |
1e2b521d YQ |
3158 | namespace selftests |
3159 | { | |
3160 | static void aarch64_process_record_test (void); | |
3161 | } | |
0d4c07af | 3162 | #endif |
1e2b521d | 3163 | |
07b287a0 MS |
3164 | void |
3165 | _initialize_aarch64_tdep (void) | |
3166 | { | |
3167 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
3168 | aarch64_dump_tdep); | |
3169 | ||
07b287a0 MS |
3170 | /* Debug this file's internals. */ |
3171 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
3172 | Set AArch64 debugging."), _("\ | |
3173 | Show AArch64 debugging."), _("\ | |
3174 | When on, AArch64 specific debugging is enabled."), | |
3175 | NULL, | |
3176 | show_aarch64_debug, | |
3177 | &setdebuglist, &showdebuglist); | |
4d9a9006 YQ |
3178 | |
3179 | #if GDB_SELF_TEST | |
1526853e SM |
3180 | selftests::register_test ("aarch64-analyze-prologue", |
3181 | selftests::aarch64_analyze_prologue_test); | |
3182 | selftests::register_test ("aarch64-process-record", | |
3183 | selftests::aarch64_process_record_test); | |
6654d750 | 3184 | selftests::record_xml_tdesc ("aarch64.xml", |
95228a0d | 3185 | aarch64_create_target_description (0)); |
4d9a9006 | 3186 | #endif |
07b287a0 | 3187 | } |
99afc88b OJ |
3188 | |
3189 | /* AArch64 process record-replay related structures, defines etc. */ | |
3190 | ||
99afc88b OJ |
3191 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ |
3192 | do \ | |
3193 | { \ | |
3194 | unsigned int reg_len = LENGTH; \ | |
3195 | if (reg_len) \ | |
3196 | { \ | |
3197 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
3198 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
3199 | } \ | |
3200 | } \ | |
3201 | while (0) | |
3202 | ||
3203 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
3204 | do \ | |
3205 | { \ | |
3206 | unsigned int mem_len = LENGTH; \ | |
3207 | if (mem_len) \ | |
3208 | { \ | |
3209 | MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \ | |
3210 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
3211 | sizeof(struct aarch64_mem_r) * LENGTH); \ | |
3212 | } \ | |
3213 | } \ | |
3214 | while (0) | |
3215 | ||
3216 | /* AArch64 record/replay structures and enumerations. */ | |
3217 | ||
3218 | struct aarch64_mem_r | |
3219 | { | |
3220 | uint64_t len; /* Record length. */ | |
3221 | uint64_t addr; /* Memory address. */ | |
3222 | }; | |
3223 | ||
3224 | enum aarch64_record_result | |
3225 | { | |
3226 | AARCH64_RECORD_SUCCESS, | |
99afc88b OJ |
3227 | AARCH64_RECORD_UNSUPPORTED, |
3228 | AARCH64_RECORD_UNKNOWN | |
3229 | }; | |
3230 | ||
3231 | typedef struct insn_decode_record_t | |
3232 | { | |
3233 | struct gdbarch *gdbarch; | |
3234 | struct regcache *regcache; | |
3235 | CORE_ADDR this_addr; /* Address of insn to be recorded. */ | |
3236 | uint32_t aarch64_insn; /* Insn to be recorded. */ | |
3237 | uint32_t mem_rec_count; /* Count of memory records. */ | |
3238 | uint32_t reg_rec_count; /* Count of register records. */ | |
3239 | uint32_t *aarch64_regs; /* Registers to be recorded. */ | |
3240 | struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */ | |
3241 | } insn_decode_record; | |
3242 | ||
3243 | /* Record handler for data processing - register instructions. */ | |
3244 | ||
3245 | static unsigned int | |
3246 | aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r) | |
3247 | { | |
3248 | uint8_t reg_rd, insn_bits24_27, insn_bits21_23; | |
3249 | uint32_t record_buf[4]; | |
3250 | ||
3251 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3252 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3253 | insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23); | |
3254 | ||
3255 | if (!bit (aarch64_insn_r->aarch64_insn, 28)) | |
3256 | { | |
3257 | uint8_t setflags; | |
3258 | ||
3259 | /* Logical (shifted register). */ | |
3260 | if (insn_bits24_27 == 0x0a) | |
3261 | setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03); | |
3262 | /* Add/subtract. */ | |
3263 | else if (insn_bits24_27 == 0x0b) | |
3264 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3265 | else | |
3266 | return AARCH64_RECORD_UNKNOWN; | |
3267 | ||
3268 | record_buf[0] = reg_rd; | |
3269 | aarch64_insn_r->reg_rec_count = 1; | |
3270 | if (setflags) | |
3271 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3272 | } | |
3273 | else | |
3274 | { | |
3275 | if (insn_bits24_27 == 0x0b) | |
3276 | { | |
3277 | /* Data-processing (3 source). */ | |
3278 | record_buf[0] = reg_rd; | |
3279 | aarch64_insn_r->reg_rec_count = 1; | |
3280 | } | |
3281 | else if (insn_bits24_27 == 0x0a) | |
3282 | { | |
3283 | if (insn_bits21_23 == 0x00) | |
3284 | { | |
3285 | /* Add/subtract (with carry). */ | |
3286 | record_buf[0] = reg_rd; | |
3287 | aarch64_insn_r->reg_rec_count = 1; | |
3288 | if (bit (aarch64_insn_r->aarch64_insn, 29)) | |
3289 | { | |
3290 | record_buf[1] = AARCH64_CPSR_REGNUM; | |
3291 | aarch64_insn_r->reg_rec_count = 2; | |
3292 | } | |
3293 | } | |
3294 | else if (insn_bits21_23 == 0x02) | |
3295 | { | |
3296 | /* Conditional compare (register) and conditional compare | |
3297 | (immediate) instructions. */ | |
3298 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3299 | aarch64_insn_r->reg_rec_count = 1; | |
3300 | } | |
3301 | else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06) | |
3302 | { | |
3303 | /* CConditional select. */ | |
3304 | /* Data-processing (2 source). */ | |
3305 | /* Data-processing (1 source). */ | |
3306 | record_buf[0] = reg_rd; | |
3307 | aarch64_insn_r->reg_rec_count = 1; | |
3308 | } | |
3309 | else | |
3310 | return AARCH64_RECORD_UNKNOWN; | |
3311 | } | |
3312 | } | |
3313 | ||
3314 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3315 | record_buf); | |
3316 | return AARCH64_RECORD_SUCCESS; | |
3317 | } | |
3318 | ||
3319 | /* Record handler for data processing - immediate instructions. */ | |
3320 | ||
3321 | static unsigned int | |
3322 | aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) | |
3323 | { | |
78cc6c2d | 3324 | uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; |
99afc88b OJ |
3325 | uint32_t record_buf[4]; |
3326 | ||
3327 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
99afc88b OJ |
3328 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); |
3329 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3330 | ||
3331 | if (insn_bits24_27 == 0x00 /* PC rel addressing. */ | |
3332 | || insn_bits24_27 == 0x03 /* Bitfield and Extract. */ | |
3333 | || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */ | |
3334 | { | |
3335 | record_buf[0] = reg_rd; | |
3336 | aarch64_insn_r->reg_rec_count = 1; | |
3337 | } | |
3338 | else if (insn_bits24_27 == 0x01) | |
3339 | { | |
3340 | /* Add/Subtract (immediate). */ | |
3341 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3342 | record_buf[0] = reg_rd; | |
3343 | aarch64_insn_r->reg_rec_count = 1; | |
3344 | if (setflags) | |
3345 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3346 | } | |
3347 | else if (insn_bits24_27 == 0x02 && !insn_bit23) | |
3348 | { | |
3349 | /* Logical (immediate). */ | |
3350 | setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03; | |
3351 | record_buf[0] = reg_rd; | |
3352 | aarch64_insn_r->reg_rec_count = 1; | |
3353 | if (setflags) | |
3354 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3355 | } | |
3356 | else | |
3357 | return AARCH64_RECORD_UNKNOWN; | |
3358 | ||
3359 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3360 | record_buf); | |
3361 | return AARCH64_RECORD_SUCCESS; | |
3362 | } | |
3363 | ||
3364 | /* Record handler for branch, exception generation and system instructions. */ | |
3365 | ||
3366 | static unsigned int | |
3367 | aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) | |
3368 | { | |
3369 | struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch); | |
3370 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23; | |
3371 | uint32_t record_buf[4]; | |
3372 | ||
3373 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3374 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3375 | insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3376 | ||
3377 | if (insn_bits28_31 == 0x0d) | |
3378 | { | |
3379 | /* Exception generation instructions. */ | |
3380 | if (insn_bits24_27 == 0x04) | |
3381 | { | |
5d98d3cd YQ |
3382 | if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) |
3383 | && !bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3384 | && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01) | |
99afc88b OJ |
3385 | { |
3386 | ULONGEST svc_number; | |
3387 | ||
3388 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8, | |
3389 | &svc_number); | |
3390 | return tdep->aarch64_syscall_record (aarch64_insn_r->regcache, | |
3391 | svc_number); | |
3392 | } | |
3393 | else | |
3394 | return AARCH64_RECORD_UNSUPPORTED; | |
3395 | } | |
3396 | /* System instructions. */ | |
3397 | else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00) | |
3398 | { | |
3399 | uint32_t reg_rt, reg_crn; | |
3400 | ||
3401 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3402 | reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3403 | ||
3404 | /* Record rt in case of sysl and mrs instructions. */ | |
3405 | if (bit (aarch64_insn_r->aarch64_insn, 21)) | |
3406 | { | |
3407 | record_buf[0] = reg_rt; | |
3408 | aarch64_insn_r->reg_rec_count = 1; | |
3409 | } | |
3410 | /* Record cpsr for hint and msr(immediate) instructions. */ | |
3411 | else if (reg_crn == 0x02 || reg_crn == 0x04) | |
3412 | { | |
3413 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3414 | aarch64_insn_r->reg_rec_count = 1; | |
3415 | } | |
3416 | } | |
3417 | /* Unconditional branch (register). */ | |
3418 | else if((insn_bits24_27 & 0x0e) == 0x06) | |
3419 | { | |
3420 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3421 | if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01) | |
3422 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3423 | } | |
3424 | else | |
3425 | return AARCH64_RECORD_UNKNOWN; | |
3426 | } | |
3427 | /* Unconditional branch (immediate). */ | |
3428 | else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04) | |
3429 | { | |
3430 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3431 | if (bit (aarch64_insn_r->aarch64_insn, 31)) | |
3432 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3433 | } | |
3434 | else | |
3435 | /* Compare & branch (immediate), Test & branch (immediate) and | |
3436 | Conditional branch (immediate). */ | |
3437 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3438 | ||
3439 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3440 | record_buf); | |
3441 | return AARCH64_RECORD_SUCCESS; | |
3442 | } | |
3443 | ||
3444 | /* Record handler for advanced SIMD load and store instructions. */ | |
3445 | ||
3446 | static unsigned int | |
3447 | aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r) | |
3448 | { | |
3449 | CORE_ADDR address; | |
3450 | uint64_t addr_offset = 0; | |
3451 | uint32_t record_buf[24]; | |
3452 | uint64_t record_buf_mem[24]; | |
3453 | uint32_t reg_rn, reg_rt; | |
3454 | uint32_t reg_index = 0, mem_index = 0; | |
3455 | uint8_t opcode_bits, size_bits; | |
3456 | ||
3457 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3458 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3459 | size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3460 | opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3461 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); | |
3462 | ||
3463 | if (record_debug) | |
b277c936 | 3464 | debug_printf ("Process record: Advanced SIMD load/store\n"); |
99afc88b OJ |
3465 | |
3466 | /* Load/store single structure. */ | |
3467 | if (bit (aarch64_insn_r->aarch64_insn, 24)) | |
3468 | { | |
3469 | uint8_t sindex, scale, selem, esize, replicate = 0; | |
3470 | scale = opcode_bits >> 2; | |
3471 | selem = ((opcode_bits & 0x02) | | |
3472 | bit (aarch64_insn_r->aarch64_insn, 21)) + 1; | |
3473 | switch (scale) | |
3474 | { | |
3475 | case 1: | |
3476 | if (size_bits & 0x01) | |
3477 | return AARCH64_RECORD_UNKNOWN; | |
3478 | break; | |
3479 | case 2: | |
3480 | if ((size_bits >> 1) & 0x01) | |
3481 | return AARCH64_RECORD_UNKNOWN; | |
3482 | if (size_bits & 0x01) | |
3483 | { | |
3484 | if (!((opcode_bits >> 1) & 0x01)) | |
3485 | scale = 3; | |
3486 | else | |
3487 | return AARCH64_RECORD_UNKNOWN; | |
3488 | } | |
3489 | break; | |
3490 | case 3: | |
3491 | if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) | |
3492 | { | |
3493 | scale = size_bits; | |
3494 | replicate = 1; | |
3495 | break; | |
3496 | } | |
3497 | else | |
3498 | return AARCH64_RECORD_UNKNOWN; | |
3499 | default: | |
3500 | break; | |
3501 | } | |
3502 | esize = 8 << scale; | |
3503 | if (replicate) | |
3504 | for (sindex = 0; sindex < selem; sindex++) | |
3505 | { | |
3506 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3507 | reg_rt = (reg_rt + 1) % 32; | |
3508 | } | |
3509 | else | |
3510 | { | |
3511 | for (sindex = 0; sindex < selem; sindex++) | |
a2e3e93f SM |
3512 | { |
3513 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3514 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3515 | else | |
3516 | { | |
3517 | record_buf_mem[mem_index++] = esize / 8; | |
3518 | record_buf_mem[mem_index++] = address + addr_offset; | |
3519 | } | |
3520 | addr_offset = addr_offset + (esize / 8); | |
3521 | reg_rt = (reg_rt + 1) % 32; | |
3522 | } | |
99afc88b OJ |
3523 | } |
3524 | } | |
3525 | /* Load/store multiple structure. */ | |
3526 | else | |
3527 | { | |
3528 | uint8_t selem, esize, rpt, elements; | |
3529 | uint8_t eindex, rindex; | |
3530 | ||
3531 | esize = 8 << size_bits; | |
3532 | if (bit (aarch64_insn_r->aarch64_insn, 30)) | |
3533 | elements = 128 / esize; | |
3534 | else | |
3535 | elements = 64 / esize; | |
3536 | ||
3537 | switch (opcode_bits) | |
3538 | { | |
3539 | /*LD/ST4 (4 Registers). */ | |
3540 | case 0: | |
3541 | rpt = 1; | |
3542 | selem = 4; | |
3543 | break; | |
3544 | /*LD/ST1 (4 Registers). */ | |
3545 | case 2: | |
3546 | rpt = 4; | |
3547 | selem = 1; | |
3548 | break; | |
3549 | /*LD/ST3 (3 Registers). */ | |
3550 | case 4: | |
3551 | rpt = 1; | |
3552 | selem = 3; | |
3553 | break; | |
3554 | /*LD/ST1 (3 Registers). */ | |
3555 | case 6: | |
3556 | rpt = 3; | |
3557 | selem = 1; | |
3558 | break; | |
3559 | /*LD/ST1 (1 Register). */ | |
3560 | case 7: | |
3561 | rpt = 1; | |
3562 | selem = 1; | |
3563 | break; | |
3564 | /*LD/ST2 (2 Registers). */ | |
3565 | case 8: | |
3566 | rpt = 1; | |
3567 | selem = 2; | |
3568 | break; | |
3569 | /*LD/ST1 (2 Registers). */ | |
3570 | case 10: | |
3571 | rpt = 2; | |
3572 | selem = 1; | |
3573 | break; | |
3574 | default: | |
3575 | return AARCH64_RECORD_UNSUPPORTED; | |
3576 | break; | |
3577 | } | |
3578 | for (rindex = 0; rindex < rpt; rindex++) | |
3579 | for (eindex = 0; eindex < elements; eindex++) | |
3580 | { | |
3581 | uint8_t reg_tt, sindex; | |
3582 | reg_tt = (reg_rt + rindex) % 32; | |
3583 | for (sindex = 0; sindex < selem; sindex++) | |
3584 | { | |
3585 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3586 | record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; | |
3587 | else | |
3588 | { | |
3589 | record_buf_mem[mem_index++] = esize / 8; | |
3590 | record_buf_mem[mem_index++] = address + addr_offset; | |
3591 | } | |
3592 | addr_offset = addr_offset + (esize / 8); | |
3593 | reg_tt = (reg_tt + 1) % 32; | |
3594 | } | |
3595 | } | |
3596 | } | |
3597 | ||
3598 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3599 | record_buf[reg_index++] = reg_rn; | |
3600 | ||
3601 | aarch64_insn_r->reg_rec_count = reg_index; | |
3602 | aarch64_insn_r->mem_rec_count = mem_index / 2; | |
3603 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3604 | record_buf_mem); | |
3605 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3606 | record_buf); | |
3607 | return AARCH64_RECORD_SUCCESS; | |
3608 | } | |
3609 | ||
3610 | /* Record handler for load and store instructions. */ | |
3611 | ||
3612 | static unsigned int | |
3613 | aarch64_record_load_store (insn_decode_record *aarch64_insn_r) | |
3614 | { | |
3615 | uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; | |
3616 | uint8_t insn_bit23, insn_bit21; | |
3617 | uint8_t opc, size_bits, ld_flag, vector_flag; | |
3618 | uint32_t reg_rn, reg_rt, reg_rt2; | |
3619 | uint64_t datasize, offset; | |
3620 | uint32_t record_buf[8]; | |
3621 | uint64_t record_buf_mem[8]; | |
3622 | CORE_ADDR address; | |
3623 | ||
3624 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3625 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3626 | insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29); | |
3627 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3628 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); | |
3629 | ld_flag = bit (aarch64_insn_r->aarch64_insn, 22); | |
3630 | vector_flag = bit (aarch64_insn_r->aarch64_insn, 26); | |
3631 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3632 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3633 | reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14); | |
3634 | size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31); | |
3635 | ||
3636 | /* Load/store exclusive. */ | |
3637 | if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00) | |
3638 | { | |
3639 | if (record_debug) | |
b277c936 | 3640 | debug_printf ("Process record: load/store exclusive\n"); |
99afc88b OJ |
3641 | |
3642 | if (ld_flag) | |
3643 | { | |
3644 | record_buf[0] = reg_rt; | |
3645 | aarch64_insn_r->reg_rec_count = 1; | |
3646 | if (insn_bit21) | |
3647 | { | |
3648 | record_buf[1] = reg_rt2; | |
3649 | aarch64_insn_r->reg_rec_count = 2; | |
3650 | } | |
3651 | } | |
3652 | else | |
3653 | { | |
3654 | if (insn_bit21) | |
3655 | datasize = (8 << size_bits) * 2; | |
3656 | else | |
3657 | datasize = (8 << size_bits); | |
3658 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3659 | &address); | |
3660 | record_buf_mem[0] = datasize / 8; | |
3661 | record_buf_mem[1] = address; | |
3662 | aarch64_insn_r->mem_rec_count = 1; | |
3663 | if (!insn_bit23) | |
3664 | { | |
3665 | /* Save register rs. */ | |
3666 | record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20); | |
3667 | aarch64_insn_r->reg_rec_count = 1; | |
3668 | } | |
3669 | } | |
3670 | } | |
3671 | /* Load register (literal) instructions decoding. */ | |
3672 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01) | |
3673 | { | |
3674 | if (record_debug) | |
b277c936 | 3675 | debug_printf ("Process record: load register (literal)\n"); |
99afc88b OJ |
3676 | if (vector_flag) |
3677 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3678 | else | |
3679 | record_buf[0] = reg_rt; | |
3680 | aarch64_insn_r->reg_rec_count = 1; | |
3681 | } | |
3682 | /* All types of load/store pair instructions decoding. */ | |
3683 | else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02) | |
3684 | { | |
3685 | if (record_debug) | |
b277c936 | 3686 | debug_printf ("Process record: load/store pair\n"); |
99afc88b OJ |
3687 | |
3688 | if (ld_flag) | |
3689 | { | |
3690 | if (vector_flag) | |
3691 | { | |
3692 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3693 | record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM; | |
3694 | } | |
3695 | else | |
3696 | { | |
3697 | record_buf[0] = reg_rt; | |
3698 | record_buf[1] = reg_rt2; | |
3699 | } | |
3700 | aarch64_insn_r->reg_rec_count = 2; | |
3701 | } | |
3702 | else | |
3703 | { | |
3704 | uint16_t imm7_off; | |
3705 | imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21); | |
3706 | if (!vector_flag) | |
3707 | size_bits = size_bits >> 1; | |
3708 | datasize = 8 << (2 + size_bits); | |
3709 | offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off; | |
3710 | offset = offset << (2 + size_bits); | |
3711 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3712 | &address); | |
3713 | if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23)) | |
3714 | { | |
3715 | if (imm7_off & 0x40) | |
3716 | address = address - offset; | |
3717 | else | |
3718 | address = address + offset; | |
3719 | } | |
3720 | ||
3721 | record_buf_mem[0] = datasize / 8; | |
3722 | record_buf_mem[1] = address; | |
3723 | record_buf_mem[2] = datasize / 8; | |
3724 | record_buf_mem[3] = address + (datasize / 8); | |
3725 | aarch64_insn_r->mem_rec_count = 2; | |
3726 | } | |
3727 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3728 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3729 | } | |
3730 | /* Load/store register (unsigned immediate) instructions. */ | |
3731 | else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03) | |
3732 | { | |
3733 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3734 | if (!(opc >> 1)) | |
33877125 YQ |
3735 | { |
3736 | if (opc & 0x01) | |
3737 | ld_flag = 0x01; | |
3738 | else | |
3739 | ld_flag = 0x0; | |
3740 | } | |
99afc88b | 3741 | else |
33877125 | 3742 | { |
1e2b521d YQ |
3743 | if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2) |
3744 | { | |
3745 | /* PRFM (immediate) */ | |
3746 | return AARCH64_RECORD_SUCCESS; | |
3747 | } | |
3748 | else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2) | |
3749 | { | |
3750 | /* LDRSW (immediate) */ | |
3751 | ld_flag = 0x1; | |
3752 | } | |
33877125 | 3753 | else |
1e2b521d YQ |
3754 | { |
3755 | if (opc & 0x01) | |
3756 | ld_flag = 0x01; | |
3757 | else | |
3758 | ld_flag = 0x0; | |
3759 | } | |
33877125 | 3760 | } |
99afc88b OJ |
3761 | |
3762 | if (record_debug) | |
3763 | { | |
b277c936 PL |
3764 | debug_printf ("Process record: load/store (unsigned immediate):" |
3765 | " size %x V %d opc %x\n", size_bits, vector_flag, | |
3766 | opc); | |
99afc88b OJ |
3767 | } |
3768 | ||
3769 | if (!ld_flag) | |
3770 | { | |
3771 | offset = bits (aarch64_insn_r->aarch64_insn, 10, 21); | |
3772 | datasize = 8 << size_bits; | |
3773 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3774 | &address); | |
3775 | offset = offset << size_bits; | |
3776 | address = address + offset; | |
3777 | ||
3778 | record_buf_mem[0] = datasize >> 3; | |
3779 | record_buf_mem[1] = address; | |
3780 | aarch64_insn_r->mem_rec_count = 1; | |
3781 | } | |
3782 | else | |
3783 | { | |
3784 | if (vector_flag) | |
3785 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3786 | else | |
3787 | record_buf[0] = reg_rt; | |
3788 | aarch64_insn_r->reg_rec_count = 1; | |
3789 | } | |
3790 | } | |
3791 | /* Load/store register (register offset) instructions. */ | |
5d98d3cd YQ |
3792 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3793 | && insn_bits10_11 == 0x02 && insn_bit21) | |
99afc88b OJ |
3794 | { |
3795 | if (record_debug) | |
b277c936 | 3796 | debug_printf ("Process record: load/store (register offset)\n"); |
99afc88b OJ |
3797 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); |
3798 | if (!(opc >> 1)) | |
3799 | if (opc & 0x01) | |
3800 | ld_flag = 0x01; | |
3801 | else | |
3802 | ld_flag = 0x0; | |
3803 | else | |
3804 | if (size_bits != 0x03) | |
3805 | ld_flag = 0x01; | |
3806 | else | |
3807 | return AARCH64_RECORD_UNKNOWN; | |
3808 | ||
3809 | if (!ld_flag) | |
3810 | { | |
d9436c7c PA |
3811 | ULONGEST reg_rm_val; |
3812 | ||
99afc88b OJ |
3813 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, |
3814 | bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val); | |
3815 | if (bit (aarch64_insn_r->aarch64_insn, 12)) | |
3816 | offset = reg_rm_val << size_bits; | |
3817 | else | |
3818 | offset = reg_rm_val; | |
3819 | datasize = 8 << size_bits; | |
3820 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3821 | &address); | |
3822 | address = address + offset; | |
3823 | record_buf_mem[0] = datasize >> 3; | |
3824 | record_buf_mem[1] = address; | |
3825 | aarch64_insn_r->mem_rec_count = 1; | |
3826 | } | |
3827 | else | |
3828 | { | |
3829 | if (vector_flag) | |
3830 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3831 | else | |
3832 | record_buf[0] = reg_rt; | |
3833 | aarch64_insn_r->reg_rec_count = 1; | |
3834 | } | |
3835 | } | |
3836 | /* Load/store register (immediate and unprivileged) instructions. */ | |
5d98d3cd YQ |
3837 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3838 | && !insn_bit21) | |
99afc88b OJ |
3839 | { |
3840 | if (record_debug) | |
3841 | { | |
b277c936 PL |
3842 | debug_printf ("Process record: load/store " |
3843 | "(immediate and unprivileged)\n"); | |
99afc88b OJ |
3844 | } |
3845 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3846 | if (!(opc >> 1)) | |
3847 | if (opc & 0x01) | |
3848 | ld_flag = 0x01; | |
3849 | else | |
3850 | ld_flag = 0x0; | |
3851 | else | |
3852 | if (size_bits != 0x03) | |
3853 | ld_flag = 0x01; | |
3854 | else | |
3855 | return AARCH64_RECORD_UNKNOWN; | |
3856 | ||
3857 | if (!ld_flag) | |
3858 | { | |
3859 | uint16_t imm9_off; | |
3860 | imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20); | |
3861 | offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off; | |
3862 | datasize = 8 << size_bits; | |
3863 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3864 | &address); | |
3865 | if (insn_bits10_11 != 0x01) | |
3866 | { | |
3867 | if (imm9_off & 0x0100) | |
3868 | address = address - offset; | |
3869 | else | |
3870 | address = address + offset; | |
3871 | } | |
3872 | record_buf_mem[0] = datasize >> 3; | |
3873 | record_buf_mem[1] = address; | |
3874 | aarch64_insn_r->mem_rec_count = 1; | |
3875 | } | |
3876 | else | |
3877 | { | |
3878 | if (vector_flag) | |
3879 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3880 | else | |
3881 | record_buf[0] = reg_rt; | |
3882 | aarch64_insn_r->reg_rec_count = 1; | |
3883 | } | |
3884 | if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) | |
3885 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3886 | } | |
3887 | /* Advanced SIMD load/store instructions. */ | |
3888 | else | |
3889 | return aarch64_record_asimd_load_store (aarch64_insn_r); | |
3890 | ||
3891 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3892 | record_buf_mem); | |
3893 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3894 | record_buf); | |
3895 | return AARCH64_RECORD_SUCCESS; | |
3896 | } | |
3897 | ||
3898 | /* Record handler for data processing SIMD and floating point instructions. */ | |
3899 | ||
3900 | static unsigned int | |
3901 | aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) | |
3902 | { | |
3903 | uint8_t insn_bit21, opcode, rmode, reg_rd; | |
3904 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; | |
3905 | uint8_t insn_bits11_14; | |
3906 | uint32_t record_buf[2]; | |
3907 | ||
3908 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3909 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3910 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3911 | insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3912 | insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); | |
3913 | opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); | |
3914 | rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); | |
3915 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3916 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3917 | ||
3918 | if (record_debug) | |
b277c936 | 3919 | debug_printf ("Process record: data processing SIMD/FP: "); |
99afc88b OJ |
3920 | |
3921 | if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) | |
3922 | { | |
3923 | /* Floating point - fixed point conversion instructions. */ | |
3924 | if (!insn_bit21) | |
3925 | { | |
3926 | if (record_debug) | |
b277c936 | 3927 | debug_printf ("FP - fixed point conversion"); |
99afc88b OJ |
3928 | |
3929 | if ((opcode >> 1) == 0x0 && rmode == 0x03) | |
3930 | record_buf[0] = reg_rd; | |
3931 | else | |
3932 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3933 | } | |
3934 | /* Floating point - conditional compare instructions. */ | |
3935 | else if (insn_bits10_11 == 0x01) | |
3936 | { | |
3937 | if (record_debug) | |
b277c936 | 3938 | debug_printf ("FP - conditional compare"); |
99afc88b OJ |
3939 | |
3940 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3941 | } | |
3942 | /* Floating point - data processing (2-source) and | |
3943 | conditional select instructions. */ | |
3944 | else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) | |
3945 | { | |
3946 | if (record_debug) | |
b277c936 | 3947 | debug_printf ("FP - DP (2-source)"); |
99afc88b OJ |
3948 | |
3949 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3950 | } | |
3951 | else if (insn_bits10_11 == 0x00) | |
3952 | { | |
3953 | /* Floating point - immediate instructions. */ | |
3954 | if ((insn_bits12_15 & 0x01) == 0x01 | |
3955 | || (insn_bits12_15 & 0x07) == 0x04) | |
3956 | { | |
3957 | if (record_debug) | |
b277c936 | 3958 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3959 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; |
3960 | } | |
3961 | /* Floating point - compare instructions. */ | |
3962 | else if ((insn_bits12_15 & 0x03) == 0x02) | |
3963 | { | |
3964 | if (record_debug) | |
b277c936 | 3965 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3966 | record_buf[0] = AARCH64_CPSR_REGNUM; |
3967 | } | |
3968 | /* Floating point - integer conversions instructions. */ | |
f62fce35 | 3969 | else if (insn_bits12_15 == 0x00) |
99afc88b OJ |
3970 | { |
3971 | /* Convert float to integer instruction. */ | |
3972 | if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) | |
3973 | { | |
3974 | if (record_debug) | |
b277c936 | 3975 | debug_printf ("float to int conversion"); |
99afc88b OJ |
3976 | |
3977 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3978 | } | |
3979 | /* Convert integer to float instruction. */ | |
3980 | else if ((opcode >> 1) == 0x01 && !rmode) | |
3981 | { | |
3982 | if (record_debug) | |
b277c936 | 3983 | debug_printf ("int to float conversion"); |
99afc88b OJ |
3984 | |
3985 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3986 | } | |
3987 | /* Move float to integer instruction. */ | |
3988 | else if ((opcode >> 1) == 0x03) | |
3989 | { | |
3990 | if (record_debug) | |
b277c936 | 3991 | debug_printf ("move float to int"); |
99afc88b OJ |
3992 | |
3993 | if (!(opcode & 0x01)) | |
3994 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3995 | else | |
3996 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3997 | } | |
f62fce35 YQ |
3998 | else |
3999 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 4000 | } |
f62fce35 YQ |
4001 | else |
4002 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 4003 | } |
f62fce35 YQ |
4004 | else |
4005 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4006 | } |
4007 | else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) | |
4008 | { | |
4009 | if (record_debug) | |
b277c936 | 4010 | debug_printf ("SIMD copy"); |
99afc88b OJ |
4011 | |
4012 | /* Advanced SIMD copy instructions. */ | |
4013 | if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
4014 | && !bit (aarch64_insn_r->aarch64_insn, 15) | |
4015 | && bit (aarch64_insn_r->aarch64_insn, 10)) | |
4016 | { | |
4017 | if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) | |
4018 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4019 | else | |
4020 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4021 | } | |
4022 | else | |
4023 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4024 | } | |
4025 | /* All remaining floating point or advanced SIMD instructions. */ | |
4026 | else | |
4027 | { | |
4028 | if (record_debug) | |
b277c936 | 4029 | debug_printf ("all remain"); |
99afc88b OJ |
4030 | |
4031 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4032 | } | |
4033 | ||
4034 | if (record_debug) | |
b277c936 | 4035 | debug_printf ("\n"); |
99afc88b OJ |
4036 | |
4037 | aarch64_insn_r->reg_rec_count++; | |
4038 | gdb_assert (aarch64_insn_r->reg_rec_count == 1); | |
4039 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
4040 | record_buf); | |
4041 | return AARCH64_RECORD_SUCCESS; | |
4042 | } | |
4043 | ||
4044 | /* Decodes insns type and invokes its record handler. */ | |
4045 | ||
4046 | static unsigned int | |
4047 | aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r) | |
4048 | { | |
4049 | uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; | |
4050 | ||
4051 | ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25); | |
4052 | ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26); | |
4053 | ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27); | |
4054 | ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28); | |
4055 | ||
4056 | /* Data processing - immediate instructions. */ | |
4057 | if (!ins_bit26 && !ins_bit27 && ins_bit28) | |
4058 | return aarch64_record_data_proc_imm (aarch64_insn_r); | |
4059 | ||
4060 | /* Branch, exception generation and system instructions. */ | |
4061 | if (ins_bit26 && !ins_bit27 && ins_bit28) | |
4062 | return aarch64_record_branch_except_sys (aarch64_insn_r); | |
4063 | ||
4064 | /* Load and store instructions. */ | |
4065 | if (!ins_bit25 && ins_bit27) | |
4066 | return aarch64_record_load_store (aarch64_insn_r); | |
4067 | ||
4068 | /* Data processing - register instructions. */ | |
4069 | if (ins_bit25 && !ins_bit26 && ins_bit27) | |
4070 | return aarch64_record_data_proc_reg (aarch64_insn_r); | |
4071 | ||
4072 | /* Data processing - SIMD and floating point instructions. */ | |
4073 | if (ins_bit25 && ins_bit26 && ins_bit27) | |
4074 | return aarch64_record_data_proc_simd_fp (aarch64_insn_r); | |
4075 | ||
4076 | return AARCH64_RECORD_UNSUPPORTED; | |
4077 | } | |
4078 | ||
4079 | /* Cleans up local record registers and memory allocations. */ | |
4080 | ||
4081 | static void | |
4082 | deallocate_reg_mem (insn_decode_record *record) | |
4083 | { | |
4084 | xfree (record->aarch64_regs); | |
4085 | xfree (record->aarch64_mems); | |
4086 | } | |
4087 | ||
1e2b521d YQ |
4088 | #if GDB_SELF_TEST |
4089 | namespace selftests { | |
4090 | ||
4091 | static void | |
4092 | aarch64_process_record_test (void) | |
4093 | { | |
4094 | struct gdbarch_info info; | |
4095 | uint32_t ret; | |
4096 | ||
4097 | gdbarch_info_init (&info); | |
4098 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
4099 | ||
4100 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
4101 | SELF_CHECK (gdbarch != NULL); | |
4102 | ||
4103 | insn_decode_record aarch64_record; | |
4104 | ||
4105 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
4106 | aarch64_record.regcache = NULL; | |
4107 | aarch64_record.this_addr = 0; | |
4108 | aarch64_record.gdbarch = gdbarch; | |
4109 | ||
4110 | /* 20 00 80 f9 prfm pldl1keep, [x1] */ | |
4111 | aarch64_record.aarch64_insn = 0xf9800020; | |
4112 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4113 | SELF_CHECK (ret == AARCH64_RECORD_SUCCESS); | |
4114 | SELF_CHECK (aarch64_record.reg_rec_count == 0); | |
4115 | SELF_CHECK (aarch64_record.mem_rec_count == 0); | |
4116 | ||
4117 | deallocate_reg_mem (&aarch64_record); | |
4118 | } | |
4119 | ||
4120 | } // namespace selftests | |
4121 | #endif /* GDB_SELF_TEST */ | |
4122 | ||
99afc88b OJ |
4123 | /* Parse the current instruction and record the values of the registers and |
4124 | memory that will be changed in current instruction to record_arch_list | |
4125 | return -1 if something is wrong. */ | |
4126 | ||
4127 | int | |
4128 | aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
4129 | CORE_ADDR insn_addr) | |
4130 | { | |
4131 | uint32_t rec_no = 0; | |
4132 | uint8_t insn_size = 4; | |
4133 | uint32_t ret = 0; | |
99afc88b OJ |
4134 | gdb_byte buf[insn_size]; |
4135 | insn_decode_record aarch64_record; | |
4136 | ||
4137 | memset (&buf[0], 0, insn_size); | |
4138 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
4139 | target_read_memory (insn_addr, &buf[0], insn_size); | |
4140 | aarch64_record.aarch64_insn | |
4141 | = (uint32_t) extract_unsigned_integer (&buf[0], | |
4142 | insn_size, | |
4143 | gdbarch_byte_order (gdbarch)); | |
4144 | aarch64_record.regcache = regcache; | |
4145 | aarch64_record.this_addr = insn_addr; | |
4146 | aarch64_record.gdbarch = gdbarch; | |
4147 | ||
4148 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4149 | if (ret == AARCH64_RECORD_UNSUPPORTED) | |
4150 | { | |
4151 | printf_unfiltered (_("Process record does not support instruction " | |
4152 | "0x%0x at address %s.\n"), | |
4153 | aarch64_record.aarch64_insn, | |
4154 | paddress (gdbarch, insn_addr)); | |
4155 | ret = -1; | |
4156 | } | |
4157 | ||
4158 | if (0 == ret) | |
4159 | { | |
4160 | /* Record registers. */ | |
4161 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4162 | AARCH64_PC_REGNUM); | |
4163 | /* Always record register CPSR. */ | |
4164 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4165 | AARCH64_CPSR_REGNUM); | |
4166 | if (aarch64_record.aarch64_regs) | |
4167 | for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++) | |
4168 | if (record_full_arch_list_add_reg (aarch64_record.regcache, | |
4169 | aarch64_record.aarch64_regs[rec_no])) | |
4170 | ret = -1; | |
4171 | ||
4172 | /* Record memories. */ | |
4173 | if (aarch64_record.aarch64_mems) | |
4174 | for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++) | |
4175 | if (record_full_arch_list_add_mem | |
4176 | ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr, | |
4177 | aarch64_record.aarch64_mems[rec_no].len)) | |
4178 | ret = -1; | |
4179 | ||
4180 | if (record_full_arch_list_add_end ()) | |
4181 | ret = -1; | |
4182 | } | |
4183 | ||
4184 | deallocate_reg_mem (&aarch64_record); | |
4185 | return ret; | |
4186 | } |