Commit | Line | Data |
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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
61baf725 | 3 | Copyright (C) 2009-2017 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
07b287a0 MS |
27 | #include "dis-asm.h" |
28 | #include "regcache.h" | |
29 | #include "reggroups.h" | |
07b287a0 MS |
30 | #include "value.h" |
31 | #include "arch-utils.h" | |
32 | #include "osabi.h" | |
33 | #include "frame-unwind.h" | |
34 | #include "frame-base.h" | |
35 | #include "trad-frame.h" | |
36 | #include "objfiles.h" | |
37 | #include "dwarf2-frame.h" | |
38 | #include "gdbtypes.h" | |
39 | #include "prologue-value.h" | |
40 | #include "target-descriptions.h" | |
41 | #include "user-regs.h" | |
42 | #include "language.h" | |
43 | #include "infcall.h" | |
ea873d8e PL |
44 | #include "ax.h" |
45 | #include "ax-gdb.h" | |
4d9a9006 | 46 | #include "selftest.h" |
07b287a0 MS |
47 | |
48 | #include "aarch64-tdep.h" | |
49 | ||
50 | #include "elf-bfd.h" | |
51 | #include "elf/aarch64.h" | |
52 | ||
07b287a0 MS |
53 | #include "vec.h" |
54 | ||
99afc88b OJ |
55 | #include "record.h" |
56 | #include "record-full.h" | |
57 | ||
07b287a0 | 58 | #include "features/aarch64.c" |
07b287a0 | 59 | |
787749ea PL |
60 | #include "arch/aarch64-insn.h" |
61 | ||
f77ee802 | 62 | #include "opcode/aarch64.h" |
325fac50 | 63 | #include <algorithm> |
f77ee802 YQ |
64 | |
65 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
66 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
67 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
68 | ||
07b287a0 MS |
69 | /* Pseudo register base numbers. */ |
70 | #define AARCH64_Q0_REGNUM 0 | |
187f5d00 | 71 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT) |
07b287a0 MS |
72 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) |
73 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
74 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
75 | ||
76 | /* The standard register names, and all the valid aliases for them. */ | |
77 | static const struct | |
78 | { | |
79 | const char *const name; | |
80 | int regnum; | |
81 | } aarch64_register_aliases[] = | |
82 | { | |
83 | /* 64-bit register names. */ | |
84 | {"fp", AARCH64_FP_REGNUM}, | |
85 | {"lr", AARCH64_LR_REGNUM}, | |
86 | {"sp", AARCH64_SP_REGNUM}, | |
87 | ||
88 | /* 32-bit register names. */ | |
89 | {"w0", AARCH64_X0_REGNUM + 0}, | |
90 | {"w1", AARCH64_X0_REGNUM + 1}, | |
91 | {"w2", AARCH64_X0_REGNUM + 2}, | |
92 | {"w3", AARCH64_X0_REGNUM + 3}, | |
93 | {"w4", AARCH64_X0_REGNUM + 4}, | |
94 | {"w5", AARCH64_X0_REGNUM + 5}, | |
95 | {"w6", AARCH64_X0_REGNUM + 6}, | |
96 | {"w7", AARCH64_X0_REGNUM + 7}, | |
97 | {"w8", AARCH64_X0_REGNUM + 8}, | |
98 | {"w9", AARCH64_X0_REGNUM + 9}, | |
99 | {"w10", AARCH64_X0_REGNUM + 10}, | |
100 | {"w11", AARCH64_X0_REGNUM + 11}, | |
101 | {"w12", AARCH64_X0_REGNUM + 12}, | |
102 | {"w13", AARCH64_X0_REGNUM + 13}, | |
103 | {"w14", AARCH64_X0_REGNUM + 14}, | |
104 | {"w15", AARCH64_X0_REGNUM + 15}, | |
105 | {"w16", AARCH64_X0_REGNUM + 16}, | |
106 | {"w17", AARCH64_X0_REGNUM + 17}, | |
107 | {"w18", AARCH64_X0_REGNUM + 18}, | |
108 | {"w19", AARCH64_X0_REGNUM + 19}, | |
109 | {"w20", AARCH64_X0_REGNUM + 20}, | |
110 | {"w21", AARCH64_X0_REGNUM + 21}, | |
111 | {"w22", AARCH64_X0_REGNUM + 22}, | |
112 | {"w23", AARCH64_X0_REGNUM + 23}, | |
113 | {"w24", AARCH64_X0_REGNUM + 24}, | |
114 | {"w25", AARCH64_X0_REGNUM + 25}, | |
115 | {"w26", AARCH64_X0_REGNUM + 26}, | |
116 | {"w27", AARCH64_X0_REGNUM + 27}, | |
117 | {"w28", AARCH64_X0_REGNUM + 28}, | |
118 | {"w29", AARCH64_X0_REGNUM + 29}, | |
119 | {"w30", AARCH64_X0_REGNUM + 30}, | |
120 | ||
121 | /* specials */ | |
122 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
123 | {"ip1", AARCH64_X0_REGNUM + 17} | |
124 | }; | |
125 | ||
126 | /* The required core 'R' registers. */ | |
127 | static const char *const aarch64_r_register_names[] = | |
128 | { | |
129 | /* These registers must appear in consecutive RAW register number | |
130 | order and they must begin with AARCH64_X0_REGNUM! */ | |
131 | "x0", "x1", "x2", "x3", | |
132 | "x4", "x5", "x6", "x7", | |
133 | "x8", "x9", "x10", "x11", | |
134 | "x12", "x13", "x14", "x15", | |
135 | "x16", "x17", "x18", "x19", | |
136 | "x20", "x21", "x22", "x23", | |
137 | "x24", "x25", "x26", "x27", | |
138 | "x28", "x29", "x30", "sp", | |
139 | "pc", "cpsr" | |
140 | }; | |
141 | ||
142 | /* The FP/SIMD 'V' registers. */ | |
143 | static const char *const aarch64_v_register_names[] = | |
144 | { | |
145 | /* These registers must appear in consecutive RAW register number | |
146 | order and they must begin with AARCH64_V0_REGNUM! */ | |
147 | "v0", "v1", "v2", "v3", | |
148 | "v4", "v5", "v6", "v7", | |
149 | "v8", "v9", "v10", "v11", | |
150 | "v12", "v13", "v14", "v15", | |
151 | "v16", "v17", "v18", "v19", | |
152 | "v20", "v21", "v22", "v23", | |
153 | "v24", "v25", "v26", "v27", | |
154 | "v28", "v29", "v30", "v31", | |
155 | "fpsr", | |
156 | "fpcr" | |
157 | }; | |
158 | ||
159 | /* AArch64 prologue cache structure. */ | |
160 | struct aarch64_prologue_cache | |
161 | { | |
db634143 PL |
162 | /* The program counter at the start of the function. It is used to |
163 | identify this frame as a prologue frame. */ | |
164 | CORE_ADDR func; | |
165 | ||
166 | /* The program counter at the time this frame was created; i.e. where | |
167 | this function was called from. It is used to identify this frame as a | |
168 | stub frame. */ | |
169 | CORE_ADDR prev_pc; | |
170 | ||
07b287a0 MS |
171 | /* The stack pointer at the time this frame was created; i.e. the |
172 | caller's stack pointer when this function was called. It is used | |
173 | to identify this frame. */ | |
174 | CORE_ADDR prev_sp; | |
175 | ||
7dfa3edc PL |
176 | /* Is the target available to read from? */ |
177 | int available_p; | |
178 | ||
07b287a0 MS |
179 | /* The frame base for this frame is just prev_sp - frame size. |
180 | FRAMESIZE is the distance from the frame pointer to the | |
181 | initial stack pointer. */ | |
182 | int framesize; | |
183 | ||
184 | /* The register used to hold the frame pointer for this frame. */ | |
185 | int framereg; | |
186 | ||
187 | /* Saved register offsets. */ | |
188 | struct trad_frame_saved_reg *saved_regs; | |
189 | }; | |
190 | ||
07b287a0 MS |
191 | static void |
192 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
193 | struct cmd_list_element *c, const char *value) | |
194 | { | |
195 | fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value); | |
196 | } | |
197 | ||
ffdbe864 YQ |
198 | namespace { |
199 | ||
4d9a9006 YQ |
200 | /* Abstract instruction reader. */ |
201 | ||
202 | class abstract_instruction_reader | |
203 | { | |
204 | public: | |
205 | /* Read in one instruction. */ | |
206 | virtual ULONGEST read (CORE_ADDR memaddr, int len, | |
207 | enum bfd_endian byte_order) = 0; | |
208 | }; | |
209 | ||
210 | /* Instruction reader from real target. */ | |
211 | ||
212 | class instruction_reader : public abstract_instruction_reader | |
213 | { | |
214 | public: | |
215 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
216 | { | |
fc2f703e | 217 | return read_code_unsigned_integer (memaddr, len, byte_order); |
4d9a9006 YQ |
218 | } |
219 | }; | |
220 | ||
ffdbe864 YQ |
221 | } // namespace |
222 | ||
07b287a0 MS |
223 | /* Analyze a prologue, looking for a recognizable stack frame |
224 | and frame pointer. Scan until we encounter a store that could | |
225 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
226 | ||
227 | static CORE_ADDR | |
228 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
229 | CORE_ADDR start, CORE_ADDR limit, | |
4d9a9006 YQ |
230 | struct aarch64_prologue_cache *cache, |
231 | abstract_instruction_reader& reader) | |
07b287a0 MS |
232 | { |
233 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
234 | int i; | |
187f5d00 YQ |
235 | /* Track X registers and D registers in prologue. */ |
236 | pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT]; | |
07b287a0 | 237 | |
187f5d00 | 238 | for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++) |
07b287a0 | 239 | regs[i] = pv_register (i, 0); |
f7b7ed97 | 240 | pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
07b287a0 MS |
241 | |
242 | for (; start < limit; start += 4) | |
243 | { | |
244 | uint32_t insn; | |
d9ebcbce | 245 | aarch64_inst inst; |
07b287a0 | 246 | |
4d9a9006 | 247 | insn = reader.read (start, 4, byte_order_for_code); |
07b287a0 | 248 | |
d9ebcbce YQ |
249 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
250 | break; | |
251 | ||
252 | if (inst.opcode->iclass == addsub_imm | |
253 | && (inst.opcode->op == OP_ADD | |
254 | || strcmp ("sub", inst.opcode->name) == 0)) | |
07b287a0 | 255 | { |
d9ebcbce YQ |
256 | unsigned rd = inst.operands[0].reg.regno; |
257 | unsigned rn = inst.operands[1].reg.regno; | |
258 | ||
259 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
260 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
261 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
262 | gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM); | |
263 | ||
264 | if (inst.opcode->op == OP_ADD) | |
265 | { | |
266 | regs[rd] = pv_add_constant (regs[rn], | |
267 | inst.operands[2].imm.value); | |
268 | } | |
269 | else | |
270 | { | |
271 | regs[rd] = pv_add_constant (regs[rn], | |
272 | -inst.operands[2].imm.value); | |
273 | } | |
274 | } | |
275 | else if (inst.opcode->iclass == pcreladdr | |
276 | && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP) | |
277 | { | |
278 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
279 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
280 | ||
281 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
07b287a0 | 282 | } |
d9ebcbce | 283 | else if (inst.opcode->iclass == branch_imm) |
07b287a0 MS |
284 | { |
285 | /* Stop analysis on branch. */ | |
286 | break; | |
287 | } | |
d9ebcbce | 288 | else if (inst.opcode->iclass == condbranch) |
07b287a0 MS |
289 | { |
290 | /* Stop analysis on branch. */ | |
291 | break; | |
292 | } | |
d9ebcbce | 293 | else if (inst.opcode->iclass == branch_reg) |
07b287a0 MS |
294 | { |
295 | /* Stop analysis on branch. */ | |
296 | break; | |
297 | } | |
d9ebcbce | 298 | else if (inst.opcode->iclass == compbranch) |
07b287a0 MS |
299 | { |
300 | /* Stop analysis on branch. */ | |
301 | break; | |
302 | } | |
d9ebcbce YQ |
303 | else if (inst.opcode->op == OP_MOVZ) |
304 | { | |
305 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
306 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
307 | } | |
308 | else if (inst.opcode->iclass == log_shift | |
309 | && strcmp (inst.opcode->name, "orr") == 0) | |
07b287a0 | 310 | { |
d9ebcbce YQ |
311 | unsigned rd = inst.operands[0].reg.regno; |
312 | unsigned rn = inst.operands[1].reg.regno; | |
313 | unsigned rm = inst.operands[2].reg.regno; | |
314 | ||
315 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
316 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn); | |
317 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT); | |
318 | ||
319 | if (inst.operands[2].shifter.amount == 0 | |
320 | && rn == AARCH64_SP_REGNUM) | |
07b287a0 MS |
321 | regs[rd] = regs[rm]; |
322 | else | |
323 | { | |
324 | if (aarch64_debug) | |
b277c936 PL |
325 | { |
326 | debug_printf ("aarch64: prologue analysis gave up " | |
0a0da556 | 327 | "addr=%s opcode=0x%x (orr x register)\n", |
b277c936 PL |
328 | core_addr_to_string_nz (start), insn); |
329 | } | |
07b287a0 MS |
330 | break; |
331 | } | |
332 | } | |
d9ebcbce | 333 | else if (inst.opcode->op == OP_STUR) |
07b287a0 | 334 | { |
d9ebcbce YQ |
335 | unsigned rt = inst.operands[0].reg.regno; |
336 | unsigned rn = inst.operands[1].addr.base_regno; | |
337 | int is64 | |
338 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
339 | ||
340 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
341 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); | |
342 | gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); | |
343 | gdb_assert (!inst.operands[1].addr.offset.is_reg); | |
344 | ||
f7b7ed97 TT |
345 | stack.store (pv_add_constant (regs[rn], |
346 | inst.operands[1].addr.offset.imm), | |
347 | is64 ? 8 : 4, regs[rt]); | |
07b287a0 | 348 | } |
d9ebcbce | 349 | else if ((inst.opcode->iclass == ldstpair_off |
03bcd739 YQ |
350 | || (inst.opcode->iclass == ldstpair_indexed |
351 | && inst.operands[2].addr.preind)) | |
d9ebcbce | 352 | && strcmp ("stp", inst.opcode->name) == 0) |
07b287a0 | 353 | { |
03bcd739 | 354 | /* STP with addressing mode Pre-indexed and Base register. */ |
187f5d00 YQ |
355 | unsigned rt1; |
356 | unsigned rt2; | |
d9ebcbce YQ |
357 | unsigned rn = inst.operands[2].addr.base_regno; |
358 | int32_t imm = inst.operands[2].addr.offset.imm; | |
359 | ||
187f5d00 YQ |
360 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
361 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
362 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2 | |
363 | || inst.operands[1].type == AARCH64_OPND_Ft2); | |
d9ebcbce YQ |
364 | gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7); |
365 | gdb_assert (!inst.operands[2].addr.offset.is_reg); | |
366 | ||
07b287a0 MS |
367 | /* If recording this store would invalidate the store area |
368 | (perhaps because rn is not known) then we should abandon | |
369 | further prologue analysis. */ | |
f7b7ed97 | 370 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm))) |
07b287a0 MS |
371 | break; |
372 | ||
f7b7ed97 | 373 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8))) |
07b287a0 MS |
374 | break; |
375 | ||
187f5d00 YQ |
376 | rt1 = inst.operands[0].reg.regno; |
377 | rt2 = inst.operands[1].reg.regno; | |
378 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
379 | { | |
380 | /* Only bottom 64-bit of each V register (D register) need | |
381 | to be preserved. */ | |
382 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
383 | rt1 += AARCH64_X_REGISTER_COUNT; | |
384 | rt2 += AARCH64_X_REGISTER_COUNT; | |
385 | } | |
386 | ||
f7b7ed97 TT |
387 | stack.store (pv_add_constant (regs[rn], imm), 8, |
388 | regs[rt1]); | |
389 | stack.store (pv_add_constant (regs[rn], imm + 8), 8, | |
390 | regs[rt2]); | |
14ac654f | 391 | |
d9ebcbce | 392 | if (inst.operands[2].addr.writeback) |
93d96012 | 393 | regs[rn] = pv_add_constant (regs[rn], imm); |
07b287a0 | 394 | |
07b287a0 | 395 | } |
432ec081 YQ |
396 | else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ |
397 | || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ | |
398 | && (inst.opcode->op == OP_STR_POS | |
399 | || inst.opcode->op == OP_STRF_POS))) | |
400 | && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM | |
401 | && strcmp ("str", inst.opcode->name) == 0) | |
402 | { | |
403 | /* STR (immediate) */ | |
404 | unsigned int rt = inst.operands[0].reg.regno; | |
405 | int32_t imm = inst.operands[1].addr.offset.imm; | |
406 | unsigned int rn = inst.operands[1].addr.base_regno; | |
407 | bool is64 | |
408 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
409 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt | |
410 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
411 | ||
412 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
413 | { | |
414 | /* Only bottom 64-bit of each V register (D register) need | |
415 | to be preserved. */ | |
416 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
417 | rt += AARCH64_X_REGISTER_COUNT; | |
418 | } | |
419 | ||
f7b7ed97 TT |
420 | stack.store (pv_add_constant (regs[rn], imm), |
421 | is64 ? 8 : 4, regs[rt]); | |
432ec081 YQ |
422 | if (inst.operands[1].addr.writeback) |
423 | regs[rn] = pv_add_constant (regs[rn], imm); | |
424 | } | |
d9ebcbce | 425 | else if (inst.opcode->iclass == testbranch) |
07b287a0 MS |
426 | { |
427 | /* Stop analysis on branch. */ | |
428 | break; | |
429 | } | |
430 | else | |
431 | { | |
432 | if (aarch64_debug) | |
b277c936 | 433 | { |
0a0da556 | 434 | debug_printf ("aarch64: prologue analysis gave up addr=%s" |
b277c936 PL |
435 | " opcode=0x%x\n", |
436 | core_addr_to_string_nz (start), insn); | |
437 | } | |
07b287a0 MS |
438 | break; |
439 | } | |
440 | } | |
441 | ||
442 | if (cache == NULL) | |
f7b7ed97 | 443 | return start; |
07b287a0 MS |
444 | |
445 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
446 | { | |
447 | /* Frame pointer is fp. Frame size is constant. */ | |
448 | cache->framereg = AARCH64_FP_REGNUM; | |
449 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
450 | } | |
451 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
452 | { | |
453 | /* Try the stack pointer. */ | |
454 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
455 | cache->framereg = AARCH64_SP_REGNUM; | |
456 | } | |
457 | else | |
458 | { | |
459 | /* We're just out of luck. We don't know where the frame is. */ | |
460 | cache->framereg = -1; | |
461 | cache->framesize = 0; | |
462 | } | |
463 | ||
464 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
465 | { | |
466 | CORE_ADDR offset; | |
467 | ||
f7b7ed97 | 468 | if (stack.find_reg (gdbarch, i, &offset)) |
07b287a0 MS |
469 | cache->saved_regs[i].addr = offset; |
470 | } | |
471 | ||
187f5d00 YQ |
472 | for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++) |
473 | { | |
474 | int regnum = gdbarch_num_regs (gdbarch); | |
475 | CORE_ADDR offset; | |
476 | ||
f7b7ed97 TT |
477 | if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT, |
478 | &offset)) | |
187f5d00 YQ |
479 | cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset; |
480 | } | |
481 | ||
07b287a0 MS |
482 | return start; |
483 | } | |
484 | ||
4d9a9006 YQ |
485 | static CORE_ADDR |
486 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
487 | CORE_ADDR start, CORE_ADDR limit, | |
488 | struct aarch64_prologue_cache *cache) | |
489 | { | |
490 | instruction_reader reader; | |
491 | ||
492 | return aarch64_analyze_prologue (gdbarch, start, limit, cache, | |
493 | reader); | |
494 | } | |
495 | ||
496 | #if GDB_SELF_TEST | |
497 | ||
498 | namespace selftests { | |
499 | ||
500 | /* Instruction reader from manually cooked instruction sequences. */ | |
501 | ||
502 | class instruction_reader_test : public abstract_instruction_reader | |
503 | { | |
504 | public: | |
505 | template<size_t SIZE> | |
506 | explicit instruction_reader_test (const uint32_t (&insns)[SIZE]) | |
507 | : m_insns (insns), m_insns_size (SIZE) | |
508 | {} | |
509 | ||
510 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
511 | { | |
512 | SELF_CHECK (len == 4); | |
513 | SELF_CHECK (memaddr % 4 == 0); | |
514 | SELF_CHECK (memaddr / 4 < m_insns_size); | |
515 | ||
516 | return m_insns[memaddr / 4]; | |
517 | } | |
518 | ||
519 | private: | |
520 | const uint32_t *m_insns; | |
521 | size_t m_insns_size; | |
522 | }; | |
523 | ||
524 | static void | |
525 | aarch64_analyze_prologue_test (void) | |
526 | { | |
527 | struct gdbarch_info info; | |
528 | ||
529 | gdbarch_info_init (&info); | |
530 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
531 | ||
532 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
533 | SELF_CHECK (gdbarch != NULL); | |
534 | ||
535 | /* Test the simple prologue in which frame pointer is used. */ | |
536 | { | |
537 | struct aarch64_prologue_cache cache; | |
538 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
539 | ||
540 | static const uint32_t insns[] = { | |
541 | 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */ | |
542 | 0x910003fd, /* mov x29, sp */ | |
543 | 0x97ffffe6, /* bl 0x400580 */ | |
544 | }; | |
545 | instruction_reader_test reader (insns); | |
546 | ||
547 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
548 | SELF_CHECK (end == 4 * 2); | |
549 | ||
550 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
551 | SELF_CHECK (cache.framesize == 272); | |
552 | ||
553 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
554 | { | |
555 | if (i == AARCH64_FP_REGNUM) | |
556 | SELF_CHECK (cache.saved_regs[i].addr == -272); | |
557 | else if (i == AARCH64_LR_REGNUM) | |
558 | SELF_CHECK (cache.saved_regs[i].addr == -264); | |
559 | else | |
560 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
561 | } | |
562 | ||
563 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
564 | { | |
565 | int regnum = gdbarch_num_regs (gdbarch); | |
566 | ||
567 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
568 | == -1); | |
569 | } | |
570 | } | |
432ec081 YQ |
571 | |
572 | /* Test a prologue in which STR is used and frame pointer is not | |
573 | used. */ | |
574 | { | |
575 | struct aarch64_prologue_cache cache; | |
576 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
577 | ||
578 | static const uint32_t insns[] = { | |
579 | 0xf81d0ff3, /* str x19, [sp, #-48]! */ | |
580 | 0xb9002fe0, /* str w0, [sp, #44] */ | |
581 | 0xf90013e1, /* str x1, [sp, #32]*/ | |
582 | 0xfd000fe0, /* str d0, [sp, #24] */ | |
583 | 0xaa0203f3, /* mov x19, x2 */ | |
584 | 0xf94013e0, /* ldr x0, [sp, #32] */ | |
585 | }; | |
586 | instruction_reader_test reader (insns); | |
587 | ||
588 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
589 | ||
590 | SELF_CHECK (end == 4 * 5); | |
591 | ||
592 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
593 | SELF_CHECK (cache.framesize == 48); | |
594 | ||
595 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
596 | { | |
597 | if (i == 1) | |
598 | SELF_CHECK (cache.saved_regs[i].addr == -16); | |
599 | else if (i == 19) | |
600 | SELF_CHECK (cache.saved_regs[i].addr == -48); | |
601 | else | |
602 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
603 | } | |
604 | ||
605 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
606 | { | |
607 | int regnum = gdbarch_num_regs (gdbarch); | |
608 | ||
609 | if (i == 0) | |
610 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
611 | == -24); | |
612 | else | |
613 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
614 | == -1); | |
615 | } | |
616 | } | |
4d9a9006 YQ |
617 | } |
618 | } // namespace selftests | |
619 | #endif /* GDB_SELF_TEST */ | |
620 | ||
07b287a0 MS |
621 | /* Implement the "skip_prologue" gdbarch method. */ |
622 | ||
623 | static CORE_ADDR | |
624 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
625 | { | |
07b287a0 | 626 | CORE_ADDR func_addr, limit_pc; |
07b287a0 MS |
627 | |
628 | /* See if we can determine the end of the prologue via the symbol | |
629 | table. If so, then return either PC, or the PC after the | |
630 | prologue, whichever is greater. */ | |
631 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
632 | { | |
633 | CORE_ADDR post_prologue_pc | |
634 | = skip_prologue_using_sal (gdbarch, func_addr); | |
635 | ||
636 | if (post_prologue_pc != 0) | |
325fac50 | 637 | return std::max (pc, post_prologue_pc); |
07b287a0 MS |
638 | } |
639 | ||
640 | /* Can't determine prologue from the symbol table, need to examine | |
641 | instructions. */ | |
642 | ||
643 | /* Find an upper limit on the function prologue using the debug | |
644 | information. If the debug information could not be used to | |
645 | provide that bound, then use an arbitrary large number as the | |
646 | upper bound. */ | |
647 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
648 | if (limit_pc == 0) | |
649 | limit_pc = pc + 128; /* Magic. */ | |
650 | ||
651 | /* Try disassembling prologue. */ | |
652 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
653 | } | |
654 | ||
655 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
656 | cache CACHE. */ | |
657 | ||
658 | static void | |
659 | aarch64_scan_prologue (struct frame_info *this_frame, | |
660 | struct aarch64_prologue_cache *cache) | |
661 | { | |
662 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
663 | CORE_ADDR prologue_start; | |
664 | CORE_ADDR prologue_end; | |
665 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
666 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
667 | ||
db634143 PL |
668 | cache->prev_pc = prev_pc; |
669 | ||
07b287a0 MS |
670 | /* Assume we do not find a frame. */ |
671 | cache->framereg = -1; | |
672 | cache->framesize = 0; | |
673 | ||
674 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
675 | &prologue_end)) | |
676 | { | |
677 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
678 | ||
679 | if (sal.line == 0) | |
680 | { | |
681 | /* No line info so use the current PC. */ | |
682 | prologue_end = prev_pc; | |
683 | } | |
684 | else if (sal.end < prologue_end) | |
685 | { | |
686 | /* The next line begins after the function end. */ | |
687 | prologue_end = sal.end; | |
688 | } | |
689 | ||
325fac50 | 690 | prologue_end = std::min (prologue_end, prev_pc); |
07b287a0 MS |
691 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
692 | } | |
693 | else | |
694 | { | |
695 | CORE_ADDR frame_loc; | |
07b287a0 MS |
696 | |
697 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
698 | if (frame_loc == 0) | |
699 | return; | |
700 | ||
701 | cache->framereg = AARCH64_FP_REGNUM; | |
702 | cache->framesize = 16; | |
703 | cache->saved_regs[29].addr = 0; | |
704 | cache->saved_regs[30].addr = 8; | |
705 | } | |
706 | } | |
707 | ||
7dfa3edc PL |
708 | /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This |
709 | function may throw an exception if the inferior's registers or memory is | |
710 | not available. */ | |
07b287a0 | 711 | |
7dfa3edc PL |
712 | static void |
713 | aarch64_make_prologue_cache_1 (struct frame_info *this_frame, | |
714 | struct aarch64_prologue_cache *cache) | |
07b287a0 | 715 | { |
07b287a0 MS |
716 | CORE_ADDR unwound_fp; |
717 | int reg; | |
718 | ||
07b287a0 MS |
719 | aarch64_scan_prologue (this_frame, cache); |
720 | ||
721 | if (cache->framereg == -1) | |
7dfa3edc | 722 | return; |
07b287a0 MS |
723 | |
724 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
725 | if (unwound_fp == 0) | |
7dfa3edc | 726 | return; |
07b287a0 MS |
727 | |
728 | cache->prev_sp = unwound_fp + cache->framesize; | |
729 | ||
730 | /* Calculate actual addresses of saved registers using offsets | |
731 | determined by aarch64_analyze_prologue. */ | |
732 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
733 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
734 | cache->saved_regs[reg].addr += cache->prev_sp; | |
735 | ||
db634143 PL |
736 | cache->func = get_frame_func (this_frame); |
737 | ||
7dfa3edc PL |
738 | cache->available_p = 1; |
739 | } | |
740 | ||
741 | /* Allocate and fill in *THIS_CACHE with information about the prologue of | |
742 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
743 | Return a pointer to the current aarch64_prologue_cache in | |
744 | *THIS_CACHE. */ | |
745 | ||
746 | static struct aarch64_prologue_cache * | |
747 | aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache) | |
748 | { | |
749 | struct aarch64_prologue_cache *cache; | |
750 | ||
751 | if (*this_cache != NULL) | |
9a3c8263 | 752 | return (struct aarch64_prologue_cache *) *this_cache; |
7dfa3edc PL |
753 | |
754 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
755 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
756 | *this_cache = cache; | |
757 | ||
758 | TRY | |
759 | { | |
760 | aarch64_make_prologue_cache_1 (this_frame, cache); | |
761 | } | |
762 | CATCH (ex, RETURN_MASK_ERROR) | |
763 | { | |
764 | if (ex.error != NOT_AVAILABLE_ERROR) | |
765 | throw_exception (ex); | |
766 | } | |
767 | END_CATCH | |
768 | ||
07b287a0 MS |
769 | return cache; |
770 | } | |
771 | ||
7dfa3edc PL |
772 | /* Implement the "stop_reason" frame_unwind method. */ |
773 | ||
774 | static enum unwind_stop_reason | |
775 | aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
776 | void **this_cache) | |
777 | { | |
778 | struct aarch64_prologue_cache *cache | |
779 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
780 | ||
781 | if (!cache->available_p) | |
782 | return UNWIND_UNAVAILABLE; | |
783 | ||
784 | /* Halt the backtrace at "_start". */ | |
785 | if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
786 | return UNWIND_OUTERMOST; | |
787 | ||
788 | /* We've hit a wall, stop. */ | |
789 | if (cache->prev_sp == 0) | |
790 | return UNWIND_OUTERMOST; | |
791 | ||
792 | return UNWIND_NO_REASON; | |
793 | } | |
794 | ||
07b287a0 MS |
795 | /* Our frame ID for a normal frame is the current function's starting |
796 | PC and the caller's SP when we were called. */ | |
797 | ||
798 | static void | |
799 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
800 | void **this_cache, struct frame_id *this_id) | |
801 | { | |
7c8edfae PL |
802 | struct aarch64_prologue_cache *cache |
803 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 | 804 | |
7dfa3edc PL |
805 | if (!cache->available_p) |
806 | *this_id = frame_id_build_unavailable_stack (cache->func); | |
807 | else | |
808 | *this_id = frame_id_build (cache->prev_sp, cache->func); | |
07b287a0 MS |
809 | } |
810 | ||
811 | /* Implement the "prev_register" frame_unwind method. */ | |
812 | ||
813 | static struct value * | |
814 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
815 | void **this_cache, int prev_regnum) | |
816 | { | |
7c8edfae PL |
817 | struct aarch64_prologue_cache *cache |
818 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
819 | |
820 | /* If we are asked to unwind the PC, then we need to return the LR | |
821 | instead. The prologue may save PC, but it will point into this | |
822 | frame's prologue, not the next frame's resume location. */ | |
823 | if (prev_regnum == AARCH64_PC_REGNUM) | |
824 | { | |
825 | CORE_ADDR lr; | |
826 | ||
827 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
828 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); | |
829 | } | |
830 | ||
831 | /* SP is generally not saved to the stack, but this frame is | |
832 | identified by the next frame's stack pointer at the time of the | |
833 | call. The value was already reconstructed into PREV_SP. */ | |
834 | /* | |
835 | +----------+ ^ | |
836 | | saved lr | | | |
837 | +->| saved fp |--+ | |
838 | | | | | |
839 | | | | <- Previous SP | |
840 | | +----------+ | |
841 | | | saved lr | | |
842 | +--| saved fp |<- FP | |
843 | | | | |
844 | | |<- SP | |
845 | +----------+ */ | |
846 | if (prev_regnum == AARCH64_SP_REGNUM) | |
847 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
848 | cache->prev_sp); | |
849 | ||
850 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
851 | prev_regnum); | |
852 | } | |
853 | ||
854 | /* AArch64 prologue unwinder. */ | |
855 | struct frame_unwind aarch64_prologue_unwind = | |
856 | { | |
857 | NORMAL_FRAME, | |
7dfa3edc | 858 | aarch64_prologue_frame_unwind_stop_reason, |
07b287a0 MS |
859 | aarch64_prologue_this_id, |
860 | aarch64_prologue_prev_register, | |
861 | NULL, | |
862 | default_frame_sniffer | |
863 | }; | |
864 | ||
8b61f75d PL |
865 | /* Allocate and fill in *THIS_CACHE with information about the prologue of |
866 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
867 | Return a pointer to the current aarch64_prologue_cache in | |
868 | *THIS_CACHE. */ | |
07b287a0 MS |
869 | |
870 | static struct aarch64_prologue_cache * | |
8b61f75d | 871 | aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache) |
07b287a0 | 872 | { |
07b287a0 | 873 | struct aarch64_prologue_cache *cache; |
8b61f75d PL |
874 | |
875 | if (*this_cache != NULL) | |
9a3c8263 | 876 | return (struct aarch64_prologue_cache *) *this_cache; |
07b287a0 MS |
877 | |
878 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
879 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
8b61f75d | 880 | *this_cache = cache; |
07b287a0 | 881 | |
02a2a705 PL |
882 | TRY |
883 | { | |
884 | cache->prev_sp = get_frame_register_unsigned (this_frame, | |
885 | AARCH64_SP_REGNUM); | |
886 | cache->prev_pc = get_frame_pc (this_frame); | |
887 | cache->available_p = 1; | |
888 | } | |
889 | CATCH (ex, RETURN_MASK_ERROR) | |
890 | { | |
891 | if (ex.error != NOT_AVAILABLE_ERROR) | |
892 | throw_exception (ex); | |
893 | } | |
894 | END_CATCH | |
07b287a0 MS |
895 | |
896 | return cache; | |
897 | } | |
898 | ||
02a2a705 PL |
899 | /* Implement the "stop_reason" frame_unwind method. */ |
900 | ||
901 | static enum unwind_stop_reason | |
902 | aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame, | |
903 | void **this_cache) | |
904 | { | |
905 | struct aarch64_prologue_cache *cache | |
906 | = aarch64_make_stub_cache (this_frame, this_cache); | |
907 | ||
908 | if (!cache->available_p) | |
909 | return UNWIND_UNAVAILABLE; | |
910 | ||
911 | return UNWIND_NO_REASON; | |
912 | } | |
913 | ||
07b287a0 MS |
914 | /* Our frame ID for a stub frame is the current SP and LR. */ |
915 | ||
916 | static void | |
917 | aarch64_stub_this_id (struct frame_info *this_frame, | |
918 | void **this_cache, struct frame_id *this_id) | |
919 | { | |
8b61f75d PL |
920 | struct aarch64_prologue_cache *cache |
921 | = aarch64_make_stub_cache (this_frame, this_cache); | |
07b287a0 | 922 | |
02a2a705 PL |
923 | if (cache->available_p) |
924 | *this_id = frame_id_build (cache->prev_sp, cache->prev_pc); | |
925 | else | |
926 | *this_id = frame_id_build_unavailable_stack (cache->prev_pc); | |
07b287a0 MS |
927 | } |
928 | ||
929 | /* Implement the "sniffer" frame_unwind method. */ | |
930 | ||
931 | static int | |
932 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
933 | struct frame_info *this_frame, | |
934 | void **this_prologue_cache) | |
935 | { | |
936 | CORE_ADDR addr_in_block; | |
937 | gdb_byte dummy[4]; | |
938 | ||
939 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 940 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
941 | /* We also use the stub winder if the target memory is unreadable |
942 | to avoid having the prologue unwinder trying to read it. */ | |
943 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
944 | return 1; | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | /* AArch64 stub unwinder. */ | |
950 | struct frame_unwind aarch64_stub_unwind = | |
951 | { | |
952 | NORMAL_FRAME, | |
02a2a705 | 953 | aarch64_stub_frame_unwind_stop_reason, |
07b287a0 MS |
954 | aarch64_stub_this_id, |
955 | aarch64_prologue_prev_register, | |
956 | NULL, | |
957 | aarch64_stub_unwind_sniffer | |
958 | }; | |
959 | ||
960 | /* Return the frame base address of *THIS_FRAME. */ | |
961 | ||
962 | static CORE_ADDR | |
963 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
964 | { | |
7c8edfae PL |
965 | struct aarch64_prologue_cache *cache |
966 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
967 | |
968 | return cache->prev_sp - cache->framesize; | |
969 | } | |
970 | ||
971 | /* AArch64 default frame base information. */ | |
972 | struct frame_base aarch64_normal_base = | |
973 | { | |
974 | &aarch64_prologue_unwind, | |
975 | aarch64_normal_frame_base, | |
976 | aarch64_normal_frame_base, | |
977 | aarch64_normal_frame_base | |
978 | }; | |
979 | ||
980 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that | |
981 | dummy frame. The frame ID's base needs to match the TOS value | |
982 | saved by save_dummy_frame_tos () and returned from | |
983 | aarch64_push_dummy_call, and the PC needs to match the dummy | |
984 | frame's breakpoint. */ | |
985 | ||
986 | static struct frame_id | |
987 | aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
988 | { | |
989 | return frame_id_build (get_frame_register_unsigned (this_frame, | |
990 | AARCH64_SP_REGNUM), | |
991 | get_frame_pc (this_frame)); | |
992 | } | |
993 | ||
994 | /* Implement the "unwind_pc" gdbarch method. */ | |
995 | ||
996 | static CORE_ADDR | |
997 | aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
998 | { | |
999 | CORE_ADDR pc | |
1000 | = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM); | |
1001 | ||
1002 | return pc; | |
1003 | } | |
1004 | ||
1005 | /* Implement the "unwind_sp" gdbarch method. */ | |
1006 | ||
1007 | static CORE_ADDR | |
1008 | aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1009 | { | |
1010 | return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1011 | } | |
1012 | ||
1013 | /* Return the value of the REGNUM register in the previous frame of | |
1014 | *THIS_FRAME. */ | |
1015 | ||
1016 | static struct value * | |
1017 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1018 | void **this_cache, int regnum) | |
1019 | { | |
07b287a0 MS |
1020 | CORE_ADDR lr; |
1021 | ||
1022 | switch (regnum) | |
1023 | { | |
1024 | case AARCH64_PC_REGNUM: | |
1025 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1026 | return frame_unwind_got_constant (this_frame, regnum, lr); | |
1027 | ||
1028 | default: | |
1029 | internal_error (__FILE__, __LINE__, | |
1030 | _("Unexpected register %d"), regnum); | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | /* Implement the "init_reg" dwarf2_frame_ops method. */ | |
1035 | ||
1036 | static void | |
1037 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1038 | struct dwarf2_frame_state_reg *reg, | |
1039 | struct frame_info *this_frame) | |
1040 | { | |
1041 | switch (regnum) | |
1042 | { | |
1043 | case AARCH64_PC_REGNUM: | |
1044 | reg->how = DWARF2_FRAME_REG_FN; | |
1045 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
1046 | break; | |
1047 | case AARCH64_SP_REGNUM: | |
1048 | reg->how = DWARF2_FRAME_REG_CFA; | |
1049 | break; | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | /* When arguments must be pushed onto the stack, they go on in reverse | |
1054 | order. The code below implements a FILO (stack) to do this. */ | |
1055 | ||
1056 | typedef struct | |
1057 | { | |
c3c87445 YQ |
1058 | /* Value to pass on stack. It can be NULL if this item is for stack |
1059 | padding. */ | |
7c543f7b | 1060 | const gdb_byte *data; |
07b287a0 MS |
1061 | |
1062 | /* Size in bytes of value to pass on stack. */ | |
1063 | int len; | |
1064 | } stack_item_t; | |
1065 | ||
1066 | DEF_VEC_O (stack_item_t); | |
1067 | ||
1068 | /* Return the alignment (in bytes) of the given type. */ | |
1069 | ||
1070 | static int | |
1071 | aarch64_type_align (struct type *t) | |
1072 | { | |
1073 | int n; | |
1074 | int align; | |
1075 | int falign; | |
1076 | ||
1077 | t = check_typedef (t); | |
1078 | switch (TYPE_CODE (t)) | |
1079 | { | |
1080 | default: | |
1081 | /* Should never happen. */ | |
1082 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1083 | return 4; | |
1084 | ||
1085 | case TYPE_CODE_PTR: | |
1086 | case TYPE_CODE_ENUM: | |
1087 | case TYPE_CODE_INT: | |
1088 | case TYPE_CODE_FLT: | |
1089 | case TYPE_CODE_SET: | |
1090 | case TYPE_CODE_RANGE: | |
1091 | case TYPE_CODE_BITSTRING: | |
1092 | case TYPE_CODE_REF: | |
aa006118 | 1093 | case TYPE_CODE_RVALUE_REF: |
07b287a0 MS |
1094 | case TYPE_CODE_CHAR: |
1095 | case TYPE_CODE_BOOL: | |
1096 | return TYPE_LENGTH (t); | |
1097 | ||
1098 | case TYPE_CODE_ARRAY: | |
238f2452 YQ |
1099 | if (TYPE_VECTOR (t)) |
1100 | { | |
1101 | /* Use the natural alignment for vector types (the same for | |
1102 | scalar type), but the maximum alignment is 128-bit. */ | |
1103 | if (TYPE_LENGTH (t) > 16) | |
1104 | return 16; | |
1105 | else | |
1106 | return TYPE_LENGTH (t); | |
1107 | } | |
1108 | else | |
1109 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
07b287a0 MS |
1110 | case TYPE_CODE_COMPLEX: |
1111 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
1112 | ||
1113 | case TYPE_CODE_STRUCT: | |
1114 | case TYPE_CODE_UNION: | |
1115 | align = 1; | |
1116 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1117 | { | |
1118 | falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n)); | |
1119 | if (falign > align) | |
1120 | align = falign; | |
1121 | } | |
1122 | return align; | |
1123 | } | |
1124 | } | |
1125 | ||
cd635f74 YQ |
1126 | /* Return 1 if *TY is a homogeneous floating-point aggregate or |
1127 | homogeneous short-vector aggregate as defined in the AAPCS64 ABI | |
1128 | document; otherwise return 0. */ | |
07b287a0 MS |
1129 | |
1130 | static int | |
cd635f74 | 1131 | is_hfa_or_hva (struct type *ty) |
07b287a0 MS |
1132 | { |
1133 | switch (TYPE_CODE (ty)) | |
1134 | { | |
1135 | case TYPE_CODE_ARRAY: | |
1136 | { | |
1137 | struct type *target_ty = TYPE_TARGET_TYPE (ty); | |
238f2452 YQ |
1138 | |
1139 | if (TYPE_VECTOR (ty)) | |
1140 | return 0; | |
1141 | ||
cd635f74 YQ |
1142 | if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */ |
1143 | && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */ | |
1144 | || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */ | |
1145 | && TYPE_VECTOR (target_ty)))) | |
07b287a0 MS |
1146 | return 1; |
1147 | break; | |
1148 | } | |
1149 | ||
1150 | case TYPE_CODE_UNION: | |
1151 | case TYPE_CODE_STRUCT: | |
1152 | { | |
cd635f74 | 1153 | /* HFA or HVA has at most four members. */ |
07b287a0 MS |
1154 | if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4) |
1155 | { | |
1156 | struct type *member0_type; | |
1157 | ||
1158 | member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0)); | |
cd635f74 YQ |
1159 | if (TYPE_CODE (member0_type) == TYPE_CODE_FLT |
1160 | || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY | |
1161 | && TYPE_VECTOR (member0_type))) | |
07b287a0 MS |
1162 | { |
1163 | int i; | |
1164 | ||
1165 | for (i = 0; i < TYPE_NFIELDS (ty); i++) | |
1166 | { | |
1167 | struct type *member1_type; | |
1168 | ||
1169 | member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i)); | |
1170 | if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type) | |
1171 | || (TYPE_LENGTH (member0_type) | |
1172 | != TYPE_LENGTH (member1_type))) | |
1173 | return 0; | |
1174 | } | |
1175 | return 1; | |
1176 | } | |
1177 | } | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | default: | |
1182 | break; | |
1183 | } | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | /* AArch64 function call information structure. */ | |
1189 | struct aarch64_call_info | |
1190 | { | |
1191 | /* the current argument number. */ | |
1192 | unsigned argnum; | |
1193 | ||
1194 | /* The next general purpose register number, equivalent to NGRN as | |
1195 | described in the AArch64 Procedure Call Standard. */ | |
1196 | unsigned ngrn; | |
1197 | ||
1198 | /* The next SIMD and floating point register number, equivalent to | |
1199 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
1200 | unsigned nsrn; | |
1201 | ||
1202 | /* The next stacked argument address, equivalent to NSAA as | |
1203 | described in the AArch64 Procedure Call Standard. */ | |
1204 | unsigned nsaa; | |
1205 | ||
1206 | /* Stack item vector. */ | |
1207 | VEC(stack_item_t) *si; | |
1208 | }; | |
1209 | ||
1210 | /* Pass a value in a sequence of consecutive X registers. The caller | |
1211 | is responsbile for ensuring sufficient registers are available. */ | |
1212 | ||
1213 | static void | |
1214 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1215 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1216 | struct value *arg) |
07b287a0 MS |
1217 | { |
1218 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1219 | int len = TYPE_LENGTH (type); | |
1220 | enum type_code typecode = TYPE_CODE (type); | |
1221 | int regnum = AARCH64_X0_REGNUM + info->ngrn; | |
8e80f9d1 | 1222 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1223 | |
1224 | info->argnum++; | |
1225 | ||
1226 | while (len > 0) | |
1227 | { | |
1228 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1229 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1230 | byte_order); | |
1231 | ||
1232 | ||
1233 | /* Adjust sub-word struct/union args when big-endian. */ | |
1234 | if (byte_order == BFD_ENDIAN_BIG | |
1235 | && partial_len < X_REGISTER_SIZE | |
1236 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1237 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1238 | ||
1239 | if (aarch64_debug) | |
b277c936 PL |
1240 | { |
1241 | debug_printf ("arg %d in %s = 0x%s\n", info->argnum, | |
1242 | gdbarch_register_name (gdbarch, regnum), | |
1243 | phex (regval, X_REGISTER_SIZE)); | |
1244 | } | |
07b287a0 MS |
1245 | regcache_cooked_write_unsigned (regcache, regnum, regval); |
1246 | len -= partial_len; | |
1247 | buf += partial_len; | |
1248 | regnum++; | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | /* Attempt to marshall a value in a V register. Return 1 if | |
1253 | successful, or 0 if insufficient registers are available. This | |
1254 | function, unlike the equivalent pass_in_x() function does not | |
1255 | handle arguments spread across multiple registers. */ | |
1256 | ||
1257 | static int | |
1258 | pass_in_v (struct gdbarch *gdbarch, | |
1259 | struct regcache *regcache, | |
1260 | struct aarch64_call_info *info, | |
0735fddd | 1261 | int len, const bfd_byte *buf) |
07b287a0 MS |
1262 | { |
1263 | if (info->nsrn < 8) | |
1264 | { | |
07b287a0 | 1265 | int regnum = AARCH64_V0_REGNUM + info->nsrn; |
0735fddd | 1266 | gdb_byte reg[V_REGISTER_SIZE]; |
07b287a0 MS |
1267 | |
1268 | info->argnum++; | |
1269 | info->nsrn++; | |
1270 | ||
0735fddd YQ |
1271 | memset (reg, 0, sizeof (reg)); |
1272 | /* PCS C.1, the argument is allocated to the least significant | |
1273 | bits of V register. */ | |
1274 | memcpy (reg, buf, len); | |
1275 | regcache_cooked_write (regcache, regnum, reg); | |
1276 | ||
07b287a0 | 1277 | if (aarch64_debug) |
b277c936 PL |
1278 | { |
1279 | debug_printf ("arg %d in %s\n", info->argnum, | |
1280 | gdbarch_register_name (gdbarch, regnum)); | |
1281 | } | |
07b287a0 MS |
1282 | return 1; |
1283 | } | |
1284 | info->nsrn = 8; | |
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | /* Marshall an argument onto the stack. */ | |
1289 | ||
1290 | static void | |
1291 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1292 | struct value *arg) |
07b287a0 | 1293 | { |
8e80f9d1 | 1294 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1295 | int len = TYPE_LENGTH (type); |
1296 | int align; | |
1297 | stack_item_t item; | |
1298 | ||
1299 | info->argnum++; | |
1300 | ||
1301 | align = aarch64_type_align (type); | |
1302 | ||
1303 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1304 | Natural alignment of the argument's type. */ | |
1305 | align = align_up (align, 8); | |
1306 | ||
1307 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1308 | if (align > 16) | |
1309 | align = 16; | |
1310 | ||
1311 | if (aarch64_debug) | |
b277c936 PL |
1312 | { |
1313 | debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len, | |
1314 | info->nsaa); | |
1315 | } | |
07b287a0 MS |
1316 | |
1317 | item.len = len; | |
1318 | item.data = buf; | |
1319 | VEC_safe_push (stack_item_t, info->si, &item); | |
1320 | ||
1321 | info->nsaa += len; | |
1322 | if (info->nsaa & (align - 1)) | |
1323 | { | |
1324 | /* Push stack alignment padding. */ | |
1325 | int pad = align - (info->nsaa & (align - 1)); | |
1326 | ||
1327 | item.len = pad; | |
c3c87445 | 1328 | item.data = NULL; |
07b287a0 MS |
1329 | |
1330 | VEC_safe_push (stack_item_t, info->si, &item); | |
1331 | info->nsaa += pad; | |
1332 | } | |
1333 | } | |
1334 | ||
1335 | /* Marshall an argument into a sequence of one or more consecutive X | |
1336 | registers or, if insufficient X registers are available then onto | |
1337 | the stack. */ | |
1338 | ||
1339 | static void | |
1340 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1341 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1342 | struct value *arg) |
07b287a0 MS |
1343 | { |
1344 | int len = TYPE_LENGTH (type); | |
1345 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1346 | ||
1347 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1348 | if (info->ngrn + nregs <= 8) | |
1349 | { | |
8e80f9d1 | 1350 | pass_in_x (gdbarch, regcache, info, type, arg); |
07b287a0 MS |
1351 | info->ngrn += nregs; |
1352 | } | |
1353 | else | |
1354 | { | |
1355 | info->ngrn = 8; | |
8e80f9d1 | 1356 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1357 | } |
1358 | } | |
1359 | ||
1360 | /* Pass a value in a V register, or on the stack if insufficient are | |
1361 | available. */ | |
1362 | ||
1363 | static void | |
1364 | pass_in_v_or_stack (struct gdbarch *gdbarch, | |
1365 | struct regcache *regcache, | |
1366 | struct aarch64_call_info *info, | |
1367 | struct type *type, | |
8e80f9d1 | 1368 | struct value *arg) |
07b287a0 | 1369 | { |
0735fddd YQ |
1370 | if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type), |
1371 | value_contents (arg))) | |
8e80f9d1 | 1372 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1373 | } |
1374 | ||
1375 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1376 | ||
1377 | static CORE_ADDR | |
1378 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1379 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1380 | int nargs, | |
1381 | struct value **args, CORE_ADDR sp, int struct_return, | |
1382 | CORE_ADDR struct_addr) | |
1383 | { | |
07b287a0 | 1384 | int argnum; |
07b287a0 MS |
1385 | struct aarch64_call_info info; |
1386 | struct type *func_type; | |
1387 | struct type *return_type; | |
1388 | int lang_struct_return; | |
1389 | ||
1390 | memset (&info, 0, sizeof (info)); | |
1391 | ||
1392 | /* We need to know what the type of the called function is in order | |
1393 | to determine the number of named/anonymous arguments for the | |
1394 | actual argument placement, and the return type in order to handle | |
1395 | return value correctly. | |
1396 | ||
1397 | The generic code above us views the decision of return in memory | |
1398 | or return in registers as a two stage processes. The language | |
1399 | handler is consulted first and may decide to return in memory (eg | |
1400 | class with copy constructor returned by value), this will cause | |
1401 | the generic code to allocate space AND insert an initial leading | |
1402 | argument. | |
1403 | ||
1404 | If the language code does not decide to pass in memory then the | |
1405 | target code is consulted. | |
1406 | ||
1407 | If the language code decides to pass in memory we want to move | |
1408 | the pointer inserted as the initial argument from the argument | |
1409 | list and into X8, the conventional AArch64 struct return pointer | |
1410 | register. | |
1411 | ||
1412 | This is slightly awkward, ideally the flag "lang_struct_return" | |
1413 | would be passed to the targets implementation of push_dummy_call. | |
1414 | Rather that change the target interface we call the language code | |
1415 | directly ourselves. */ | |
1416 | ||
1417 | func_type = check_typedef (value_type (function)); | |
1418 | ||
1419 | /* Dereference function pointer types. */ | |
1420 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
1421 | func_type = TYPE_TARGET_TYPE (func_type); | |
1422 | ||
1423 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
1424 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
1425 | ||
1426 | /* If language_pass_by_reference () returned true we will have been | |
1427 | given an additional initial argument, a hidden pointer to the | |
1428 | return slot in memory. */ | |
1429 | return_type = TYPE_TARGET_TYPE (func_type); | |
1430 | lang_struct_return = language_pass_by_reference (return_type); | |
1431 | ||
1432 | /* Set the return address. For the AArch64, the return breakpoint | |
1433 | is always at BP_ADDR. */ | |
1434 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1435 | ||
1436 | /* If we were given an initial argument for the return slot because | |
1437 | lang_struct_return was true, lose it. */ | |
1438 | if (lang_struct_return) | |
1439 | { | |
1440 | args++; | |
1441 | nargs--; | |
1442 | } | |
1443 | ||
1444 | /* The struct_return pointer occupies X8. */ | |
1445 | if (struct_return || lang_struct_return) | |
1446 | { | |
1447 | if (aarch64_debug) | |
b277c936 PL |
1448 | { |
1449 | debug_printf ("struct return in %s = 0x%s\n", | |
1450 | gdbarch_register_name (gdbarch, | |
1451 | AARCH64_STRUCT_RETURN_REGNUM), | |
1452 | paddress (gdbarch, struct_addr)); | |
1453 | } | |
07b287a0 MS |
1454 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, |
1455 | struct_addr); | |
1456 | } | |
1457 | ||
1458 | for (argnum = 0; argnum < nargs; argnum++) | |
1459 | { | |
1460 | struct value *arg = args[argnum]; | |
1461 | struct type *arg_type; | |
1462 | int len; | |
1463 | ||
1464 | arg_type = check_typedef (value_type (arg)); | |
1465 | len = TYPE_LENGTH (arg_type); | |
1466 | ||
1467 | switch (TYPE_CODE (arg_type)) | |
1468 | { | |
1469 | case TYPE_CODE_INT: | |
1470 | case TYPE_CODE_BOOL: | |
1471 | case TYPE_CODE_CHAR: | |
1472 | case TYPE_CODE_RANGE: | |
1473 | case TYPE_CODE_ENUM: | |
1474 | if (len < 4) | |
1475 | { | |
1476 | /* Promote to 32 bit integer. */ | |
1477 | if (TYPE_UNSIGNED (arg_type)) | |
1478 | arg_type = builtin_type (gdbarch)->builtin_uint32; | |
1479 | else | |
1480 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1481 | arg = value_cast (arg_type, arg); | |
1482 | } | |
8e80f9d1 | 1483 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1484 | break; |
1485 | ||
1486 | case TYPE_CODE_COMPLEX: | |
1487 | if (info.nsrn <= 6) | |
1488 | { | |
1489 | const bfd_byte *buf = value_contents (arg); | |
1490 | struct type *target_type = | |
1491 | check_typedef (TYPE_TARGET_TYPE (arg_type)); | |
1492 | ||
07b287a0 | 1493 | pass_in_v (gdbarch, regcache, &info, |
0735fddd YQ |
1494 | TYPE_LENGTH (target_type), buf); |
1495 | pass_in_v (gdbarch, regcache, &info, | |
1496 | TYPE_LENGTH (target_type), | |
07b287a0 MS |
1497 | buf + TYPE_LENGTH (target_type)); |
1498 | } | |
1499 | else | |
1500 | { | |
1501 | info.nsrn = 8; | |
8e80f9d1 | 1502 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1503 | } |
1504 | break; | |
1505 | case TYPE_CODE_FLT: | |
8e80f9d1 | 1506 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1507 | break; |
1508 | ||
1509 | case TYPE_CODE_STRUCT: | |
1510 | case TYPE_CODE_ARRAY: | |
1511 | case TYPE_CODE_UNION: | |
cd635f74 | 1512 | if (is_hfa_or_hva (arg_type)) |
07b287a0 MS |
1513 | { |
1514 | int elements = TYPE_NFIELDS (arg_type); | |
1515 | ||
1516 | /* Homogeneous Aggregates */ | |
1517 | if (info.nsrn + elements < 8) | |
1518 | { | |
1519 | int i; | |
1520 | ||
1521 | for (i = 0; i < elements; i++) | |
1522 | { | |
1523 | /* We know that we have sufficient registers | |
1524 | available therefore this will never fallback | |
1525 | to the stack. */ | |
1526 | struct value *field = | |
1527 | value_primitive_field (arg, 0, i, arg_type); | |
1528 | struct type *field_type = | |
1529 | check_typedef (value_type (field)); | |
1530 | ||
8e80f9d1 YQ |
1531 | pass_in_v_or_stack (gdbarch, regcache, &info, |
1532 | field_type, field); | |
07b287a0 MS |
1533 | } |
1534 | } | |
1535 | else | |
1536 | { | |
1537 | info.nsrn = 8; | |
8e80f9d1 | 1538 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1539 | } |
1540 | } | |
238f2452 YQ |
1541 | else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY |
1542 | && TYPE_VECTOR (arg_type) && (len == 16 || len == 8)) | |
1543 | { | |
1544 | /* Short vector types are passed in V registers. */ | |
1545 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); | |
1546 | } | |
07b287a0 MS |
1547 | else if (len > 16) |
1548 | { | |
1549 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1550 | invisible reference. */ | |
1551 | ||
1552 | /* Allocate aligned storage. */ | |
1553 | sp = align_down (sp - len, 16); | |
1554 | ||
1555 | /* Write the real data into the stack. */ | |
1556 | write_memory (sp, value_contents (arg), len); | |
1557 | ||
1558 | /* Construct the indirection. */ | |
1559 | arg_type = lookup_pointer_type (arg_type); | |
1560 | arg = value_from_pointer (arg_type, sp); | |
8e80f9d1 | 1561 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1562 | } |
1563 | else | |
1564 | /* PCS C.15 / C.18 multiple values pass. */ | |
8e80f9d1 | 1565 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1566 | break; |
1567 | ||
1568 | default: | |
8e80f9d1 | 1569 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1570 | break; |
1571 | } | |
1572 | } | |
1573 | ||
1574 | /* Make sure stack retains 16 byte alignment. */ | |
1575 | if (info.nsaa & 15) | |
1576 | sp -= 16 - (info.nsaa & 15); | |
1577 | ||
1578 | while (!VEC_empty (stack_item_t, info.si)) | |
1579 | { | |
1580 | stack_item_t *si = VEC_last (stack_item_t, info.si); | |
1581 | ||
1582 | sp -= si->len; | |
c3c87445 YQ |
1583 | if (si->data != NULL) |
1584 | write_memory (sp, si->data, si->len); | |
07b287a0 MS |
1585 | VEC_pop (stack_item_t, info.si); |
1586 | } | |
1587 | ||
1588 | VEC_free (stack_item_t, info.si); | |
1589 | ||
1590 | /* Finally, update the SP register. */ | |
1591 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1592 | ||
1593 | return sp; | |
1594 | } | |
1595 | ||
1596 | /* Implement the "frame_align" gdbarch method. */ | |
1597 | ||
1598 | static CORE_ADDR | |
1599 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1600 | { | |
1601 | /* Align the stack to sixteen bytes. */ | |
1602 | return sp & ~(CORE_ADDR) 15; | |
1603 | } | |
1604 | ||
1605 | /* Return the type for an AdvSISD Q register. */ | |
1606 | ||
1607 | static struct type * | |
1608 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
1609 | { | |
1610 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1611 | ||
1612 | if (tdep->vnq_type == NULL) | |
1613 | { | |
1614 | struct type *t; | |
1615 | struct type *elem; | |
1616 | ||
1617 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
1618 | TYPE_CODE_UNION); | |
1619 | ||
1620 | elem = builtin_type (gdbarch)->builtin_uint128; | |
1621 | append_composite_type_field (t, "u", elem); | |
1622 | ||
1623 | elem = builtin_type (gdbarch)->builtin_int128; | |
1624 | append_composite_type_field (t, "s", elem); | |
1625 | ||
1626 | tdep->vnq_type = t; | |
1627 | } | |
1628 | ||
1629 | return tdep->vnq_type; | |
1630 | } | |
1631 | ||
1632 | /* Return the type for an AdvSISD D register. */ | |
1633 | ||
1634 | static struct type * | |
1635 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
1636 | { | |
1637 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1638 | ||
1639 | if (tdep->vnd_type == NULL) | |
1640 | { | |
1641 | struct type *t; | |
1642 | struct type *elem; | |
1643 | ||
1644 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
1645 | TYPE_CODE_UNION); | |
1646 | ||
1647 | elem = builtin_type (gdbarch)->builtin_double; | |
1648 | append_composite_type_field (t, "f", elem); | |
1649 | ||
1650 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1651 | append_composite_type_field (t, "u", elem); | |
1652 | ||
1653 | elem = builtin_type (gdbarch)->builtin_int64; | |
1654 | append_composite_type_field (t, "s", elem); | |
1655 | ||
1656 | tdep->vnd_type = t; | |
1657 | } | |
1658 | ||
1659 | return tdep->vnd_type; | |
1660 | } | |
1661 | ||
1662 | /* Return the type for an AdvSISD S register. */ | |
1663 | ||
1664 | static struct type * | |
1665 | aarch64_vns_type (struct gdbarch *gdbarch) | |
1666 | { | |
1667 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1668 | ||
1669 | if (tdep->vns_type == NULL) | |
1670 | { | |
1671 | struct type *t; | |
1672 | struct type *elem; | |
1673 | ||
1674 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
1675 | TYPE_CODE_UNION); | |
1676 | ||
1677 | elem = builtin_type (gdbarch)->builtin_float; | |
1678 | append_composite_type_field (t, "f", elem); | |
1679 | ||
1680 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1681 | append_composite_type_field (t, "u", elem); | |
1682 | ||
1683 | elem = builtin_type (gdbarch)->builtin_int32; | |
1684 | append_composite_type_field (t, "s", elem); | |
1685 | ||
1686 | tdep->vns_type = t; | |
1687 | } | |
1688 | ||
1689 | return tdep->vns_type; | |
1690 | } | |
1691 | ||
1692 | /* Return the type for an AdvSISD H register. */ | |
1693 | ||
1694 | static struct type * | |
1695 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
1696 | { | |
1697 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1698 | ||
1699 | if (tdep->vnh_type == NULL) | |
1700 | { | |
1701 | struct type *t; | |
1702 | struct type *elem; | |
1703 | ||
1704 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
1705 | TYPE_CODE_UNION); | |
1706 | ||
1707 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1708 | append_composite_type_field (t, "u", elem); | |
1709 | ||
1710 | elem = builtin_type (gdbarch)->builtin_int16; | |
1711 | append_composite_type_field (t, "s", elem); | |
1712 | ||
1713 | tdep->vnh_type = t; | |
1714 | } | |
1715 | ||
1716 | return tdep->vnh_type; | |
1717 | } | |
1718 | ||
1719 | /* Return the type for an AdvSISD B register. */ | |
1720 | ||
1721 | static struct type * | |
1722 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
1723 | { | |
1724 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1725 | ||
1726 | if (tdep->vnb_type == NULL) | |
1727 | { | |
1728 | struct type *t; | |
1729 | struct type *elem; | |
1730 | ||
1731 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
1732 | TYPE_CODE_UNION); | |
1733 | ||
1734 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1735 | append_composite_type_field (t, "u", elem); | |
1736 | ||
1737 | elem = builtin_type (gdbarch)->builtin_int8; | |
1738 | append_composite_type_field (t, "s", elem); | |
1739 | ||
1740 | tdep->vnb_type = t; | |
1741 | } | |
1742 | ||
1743 | return tdep->vnb_type; | |
1744 | } | |
1745 | ||
1746 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ | |
1747 | ||
1748 | static int | |
1749 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1750 | { | |
1751 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) | |
1752 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
1753 | ||
1754 | if (reg == AARCH64_DWARF_SP) | |
1755 | return AARCH64_SP_REGNUM; | |
1756 | ||
1757 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) | |
1758 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
1759 | ||
1760 | return -1; | |
1761 | } | |
1762 | \f | |
1763 | ||
1764 | /* Implement the "print_insn" gdbarch method. */ | |
1765 | ||
1766 | static int | |
1767 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
1768 | { | |
1769 | info->symbols = NULL; | |
6394c606 | 1770 | return default_print_insn (memaddr, info); |
07b287a0 MS |
1771 | } |
1772 | ||
1773 | /* AArch64 BRK software debug mode instruction. | |
1774 | Note that AArch64 code is always little-endian. | |
1775 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
04180708 | 1776 | constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 | 1777 | |
04180708 | 1778 | typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint; |
07b287a0 MS |
1779 | |
1780 | /* Extract from an array REGS containing the (raw) register state a | |
1781 | function return value of type TYPE, and copy that, in virtual | |
1782 | format, into VALBUF. */ | |
1783 | ||
1784 | static void | |
1785 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
1786 | gdb_byte *valbuf) | |
1787 | { | |
ac7936df | 1788 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 MS |
1789 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1790 | ||
1791 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1792 | { | |
1793 | bfd_byte buf[V_REGISTER_SIZE]; | |
1794 | int len = TYPE_LENGTH (type); | |
1795 | ||
1796 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1797 | memcpy (valbuf, buf, len); | |
1798 | } | |
1799 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1800 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1801 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1802 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 1803 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
1804 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
1805 | { | |
1806 | /* If the the type is a plain integer, then the access is | |
1807 | straight-forward. Otherwise we have to play around a bit | |
1808 | more. */ | |
1809 | int len = TYPE_LENGTH (type); | |
1810 | int regno = AARCH64_X0_REGNUM; | |
1811 | ULONGEST tmp; | |
1812 | ||
1813 | while (len > 0) | |
1814 | { | |
1815 | /* By using store_unsigned_integer we avoid having to do | |
1816 | anything special for small big-endian values. */ | |
1817 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
1818 | store_unsigned_integer (valbuf, | |
1819 | (len > X_REGISTER_SIZE | |
1820 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
1821 | len -= X_REGISTER_SIZE; | |
1822 | valbuf += X_REGISTER_SIZE; | |
1823 | } | |
1824 | } | |
1825 | else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX) | |
1826 | { | |
1827 | int regno = AARCH64_V0_REGNUM; | |
1828 | bfd_byte buf[V_REGISTER_SIZE]; | |
1829 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1830 | int len = TYPE_LENGTH (target_type); | |
1831 | ||
1832 | regcache_cooked_read (regs, regno, buf); | |
1833 | memcpy (valbuf, buf, len); | |
1834 | valbuf += len; | |
1835 | regcache_cooked_read (regs, regno + 1, buf); | |
1836 | memcpy (valbuf, buf, len); | |
1837 | valbuf += len; | |
1838 | } | |
cd635f74 | 1839 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
1840 | { |
1841 | int elements = TYPE_NFIELDS (type); | |
1842 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1843 | int len = TYPE_LENGTH (member_type); | |
1844 | int i; | |
1845 | ||
1846 | for (i = 0; i < elements; i++) | |
1847 | { | |
1848 | int regno = AARCH64_V0_REGNUM + i; | |
db3516bb | 1849 | bfd_byte buf[V_REGISTER_SIZE]; |
07b287a0 MS |
1850 | |
1851 | if (aarch64_debug) | |
b277c936 | 1852 | { |
cd635f74 | 1853 | debug_printf ("read HFA or HVA return value element %d from %s\n", |
b277c936 PL |
1854 | i + 1, |
1855 | gdbarch_register_name (gdbarch, regno)); | |
1856 | } | |
07b287a0 MS |
1857 | regcache_cooked_read (regs, regno, buf); |
1858 | ||
1859 | memcpy (valbuf, buf, len); | |
1860 | valbuf += len; | |
1861 | } | |
1862 | } | |
238f2452 YQ |
1863 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
1864 | && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8)) | |
1865 | { | |
1866 | /* Short vector is returned in V register. */ | |
1867 | gdb_byte buf[V_REGISTER_SIZE]; | |
1868 | ||
1869 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1870 | memcpy (valbuf, buf, TYPE_LENGTH (type)); | |
1871 | } | |
07b287a0 MS |
1872 | else |
1873 | { | |
1874 | /* For a structure or union the behaviour is as if the value had | |
1875 | been stored to word-aligned memory and then loaded into | |
1876 | registers with 64-bit load instruction(s). */ | |
1877 | int len = TYPE_LENGTH (type); | |
1878 | int regno = AARCH64_X0_REGNUM; | |
1879 | bfd_byte buf[X_REGISTER_SIZE]; | |
1880 | ||
1881 | while (len > 0) | |
1882 | { | |
1883 | regcache_cooked_read (regs, regno++, buf); | |
1884 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
1885 | len -= X_REGISTER_SIZE; | |
1886 | valbuf += X_REGISTER_SIZE; | |
1887 | } | |
1888 | } | |
1889 | } | |
1890 | ||
1891 | ||
1892 | /* Will a function return an aggregate type in memory or in a | |
1893 | register? Return 0 if an aggregate type can be returned in a | |
1894 | register, 1 if it must be returned in memory. */ | |
1895 | ||
1896 | static int | |
1897 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
1898 | { | |
f168693b | 1899 | type = check_typedef (type); |
07b287a0 | 1900 | |
cd635f74 | 1901 | if (is_hfa_or_hva (type)) |
07b287a0 | 1902 | { |
cd635f74 YQ |
1903 | /* v0-v7 are used to return values and one register is allocated |
1904 | for one member. However, HFA or HVA has at most four members. */ | |
07b287a0 MS |
1905 | return 0; |
1906 | } | |
1907 | ||
1908 | if (TYPE_LENGTH (type) > 16) | |
1909 | { | |
1910 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
1911 | invisible reference. */ | |
1912 | ||
1913 | return 1; | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | /* Write into appropriate registers a function return value of type | |
1920 | TYPE, given in virtual format. */ | |
1921 | ||
1922 | static void | |
1923 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
1924 | const gdb_byte *valbuf) | |
1925 | { | |
ac7936df | 1926 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 MS |
1927 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1928 | ||
1929 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1930 | { | |
1931 | bfd_byte buf[V_REGISTER_SIZE]; | |
1932 | int len = TYPE_LENGTH (type); | |
1933 | ||
1934 | memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
1935 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
1936 | } | |
1937 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1938 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1939 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1940 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 1941 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
1942 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
1943 | { | |
1944 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
1945 | { | |
1946 | /* Values of one word or less are zero/sign-extended and | |
1947 | returned in r0. */ | |
1948 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
1949 | LONGEST val = unpack_long (type, valbuf); | |
1950 | ||
1951 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
1952 | regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf); | |
1953 | } | |
1954 | else | |
1955 | { | |
1956 | /* Integral values greater than one word are stored in | |
1957 | consecutive registers starting with r0. This will always | |
1958 | be a multiple of the regiser size. */ | |
1959 | int len = TYPE_LENGTH (type); | |
1960 | int regno = AARCH64_X0_REGNUM; | |
1961 | ||
1962 | while (len > 0) | |
1963 | { | |
1964 | regcache_cooked_write (regs, regno++, valbuf); | |
1965 | len -= X_REGISTER_SIZE; | |
1966 | valbuf += X_REGISTER_SIZE; | |
1967 | } | |
1968 | } | |
1969 | } | |
cd635f74 | 1970 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
1971 | { |
1972 | int elements = TYPE_NFIELDS (type); | |
1973 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1974 | int len = TYPE_LENGTH (member_type); | |
1975 | int i; | |
1976 | ||
1977 | for (i = 0; i < elements; i++) | |
1978 | { | |
1979 | int regno = AARCH64_V0_REGNUM + i; | |
d1be909e | 1980 | bfd_byte tmpbuf[V_REGISTER_SIZE]; |
07b287a0 MS |
1981 | |
1982 | if (aarch64_debug) | |
b277c936 | 1983 | { |
cd635f74 | 1984 | debug_printf ("write HFA or HVA return value element %d to %s\n", |
b277c936 PL |
1985 | i + 1, |
1986 | gdbarch_register_name (gdbarch, regno)); | |
1987 | } | |
07b287a0 MS |
1988 | |
1989 | memcpy (tmpbuf, valbuf, len); | |
1990 | regcache_cooked_write (regs, regno, tmpbuf); | |
1991 | valbuf += len; | |
1992 | } | |
1993 | } | |
238f2452 YQ |
1994 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
1995 | && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16)) | |
1996 | { | |
1997 | /* Short vector. */ | |
1998 | gdb_byte buf[V_REGISTER_SIZE]; | |
1999 | ||
2000 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
2001 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
2002 | } | |
07b287a0 MS |
2003 | else |
2004 | { | |
2005 | /* For a structure or union the behaviour is as if the value had | |
2006 | been stored to word-aligned memory and then loaded into | |
2007 | registers with 64-bit load instruction(s). */ | |
2008 | int len = TYPE_LENGTH (type); | |
2009 | int regno = AARCH64_X0_REGNUM; | |
2010 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2011 | ||
2012 | while (len > 0) | |
2013 | { | |
2014 | memcpy (tmpbuf, valbuf, | |
2015 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2016 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2017 | len -= X_REGISTER_SIZE; | |
2018 | valbuf += X_REGISTER_SIZE; | |
2019 | } | |
2020 | } | |
2021 | } | |
2022 | ||
2023 | /* Implement the "return_value" gdbarch method. */ | |
2024 | ||
2025 | static enum return_value_convention | |
2026 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2027 | struct type *valtype, struct regcache *regcache, | |
2028 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2029 | { | |
07b287a0 MS |
2030 | |
2031 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2032 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2033 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2034 | { | |
2035 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2036 | { | |
2037 | if (aarch64_debug) | |
b277c936 | 2038 | debug_printf ("return value in memory\n"); |
07b287a0 MS |
2039 | return RETURN_VALUE_STRUCT_CONVENTION; |
2040 | } | |
2041 | } | |
2042 | ||
2043 | if (writebuf) | |
2044 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2045 | ||
2046 | if (readbuf) | |
2047 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2048 | ||
2049 | if (aarch64_debug) | |
b277c936 | 2050 | debug_printf ("return value in registers\n"); |
07b287a0 MS |
2051 | |
2052 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2053 | } | |
2054 | ||
2055 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2056 | ||
2057 | static int | |
2058 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2059 | { | |
2060 | CORE_ADDR jb_addr; | |
2061 | gdb_byte buf[X_REGISTER_SIZE]; | |
2062 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2063 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2064 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2065 | ||
2066 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2067 | ||
2068 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2069 | X_REGISTER_SIZE)) | |
2070 | return 0; | |
2071 | ||
2072 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2073 | return 1; | |
2074 | } | |
ea873d8e PL |
2075 | |
2076 | /* Implement the "gen_return_address" gdbarch method. */ | |
2077 | ||
2078 | static void | |
2079 | aarch64_gen_return_address (struct gdbarch *gdbarch, | |
2080 | struct agent_expr *ax, struct axs_value *value, | |
2081 | CORE_ADDR scope) | |
2082 | { | |
2083 | value->type = register_type (gdbarch, AARCH64_LR_REGNUM); | |
2084 | value->kind = axs_lvalue_register; | |
2085 | value->u.reg = AARCH64_LR_REGNUM; | |
2086 | } | |
07b287a0 MS |
2087 | \f |
2088 | ||
2089 | /* Return the pseudo register name corresponding to register regnum. */ | |
2090 | ||
2091 | static const char * | |
2092 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2093 | { | |
2094 | static const char *const q_name[] = | |
2095 | { | |
2096 | "q0", "q1", "q2", "q3", | |
2097 | "q4", "q5", "q6", "q7", | |
2098 | "q8", "q9", "q10", "q11", | |
2099 | "q12", "q13", "q14", "q15", | |
2100 | "q16", "q17", "q18", "q19", | |
2101 | "q20", "q21", "q22", "q23", | |
2102 | "q24", "q25", "q26", "q27", | |
2103 | "q28", "q29", "q30", "q31", | |
2104 | }; | |
2105 | ||
2106 | static const char *const d_name[] = | |
2107 | { | |
2108 | "d0", "d1", "d2", "d3", | |
2109 | "d4", "d5", "d6", "d7", | |
2110 | "d8", "d9", "d10", "d11", | |
2111 | "d12", "d13", "d14", "d15", | |
2112 | "d16", "d17", "d18", "d19", | |
2113 | "d20", "d21", "d22", "d23", | |
2114 | "d24", "d25", "d26", "d27", | |
2115 | "d28", "d29", "d30", "d31", | |
2116 | }; | |
2117 | ||
2118 | static const char *const s_name[] = | |
2119 | { | |
2120 | "s0", "s1", "s2", "s3", | |
2121 | "s4", "s5", "s6", "s7", | |
2122 | "s8", "s9", "s10", "s11", | |
2123 | "s12", "s13", "s14", "s15", | |
2124 | "s16", "s17", "s18", "s19", | |
2125 | "s20", "s21", "s22", "s23", | |
2126 | "s24", "s25", "s26", "s27", | |
2127 | "s28", "s29", "s30", "s31", | |
2128 | }; | |
2129 | ||
2130 | static const char *const h_name[] = | |
2131 | { | |
2132 | "h0", "h1", "h2", "h3", | |
2133 | "h4", "h5", "h6", "h7", | |
2134 | "h8", "h9", "h10", "h11", | |
2135 | "h12", "h13", "h14", "h15", | |
2136 | "h16", "h17", "h18", "h19", | |
2137 | "h20", "h21", "h22", "h23", | |
2138 | "h24", "h25", "h26", "h27", | |
2139 | "h28", "h29", "h30", "h31", | |
2140 | }; | |
2141 | ||
2142 | static const char *const b_name[] = | |
2143 | { | |
2144 | "b0", "b1", "b2", "b3", | |
2145 | "b4", "b5", "b6", "b7", | |
2146 | "b8", "b9", "b10", "b11", | |
2147 | "b12", "b13", "b14", "b15", | |
2148 | "b16", "b17", "b18", "b19", | |
2149 | "b20", "b21", "b22", "b23", | |
2150 | "b24", "b25", "b26", "b27", | |
2151 | "b28", "b29", "b30", "b31", | |
2152 | }; | |
2153 | ||
2154 | regnum -= gdbarch_num_regs (gdbarch); | |
2155 | ||
2156 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2157 | return q_name[regnum - AARCH64_Q0_REGNUM]; | |
2158 | ||
2159 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2160 | return d_name[regnum - AARCH64_D0_REGNUM]; | |
2161 | ||
2162 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2163 | return s_name[regnum - AARCH64_S0_REGNUM]; | |
2164 | ||
2165 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2166 | return h_name[regnum - AARCH64_H0_REGNUM]; | |
2167 | ||
2168 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2169 | return b_name[regnum - AARCH64_B0_REGNUM]; | |
2170 | ||
2171 | internal_error (__FILE__, __LINE__, | |
2172 | _("aarch64_pseudo_register_name: bad register number %d"), | |
2173 | regnum); | |
2174 | } | |
2175 | ||
2176 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2177 | ||
2178 | static struct type * | |
2179 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2180 | { | |
2181 | regnum -= gdbarch_num_regs (gdbarch); | |
2182 | ||
2183 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2184 | return aarch64_vnq_type (gdbarch); | |
2185 | ||
2186 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2187 | return aarch64_vnd_type (gdbarch); | |
2188 | ||
2189 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2190 | return aarch64_vns_type (gdbarch); | |
2191 | ||
2192 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2193 | return aarch64_vnh_type (gdbarch); | |
2194 | ||
2195 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2196 | return aarch64_vnb_type (gdbarch); | |
2197 | ||
2198 | internal_error (__FILE__, __LINE__, | |
2199 | _("aarch64_pseudo_register_type: bad register number %d"), | |
2200 | regnum); | |
2201 | } | |
2202 | ||
2203 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2204 | ||
2205 | static int | |
2206 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2207 | struct reggroup *group) | |
2208 | { | |
2209 | regnum -= gdbarch_num_regs (gdbarch); | |
2210 | ||
2211 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2212 | return group == all_reggroup || group == vector_reggroup; | |
2213 | else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2214 | return (group == all_reggroup || group == vector_reggroup | |
2215 | || group == float_reggroup); | |
2216 | else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2217 | return (group == all_reggroup || group == vector_reggroup | |
2218 | || group == float_reggroup); | |
2219 | else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2220 | return group == all_reggroup || group == vector_reggroup; | |
2221 | else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2222 | return group == all_reggroup || group == vector_reggroup; | |
2223 | ||
2224 | return group == all_reggroup; | |
2225 | } | |
2226 | ||
2227 | /* Implement the "pseudo_register_read_value" gdbarch method. */ | |
2228 | ||
2229 | static struct value * | |
2230 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, | |
2231 | struct regcache *regcache, | |
2232 | int regnum) | |
2233 | { | |
d1be909e | 2234 | gdb_byte reg_buf[V_REGISTER_SIZE]; |
07b287a0 MS |
2235 | struct value *result_value; |
2236 | gdb_byte *buf; | |
2237 | ||
2238 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
2239 | VALUE_LVAL (result_value) = lval_register; | |
2240 | VALUE_REGNUM (result_value) = regnum; | |
2241 | buf = value_contents_raw (result_value); | |
2242 | ||
2243 | regnum -= gdbarch_num_regs (gdbarch); | |
2244 | ||
2245 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2246 | { | |
2247 | enum register_status status; | |
2248 | unsigned v_regnum; | |
2249 | ||
2250 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2251 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2252 | if (status != REG_VALID) | |
2253 | mark_value_bytes_unavailable (result_value, 0, | |
2254 | TYPE_LENGTH (value_type (result_value))); | |
2255 | else | |
2256 | memcpy (buf, reg_buf, Q_REGISTER_SIZE); | |
2257 | return result_value; | |
2258 | } | |
2259 | ||
2260 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2261 | { | |
2262 | enum register_status status; | |
2263 | unsigned v_regnum; | |
2264 | ||
2265 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2266 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2267 | if (status != REG_VALID) | |
2268 | mark_value_bytes_unavailable (result_value, 0, | |
2269 | TYPE_LENGTH (value_type (result_value))); | |
2270 | else | |
2271 | memcpy (buf, reg_buf, D_REGISTER_SIZE); | |
2272 | return result_value; | |
2273 | } | |
2274 | ||
2275 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2276 | { | |
2277 | enum register_status status; | |
2278 | unsigned v_regnum; | |
2279 | ||
2280 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2281 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
4bcddace PL |
2282 | if (status != REG_VALID) |
2283 | mark_value_bytes_unavailable (result_value, 0, | |
2284 | TYPE_LENGTH (value_type (result_value))); | |
2285 | else | |
2286 | memcpy (buf, reg_buf, S_REGISTER_SIZE); | |
07b287a0 MS |
2287 | return result_value; |
2288 | } | |
2289 | ||
2290 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2291 | { | |
2292 | enum register_status status; | |
2293 | unsigned v_regnum; | |
2294 | ||
2295 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2296 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2297 | if (status != REG_VALID) | |
2298 | mark_value_bytes_unavailable (result_value, 0, | |
2299 | TYPE_LENGTH (value_type (result_value))); | |
2300 | else | |
2301 | memcpy (buf, reg_buf, H_REGISTER_SIZE); | |
2302 | return result_value; | |
2303 | } | |
2304 | ||
2305 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2306 | { | |
2307 | enum register_status status; | |
2308 | unsigned v_regnum; | |
2309 | ||
2310 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2311 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2312 | if (status != REG_VALID) | |
2313 | mark_value_bytes_unavailable (result_value, 0, | |
2314 | TYPE_LENGTH (value_type (result_value))); | |
2315 | else | |
2316 | memcpy (buf, reg_buf, B_REGISTER_SIZE); | |
2317 | return result_value; | |
2318 | } | |
2319 | ||
2320 | gdb_assert_not_reached ("regnum out of bound"); | |
2321 | } | |
2322 | ||
2323 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2324 | ||
2325 | static void | |
2326 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2327 | int regnum, const gdb_byte *buf) | |
2328 | { | |
d1be909e | 2329 | gdb_byte reg_buf[V_REGISTER_SIZE]; |
07b287a0 MS |
2330 | |
2331 | /* Ensure the register buffer is zero, we want gdb writes of the | |
2332 | various 'scalar' pseudo registers to behavior like architectural | |
2333 | writes, register width bytes are written the remainder are set to | |
2334 | zero. */ | |
2335 | memset (reg_buf, 0, sizeof (reg_buf)); | |
2336 | ||
2337 | regnum -= gdbarch_num_regs (gdbarch); | |
2338 | ||
2339 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2340 | { | |
2341 | /* pseudo Q registers */ | |
2342 | unsigned v_regnum; | |
2343 | ||
2344 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2345 | memcpy (reg_buf, buf, Q_REGISTER_SIZE); | |
2346 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2347 | return; | |
2348 | } | |
2349 | ||
2350 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2351 | { | |
2352 | /* pseudo D registers */ | |
2353 | unsigned v_regnum; | |
2354 | ||
2355 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2356 | memcpy (reg_buf, buf, D_REGISTER_SIZE); | |
2357 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2358 | return; | |
2359 | } | |
2360 | ||
2361 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2362 | { | |
2363 | unsigned v_regnum; | |
2364 | ||
2365 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2366 | memcpy (reg_buf, buf, S_REGISTER_SIZE); | |
2367 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2368 | return; | |
2369 | } | |
2370 | ||
2371 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2372 | { | |
2373 | /* pseudo H registers */ | |
2374 | unsigned v_regnum; | |
2375 | ||
2376 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2377 | memcpy (reg_buf, buf, H_REGISTER_SIZE); | |
2378 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2379 | return; | |
2380 | } | |
2381 | ||
2382 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2383 | { | |
2384 | /* pseudo B registers */ | |
2385 | unsigned v_regnum; | |
2386 | ||
2387 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2388 | memcpy (reg_buf, buf, B_REGISTER_SIZE); | |
2389 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2390 | return; | |
2391 | } | |
2392 | ||
2393 | gdb_assert_not_reached ("regnum out of bound"); | |
2394 | } | |
2395 | ||
07b287a0 MS |
2396 | /* Callback function for user_reg_add. */ |
2397 | ||
2398 | static struct value * | |
2399 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2400 | { | |
9a3c8263 | 2401 | const int *reg_p = (const int *) baton; |
07b287a0 MS |
2402 | |
2403 | return value_of_register (*reg_p, frame); | |
2404 | } | |
2405 | \f | |
2406 | ||
9404b58f KM |
2407 | /* Implement the "software_single_step" gdbarch method, needed to |
2408 | single step through atomic sequences on AArch64. */ | |
2409 | ||
a0ff9e1a | 2410 | static std::vector<CORE_ADDR> |
f5ea389a | 2411 | aarch64_software_single_step (struct regcache *regcache) |
9404b58f | 2412 | { |
ac7936df | 2413 | struct gdbarch *gdbarch = regcache->arch (); |
9404b58f KM |
2414 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2415 | const int insn_size = 4; | |
2416 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
0187a92f | 2417 | CORE_ADDR pc = regcache_read_pc (regcache); |
9404b58f KM |
2418 | CORE_ADDR breaks[2] = { -1, -1 }; |
2419 | CORE_ADDR loc = pc; | |
2420 | CORE_ADDR closing_insn = 0; | |
2421 | uint32_t insn = read_memory_unsigned_integer (loc, insn_size, | |
2422 | byte_order_for_code); | |
2423 | int index; | |
2424 | int insn_count; | |
2425 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2426 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
f77ee802 YQ |
2427 | aarch64_inst inst; |
2428 | ||
43cdf5ae | 2429 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
a0ff9e1a | 2430 | return {}; |
9404b58f KM |
2431 | |
2432 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
f77ee802 | 2433 | if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) |
a0ff9e1a | 2434 | return {}; |
9404b58f KM |
2435 | |
2436 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2437 | { | |
9404b58f KM |
2438 | loc += insn_size; |
2439 | insn = read_memory_unsigned_integer (loc, insn_size, | |
2440 | byte_order_for_code); | |
2441 | ||
43cdf5ae | 2442 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
a0ff9e1a | 2443 | return {}; |
9404b58f | 2444 | /* Check if the instruction is a conditional branch. */ |
f77ee802 | 2445 | if (inst.opcode->iclass == condbranch) |
9404b58f | 2446 | { |
f77ee802 YQ |
2447 | gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); |
2448 | ||
9404b58f | 2449 | if (bc_insn_count >= 1) |
a0ff9e1a | 2450 | return {}; |
9404b58f KM |
2451 | |
2452 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
f77ee802 | 2453 | breaks[1] = loc + inst.operands[0].imm.value; |
9404b58f KM |
2454 | |
2455 | bc_insn_count++; | |
2456 | last_breakpoint++; | |
2457 | } | |
2458 | ||
2459 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
f77ee802 | 2460 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) |
9404b58f KM |
2461 | { |
2462 | closing_insn = loc; | |
2463 | break; | |
2464 | } | |
2465 | } | |
2466 | ||
2467 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
2468 | if (!closing_insn) | |
a0ff9e1a | 2469 | return {}; |
9404b58f KM |
2470 | |
2471 | /* Insert breakpoint after the end of the atomic sequence. */ | |
2472 | breaks[0] = loc + insn_size; | |
2473 | ||
2474 | /* Check for duplicated breakpoints, and also check that the second | |
2475 | breakpoint is not within the atomic sequence. */ | |
2476 | if (last_breakpoint | |
2477 | && (breaks[1] == breaks[0] | |
2478 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
2479 | last_breakpoint = 0; | |
2480 | ||
a0ff9e1a SM |
2481 | std::vector<CORE_ADDR> next_pcs; |
2482 | ||
9404b58f KM |
2483 | /* Insert the breakpoint at the end of the sequence, and one at the |
2484 | destination of the conditional branch, if it exists. */ | |
2485 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 2486 | next_pcs.push_back (breaks[index]); |
9404b58f | 2487 | |
93f9a11f | 2488 | return next_pcs; |
9404b58f KM |
2489 | } |
2490 | ||
cfba9872 | 2491 | struct aarch64_displaced_step_closure : public displaced_step_closure |
b6542f81 YQ |
2492 | { |
2493 | /* It is true when condition instruction, such as B.CON, TBZ, etc, | |
2494 | is being displaced stepping. */ | |
cfba9872 | 2495 | int cond = 0; |
b6542f81 YQ |
2496 | |
2497 | /* PC adjustment offset after displaced stepping. */ | |
cfba9872 | 2498 | int32_t pc_adjust = 0; |
b6542f81 YQ |
2499 | }; |
2500 | ||
2501 | /* Data when visiting instructions for displaced stepping. */ | |
2502 | ||
2503 | struct aarch64_displaced_step_data | |
2504 | { | |
2505 | struct aarch64_insn_data base; | |
2506 | ||
2507 | /* The address where the instruction will be executed at. */ | |
2508 | CORE_ADDR new_addr; | |
2509 | /* Buffer of instructions to be copied to NEW_ADDR to execute. */ | |
2510 | uint32_t insn_buf[DISPLACED_MODIFIED_INSNS]; | |
2511 | /* Number of instructions in INSN_BUF. */ | |
2512 | unsigned insn_count; | |
2513 | /* Registers when doing displaced stepping. */ | |
2514 | struct regcache *regs; | |
2515 | ||
cfba9872 | 2516 | aarch64_displaced_step_closure *dsc; |
b6542f81 YQ |
2517 | }; |
2518 | ||
2519 | /* Implementation of aarch64_insn_visitor method "b". */ | |
2520 | ||
2521 | static void | |
2522 | aarch64_displaced_step_b (const int is_bl, const int32_t offset, | |
2523 | struct aarch64_insn_data *data) | |
2524 | { | |
2525 | struct aarch64_displaced_step_data *dsd | |
2526 | = (struct aarch64_displaced_step_data *) data; | |
2ac09a5b | 2527 | int64_t new_offset = data->insn_addr - dsd->new_addr + offset; |
b6542f81 YQ |
2528 | |
2529 | if (can_encode_int32 (new_offset, 28)) | |
2530 | { | |
2531 | /* Emit B rather than BL, because executing BL on a new address | |
2532 | will get the wrong address into LR. In order to avoid this, | |
2533 | we emit B, and update LR if the instruction is BL. */ | |
2534 | emit_b (dsd->insn_buf, 0, new_offset); | |
2535 | dsd->insn_count++; | |
2536 | } | |
2537 | else | |
2538 | { | |
2539 | /* Write NOP. */ | |
2540 | emit_nop (dsd->insn_buf); | |
2541 | dsd->insn_count++; | |
2542 | dsd->dsc->pc_adjust = offset; | |
2543 | } | |
2544 | ||
2545 | if (is_bl) | |
2546 | { | |
2547 | /* Update LR. */ | |
2548 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
2549 | data->insn_addr + 4); | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | /* Implementation of aarch64_insn_visitor method "b_cond". */ | |
2554 | ||
2555 | static void | |
2556 | aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset, | |
2557 | struct aarch64_insn_data *data) | |
2558 | { | |
2559 | struct aarch64_displaced_step_data *dsd | |
2560 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2561 | |
2562 | /* GDB has to fix up PC after displaced step this instruction | |
2563 | differently according to the condition is true or false. Instead | |
2564 | of checking COND against conditional flags, we can use | |
2565 | the following instructions, and GDB can tell how to fix up PC | |
2566 | according to the PC value. | |
2567 | ||
2568 | B.COND TAKEN ; If cond is true, then jump to TAKEN. | |
2569 | INSN1 ; | |
2570 | TAKEN: | |
2571 | INSN2 | |
2572 | */ | |
2573 | ||
2574 | emit_bcond (dsd->insn_buf, cond, 8); | |
2575 | dsd->dsc->cond = 1; | |
2576 | dsd->dsc->pc_adjust = offset; | |
2577 | dsd->insn_count = 1; | |
2578 | } | |
2579 | ||
2580 | /* Dynamically allocate a new register. If we know the register | |
2581 | statically, we should make it a global as above instead of using this | |
2582 | helper function. */ | |
2583 | ||
2584 | static struct aarch64_register | |
2585 | aarch64_register (unsigned num, int is64) | |
2586 | { | |
2587 | return (struct aarch64_register) { num, is64 }; | |
2588 | } | |
2589 | ||
2590 | /* Implementation of aarch64_insn_visitor method "cb". */ | |
2591 | ||
2592 | static void | |
2593 | aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz, | |
2594 | const unsigned rn, int is64, | |
2595 | struct aarch64_insn_data *data) | |
2596 | { | |
2597 | struct aarch64_displaced_step_data *dsd | |
2598 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2599 | |
2600 | /* The offset is out of range for a compare and branch | |
2601 | instruction. We can use the following instructions instead: | |
2602 | ||
2603 | CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. | |
2604 | INSN1 ; | |
2605 | TAKEN: | |
2606 | INSN2 | |
2607 | */ | |
2608 | emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8); | |
2609 | dsd->insn_count = 1; | |
2610 | dsd->dsc->cond = 1; | |
2611 | dsd->dsc->pc_adjust = offset; | |
2612 | } | |
2613 | ||
2614 | /* Implementation of aarch64_insn_visitor method "tb". */ | |
2615 | ||
2616 | static void | |
2617 | aarch64_displaced_step_tb (const int32_t offset, int is_tbnz, | |
2618 | const unsigned rt, unsigned bit, | |
2619 | struct aarch64_insn_data *data) | |
2620 | { | |
2621 | struct aarch64_displaced_step_data *dsd | |
2622 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2623 | |
2624 | /* The offset is out of range for a test bit and branch | |
2625 | instruction We can use the following instructions instead: | |
2626 | ||
2627 | TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. | |
2628 | INSN1 ; | |
2629 | TAKEN: | |
2630 | INSN2 | |
2631 | ||
2632 | */ | |
2633 | emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8); | |
2634 | dsd->insn_count = 1; | |
2635 | dsd->dsc->cond = 1; | |
2636 | dsd->dsc->pc_adjust = offset; | |
2637 | } | |
2638 | ||
2639 | /* Implementation of aarch64_insn_visitor method "adr". */ | |
2640 | ||
2641 | static void | |
2642 | aarch64_displaced_step_adr (const int32_t offset, const unsigned rd, | |
2643 | const int is_adrp, struct aarch64_insn_data *data) | |
2644 | { | |
2645 | struct aarch64_displaced_step_data *dsd | |
2646 | = (struct aarch64_displaced_step_data *) data; | |
2647 | /* We know exactly the address the ADR{P,} instruction will compute. | |
2648 | We can just write it to the destination register. */ | |
2649 | CORE_ADDR address = data->insn_addr + offset; | |
2650 | ||
2651 | if (is_adrp) | |
2652 | { | |
2653 | /* Clear the lower 12 bits of the offset to get the 4K page. */ | |
2654 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2655 | address & ~0xfff); | |
2656 | } | |
2657 | else | |
2658 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2659 | address); | |
2660 | ||
2661 | dsd->dsc->pc_adjust = 4; | |
2662 | emit_nop (dsd->insn_buf); | |
2663 | dsd->insn_count = 1; | |
2664 | } | |
2665 | ||
2666 | /* Implementation of aarch64_insn_visitor method "ldr_literal". */ | |
2667 | ||
2668 | static void | |
2669 | aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw, | |
2670 | const unsigned rt, const int is64, | |
2671 | struct aarch64_insn_data *data) | |
2672 | { | |
2673 | struct aarch64_displaced_step_data *dsd | |
2674 | = (struct aarch64_displaced_step_data *) data; | |
2675 | CORE_ADDR address = data->insn_addr + offset; | |
2676 | struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 }; | |
2677 | ||
2678 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt, | |
2679 | address); | |
2680 | ||
2681 | if (is_sw) | |
2682 | dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1), | |
2683 | aarch64_register (rt, 1), zero); | |
2684 | else | |
2685 | dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64), | |
2686 | aarch64_register (rt, 1), zero); | |
2687 | ||
2688 | dsd->dsc->pc_adjust = 4; | |
2689 | } | |
2690 | ||
2691 | /* Implementation of aarch64_insn_visitor method "others". */ | |
2692 | ||
2693 | static void | |
2694 | aarch64_displaced_step_others (const uint32_t insn, | |
2695 | struct aarch64_insn_data *data) | |
2696 | { | |
2697 | struct aarch64_displaced_step_data *dsd | |
2698 | = (struct aarch64_displaced_step_data *) data; | |
2699 | ||
e1c587c3 | 2700 | aarch64_emit_insn (dsd->insn_buf, insn); |
b6542f81 YQ |
2701 | dsd->insn_count = 1; |
2702 | ||
2703 | if ((insn & 0xfffffc1f) == 0xd65f0000) | |
2704 | { | |
2705 | /* RET */ | |
2706 | dsd->dsc->pc_adjust = 0; | |
2707 | } | |
2708 | else | |
2709 | dsd->dsc->pc_adjust = 4; | |
2710 | } | |
2711 | ||
2712 | static const struct aarch64_insn_visitor visitor = | |
2713 | { | |
2714 | aarch64_displaced_step_b, | |
2715 | aarch64_displaced_step_b_cond, | |
2716 | aarch64_displaced_step_cb, | |
2717 | aarch64_displaced_step_tb, | |
2718 | aarch64_displaced_step_adr, | |
2719 | aarch64_displaced_step_ldr_literal, | |
2720 | aarch64_displaced_step_others, | |
2721 | }; | |
2722 | ||
2723 | /* Implement the "displaced_step_copy_insn" gdbarch method. */ | |
2724 | ||
2725 | struct displaced_step_closure * | |
2726 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
2727 | CORE_ADDR from, CORE_ADDR to, | |
2728 | struct regcache *regs) | |
2729 | { | |
b6542f81 YQ |
2730 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2731 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); | |
2732 | struct aarch64_displaced_step_data dsd; | |
c86a40c6 YQ |
2733 | aarch64_inst inst; |
2734 | ||
2735 | if (aarch64_decode_insn (insn, &inst, 1) != 0) | |
2736 | return NULL; | |
b6542f81 YQ |
2737 | |
2738 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
c86a40c6 | 2739 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) |
b6542f81 YQ |
2740 | { |
2741 | /* We can't displaced step atomic sequences. */ | |
2742 | return NULL; | |
2743 | } | |
2744 | ||
cfba9872 SM |
2745 | std::unique_ptr<aarch64_displaced_step_closure> dsc |
2746 | (new aarch64_displaced_step_closure); | |
b6542f81 YQ |
2747 | dsd.base.insn_addr = from; |
2748 | dsd.new_addr = to; | |
2749 | dsd.regs = regs; | |
cfba9872 | 2750 | dsd.dsc = dsc.get (); |
034f1a81 | 2751 | dsd.insn_count = 0; |
b6542f81 YQ |
2752 | aarch64_relocate_instruction (insn, &visitor, |
2753 | (struct aarch64_insn_data *) &dsd); | |
2754 | gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS); | |
2755 | ||
2756 | if (dsd.insn_count != 0) | |
2757 | { | |
2758 | int i; | |
2759 | ||
2760 | /* Instruction can be relocated to scratch pad. Copy | |
2761 | relocated instruction(s) there. */ | |
2762 | for (i = 0; i < dsd.insn_count; i++) | |
2763 | { | |
2764 | if (debug_displaced) | |
2765 | { | |
2766 | debug_printf ("displaced: writing insn "); | |
2767 | debug_printf ("%.8x", dsd.insn_buf[i]); | |
2768 | debug_printf (" at %s\n", paddress (gdbarch, to + i * 4)); | |
2769 | } | |
2770 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, | |
2771 | (ULONGEST) dsd.insn_buf[i]); | |
2772 | } | |
2773 | } | |
2774 | else | |
2775 | { | |
b6542f81 YQ |
2776 | dsc = NULL; |
2777 | } | |
2778 | ||
cfba9872 | 2779 | return dsc.release (); |
b6542f81 YQ |
2780 | } |
2781 | ||
2782 | /* Implement the "displaced_step_fixup" gdbarch method. */ | |
2783 | ||
2784 | void | |
2785 | aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
cfba9872 | 2786 | struct displaced_step_closure *dsc_, |
b6542f81 YQ |
2787 | CORE_ADDR from, CORE_ADDR to, |
2788 | struct regcache *regs) | |
2789 | { | |
cfba9872 SM |
2790 | aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_; |
2791 | ||
b6542f81 YQ |
2792 | if (dsc->cond) |
2793 | { | |
2794 | ULONGEST pc; | |
2795 | ||
2796 | regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc); | |
2797 | if (pc - to == 8) | |
2798 | { | |
2799 | /* Condition is true. */ | |
2800 | } | |
2801 | else if (pc - to == 4) | |
2802 | { | |
2803 | /* Condition is false. */ | |
2804 | dsc->pc_adjust = 4; | |
2805 | } | |
2806 | else | |
2807 | gdb_assert_not_reached ("Unexpected PC value after displaced stepping"); | |
2808 | } | |
2809 | ||
2810 | if (dsc->pc_adjust != 0) | |
2811 | { | |
2812 | if (debug_displaced) | |
2813 | { | |
2814 | debug_printf ("displaced: fixup: set PC to %s:%d\n", | |
2815 | paddress (gdbarch, from), dsc->pc_adjust); | |
2816 | } | |
2817 | regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM, | |
2818 | from + dsc->pc_adjust); | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* Implement the "displaced_step_hw_singlestep" gdbarch method. */ | |
2823 | ||
2824 | int | |
2825 | aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
2826 | struct displaced_step_closure *closure) | |
2827 | { | |
2828 | return 1; | |
2829 | } | |
2830 | ||
07b287a0 MS |
2831 | /* Initialize the current architecture based on INFO. If possible, |
2832 | re-use an architecture from ARCHES, which is a list of | |
2833 | architectures already created during this debugging session. | |
2834 | ||
2835 | Called e.g. at program startup, when reading a core file, and when | |
2836 | reading a binary file. */ | |
2837 | ||
2838 | static struct gdbarch * | |
2839 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2840 | { | |
2841 | struct gdbarch_tdep *tdep; | |
2842 | struct gdbarch *gdbarch; | |
2843 | struct gdbarch_list *best_arch; | |
2844 | struct tdesc_arch_data *tdesc_data = NULL; | |
2845 | const struct target_desc *tdesc = info.target_desc; | |
2846 | int i; | |
07b287a0 MS |
2847 | int valid_p = 1; |
2848 | const struct tdesc_feature *feature; | |
2849 | int num_regs = 0; | |
2850 | int num_pseudo_regs = 0; | |
2851 | ||
2852 | /* Ensure we always have a target descriptor. */ | |
2853 | if (!tdesc_has_registers (tdesc)) | |
2854 | tdesc = tdesc_aarch64; | |
2855 | ||
2856 | gdb_assert (tdesc); | |
2857 | ||
2858 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core"); | |
2859 | ||
2860 | if (feature == NULL) | |
2861 | return NULL; | |
2862 | ||
2863 | tdesc_data = tdesc_data_alloc (); | |
2864 | ||
2865 | /* Validate the descriptor provides the mandatory core R registers | |
2866 | and allocate their numbers. */ | |
2867 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
2868 | valid_p &= | |
2869 | tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i, | |
2870 | aarch64_r_register_names[i]); | |
2871 | ||
2872 | num_regs = AARCH64_X0_REGNUM + i; | |
2873 | ||
2874 | /* Look for the V registers. */ | |
2875 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); | |
2876 | if (feature) | |
2877 | { | |
2878 | /* Validate the descriptor provides the mandatory V registers | |
2879 | and allocate their numbers. */ | |
2880 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) | |
2881 | valid_p &= | |
2882 | tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i, | |
2883 | aarch64_v_register_names[i]); | |
2884 | ||
2885 | num_regs = AARCH64_V0_REGNUM + i; | |
2886 | ||
2887 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ | |
2888 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
2889 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
2890 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
2891 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
2892 | } | |
2893 | ||
2894 | if (!valid_p) | |
2895 | { | |
2896 | tdesc_data_cleanup (tdesc_data); | |
2897 | return NULL; | |
2898 | } | |
2899 | ||
2900 | /* AArch64 code is always little-endian. */ | |
2901 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
2902 | ||
2903 | /* If there is already a candidate, use it. */ | |
2904 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2905 | best_arch != NULL; | |
2906 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2907 | { | |
2908 | /* Found a match. */ | |
2909 | break; | |
2910 | } | |
2911 | ||
2912 | if (best_arch != NULL) | |
2913 | { | |
2914 | if (tdesc_data != NULL) | |
2915 | tdesc_data_cleanup (tdesc_data); | |
2916 | return best_arch->gdbarch; | |
2917 | } | |
2918 | ||
8d749320 | 2919 | tdep = XCNEW (struct gdbarch_tdep); |
07b287a0 MS |
2920 | gdbarch = gdbarch_alloc (&info, tdep); |
2921 | ||
2922 | /* This should be low enough for everything. */ | |
2923 | tdep->lowest_pc = 0x20; | |
2924 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
2925 | tdep->jb_elt_size = 8; | |
2926 | ||
2927 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); | |
2928 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
2929 | ||
07b287a0 MS |
2930 | /* Frame handling. */ |
2931 | set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id); | |
2932 | set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc); | |
2933 | set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp); | |
2934 | ||
2935 | /* Advance PC across function entry code. */ | |
2936 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
2937 | ||
2938 | /* The stack grows downward. */ | |
2939 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2940 | ||
2941 | /* Breakpoint manipulation. */ | |
04180708 YQ |
2942 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
2943 | aarch64_breakpoint::kind_from_pc); | |
2944 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
2945 | aarch64_breakpoint::bp_from_kind); | |
07b287a0 | 2946 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 2947 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
2948 | |
2949 | /* Information about registers, etc. */ | |
2950 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
2951 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
2952 | set_gdbarch_num_regs (gdbarch, num_regs); | |
2953 | ||
2954 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
2955 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
2956 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
2957 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
2958 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
2959 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
2960 | aarch64_pseudo_register_reggroup_p); | |
2961 | ||
2962 | /* ABI */ | |
2963 | set_gdbarch_short_bit (gdbarch, 16); | |
2964 | set_gdbarch_int_bit (gdbarch, 32); | |
2965 | set_gdbarch_float_bit (gdbarch, 32); | |
2966 | set_gdbarch_double_bit (gdbarch, 64); | |
2967 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2968 | set_gdbarch_long_bit (gdbarch, 64); | |
2969 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2970 | set_gdbarch_ptr_bit (gdbarch, 64); | |
2971 | set_gdbarch_char_signed (gdbarch, 0); | |
53375380 | 2972 | set_gdbarch_wchar_signed (gdbarch, 0); |
07b287a0 MS |
2973 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
2974 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
2975 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2976 | ||
2977 | /* Internal <-> external register number maps. */ | |
2978 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
2979 | ||
2980 | /* Returning results. */ | |
2981 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
2982 | ||
2983 | /* Disassembly. */ | |
2984 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
2985 | ||
2986 | /* Virtual tables. */ | |
2987 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
2988 | ||
2989 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
2990 | info.target_desc = tdesc; | |
0dba2a6c | 2991 | info.tdesc_data = tdesc_data; |
07b287a0 MS |
2992 | gdbarch_init_osabi (info, gdbarch); |
2993 | ||
2994 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
2995 | ||
2996 | /* Add some default predicates. */ | |
2997 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
2998 | dwarf2_append_unwinders (gdbarch); | |
2999 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
3000 | ||
3001 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
3002 | ||
3003 | /* Now we have tuned the configuration, set a few final things, | |
3004 | based on what the OS ABI has told us. */ | |
3005 | ||
3006 | if (tdep->jb_pc >= 0) | |
3007 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
3008 | ||
ea873d8e PL |
3009 | set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address); |
3010 | ||
07b287a0 MS |
3011 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
3012 | ||
3013 | /* Add standard register aliases. */ | |
3014 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
3015 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
3016 | value_of_aarch64_user_reg, | |
3017 | &aarch64_register_aliases[i].regnum); | |
3018 | ||
3019 | return gdbarch; | |
3020 | } | |
3021 | ||
3022 | static void | |
3023 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3024 | { | |
3025 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3026 | ||
3027 | if (tdep == NULL) | |
3028 | return; | |
3029 | ||
3030 | fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), | |
3031 | paddress (gdbarch, tdep->lowest_pc)); | |
3032 | } | |
3033 | ||
0d4c07af | 3034 | #if GDB_SELF_TEST |
1e2b521d YQ |
3035 | namespace selftests |
3036 | { | |
3037 | static void aarch64_process_record_test (void); | |
3038 | } | |
0d4c07af | 3039 | #endif |
1e2b521d | 3040 | |
07b287a0 MS |
3041 | void |
3042 | _initialize_aarch64_tdep (void) | |
3043 | { | |
3044 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
3045 | aarch64_dump_tdep); | |
3046 | ||
3047 | initialize_tdesc_aarch64 (); | |
07b287a0 MS |
3048 | |
3049 | /* Debug this file's internals. */ | |
3050 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
3051 | Set AArch64 debugging."), _("\ | |
3052 | Show AArch64 debugging."), _("\ | |
3053 | When on, AArch64 specific debugging is enabled."), | |
3054 | NULL, | |
3055 | show_aarch64_debug, | |
3056 | &setdebuglist, &showdebuglist); | |
4d9a9006 YQ |
3057 | |
3058 | #if GDB_SELF_TEST | |
1526853e SM |
3059 | selftests::register_test ("aarch64-analyze-prologue", |
3060 | selftests::aarch64_analyze_prologue_test); | |
3061 | selftests::register_test ("aarch64-process-record", | |
3062 | selftests::aarch64_process_record_test); | |
4d9a9006 | 3063 | #endif |
07b287a0 | 3064 | } |
99afc88b OJ |
3065 | |
3066 | /* AArch64 process record-replay related structures, defines etc. */ | |
3067 | ||
99afc88b OJ |
3068 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ |
3069 | do \ | |
3070 | { \ | |
3071 | unsigned int reg_len = LENGTH; \ | |
3072 | if (reg_len) \ | |
3073 | { \ | |
3074 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
3075 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
3076 | } \ | |
3077 | } \ | |
3078 | while (0) | |
3079 | ||
3080 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
3081 | do \ | |
3082 | { \ | |
3083 | unsigned int mem_len = LENGTH; \ | |
3084 | if (mem_len) \ | |
3085 | { \ | |
3086 | MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \ | |
3087 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
3088 | sizeof(struct aarch64_mem_r) * LENGTH); \ | |
3089 | } \ | |
3090 | } \ | |
3091 | while (0) | |
3092 | ||
3093 | /* AArch64 record/replay structures and enumerations. */ | |
3094 | ||
3095 | struct aarch64_mem_r | |
3096 | { | |
3097 | uint64_t len; /* Record length. */ | |
3098 | uint64_t addr; /* Memory address. */ | |
3099 | }; | |
3100 | ||
3101 | enum aarch64_record_result | |
3102 | { | |
3103 | AARCH64_RECORD_SUCCESS, | |
99afc88b OJ |
3104 | AARCH64_RECORD_UNSUPPORTED, |
3105 | AARCH64_RECORD_UNKNOWN | |
3106 | }; | |
3107 | ||
3108 | typedef struct insn_decode_record_t | |
3109 | { | |
3110 | struct gdbarch *gdbarch; | |
3111 | struct regcache *regcache; | |
3112 | CORE_ADDR this_addr; /* Address of insn to be recorded. */ | |
3113 | uint32_t aarch64_insn; /* Insn to be recorded. */ | |
3114 | uint32_t mem_rec_count; /* Count of memory records. */ | |
3115 | uint32_t reg_rec_count; /* Count of register records. */ | |
3116 | uint32_t *aarch64_regs; /* Registers to be recorded. */ | |
3117 | struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */ | |
3118 | } insn_decode_record; | |
3119 | ||
3120 | /* Record handler for data processing - register instructions. */ | |
3121 | ||
3122 | static unsigned int | |
3123 | aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r) | |
3124 | { | |
3125 | uint8_t reg_rd, insn_bits24_27, insn_bits21_23; | |
3126 | uint32_t record_buf[4]; | |
3127 | ||
3128 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3129 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3130 | insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23); | |
3131 | ||
3132 | if (!bit (aarch64_insn_r->aarch64_insn, 28)) | |
3133 | { | |
3134 | uint8_t setflags; | |
3135 | ||
3136 | /* Logical (shifted register). */ | |
3137 | if (insn_bits24_27 == 0x0a) | |
3138 | setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03); | |
3139 | /* Add/subtract. */ | |
3140 | else if (insn_bits24_27 == 0x0b) | |
3141 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3142 | else | |
3143 | return AARCH64_RECORD_UNKNOWN; | |
3144 | ||
3145 | record_buf[0] = reg_rd; | |
3146 | aarch64_insn_r->reg_rec_count = 1; | |
3147 | if (setflags) | |
3148 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3149 | } | |
3150 | else | |
3151 | { | |
3152 | if (insn_bits24_27 == 0x0b) | |
3153 | { | |
3154 | /* Data-processing (3 source). */ | |
3155 | record_buf[0] = reg_rd; | |
3156 | aarch64_insn_r->reg_rec_count = 1; | |
3157 | } | |
3158 | else if (insn_bits24_27 == 0x0a) | |
3159 | { | |
3160 | if (insn_bits21_23 == 0x00) | |
3161 | { | |
3162 | /* Add/subtract (with carry). */ | |
3163 | record_buf[0] = reg_rd; | |
3164 | aarch64_insn_r->reg_rec_count = 1; | |
3165 | if (bit (aarch64_insn_r->aarch64_insn, 29)) | |
3166 | { | |
3167 | record_buf[1] = AARCH64_CPSR_REGNUM; | |
3168 | aarch64_insn_r->reg_rec_count = 2; | |
3169 | } | |
3170 | } | |
3171 | else if (insn_bits21_23 == 0x02) | |
3172 | { | |
3173 | /* Conditional compare (register) and conditional compare | |
3174 | (immediate) instructions. */ | |
3175 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3176 | aarch64_insn_r->reg_rec_count = 1; | |
3177 | } | |
3178 | else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06) | |
3179 | { | |
3180 | /* CConditional select. */ | |
3181 | /* Data-processing (2 source). */ | |
3182 | /* Data-processing (1 source). */ | |
3183 | record_buf[0] = reg_rd; | |
3184 | aarch64_insn_r->reg_rec_count = 1; | |
3185 | } | |
3186 | else | |
3187 | return AARCH64_RECORD_UNKNOWN; | |
3188 | } | |
3189 | } | |
3190 | ||
3191 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3192 | record_buf); | |
3193 | return AARCH64_RECORD_SUCCESS; | |
3194 | } | |
3195 | ||
3196 | /* Record handler for data processing - immediate instructions. */ | |
3197 | ||
3198 | static unsigned int | |
3199 | aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) | |
3200 | { | |
78cc6c2d | 3201 | uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; |
99afc88b OJ |
3202 | uint32_t record_buf[4]; |
3203 | ||
3204 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
99afc88b OJ |
3205 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); |
3206 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3207 | ||
3208 | if (insn_bits24_27 == 0x00 /* PC rel addressing. */ | |
3209 | || insn_bits24_27 == 0x03 /* Bitfield and Extract. */ | |
3210 | || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */ | |
3211 | { | |
3212 | record_buf[0] = reg_rd; | |
3213 | aarch64_insn_r->reg_rec_count = 1; | |
3214 | } | |
3215 | else if (insn_bits24_27 == 0x01) | |
3216 | { | |
3217 | /* Add/Subtract (immediate). */ | |
3218 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3219 | record_buf[0] = reg_rd; | |
3220 | aarch64_insn_r->reg_rec_count = 1; | |
3221 | if (setflags) | |
3222 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3223 | } | |
3224 | else if (insn_bits24_27 == 0x02 && !insn_bit23) | |
3225 | { | |
3226 | /* Logical (immediate). */ | |
3227 | setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03; | |
3228 | record_buf[0] = reg_rd; | |
3229 | aarch64_insn_r->reg_rec_count = 1; | |
3230 | if (setflags) | |
3231 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3232 | } | |
3233 | else | |
3234 | return AARCH64_RECORD_UNKNOWN; | |
3235 | ||
3236 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3237 | record_buf); | |
3238 | return AARCH64_RECORD_SUCCESS; | |
3239 | } | |
3240 | ||
3241 | /* Record handler for branch, exception generation and system instructions. */ | |
3242 | ||
3243 | static unsigned int | |
3244 | aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) | |
3245 | { | |
3246 | struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch); | |
3247 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23; | |
3248 | uint32_t record_buf[4]; | |
3249 | ||
3250 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3251 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3252 | insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3253 | ||
3254 | if (insn_bits28_31 == 0x0d) | |
3255 | { | |
3256 | /* Exception generation instructions. */ | |
3257 | if (insn_bits24_27 == 0x04) | |
3258 | { | |
5d98d3cd YQ |
3259 | if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) |
3260 | && !bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3261 | && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01) | |
99afc88b OJ |
3262 | { |
3263 | ULONGEST svc_number; | |
3264 | ||
3265 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8, | |
3266 | &svc_number); | |
3267 | return tdep->aarch64_syscall_record (aarch64_insn_r->regcache, | |
3268 | svc_number); | |
3269 | } | |
3270 | else | |
3271 | return AARCH64_RECORD_UNSUPPORTED; | |
3272 | } | |
3273 | /* System instructions. */ | |
3274 | else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00) | |
3275 | { | |
3276 | uint32_t reg_rt, reg_crn; | |
3277 | ||
3278 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3279 | reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3280 | ||
3281 | /* Record rt in case of sysl and mrs instructions. */ | |
3282 | if (bit (aarch64_insn_r->aarch64_insn, 21)) | |
3283 | { | |
3284 | record_buf[0] = reg_rt; | |
3285 | aarch64_insn_r->reg_rec_count = 1; | |
3286 | } | |
3287 | /* Record cpsr for hint and msr(immediate) instructions. */ | |
3288 | else if (reg_crn == 0x02 || reg_crn == 0x04) | |
3289 | { | |
3290 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3291 | aarch64_insn_r->reg_rec_count = 1; | |
3292 | } | |
3293 | } | |
3294 | /* Unconditional branch (register). */ | |
3295 | else if((insn_bits24_27 & 0x0e) == 0x06) | |
3296 | { | |
3297 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3298 | if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01) | |
3299 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3300 | } | |
3301 | else | |
3302 | return AARCH64_RECORD_UNKNOWN; | |
3303 | } | |
3304 | /* Unconditional branch (immediate). */ | |
3305 | else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04) | |
3306 | { | |
3307 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3308 | if (bit (aarch64_insn_r->aarch64_insn, 31)) | |
3309 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3310 | } | |
3311 | else | |
3312 | /* Compare & branch (immediate), Test & branch (immediate) and | |
3313 | Conditional branch (immediate). */ | |
3314 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3315 | ||
3316 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3317 | record_buf); | |
3318 | return AARCH64_RECORD_SUCCESS; | |
3319 | } | |
3320 | ||
3321 | /* Record handler for advanced SIMD load and store instructions. */ | |
3322 | ||
3323 | static unsigned int | |
3324 | aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r) | |
3325 | { | |
3326 | CORE_ADDR address; | |
3327 | uint64_t addr_offset = 0; | |
3328 | uint32_t record_buf[24]; | |
3329 | uint64_t record_buf_mem[24]; | |
3330 | uint32_t reg_rn, reg_rt; | |
3331 | uint32_t reg_index = 0, mem_index = 0; | |
3332 | uint8_t opcode_bits, size_bits; | |
3333 | ||
3334 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3335 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3336 | size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3337 | opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3338 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); | |
3339 | ||
3340 | if (record_debug) | |
b277c936 | 3341 | debug_printf ("Process record: Advanced SIMD load/store\n"); |
99afc88b OJ |
3342 | |
3343 | /* Load/store single structure. */ | |
3344 | if (bit (aarch64_insn_r->aarch64_insn, 24)) | |
3345 | { | |
3346 | uint8_t sindex, scale, selem, esize, replicate = 0; | |
3347 | scale = opcode_bits >> 2; | |
3348 | selem = ((opcode_bits & 0x02) | | |
3349 | bit (aarch64_insn_r->aarch64_insn, 21)) + 1; | |
3350 | switch (scale) | |
3351 | { | |
3352 | case 1: | |
3353 | if (size_bits & 0x01) | |
3354 | return AARCH64_RECORD_UNKNOWN; | |
3355 | break; | |
3356 | case 2: | |
3357 | if ((size_bits >> 1) & 0x01) | |
3358 | return AARCH64_RECORD_UNKNOWN; | |
3359 | if (size_bits & 0x01) | |
3360 | { | |
3361 | if (!((opcode_bits >> 1) & 0x01)) | |
3362 | scale = 3; | |
3363 | else | |
3364 | return AARCH64_RECORD_UNKNOWN; | |
3365 | } | |
3366 | break; | |
3367 | case 3: | |
3368 | if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) | |
3369 | { | |
3370 | scale = size_bits; | |
3371 | replicate = 1; | |
3372 | break; | |
3373 | } | |
3374 | else | |
3375 | return AARCH64_RECORD_UNKNOWN; | |
3376 | default: | |
3377 | break; | |
3378 | } | |
3379 | esize = 8 << scale; | |
3380 | if (replicate) | |
3381 | for (sindex = 0; sindex < selem; sindex++) | |
3382 | { | |
3383 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3384 | reg_rt = (reg_rt + 1) % 32; | |
3385 | } | |
3386 | else | |
3387 | { | |
3388 | for (sindex = 0; sindex < selem; sindex++) | |
a2e3e93f SM |
3389 | { |
3390 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3391 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3392 | else | |
3393 | { | |
3394 | record_buf_mem[mem_index++] = esize / 8; | |
3395 | record_buf_mem[mem_index++] = address + addr_offset; | |
3396 | } | |
3397 | addr_offset = addr_offset + (esize / 8); | |
3398 | reg_rt = (reg_rt + 1) % 32; | |
3399 | } | |
99afc88b OJ |
3400 | } |
3401 | } | |
3402 | /* Load/store multiple structure. */ | |
3403 | else | |
3404 | { | |
3405 | uint8_t selem, esize, rpt, elements; | |
3406 | uint8_t eindex, rindex; | |
3407 | ||
3408 | esize = 8 << size_bits; | |
3409 | if (bit (aarch64_insn_r->aarch64_insn, 30)) | |
3410 | elements = 128 / esize; | |
3411 | else | |
3412 | elements = 64 / esize; | |
3413 | ||
3414 | switch (opcode_bits) | |
3415 | { | |
3416 | /*LD/ST4 (4 Registers). */ | |
3417 | case 0: | |
3418 | rpt = 1; | |
3419 | selem = 4; | |
3420 | break; | |
3421 | /*LD/ST1 (4 Registers). */ | |
3422 | case 2: | |
3423 | rpt = 4; | |
3424 | selem = 1; | |
3425 | break; | |
3426 | /*LD/ST3 (3 Registers). */ | |
3427 | case 4: | |
3428 | rpt = 1; | |
3429 | selem = 3; | |
3430 | break; | |
3431 | /*LD/ST1 (3 Registers). */ | |
3432 | case 6: | |
3433 | rpt = 3; | |
3434 | selem = 1; | |
3435 | break; | |
3436 | /*LD/ST1 (1 Register). */ | |
3437 | case 7: | |
3438 | rpt = 1; | |
3439 | selem = 1; | |
3440 | break; | |
3441 | /*LD/ST2 (2 Registers). */ | |
3442 | case 8: | |
3443 | rpt = 1; | |
3444 | selem = 2; | |
3445 | break; | |
3446 | /*LD/ST1 (2 Registers). */ | |
3447 | case 10: | |
3448 | rpt = 2; | |
3449 | selem = 1; | |
3450 | break; | |
3451 | default: | |
3452 | return AARCH64_RECORD_UNSUPPORTED; | |
3453 | break; | |
3454 | } | |
3455 | for (rindex = 0; rindex < rpt; rindex++) | |
3456 | for (eindex = 0; eindex < elements; eindex++) | |
3457 | { | |
3458 | uint8_t reg_tt, sindex; | |
3459 | reg_tt = (reg_rt + rindex) % 32; | |
3460 | for (sindex = 0; sindex < selem; sindex++) | |
3461 | { | |
3462 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3463 | record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; | |
3464 | else | |
3465 | { | |
3466 | record_buf_mem[mem_index++] = esize / 8; | |
3467 | record_buf_mem[mem_index++] = address + addr_offset; | |
3468 | } | |
3469 | addr_offset = addr_offset + (esize / 8); | |
3470 | reg_tt = (reg_tt + 1) % 32; | |
3471 | } | |
3472 | } | |
3473 | } | |
3474 | ||
3475 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3476 | record_buf[reg_index++] = reg_rn; | |
3477 | ||
3478 | aarch64_insn_r->reg_rec_count = reg_index; | |
3479 | aarch64_insn_r->mem_rec_count = mem_index / 2; | |
3480 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3481 | record_buf_mem); | |
3482 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3483 | record_buf); | |
3484 | return AARCH64_RECORD_SUCCESS; | |
3485 | } | |
3486 | ||
3487 | /* Record handler for load and store instructions. */ | |
3488 | ||
3489 | static unsigned int | |
3490 | aarch64_record_load_store (insn_decode_record *aarch64_insn_r) | |
3491 | { | |
3492 | uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; | |
3493 | uint8_t insn_bit23, insn_bit21; | |
3494 | uint8_t opc, size_bits, ld_flag, vector_flag; | |
3495 | uint32_t reg_rn, reg_rt, reg_rt2; | |
3496 | uint64_t datasize, offset; | |
3497 | uint32_t record_buf[8]; | |
3498 | uint64_t record_buf_mem[8]; | |
3499 | CORE_ADDR address; | |
3500 | ||
3501 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3502 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3503 | insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29); | |
3504 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3505 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); | |
3506 | ld_flag = bit (aarch64_insn_r->aarch64_insn, 22); | |
3507 | vector_flag = bit (aarch64_insn_r->aarch64_insn, 26); | |
3508 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3509 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3510 | reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14); | |
3511 | size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31); | |
3512 | ||
3513 | /* Load/store exclusive. */ | |
3514 | if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00) | |
3515 | { | |
3516 | if (record_debug) | |
b277c936 | 3517 | debug_printf ("Process record: load/store exclusive\n"); |
99afc88b OJ |
3518 | |
3519 | if (ld_flag) | |
3520 | { | |
3521 | record_buf[0] = reg_rt; | |
3522 | aarch64_insn_r->reg_rec_count = 1; | |
3523 | if (insn_bit21) | |
3524 | { | |
3525 | record_buf[1] = reg_rt2; | |
3526 | aarch64_insn_r->reg_rec_count = 2; | |
3527 | } | |
3528 | } | |
3529 | else | |
3530 | { | |
3531 | if (insn_bit21) | |
3532 | datasize = (8 << size_bits) * 2; | |
3533 | else | |
3534 | datasize = (8 << size_bits); | |
3535 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3536 | &address); | |
3537 | record_buf_mem[0] = datasize / 8; | |
3538 | record_buf_mem[1] = address; | |
3539 | aarch64_insn_r->mem_rec_count = 1; | |
3540 | if (!insn_bit23) | |
3541 | { | |
3542 | /* Save register rs. */ | |
3543 | record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20); | |
3544 | aarch64_insn_r->reg_rec_count = 1; | |
3545 | } | |
3546 | } | |
3547 | } | |
3548 | /* Load register (literal) instructions decoding. */ | |
3549 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01) | |
3550 | { | |
3551 | if (record_debug) | |
b277c936 | 3552 | debug_printf ("Process record: load register (literal)\n"); |
99afc88b OJ |
3553 | if (vector_flag) |
3554 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3555 | else | |
3556 | record_buf[0] = reg_rt; | |
3557 | aarch64_insn_r->reg_rec_count = 1; | |
3558 | } | |
3559 | /* All types of load/store pair instructions decoding. */ | |
3560 | else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02) | |
3561 | { | |
3562 | if (record_debug) | |
b277c936 | 3563 | debug_printf ("Process record: load/store pair\n"); |
99afc88b OJ |
3564 | |
3565 | if (ld_flag) | |
3566 | { | |
3567 | if (vector_flag) | |
3568 | { | |
3569 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3570 | record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM; | |
3571 | } | |
3572 | else | |
3573 | { | |
3574 | record_buf[0] = reg_rt; | |
3575 | record_buf[1] = reg_rt2; | |
3576 | } | |
3577 | aarch64_insn_r->reg_rec_count = 2; | |
3578 | } | |
3579 | else | |
3580 | { | |
3581 | uint16_t imm7_off; | |
3582 | imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21); | |
3583 | if (!vector_flag) | |
3584 | size_bits = size_bits >> 1; | |
3585 | datasize = 8 << (2 + size_bits); | |
3586 | offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off; | |
3587 | offset = offset << (2 + size_bits); | |
3588 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3589 | &address); | |
3590 | if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23)) | |
3591 | { | |
3592 | if (imm7_off & 0x40) | |
3593 | address = address - offset; | |
3594 | else | |
3595 | address = address + offset; | |
3596 | } | |
3597 | ||
3598 | record_buf_mem[0] = datasize / 8; | |
3599 | record_buf_mem[1] = address; | |
3600 | record_buf_mem[2] = datasize / 8; | |
3601 | record_buf_mem[3] = address + (datasize / 8); | |
3602 | aarch64_insn_r->mem_rec_count = 2; | |
3603 | } | |
3604 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3605 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3606 | } | |
3607 | /* Load/store register (unsigned immediate) instructions. */ | |
3608 | else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03) | |
3609 | { | |
3610 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3611 | if (!(opc >> 1)) | |
33877125 YQ |
3612 | { |
3613 | if (opc & 0x01) | |
3614 | ld_flag = 0x01; | |
3615 | else | |
3616 | ld_flag = 0x0; | |
3617 | } | |
99afc88b | 3618 | else |
33877125 | 3619 | { |
1e2b521d YQ |
3620 | if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2) |
3621 | { | |
3622 | /* PRFM (immediate) */ | |
3623 | return AARCH64_RECORD_SUCCESS; | |
3624 | } | |
3625 | else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2) | |
3626 | { | |
3627 | /* LDRSW (immediate) */ | |
3628 | ld_flag = 0x1; | |
3629 | } | |
33877125 | 3630 | else |
1e2b521d YQ |
3631 | { |
3632 | if (opc & 0x01) | |
3633 | ld_flag = 0x01; | |
3634 | else | |
3635 | ld_flag = 0x0; | |
3636 | } | |
33877125 | 3637 | } |
99afc88b OJ |
3638 | |
3639 | if (record_debug) | |
3640 | { | |
b277c936 PL |
3641 | debug_printf ("Process record: load/store (unsigned immediate):" |
3642 | " size %x V %d opc %x\n", size_bits, vector_flag, | |
3643 | opc); | |
99afc88b OJ |
3644 | } |
3645 | ||
3646 | if (!ld_flag) | |
3647 | { | |
3648 | offset = bits (aarch64_insn_r->aarch64_insn, 10, 21); | |
3649 | datasize = 8 << size_bits; | |
3650 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3651 | &address); | |
3652 | offset = offset << size_bits; | |
3653 | address = address + offset; | |
3654 | ||
3655 | record_buf_mem[0] = datasize >> 3; | |
3656 | record_buf_mem[1] = address; | |
3657 | aarch64_insn_r->mem_rec_count = 1; | |
3658 | } | |
3659 | else | |
3660 | { | |
3661 | if (vector_flag) | |
3662 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3663 | else | |
3664 | record_buf[0] = reg_rt; | |
3665 | aarch64_insn_r->reg_rec_count = 1; | |
3666 | } | |
3667 | } | |
3668 | /* Load/store register (register offset) instructions. */ | |
5d98d3cd YQ |
3669 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3670 | && insn_bits10_11 == 0x02 && insn_bit21) | |
99afc88b OJ |
3671 | { |
3672 | if (record_debug) | |
b277c936 | 3673 | debug_printf ("Process record: load/store (register offset)\n"); |
99afc88b OJ |
3674 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); |
3675 | if (!(opc >> 1)) | |
3676 | if (opc & 0x01) | |
3677 | ld_flag = 0x01; | |
3678 | else | |
3679 | ld_flag = 0x0; | |
3680 | else | |
3681 | if (size_bits != 0x03) | |
3682 | ld_flag = 0x01; | |
3683 | else | |
3684 | return AARCH64_RECORD_UNKNOWN; | |
3685 | ||
3686 | if (!ld_flag) | |
3687 | { | |
d9436c7c PA |
3688 | ULONGEST reg_rm_val; |
3689 | ||
99afc88b OJ |
3690 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, |
3691 | bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val); | |
3692 | if (bit (aarch64_insn_r->aarch64_insn, 12)) | |
3693 | offset = reg_rm_val << size_bits; | |
3694 | else | |
3695 | offset = reg_rm_val; | |
3696 | datasize = 8 << size_bits; | |
3697 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3698 | &address); | |
3699 | address = address + offset; | |
3700 | record_buf_mem[0] = datasize >> 3; | |
3701 | record_buf_mem[1] = address; | |
3702 | aarch64_insn_r->mem_rec_count = 1; | |
3703 | } | |
3704 | else | |
3705 | { | |
3706 | if (vector_flag) | |
3707 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3708 | else | |
3709 | record_buf[0] = reg_rt; | |
3710 | aarch64_insn_r->reg_rec_count = 1; | |
3711 | } | |
3712 | } | |
3713 | /* Load/store register (immediate and unprivileged) instructions. */ | |
5d98d3cd YQ |
3714 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3715 | && !insn_bit21) | |
99afc88b OJ |
3716 | { |
3717 | if (record_debug) | |
3718 | { | |
b277c936 PL |
3719 | debug_printf ("Process record: load/store " |
3720 | "(immediate and unprivileged)\n"); | |
99afc88b OJ |
3721 | } |
3722 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3723 | if (!(opc >> 1)) | |
3724 | if (opc & 0x01) | |
3725 | ld_flag = 0x01; | |
3726 | else | |
3727 | ld_flag = 0x0; | |
3728 | else | |
3729 | if (size_bits != 0x03) | |
3730 | ld_flag = 0x01; | |
3731 | else | |
3732 | return AARCH64_RECORD_UNKNOWN; | |
3733 | ||
3734 | if (!ld_flag) | |
3735 | { | |
3736 | uint16_t imm9_off; | |
3737 | imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20); | |
3738 | offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off; | |
3739 | datasize = 8 << size_bits; | |
3740 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3741 | &address); | |
3742 | if (insn_bits10_11 != 0x01) | |
3743 | { | |
3744 | if (imm9_off & 0x0100) | |
3745 | address = address - offset; | |
3746 | else | |
3747 | address = address + offset; | |
3748 | } | |
3749 | record_buf_mem[0] = datasize >> 3; | |
3750 | record_buf_mem[1] = address; | |
3751 | aarch64_insn_r->mem_rec_count = 1; | |
3752 | } | |
3753 | else | |
3754 | { | |
3755 | if (vector_flag) | |
3756 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3757 | else | |
3758 | record_buf[0] = reg_rt; | |
3759 | aarch64_insn_r->reg_rec_count = 1; | |
3760 | } | |
3761 | if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) | |
3762 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3763 | } | |
3764 | /* Advanced SIMD load/store instructions. */ | |
3765 | else | |
3766 | return aarch64_record_asimd_load_store (aarch64_insn_r); | |
3767 | ||
3768 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3769 | record_buf_mem); | |
3770 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3771 | record_buf); | |
3772 | return AARCH64_RECORD_SUCCESS; | |
3773 | } | |
3774 | ||
3775 | /* Record handler for data processing SIMD and floating point instructions. */ | |
3776 | ||
3777 | static unsigned int | |
3778 | aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) | |
3779 | { | |
3780 | uint8_t insn_bit21, opcode, rmode, reg_rd; | |
3781 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; | |
3782 | uint8_t insn_bits11_14; | |
3783 | uint32_t record_buf[2]; | |
3784 | ||
3785 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3786 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3787 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3788 | insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3789 | insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); | |
3790 | opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); | |
3791 | rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); | |
3792 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3793 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3794 | ||
3795 | if (record_debug) | |
b277c936 | 3796 | debug_printf ("Process record: data processing SIMD/FP: "); |
99afc88b OJ |
3797 | |
3798 | if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) | |
3799 | { | |
3800 | /* Floating point - fixed point conversion instructions. */ | |
3801 | if (!insn_bit21) | |
3802 | { | |
3803 | if (record_debug) | |
b277c936 | 3804 | debug_printf ("FP - fixed point conversion"); |
99afc88b OJ |
3805 | |
3806 | if ((opcode >> 1) == 0x0 && rmode == 0x03) | |
3807 | record_buf[0] = reg_rd; | |
3808 | else | |
3809 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3810 | } | |
3811 | /* Floating point - conditional compare instructions. */ | |
3812 | else if (insn_bits10_11 == 0x01) | |
3813 | { | |
3814 | if (record_debug) | |
b277c936 | 3815 | debug_printf ("FP - conditional compare"); |
99afc88b OJ |
3816 | |
3817 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3818 | } | |
3819 | /* Floating point - data processing (2-source) and | |
3820 | conditional select instructions. */ | |
3821 | else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) | |
3822 | { | |
3823 | if (record_debug) | |
b277c936 | 3824 | debug_printf ("FP - DP (2-source)"); |
99afc88b OJ |
3825 | |
3826 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3827 | } | |
3828 | else if (insn_bits10_11 == 0x00) | |
3829 | { | |
3830 | /* Floating point - immediate instructions. */ | |
3831 | if ((insn_bits12_15 & 0x01) == 0x01 | |
3832 | || (insn_bits12_15 & 0x07) == 0x04) | |
3833 | { | |
3834 | if (record_debug) | |
b277c936 | 3835 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3836 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; |
3837 | } | |
3838 | /* Floating point - compare instructions. */ | |
3839 | else if ((insn_bits12_15 & 0x03) == 0x02) | |
3840 | { | |
3841 | if (record_debug) | |
b277c936 | 3842 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3843 | record_buf[0] = AARCH64_CPSR_REGNUM; |
3844 | } | |
3845 | /* Floating point - integer conversions instructions. */ | |
f62fce35 | 3846 | else if (insn_bits12_15 == 0x00) |
99afc88b OJ |
3847 | { |
3848 | /* Convert float to integer instruction. */ | |
3849 | if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) | |
3850 | { | |
3851 | if (record_debug) | |
b277c936 | 3852 | debug_printf ("float to int conversion"); |
99afc88b OJ |
3853 | |
3854 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3855 | } | |
3856 | /* Convert integer to float instruction. */ | |
3857 | else if ((opcode >> 1) == 0x01 && !rmode) | |
3858 | { | |
3859 | if (record_debug) | |
b277c936 | 3860 | debug_printf ("int to float conversion"); |
99afc88b OJ |
3861 | |
3862 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3863 | } | |
3864 | /* Move float to integer instruction. */ | |
3865 | else if ((opcode >> 1) == 0x03) | |
3866 | { | |
3867 | if (record_debug) | |
b277c936 | 3868 | debug_printf ("move float to int"); |
99afc88b OJ |
3869 | |
3870 | if (!(opcode & 0x01)) | |
3871 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3872 | else | |
3873 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3874 | } | |
f62fce35 YQ |
3875 | else |
3876 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 3877 | } |
f62fce35 YQ |
3878 | else |
3879 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 3880 | } |
f62fce35 YQ |
3881 | else |
3882 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
3883 | } |
3884 | else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) | |
3885 | { | |
3886 | if (record_debug) | |
b277c936 | 3887 | debug_printf ("SIMD copy"); |
99afc88b OJ |
3888 | |
3889 | /* Advanced SIMD copy instructions. */ | |
3890 | if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3891 | && !bit (aarch64_insn_r->aarch64_insn, 15) | |
3892 | && bit (aarch64_insn_r->aarch64_insn, 10)) | |
3893 | { | |
3894 | if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) | |
3895 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3896 | else | |
3897 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3898 | } | |
3899 | else | |
3900 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3901 | } | |
3902 | /* All remaining floating point or advanced SIMD instructions. */ | |
3903 | else | |
3904 | { | |
3905 | if (record_debug) | |
b277c936 | 3906 | debug_printf ("all remain"); |
99afc88b OJ |
3907 | |
3908 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3909 | } | |
3910 | ||
3911 | if (record_debug) | |
b277c936 | 3912 | debug_printf ("\n"); |
99afc88b OJ |
3913 | |
3914 | aarch64_insn_r->reg_rec_count++; | |
3915 | gdb_assert (aarch64_insn_r->reg_rec_count == 1); | |
3916 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3917 | record_buf); | |
3918 | return AARCH64_RECORD_SUCCESS; | |
3919 | } | |
3920 | ||
3921 | /* Decodes insns type and invokes its record handler. */ | |
3922 | ||
3923 | static unsigned int | |
3924 | aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r) | |
3925 | { | |
3926 | uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; | |
3927 | ||
3928 | ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25); | |
3929 | ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26); | |
3930 | ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27); | |
3931 | ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28); | |
3932 | ||
3933 | /* Data processing - immediate instructions. */ | |
3934 | if (!ins_bit26 && !ins_bit27 && ins_bit28) | |
3935 | return aarch64_record_data_proc_imm (aarch64_insn_r); | |
3936 | ||
3937 | /* Branch, exception generation and system instructions. */ | |
3938 | if (ins_bit26 && !ins_bit27 && ins_bit28) | |
3939 | return aarch64_record_branch_except_sys (aarch64_insn_r); | |
3940 | ||
3941 | /* Load and store instructions. */ | |
3942 | if (!ins_bit25 && ins_bit27) | |
3943 | return aarch64_record_load_store (aarch64_insn_r); | |
3944 | ||
3945 | /* Data processing - register instructions. */ | |
3946 | if (ins_bit25 && !ins_bit26 && ins_bit27) | |
3947 | return aarch64_record_data_proc_reg (aarch64_insn_r); | |
3948 | ||
3949 | /* Data processing - SIMD and floating point instructions. */ | |
3950 | if (ins_bit25 && ins_bit26 && ins_bit27) | |
3951 | return aarch64_record_data_proc_simd_fp (aarch64_insn_r); | |
3952 | ||
3953 | return AARCH64_RECORD_UNSUPPORTED; | |
3954 | } | |
3955 | ||
3956 | /* Cleans up local record registers and memory allocations. */ | |
3957 | ||
3958 | static void | |
3959 | deallocate_reg_mem (insn_decode_record *record) | |
3960 | { | |
3961 | xfree (record->aarch64_regs); | |
3962 | xfree (record->aarch64_mems); | |
3963 | } | |
3964 | ||
1e2b521d YQ |
3965 | #if GDB_SELF_TEST |
3966 | namespace selftests { | |
3967 | ||
3968 | static void | |
3969 | aarch64_process_record_test (void) | |
3970 | { | |
3971 | struct gdbarch_info info; | |
3972 | uint32_t ret; | |
3973 | ||
3974 | gdbarch_info_init (&info); | |
3975 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
3976 | ||
3977 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
3978 | SELF_CHECK (gdbarch != NULL); | |
3979 | ||
3980 | insn_decode_record aarch64_record; | |
3981 | ||
3982 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
3983 | aarch64_record.regcache = NULL; | |
3984 | aarch64_record.this_addr = 0; | |
3985 | aarch64_record.gdbarch = gdbarch; | |
3986 | ||
3987 | /* 20 00 80 f9 prfm pldl1keep, [x1] */ | |
3988 | aarch64_record.aarch64_insn = 0xf9800020; | |
3989 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
3990 | SELF_CHECK (ret == AARCH64_RECORD_SUCCESS); | |
3991 | SELF_CHECK (aarch64_record.reg_rec_count == 0); | |
3992 | SELF_CHECK (aarch64_record.mem_rec_count == 0); | |
3993 | ||
3994 | deallocate_reg_mem (&aarch64_record); | |
3995 | } | |
3996 | ||
3997 | } // namespace selftests | |
3998 | #endif /* GDB_SELF_TEST */ | |
3999 | ||
99afc88b OJ |
4000 | /* Parse the current instruction and record the values of the registers and |
4001 | memory that will be changed in current instruction to record_arch_list | |
4002 | return -1 if something is wrong. */ | |
4003 | ||
4004 | int | |
4005 | aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
4006 | CORE_ADDR insn_addr) | |
4007 | { | |
4008 | uint32_t rec_no = 0; | |
4009 | uint8_t insn_size = 4; | |
4010 | uint32_t ret = 0; | |
99afc88b OJ |
4011 | gdb_byte buf[insn_size]; |
4012 | insn_decode_record aarch64_record; | |
4013 | ||
4014 | memset (&buf[0], 0, insn_size); | |
4015 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
4016 | target_read_memory (insn_addr, &buf[0], insn_size); | |
4017 | aarch64_record.aarch64_insn | |
4018 | = (uint32_t) extract_unsigned_integer (&buf[0], | |
4019 | insn_size, | |
4020 | gdbarch_byte_order (gdbarch)); | |
4021 | aarch64_record.regcache = regcache; | |
4022 | aarch64_record.this_addr = insn_addr; | |
4023 | aarch64_record.gdbarch = gdbarch; | |
4024 | ||
4025 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4026 | if (ret == AARCH64_RECORD_UNSUPPORTED) | |
4027 | { | |
4028 | printf_unfiltered (_("Process record does not support instruction " | |
4029 | "0x%0x at address %s.\n"), | |
4030 | aarch64_record.aarch64_insn, | |
4031 | paddress (gdbarch, insn_addr)); | |
4032 | ret = -1; | |
4033 | } | |
4034 | ||
4035 | if (0 == ret) | |
4036 | { | |
4037 | /* Record registers. */ | |
4038 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4039 | AARCH64_PC_REGNUM); | |
4040 | /* Always record register CPSR. */ | |
4041 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4042 | AARCH64_CPSR_REGNUM); | |
4043 | if (aarch64_record.aarch64_regs) | |
4044 | for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++) | |
4045 | if (record_full_arch_list_add_reg (aarch64_record.regcache, | |
4046 | aarch64_record.aarch64_regs[rec_no])) | |
4047 | ret = -1; | |
4048 | ||
4049 | /* Record memories. */ | |
4050 | if (aarch64_record.aarch64_mems) | |
4051 | for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++) | |
4052 | if (record_full_arch_list_add_mem | |
4053 | ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr, | |
4054 | aarch64_record.aarch64_mems[rec_no].len)) | |
4055 | ret = -1; | |
4056 | ||
4057 | if (record_full_arch_list_add_end ()) | |
4058 | ret = -1; | |
4059 | } | |
4060 | ||
4061 | deallocate_reg_mem (&aarch64_record); | |
4062 | return ret; | |
4063 | } |