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Use ELF_SECTION_IN_SEGMENT to map segments
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
e2882c85 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
24#include "inferior.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
07b287a0
MS		 27#include "dis-asm.h"
28#include "regcache.h"
29#include "reggroups.h"
07b287a0
MS		 30#include "value.h"
31#include "arch-utils.h"
32#include "osabi.h"
33#include "frame-unwind.h"
34#include "frame-base.h"
35#include "trad-frame.h"
36#include "objfiles.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
41#include "user-regs.h"
42#include "language.h"
43#include "infcall.h"
ea873d8e
PL		 44#include "ax.h"
45#include "ax-gdb.h"
4d9a9006 46#include "selftest.h"
07b287a0
MS		 47
48#include "aarch64-tdep.h"
49
50#include "elf-bfd.h"
51#include "elf/aarch64.h"
52
07b287a0
MS		 53#include "vec.h"
54
99afc88b
OJ		 55#include "record.h"
56#include "record-full.h"
787749ea
PL		 57#include "arch/aarch64-insn.h"
58
f77ee802 59#include "opcode/aarch64.h"
325fac50 60#include <algorithm>
f77ee802
YQ		 61
62#define submask(x) ((1L << ((x) + 1)) - 1)
63#define bit(obj,st) (((obj) >> (st)) & 1)
64#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
65
07b287a0
MS		 66/* Pseudo register base numbers. */
67#define AARCH64_Q0_REGNUM 0
187f5d00 68#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
07b287a0
MS		 69#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
72
95228a0d
AH		 73/* All possible aarch64 target descriptors. */
74struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1];
75
07b287a0
MS		 76/* The standard register names, and all the valid aliases for them. */
77static const struct
78{
79 const char *const name;
80 int regnum;
81} aarch64_register_aliases[] =
82{
83 /* 64-bit register names. */
84 {"fp", AARCH64_FP_REGNUM},
85 {"lr", AARCH64_LR_REGNUM},
86 {"sp", AARCH64_SP_REGNUM},
87
88 /* 32-bit register names. */
89 {"w0", AARCH64_X0_REGNUM + 0},
90 {"w1", AARCH64_X0_REGNUM + 1},
91 {"w2", AARCH64_X0_REGNUM + 2},
92 {"w3", AARCH64_X0_REGNUM + 3},
93 {"w4", AARCH64_X0_REGNUM + 4},
94 {"w5", AARCH64_X0_REGNUM + 5},
95 {"w6", AARCH64_X0_REGNUM + 6},
96 {"w7", AARCH64_X0_REGNUM + 7},
97 {"w8", AARCH64_X0_REGNUM + 8},
98 {"w9", AARCH64_X0_REGNUM + 9},
99 {"w10", AARCH64_X0_REGNUM + 10},
100 {"w11", AARCH64_X0_REGNUM + 11},
101 {"w12", AARCH64_X0_REGNUM + 12},
102 {"w13", AARCH64_X0_REGNUM + 13},
103 {"w14", AARCH64_X0_REGNUM + 14},
104 {"w15", AARCH64_X0_REGNUM + 15},
105 {"w16", AARCH64_X0_REGNUM + 16},
106 {"w17", AARCH64_X0_REGNUM + 17},
107 {"w18", AARCH64_X0_REGNUM + 18},
108 {"w19", AARCH64_X0_REGNUM + 19},
109 {"w20", AARCH64_X0_REGNUM + 20},
110 {"w21", AARCH64_X0_REGNUM + 21},
111 {"w22", AARCH64_X0_REGNUM + 22},
112 {"w23", AARCH64_X0_REGNUM + 23},
113 {"w24", AARCH64_X0_REGNUM + 24},
114 {"w25", AARCH64_X0_REGNUM + 25},
115 {"w26", AARCH64_X0_REGNUM + 26},
116 {"w27", AARCH64_X0_REGNUM + 27},
117 {"w28", AARCH64_X0_REGNUM + 28},
118 {"w29", AARCH64_X0_REGNUM + 29},
119 {"w30", AARCH64_X0_REGNUM + 30},
120
121 /* specials */
122 {"ip0", AARCH64_X0_REGNUM + 16},
123 {"ip1", AARCH64_X0_REGNUM + 17}
124};
125
126/* The required core 'R' registers. */
127static const char *const aarch64_r_register_names[] =
128{
129 /* These registers must appear in consecutive RAW register number
130 order and they must begin with AARCH64_X0_REGNUM! */
131 "x0", "x1", "x2", "x3",
132 "x4", "x5", "x6", "x7",
133 "x8", "x9", "x10", "x11",
134 "x12", "x13", "x14", "x15",
135 "x16", "x17", "x18", "x19",
136 "x20", "x21", "x22", "x23",
137 "x24", "x25", "x26", "x27",
138 "x28", "x29", "x30", "sp",
139 "pc", "cpsr"
140};
141
142/* The FP/SIMD 'V' registers. */
143static const char *const aarch64_v_register_names[] =
144{
145 /* These registers must appear in consecutive RAW register number
146 order and they must begin with AARCH64_V0_REGNUM! */
147 "v0", "v1", "v2", "v3",
148 "v4", "v5", "v6", "v7",
149 "v8", "v9", "v10", "v11",
150 "v12", "v13", "v14", "v15",
151 "v16", "v17", "v18", "v19",
152 "v20", "v21", "v22", "v23",
153 "v24", "v25", "v26", "v27",
154 "v28", "v29", "v30", "v31",
155 "fpsr",
156 "fpcr"
157};
158
739e8682
AH		 159/* The SVE 'Z' and 'P' registers. */
160static const char *const aarch64_sve_register_names[] =
161{
162 /* These registers must appear in consecutive RAW register number
163 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
164 "z0", "z1", "z2", "z3",
165 "z4", "z5", "z6", "z7",
166 "z8", "z9", "z10", "z11",
167 "z12", "z13", "z14", "z15",
168 "z16", "z17", "z18", "z19",
169 "z20", "z21", "z22", "z23",
170 "z24", "z25", "z26", "z27",
171 "z28", "z29", "z30", "z31",
172 "fpsr", "fpcr",
173 "p0", "p1", "p2", "p3",
174 "p4", "p5", "p6", "p7",
175 "p8", "p9", "p10", "p11",
176 "p12", "p13", "p14", "p15",
177 "ffr", "vg"
178};
179
07b287a0
MS		 180/* AArch64 prologue cache structure. */
181struct aarch64_prologue_cache
182{
db634143
PL		 183 /* The program counter at the start of the function. It is used to
184 identify this frame as a prologue frame. */
185 CORE_ADDR func;
186
187 /* The program counter at the time this frame was created; i.e. where
188 this function was called from. It is used to identify this frame as a
189 stub frame. */
190 CORE_ADDR prev_pc;
191
07b287a0
MS		 192 /* The stack pointer at the time this frame was created; i.e. the
193 caller's stack pointer when this function was called. It is used
194 to identify this frame. */
195 CORE_ADDR prev_sp;
196
7dfa3edc
PL		 197 /* Is the target available to read from? */
198 int available_p;
199
07b287a0
MS		 200 /* The frame base for this frame is just prev_sp - frame size.
201 FRAMESIZE is the distance from the frame pointer to the
202 initial stack pointer. */
203 int framesize;
204
205 /* The register used to hold the frame pointer for this frame. */
206 int framereg;
207
208 /* Saved register offsets. */
209 struct trad_frame_saved_reg *saved_regs;
210};
211
07b287a0
MS		 212static void
213show_aarch64_debug (struct ui_file *file, int from_tty,
214 struct cmd_list_element *c, const char *value)
215{
216 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
217}
218
ffdbe864
YQ		 219namespace {
220
4d9a9006
YQ		 221/* Abstract instruction reader. */
222
223class abstract_instruction_reader
224{
225public:
226 /* Read in one instruction. */
227 virtual ULONGEST read (CORE_ADDR memaddr, int len,
228 enum bfd_endian byte_order) = 0;
229};
230
231/* Instruction reader from real target. */
232
233class instruction_reader : public abstract_instruction_reader
234{
235 public:
236 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 237 override
4d9a9006 238 {
fc2f703e 239 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 240 }
241};
242
ffdbe864
YQ		 243} // namespace
244
07b287a0
MS		 245/* Analyze a prologue, looking for a recognizable stack frame
246 and frame pointer. Scan until we encounter a store that could
247 clobber the stack frame unexpectedly, or an unknown instruction. */
248
249static CORE_ADDR
250aarch64_analyze_prologue (struct gdbarch *gdbarch,
251 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 252 struct aarch64_prologue_cache *cache,
253 abstract_instruction_reader& reader)
07b287a0
MS		 254{
255 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
256 int i;
187f5d00
YQ		 257 /* Track X registers and D registers in prologue. */
258 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 259
187f5d00 260 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 261 regs[i] = pv_register (i, 0);
f7b7ed97 262 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 263
264 for (; start < limit; start += 4)
265 {
266 uint32_t insn;
d9ebcbce 267 aarch64_inst inst;
07b287a0 268
4d9a9006 269 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 270
561a72d4 271 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 272 break;
273
274 if (inst.opcode->iclass == addsub_imm
275 && (inst.opcode->op == OP_ADD
276 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 277 {
d9ebcbce
YQ		 278 unsigned rd = inst.operands[0].reg.regno;
279 unsigned rn = inst.operands[1].reg.regno;
280
281 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
282 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
283 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
284 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
285
286 if (inst.opcode->op == OP_ADD)
287 {
288 regs[rd] = pv_add_constant (regs[rn],
289 inst.operands[2].imm.value);
290 }
291 else
292 {
293 regs[rd] = pv_add_constant (regs[rn],
294 -inst.operands[2].imm.value);
295 }
296 }
297 else if (inst.opcode->iclass == pcreladdr
298 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
299 {
300 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
301 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
302
303 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 304 }
d9ebcbce 305 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 306 {
307 /* Stop analysis on branch. */
308 break;
309 }
d9ebcbce 310 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 311 {
312 /* Stop analysis on branch. */
313 break;
314 }
d9ebcbce 315 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 316 {
317 /* Stop analysis on branch. */
318 break;
319 }
d9ebcbce 320 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 321 {
322 /* Stop analysis on branch. */
323 break;
324 }
d9ebcbce
YQ		 325 else if (inst.opcode->op == OP_MOVZ)
326 {
327 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
328 regs[inst.operands[0].reg.regno] = pv_unknown ();
329 }
330 else if (inst.opcode->iclass == log_shift
331 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 332 {
d9ebcbce
YQ		 333 unsigned rd = inst.operands[0].reg.regno;
334 unsigned rn = inst.operands[1].reg.regno;
335 unsigned rm = inst.operands[2].reg.regno;
336
337 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
338 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
339 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
340
341 if (inst.operands[2].shifter.amount == 0
342 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 343 regs[rd] = regs[rm];
344 else
345 {
346 if (aarch64_debug)
b277c936
PL		 347 {
348 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 349 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 350 core_addr_to_string_nz (start), insn);
351 }
07b287a0
MS		 352 break;
353 }
354 }
d9ebcbce 355 else if (inst.opcode->op == OP_STUR)
07b287a0 356 {
d9ebcbce
YQ		 357 unsigned rt = inst.operands[0].reg.regno;
358 unsigned rn = inst.operands[1].addr.base_regno;
359 int is64
360 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
361
362 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
363 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
364 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
365 gdb_assert (!inst.operands[1].addr.offset.is_reg);
366
f7b7ed97
TT		 367 stack.store (pv_add_constant (regs[rn],
368 inst.operands[1].addr.offset.imm),
369 is64 ? 8 : 4, regs[rt]);
07b287a0 370 }
d9ebcbce 371 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 372 || (inst.opcode->iclass == ldstpair_indexed
373 && inst.operands[2].addr.preind))
d9ebcbce 374 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 375 {
03bcd739 376 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 377 unsigned rt1;
378 unsigned rt2;
d9ebcbce
YQ		 379 unsigned rn = inst.operands[2].addr.base_regno;
380 int32_t imm = inst.operands[2].addr.offset.imm;
381
187f5d00
YQ		 382 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
383 || inst.operands[0].type == AARCH64_OPND_Ft);
384 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
385 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 386 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
387 gdb_assert (!inst.operands[2].addr.offset.is_reg);
388
07b287a0
MS		 389 /* If recording this store would invalidate the store area
390 (perhaps because rn is not known) then we should abandon
391 further prologue analysis. */
f7b7ed97 392 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 393 break;
394
f7b7ed97 395 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 396 break;
397
187f5d00
YQ		 398 rt1 = inst.operands[0].reg.regno;
399 rt2 = inst.operands[1].reg.regno;
400 if (inst.operands[0].type == AARCH64_OPND_Ft)
401 {
402 /* Only bottom 64-bit of each V register (D register) need
403 to be preserved. */
404 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
405 rt1 += AARCH64_X_REGISTER_COUNT;
406 rt2 += AARCH64_X_REGISTER_COUNT;
407 }
408
f7b7ed97
TT		 409 stack.store (pv_add_constant (regs[rn], imm), 8,
410 regs[rt1]);
411 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
412 regs[rt2]);
14ac654f 413
d9ebcbce 414 if (inst.operands[2].addr.writeback)
93d96012 415 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 416
07b287a0 417 }
432ec081
YQ		 418 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
419 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
420 && (inst.opcode->op == OP_STR_POS
421 || inst.opcode->op == OP_STRF_POS)))
422 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
423 && strcmp ("str", inst.opcode->name) == 0)
424 {
425 /* STR (immediate) */
426 unsigned int rt = inst.operands[0].reg.regno;
427 int32_t imm = inst.operands[1].addr.offset.imm;
428 unsigned int rn = inst.operands[1].addr.base_regno;
429 bool is64
430 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
431 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
432 || inst.operands[0].type == AARCH64_OPND_Ft);
433
434 if (inst.operands[0].type == AARCH64_OPND_Ft)
435 {
436 /* Only bottom 64-bit of each V register (D register) need
437 to be preserved. */
438 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
439 rt += AARCH64_X_REGISTER_COUNT;
440 }
441
f7b7ed97
TT		 442 stack.store (pv_add_constant (regs[rn], imm),
443 is64 ? 8 : 4, regs[rt]);
432ec081
YQ		 444 if (inst.operands[1].addr.writeback)
445 regs[rn] = pv_add_constant (regs[rn], imm);
446 }
d9ebcbce 447 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 448 {
449 /* Stop analysis on branch. */
450 break;
451 }
452 else
453 {
454 if (aarch64_debug)
b277c936 455 {
0a0da556 456 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 457 " opcode=0x%x\n",
458 core_addr_to_string_nz (start), insn);
459 }
07b287a0
MS		 460 break;
461 }
462 }
463
464 if (cache == NULL)
f7b7ed97 465 return start;
07b287a0
MS		 466
467 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
468 {
469 /* Frame pointer is fp. Frame size is constant. */
470 cache->framereg = AARCH64_FP_REGNUM;
471 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
472 }
473 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
474 {
475 /* Try the stack pointer. */
476 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
477 cache->framereg = AARCH64_SP_REGNUM;
478 }
479 else
480 {
481 /* We're just out of luck. We don't know where the frame is. */
482 cache->framereg = -1;
483 cache->framesize = 0;
484 }
485
486 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
487 {
488 CORE_ADDR offset;
489
f7b7ed97 490 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 491 cache->saved_regs[i].addr = offset;
492 }
493
187f5d00
YQ		 494 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
495 {
496 int regnum = gdbarch_num_regs (gdbarch);
497 CORE_ADDR offset;
498
f7b7ed97
TT		 499 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
500 &offset))
187f5d00
YQ		 501 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
502 }
503
07b287a0
MS		 504 return start;
505}
506
4d9a9006
YQ		 507static CORE_ADDR
508aarch64_analyze_prologue (struct gdbarch *gdbarch,
509 CORE_ADDR start, CORE_ADDR limit,
510 struct aarch64_prologue_cache *cache)
511{
512 instruction_reader reader;
513
514 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
515 reader);
516}
517
518#if GDB_SELF_TEST
519
520namespace selftests {
521
522/* Instruction reader from manually cooked instruction sequences. */
523
524class instruction_reader_test : public abstract_instruction_reader
525{
526public:
527 template<size_t SIZE>
528 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
529 : m_insns (insns), m_insns_size (SIZE)
530 {}
531
532 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 533 override
4d9a9006
YQ		 534 {
535 SELF_CHECK (len == 4);
536 SELF_CHECK (memaddr % 4 == 0);
537 SELF_CHECK (memaddr / 4 < m_insns_size);
538
539 return m_insns[memaddr / 4];
540 }
541
542private:
543 const uint32_t *m_insns;
544 size_t m_insns_size;
545};
546
547static void
548aarch64_analyze_prologue_test (void)
549{
550 struct gdbarch_info info;
551
552 gdbarch_info_init (&info);
553 info.bfd_arch_info = bfd_scan_arch ("aarch64");
554
555 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
556 SELF_CHECK (gdbarch != NULL);
557
558 /* Test the simple prologue in which frame pointer is used. */
559 {
560 struct aarch64_prologue_cache cache;
561 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
562
563 static const uint32_t insns[] = {
564 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
565 0x910003fd, /* mov x29, sp */
566 0x97ffffe6, /* bl 0x400580 */
567 };
568 instruction_reader_test reader (insns);
569
570 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
571 SELF_CHECK (end == 4 * 2);
572
573 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
574 SELF_CHECK (cache.framesize == 272);
575
576 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
577 {
578 if (i == AARCH64_FP_REGNUM)
579 SELF_CHECK (cache.saved_regs[i].addr == -272);
580 else if (i == AARCH64_LR_REGNUM)
581 SELF_CHECK (cache.saved_regs[i].addr == -264);
582 else
583 SELF_CHECK (cache.saved_regs[i].addr == -1);
584 }
585
586 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
587 {
588 int regnum = gdbarch_num_regs (gdbarch);
589
590 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
591 == -1);
592 }
593 }
432ec081
YQ		 594
595 /* Test a prologue in which STR is used and frame pointer is not
596 used. */
597 {
598 struct aarch64_prologue_cache cache;
599 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
600
601 static const uint32_t insns[] = {
602 0xf81d0ff3, /* str x19, [sp, #-48]! */
603 0xb9002fe0, /* str w0, [sp, #44] */
604 0xf90013e1, /* str x1, [sp, #32]*/
605 0xfd000fe0, /* str d0, [sp, #24] */
606 0xaa0203f3, /* mov x19, x2 */
607 0xf94013e0, /* ldr x0, [sp, #32] */
608 };
609 instruction_reader_test reader (insns);
610
611 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
612
613 SELF_CHECK (end == 4 * 5);
614
615 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
616 SELF_CHECK (cache.framesize == 48);
617
618 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
619 {
620 if (i == 1)
621 SELF_CHECK (cache.saved_regs[i].addr == -16);
622 else if (i == 19)
623 SELF_CHECK (cache.saved_regs[i].addr == -48);
624 else
625 SELF_CHECK (cache.saved_regs[i].addr == -1);
626 }
627
628 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
629 {
630 int regnum = gdbarch_num_regs (gdbarch);
631
632 if (i == 0)
633 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
634 == -24);
635 else
636 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
637 == -1);
638 }
639 }
4d9a9006
YQ		 640}
641} // namespace selftests
642#endif /* GDB_SELF_TEST */
643
07b287a0
MS		 644/* Implement the "skip_prologue" gdbarch method. */
645
646static CORE_ADDR
647aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
648{
07b287a0 649 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 650
651 /* See if we can determine the end of the prologue via the symbol
652 table. If so, then return either PC, or the PC after the
653 prologue, whichever is greater. */
654 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
655 {
656 CORE_ADDR post_prologue_pc
657 = skip_prologue_using_sal (gdbarch, func_addr);
658
659 if (post_prologue_pc != 0)
325fac50 660 return std::max (pc, post_prologue_pc);
07b287a0
MS		 661 }
662
663 /* Can't determine prologue from the symbol table, need to examine
664 instructions. */
665
666 /* Find an upper limit on the function prologue using the debug
667 information. If the debug information could not be used to
668 provide that bound, then use an arbitrary large number as the
669 upper bound. */
670 limit_pc = skip_prologue_using_sal (gdbarch, pc);
671 if (limit_pc == 0)
672 limit_pc = pc + 128; /* Magic. */
673
674 /* Try disassembling prologue. */
675 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
676}
677
678/* Scan the function prologue for THIS_FRAME and populate the prologue
679 cache CACHE. */
680
681static void
682aarch64_scan_prologue (struct frame_info *this_frame,
683 struct aarch64_prologue_cache *cache)
684{
685 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
686 CORE_ADDR prologue_start;
687 CORE_ADDR prologue_end;
688 CORE_ADDR prev_pc = get_frame_pc (this_frame);
689 struct gdbarch *gdbarch = get_frame_arch (this_frame);
690
db634143
PL		 691 cache->prev_pc = prev_pc;
692
07b287a0
MS		 693 /* Assume we do not find a frame. */
694 cache->framereg = -1;
695 cache->framesize = 0;
696
697 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
698 &prologue_end))
699 {
700 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
701
702 if (sal.line == 0)
703 {
704 /* No line info so use the current PC. */
705 prologue_end = prev_pc;
706 }
707 else if (sal.end < prologue_end)
708 {
709 /* The next line begins after the function end. */
710 prologue_end = sal.end;
711 }
712
325fac50 713 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 714 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
715 }
716 else
717 {
718 CORE_ADDR frame_loc;
07b287a0
MS		 719
720 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
721 if (frame_loc == 0)
722 return;
723
724 cache->framereg = AARCH64_FP_REGNUM;
725 cache->framesize = 16;
726 cache->saved_regs[29].addr = 0;
727 cache->saved_regs[30].addr = 8;
728 }
729}
730
7dfa3edc
PL		 731/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
732 function may throw an exception if the inferior's registers or memory is
733 not available. */
07b287a0 734
7dfa3edc
PL		 735static void
736aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
737 struct aarch64_prologue_cache *cache)
07b287a0 738{
07b287a0
MS		 739 CORE_ADDR unwound_fp;
740 int reg;
741
07b287a0
MS		 742 aarch64_scan_prologue (this_frame, cache);
743
744 if (cache->framereg == -1)
7dfa3edc 745 return;
07b287a0
MS		 746
747 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
748 if (unwound_fp == 0)
7dfa3edc 749 return;
07b287a0
MS		 750
751 cache->prev_sp = unwound_fp + cache->framesize;
752
753 /* Calculate actual addresses of saved registers using offsets
754 determined by aarch64_analyze_prologue. */
755 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
756 if (trad_frame_addr_p (cache->saved_regs, reg))
757 cache->saved_regs[reg].addr += cache->prev_sp;
758
db634143
PL		 759 cache->func = get_frame_func (this_frame);
760
7dfa3edc
PL		 761 cache->available_p = 1;
762}
763
764/* Allocate and fill in *THIS_CACHE with information about the prologue of
765 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
766 Return a pointer to the current aarch64_prologue_cache in
767 *THIS_CACHE. */
768
769static struct aarch64_prologue_cache *
770aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
771{
772 struct aarch64_prologue_cache *cache;
773
774 if (*this_cache != NULL)
9a3c8263 775 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 776
777 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
778 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
779 *this_cache = cache;
780
781 TRY
782 {
783 aarch64_make_prologue_cache_1 (this_frame, cache);
784 }
785 CATCH (ex, RETURN_MASK_ERROR)
786 {
787 if (ex.error != NOT_AVAILABLE_ERROR)
788 throw_exception (ex);
789 }
790 END_CATCH
791
07b287a0
MS		 792 return cache;
793}
794
7dfa3edc
PL		 795/* Implement the "stop_reason" frame_unwind method. */
796
797static enum unwind_stop_reason
798aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
799 void **this_cache)
800{
801 struct aarch64_prologue_cache *cache
802 = aarch64_make_prologue_cache (this_frame, this_cache);
803
804 if (!cache->available_p)
805 return UNWIND_UNAVAILABLE;
806
807 /* Halt the backtrace at "_start". */
808 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
809 return UNWIND_OUTERMOST;
810
811 /* We've hit a wall, stop. */
812 if (cache->prev_sp == 0)
813 return UNWIND_OUTERMOST;
814
815 return UNWIND_NO_REASON;
816}
817
07b287a0
MS		 818/* Our frame ID for a normal frame is the current function's starting
819 PC and the caller's SP when we were called. */
820
821static void
822aarch64_prologue_this_id (struct frame_info *this_frame,
823 void **this_cache, struct frame_id *this_id)
824{
7c8edfae
PL		 825 struct aarch64_prologue_cache *cache
826 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 827
7dfa3edc
PL		 828 if (!cache->available_p)
829 *this_id = frame_id_build_unavailable_stack (cache->func);
830 else
831 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 832}
833
834/* Implement the "prev_register" frame_unwind method. */
835
836static struct value *
837aarch64_prologue_prev_register (struct frame_info *this_frame,
838 void **this_cache, int prev_regnum)
839{
7c8edfae
PL		 840 struct aarch64_prologue_cache *cache
841 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 842
843 /* If we are asked to unwind the PC, then we need to return the LR
844 instead. The prologue may save PC, but it will point into this
845 frame's prologue, not the next frame's resume location. */
846 if (prev_regnum == AARCH64_PC_REGNUM)
847 {
848 CORE_ADDR lr;
849
850 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
851 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
852 }
853
854 /* SP is generally not saved to the stack, but this frame is
855 identified by the next frame's stack pointer at the time of the
856 call. The value was already reconstructed into PREV_SP. */
857 /*
858 +----------+ ^
859 | saved lr | |
860 +->| saved fp |--+
861 | | |
862 | | | <- Previous SP
863 | +----------+
864 | | saved lr |
865 +--| saved fp |<- FP
866 | |
867 | |<- SP
868 +----------+ */
869 if (prev_regnum == AARCH64_SP_REGNUM)
870 return frame_unwind_got_constant (this_frame, prev_regnum,
871 cache->prev_sp);
872
873 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
874 prev_regnum);
875}
876
877/* AArch64 prologue unwinder. */
878struct frame_unwind aarch64_prologue_unwind =
879{
880 NORMAL_FRAME,
7dfa3edc 881 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 882 aarch64_prologue_this_id,
883 aarch64_prologue_prev_register,
884 NULL,
885 default_frame_sniffer
886};
887
8b61f75d
PL		 888/* Allocate and fill in *THIS_CACHE with information about the prologue of
889 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
890 Return a pointer to the current aarch64_prologue_cache in
891 *THIS_CACHE. */
07b287a0
MS		 892
893static struct aarch64_prologue_cache *
8b61f75d 894aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 895{
07b287a0 896 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 897
898 if (*this_cache != NULL)
9a3c8263 899 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 900
901 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
902 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 903 *this_cache = cache;
07b287a0 904
02a2a705
PL		 905 TRY
906 {
907 cache->prev_sp = get_frame_register_unsigned (this_frame,
908 AARCH64_SP_REGNUM);
909 cache->prev_pc = get_frame_pc (this_frame);
910 cache->available_p = 1;
911 }
912 CATCH (ex, RETURN_MASK_ERROR)
913 {
914 if (ex.error != NOT_AVAILABLE_ERROR)
915 throw_exception (ex);
916 }
917 END_CATCH
07b287a0
MS		 918
919 return cache;
920}
921
02a2a705
PL		 922/* Implement the "stop_reason" frame_unwind method. */
923
924static enum unwind_stop_reason
925aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
926 void **this_cache)
927{
928 struct aarch64_prologue_cache *cache
929 = aarch64_make_stub_cache (this_frame, this_cache);
930
931 if (!cache->available_p)
932 return UNWIND_UNAVAILABLE;
933
934 return UNWIND_NO_REASON;
935}
936
07b287a0
MS		 937/* Our frame ID for a stub frame is the current SP and LR. */
938
939static void
940aarch64_stub_this_id (struct frame_info *this_frame,
941 void **this_cache, struct frame_id *this_id)
942{
8b61f75d
PL		 943 struct aarch64_prologue_cache *cache
944 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 945
02a2a705
PL		 946 if (cache->available_p)
947 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
948 else
949 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 950}
951
952/* Implement the "sniffer" frame_unwind method. */
953
954static int
955aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
956 struct frame_info *this_frame,
957 void **this_prologue_cache)
958{
959 CORE_ADDR addr_in_block;
960 gdb_byte dummy[4];
961
962 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 963 if (in_plt_section (addr_in_block)
07b287a0
MS		 964 /* We also use the stub winder if the target memory is unreadable
965 to avoid having the prologue unwinder trying to read it. */
966 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
967 return 1;
968
969 return 0;
970}
971
972/* AArch64 stub unwinder. */
973struct frame_unwind aarch64_stub_unwind =
974{
975 NORMAL_FRAME,
02a2a705 976 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 977 aarch64_stub_this_id,
978 aarch64_prologue_prev_register,
979 NULL,
980 aarch64_stub_unwind_sniffer
981};
982
983/* Return the frame base address of *THIS_FRAME. */
984
985static CORE_ADDR
986aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
987{
7c8edfae
PL		 988 struct aarch64_prologue_cache *cache
989 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 990
991 return cache->prev_sp - cache->framesize;
992}
993
994/* AArch64 default frame base information. */
995struct frame_base aarch64_normal_base =
996{
997 &aarch64_prologue_unwind,
998 aarch64_normal_frame_base,
999 aarch64_normal_frame_base,
1000 aarch64_normal_frame_base
1001};
1002
1003/* Assuming THIS_FRAME is a dummy, return the frame ID of that
1004 dummy frame. The frame ID's base needs to match the TOS value
1005 saved by save_dummy_frame_tos () and returned from
1006 aarch64_push_dummy_call, and the PC needs to match the dummy
1007 frame's breakpoint. */
1008
1009static struct frame_id
1010aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1011{
1012 return frame_id_build (get_frame_register_unsigned (this_frame,
1013 AARCH64_SP_REGNUM),
1014 get_frame_pc (this_frame));
1015}
1016
1017/* Implement the "unwind_pc" gdbarch method. */
1018
1019static CORE_ADDR
1020aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1021{
1022 CORE_ADDR pc
1023 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
1024
1025 return pc;
1026}
1027
1028/* Implement the "unwind_sp" gdbarch method. */
1029
1030static CORE_ADDR
1031aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1032{
1033 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
1034}
1035
1036/* Return the value of the REGNUM register in the previous frame of
1037 *THIS_FRAME. */
1038
1039static struct value *
1040aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1041 void **this_cache, int regnum)
1042{
07b287a0
MS		 1043 CORE_ADDR lr;
1044
1045 switch (regnum)
1046 {
1047 case AARCH64_PC_REGNUM:
1048 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1049 return frame_unwind_got_constant (this_frame, regnum, lr);
1050
1051 default:
1052 internal_error (__FILE__, __LINE__,
1053 _("Unexpected register %d"), regnum);
1054 }
1055}
1056
1057/* Implement the "init_reg" dwarf2_frame_ops method. */
1058
1059static void
1060aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1061 struct dwarf2_frame_state_reg *reg,
1062 struct frame_info *this_frame)
1063{
1064 switch (regnum)
1065 {
1066 case AARCH64_PC_REGNUM:
1067 reg->how = DWARF2_FRAME_REG_FN;
1068 reg->loc.fn = aarch64_dwarf2_prev_register;
1069 break;
1070 case AARCH64_SP_REGNUM:
1071 reg->how = DWARF2_FRAME_REG_CFA;
1072 break;
1073 }
1074}
1075
1076/* When arguments must be pushed onto the stack, they go on in reverse
1077 order. The code below implements a FILO (stack) to do this. */
1078
1079typedef struct
1080{
c3c87445
YQ		 1081 /* Value to pass on stack. It can be NULL if this item is for stack
1082 padding. */
7c543f7b 1083 const gdb_byte *data;
07b287a0
MS		 1084
1085 /* Size in bytes of value to pass on stack. */
1086 int len;
1087} stack_item_t;
1088
1089DEF_VEC_O (stack_item_t);
1090
1091/* Return the alignment (in bytes) of the given type. */
1092
1093static int
1094aarch64_type_align (struct type *t)
1095{
1096 int n;
1097 int align;
1098 int falign;
1099
1100 t = check_typedef (t);
1101 switch (TYPE_CODE (t))
1102 {
1103 default:
1104 /* Should never happen. */
1105 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1106 return 4;
1107
1108 case TYPE_CODE_PTR:
1109 case TYPE_CODE_ENUM:
1110 case TYPE_CODE_INT:
1111 case TYPE_CODE_FLT:
1112 case TYPE_CODE_SET:
1113 case TYPE_CODE_RANGE:
1114 case TYPE_CODE_BITSTRING:
1115 case TYPE_CODE_REF:
aa006118 1116 case TYPE_CODE_RVALUE_REF:
07b287a0
MS		 1117 case TYPE_CODE_CHAR:
1118 case TYPE_CODE_BOOL:
1119 return TYPE_LENGTH (t);
1120
1121 case TYPE_CODE_ARRAY:
238f2452
YQ		 1122 if (TYPE_VECTOR (t))
1123 {
1124 /* Use the natural alignment for vector types (the same for
1125 scalar type), but the maximum alignment is 128-bit. */
1126 if (TYPE_LENGTH (t) > 16)
1127 return 16;
1128 else
1129 return TYPE_LENGTH (t);
1130 }
1131 else
1132 return aarch64_type_align (TYPE_TARGET_TYPE (t));
07b287a0
MS		 1133 case TYPE_CODE_COMPLEX:
1134 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1135
1136 case TYPE_CODE_STRUCT:
1137 case TYPE_CODE_UNION:
1138 align = 1;
1139 for (n = 0; n < TYPE_NFIELDS (t); n++)
1140 {
1141 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1142 if (falign > align)
1143 align = falign;
1144 }
1145 return align;
1146 }
1147}
1148
cd635f74
YQ		 1149/* Return 1 if *TY is a homogeneous floating-point aggregate or
1150 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1151 document; otherwise return 0. */
07b287a0
MS		 1152
1153static int
cd635f74 1154is_hfa_or_hva (struct type *ty)
07b287a0
MS		 1155{
1156 switch (TYPE_CODE (ty))
1157 {
1158 case TYPE_CODE_ARRAY:
1159 {
1160 struct type *target_ty = TYPE_TARGET_TYPE (ty);
238f2452
YQ		 1161
1162 if (TYPE_VECTOR (ty))
1163 return 0;
1164
cd635f74
YQ		 1165 if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */
1166 && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */
1167 || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */
1168 && TYPE_VECTOR (target_ty))))
07b287a0
MS		 1169 return 1;
1170 break;
1171 }
1172
1173 case TYPE_CODE_UNION:
1174 case TYPE_CODE_STRUCT:
1175 {
cd635f74 1176 /* HFA or HVA has at most four members. */
07b287a0
MS		 1177 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
1178 {
1179 struct type *member0_type;
1180
1181 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
cd635f74
YQ		 1182 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT
1183 || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY
1184 && TYPE_VECTOR (member0_type)))
07b287a0
MS		 1185 {
1186 int i;
1187
1188 for (i = 0; i < TYPE_NFIELDS (ty); i++)
1189 {
1190 struct type *member1_type;
1191
1192 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
1193 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
1194 || (TYPE_LENGTH (member0_type)
1195 != TYPE_LENGTH (member1_type)))
1196 return 0;
1197 }
1198 return 1;
1199 }
1200 }
1201 return 0;
1202 }
1203
1204 default:
1205 break;
1206 }
1207
1208 return 0;
1209}
1210
1211/* AArch64 function call information structure. */
1212struct aarch64_call_info
1213{
1214 /* the current argument number. */
1215 unsigned argnum;
1216
1217 /* The next general purpose register number, equivalent to NGRN as
1218 described in the AArch64 Procedure Call Standard. */
1219 unsigned ngrn;
1220
1221 /* The next SIMD and floating point register number, equivalent to
1222 NSRN as described in the AArch64 Procedure Call Standard. */
1223 unsigned nsrn;
1224
1225 /* The next stacked argument address, equivalent to NSAA as
1226 described in the AArch64 Procedure Call Standard. */
1227 unsigned nsaa;
1228
1229 /* Stack item vector. */
1230 VEC(stack_item_t) *si;
1231};
1232
1233/* Pass a value in a sequence of consecutive X registers. The caller
1234 is responsbile for ensuring sufficient registers are available. */
1235
1236static void
1237pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1238 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1239 struct value *arg)
07b287a0
MS		 1240{
1241 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1242 int len = TYPE_LENGTH (type);
1243 enum type_code typecode = TYPE_CODE (type);
1244 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1245 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1246
1247 info->argnum++;
1248
1249 while (len > 0)
1250 {
1251 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1252 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1253 byte_order);
1254
1255
1256 /* Adjust sub-word struct/union args when big-endian. */
1257 if (byte_order == BFD_ENDIAN_BIG
1258 && partial_len < X_REGISTER_SIZE
1259 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1260 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1261
1262 if (aarch64_debug)
b277c936
PL		 1263 {
1264 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1265 gdbarch_register_name (gdbarch, regnum),
1266 phex (regval, X_REGISTER_SIZE));
1267 }
07b287a0
MS		 1268 regcache_cooked_write_unsigned (regcache, regnum, regval);
1269 len -= partial_len;
1270 buf += partial_len;
1271 regnum++;
1272 }
1273}
1274
1275/* Attempt to marshall a value in a V register. Return 1 if
1276 successful, or 0 if insufficient registers are available. This
1277 function, unlike the equivalent pass_in_x() function does not
1278 handle arguments spread across multiple registers. */
1279
1280static int
1281pass_in_v (struct gdbarch *gdbarch,
1282 struct regcache *regcache,
1283 struct aarch64_call_info *info,
0735fddd 1284 int len, const bfd_byte *buf)
07b287a0
MS		 1285{
1286 if (info->nsrn < 8)
1287 {
07b287a0 1288 int regnum = AARCH64_V0_REGNUM + info->nsrn;
0735fddd 1289 gdb_byte reg[V_REGISTER_SIZE];
07b287a0
MS		 1290
1291 info->argnum++;
1292 info->nsrn++;
1293
0735fddd
YQ		 1294 memset (reg, 0, sizeof (reg));
1295 /* PCS C.1, the argument is allocated to the least significant
1296 bits of V register. */
1297 memcpy (reg, buf, len);
b66f5587 1298 regcache->cooked_write (regnum, reg);
0735fddd 1299
07b287a0 1300 if (aarch64_debug)
b277c936
PL		 1301 {
1302 debug_printf ("arg %d in %s\n", info->argnum,
1303 gdbarch_register_name (gdbarch, regnum));
1304 }
07b287a0
MS		 1305 return 1;
1306 }
1307 info->nsrn = 8;
1308 return 0;
1309}
1310
1311/* Marshall an argument onto the stack. */
1312
1313static void
1314pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1315 struct value *arg)
07b287a0 1316{
8e80f9d1 1317 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1318 int len = TYPE_LENGTH (type);
1319 int align;
1320 stack_item_t item;
1321
1322 info->argnum++;
1323
1324 align = aarch64_type_align (type);
1325
1326 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1327 Natural alignment of the argument's type. */
1328 align = align_up (align, 8);
1329
1330 /* The AArch64 PCS requires at most doubleword alignment. */
1331 if (align > 16)
1332 align = 16;
1333
1334 if (aarch64_debug)
b277c936
PL		 1335 {
1336 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1337 info->nsaa);
1338 }
07b287a0
MS		 1339
1340 item.len = len;
1341 item.data = buf;
1342 VEC_safe_push (stack_item_t, info->si, &item);
1343
1344 info->nsaa += len;
1345 if (info->nsaa & (align - 1))
1346 {
1347 /* Push stack alignment padding. */
1348 int pad = align - (info->nsaa & (align - 1));
1349
1350 item.len = pad;
c3c87445 1351 item.data = NULL;
07b287a0
MS		 1352
1353 VEC_safe_push (stack_item_t, info->si, &item);
1354 info->nsaa += pad;
1355 }
1356}
1357
1358/* Marshall an argument into a sequence of one or more consecutive X
1359 registers or, if insufficient X registers are available then onto
1360 the stack. */
1361
1362static void
1363pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1364 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1365 struct value *arg)
07b287a0
MS		 1366{
1367 int len = TYPE_LENGTH (type);
1368 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1369
1370 /* PCS C.13 - Pass in registers if we have enough spare */
1371 if (info->ngrn + nregs <= 8)
1372 {
8e80f9d1 1373 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1374 info->ngrn += nregs;
1375 }
1376 else
1377 {
1378 info->ngrn = 8;
8e80f9d1 1379 pass_on_stack (info, type, arg);
07b287a0
MS		 1380 }
1381}
1382
1383/* Pass a value in a V register, or on the stack if insufficient are
1384 available. */
1385
1386static void
1387pass_in_v_or_stack (struct gdbarch *gdbarch,
1388 struct regcache *regcache,
1389 struct aarch64_call_info *info,
1390 struct type *type,
8e80f9d1 1391 struct value *arg)
07b287a0 1392{
0735fddd
YQ		 1393 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type),
1394 value_contents (arg)))
8e80f9d1 1395 pass_on_stack (info, type, arg);
07b287a0
MS		 1396}
1397
1398/* Implement the "push_dummy_call" gdbarch method. */
1399
1400static CORE_ADDR
1401aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402 struct regcache *regcache, CORE_ADDR bp_addr,
1403 int nargs,
1404 struct value **args, CORE_ADDR sp, int struct_return,
1405 CORE_ADDR struct_addr)
1406{
07b287a0 1407 int argnum;
07b287a0
MS		 1408 struct aarch64_call_info info;
1409 struct type *func_type;
1410 struct type *return_type;
1411 int lang_struct_return;
1412
1413 memset (&info, 0, sizeof (info));
1414
1415 /* We need to know what the type of the called function is in order
1416 to determine the number of named/anonymous arguments for the
1417 actual argument placement, and the return type in order to handle
1418 return value correctly.
1419
1420 The generic code above us views the decision of return in memory
1421 or return in registers as a two stage processes. The language
1422 handler is consulted first and may decide to return in memory (eg
1423 class with copy constructor returned by value), this will cause
1424 the generic code to allocate space AND insert an initial leading
1425 argument.
1426
1427 If the language code does not decide to pass in memory then the
1428 target code is consulted.
1429
1430 If the language code decides to pass in memory we want to move
1431 the pointer inserted as the initial argument from the argument
1432 list and into X8, the conventional AArch64 struct return pointer
1433 register.
1434
1435 This is slightly awkward, ideally the flag "lang_struct_return"
1436 would be passed to the targets implementation of push_dummy_call.
1437 Rather that change the target interface we call the language code
1438 directly ourselves. */
1439
1440 func_type = check_typedef (value_type (function));
1441
1442 /* Dereference function pointer types. */
1443 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1444 func_type = TYPE_TARGET_TYPE (func_type);
1445
1446 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1447 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1448
1449 /* If language_pass_by_reference () returned true we will have been
1450 given an additional initial argument, a hidden pointer to the
1451 return slot in memory. */
1452 return_type = TYPE_TARGET_TYPE (func_type);
1453 lang_struct_return = language_pass_by_reference (return_type);
1454
1455 /* Set the return address. For the AArch64, the return breakpoint
1456 is always at BP_ADDR. */
1457 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1458
1459 /* If we were given an initial argument for the return slot because
1460 lang_struct_return was true, lose it. */
1461 if (lang_struct_return)
1462 {
1463 args++;
1464 nargs--;
1465 }
1466
1467 /* The struct_return pointer occupies X8. */
1468 if (struct_return || lang_struct_return)
1469 {
1470 if (aarch64_debug)
b277c936
PL		 1471 {
1472 debug_printf ("struct return in %s = 0x%s\n",
1473 gdbarch_register_name (gdbarch,
1474 AARCH64_STRUCT_RETURN_REGNUM),
1475 paddress (gdbarch, struct_addr));
1476 }
07b287a0
MS		 1477 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1478 struct_addr);
1479 }
1480
1481 for (argnum = 0; argnum < nargs; argnum++)
1482 {
1483 struct value *arg = args[argnum];
1484 struct type *arg_type;
1485 int len;
1486
1487 arg_type = check_typedef (value_type (arg));
1488 len = TYPE_LENGTH (arg_type);
1489
1490 switch (TYPE_CODE (arg_type))
1491 {
1492 case TYPE_CODE_INT:
1493 case TYPE_CODE_BOOL:
1494 case TYPE_CODE_CHAR:
1495 case TYPE_CODE_RANGE:
1496 case TYPE_CODE_ENUM:
1497 if (len < 4)
1498 {
1499 /* Promote to 32 bit integer. */
1500 if (TYPE_UNSIGNED (arg_type))
1501 arg_type = builtin_type (gdbarch)->builtin_uint32;
1502 else
1503 arg_type = builtin_type (gdbarch)->builtin_int32;
1504 arg = value_cast (arg_type, arg);
1505 }
8e80f9d1 1506 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1507 break;
1508
1509 case TYPE_CODE_COMPLEX:
1510 if (info.nsrn <= 6)
1511 {
1512 const bfd_byte *buf = value_contents (arg);
1513 struct type *target_type =
1514 check_typedef (TYPE_TARGET_TYPE (arg_type));
1515
07b287a0 1516 pass_in_v (gdbarch, regcache, &info,
0735fddd
YQ		 1517 TYPE_LENGTH (target_type), buf);
1518 pass_in_v (gdbarch, regcache, &info,
1519 TYPE_LENGTH (target_type),
07b287a0
MS		 1520 buf + TYPE_LENGTH (target_type));
1521 }
1522 else
1523 {
1524 info.nsrn = 8;
8e80f9d1 1525 pass_on_stack (&info, arg_type, arg);
07b287a0
MS		 1526 }
1527 break;
1528 case TYPE_CODE_FLT:
8e80f9d1 1529 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1530 break;
1531
1532 case TYPE_CODE_STRUCT:
1533 case TYPE_CODE_ARRAY:
1534 case TYPE_CODE_UNION:
cd635f74 1535 if (is_hfa_or_hva (arg_type))
07b287a0
MS		 1536 {
1537 int elements = TYPE_NFIELDS (arg_type);
1538
1539 /* Homogeneous Aggregates */
1540 if (info.nsrn + elements < 8)
1541 {
1542 int i;
1543
1544 for (i = 0; i < elements; i++)
1545 {
1546 /* We know that we have sufficient registers
1547 available therefore this will never fallback
1548 to the stack. */
1549 struct value *field =
1550 value_primitive_field (arg, 0, i, arg_type);
1551 struct type *field_type =
1552 check_typedef (value_type (field));
1553
8e80f9d1
YQ		 1554 pass_in_v_or_stack (gdbarch, regcache, &info,
1555 field_type, field);
07b287a0
MS		 1556 }
1557 }
1558 else
1559 {
1560 info.nsrn = 8;
8e80f9d1 1561 pass_on_stack (&info, arg_type, arg);
07b287a0
MS		 1562 }
1563 }
238f2452
YQ		 1564 else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
1565 && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
1566 {
1567 /* Short vector types are passed in V registers. */
1568 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1569 }
07b287a0
MS		 1570 else if (len > 16)
1571 {
1572 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1573 invisible reference. */
1574
1575 /* Allocate aligned storage. */
1576 sp = align_down (sp - len, 16);
1577
1578 /* Write the real data into the stack. */
1579 write_memory (sp, value_contents (arg), len);
1580
1581 /* Construct the indirection. */
1582 arg_type = lookup_pointer_type (arg_type);
1583 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1584 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1585 }
1586 else
1587 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1588 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1589 break;
1590
1591 default:
8e80f9d1 1592 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1593 break;
1594 }
1595 }
1596
1597 /* Make sure stack retains 16 byte alignment. */
1598 if (info.nsaa & 15)
1599 sp -= 16 - (info.nsaa & 15);
1600
1601 while (!VEC_empty (stack_item_t, info.si))
1602 {
1603 stack_item_t *si = VEC_last (stack_item_t, info.si);
1604
1605 sp -= si->len;
c3c87445
YQ		 1606 if (si->data != NULL)
1607 write_memory (sp, si->data, si->len);
07b287a0
MS		 1608 VEC_pop (stack_item_t, info.si);
1609 }
1610
1611 VEC_free (stack_item_t, info.si);
1612
1613 /* Finally, update the SP register. */
1614 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1615
1616 return sp;
1617}
1618
1619/* Implement the "frame_align" gdbarch method. */
1620
1621static CORE_ADDR
1622aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1623{
1624 /* Align the stack to sixteen bytes. */
1625 return sp & ~(CORE_ADDR) 15;
1626}
1627
1628/* Return the type for an AdvSISD Q register. */
1629
1630static struct type *
1631aarch64_vnq_type (struct gdbarch *gdbarch)
1632{
1633 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1634
1635 if (tdep->vnq_type == NULL)
1636 {
1637 struct type *t;
1638 struct type *elem;
1639
1640 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1641 TYPE_CODE_UNION);
1642
1643 elem = builtin_type (gdbarch)->builtin_uint128;
1644 append_composite_type_field (t, "u", elem);
1645
1646 elem = builtin_type (gdbarch)->builtin_int128;
1647 append_composite_type_field (t, "s", elem);
1648
1649 tdep->vnq_type = t;
1650 }
1651
1652 return tdep->vnq_type;
1653}
1654
1655/* Return the type for an AdvSISD D register. */
1656
1657static struct type *
1658aarch64_vnd_type (struct gdbarch *gdbarch)
1659{
1660 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1661
1662 if (tdep->vnd_type == NULL)
1663 {
1664 struct type *t;
1665 struct type *elem;
1666
1667 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1668 TYPE_CODE_UNION);
1669
1670 elem = builtin_type (gdbarch)->builtin_double;
1671 append_composite_type_field (t, "f", elem);
1672
1673 elem = builtin_type (gdbarch)->builtin_uint64;
1674 append_composite_type_field (t, "u", elem);
1675
1676 elem = builtin_type (gdbarch)->builtin_int64;
1677 append_composite_type_field (t, "s", elem);
1678
1679 tdep->vnd_type = t;
1680 }
1681
1682 return tdep->vnd_type;
1683}
1684
1685/* Return the type for an AdvSISD S register. */
1686
1687static struct type *
1688aarch64_vns_type (struct gdbarch *gdbarch)
1689{
1690 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1691
1692 if (tdep->vns_type == NULL)
1693 {
1694 struct type *t;
1695 struct type *elem;
1696
1697 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1698 TYPE_CODE_UNION);
1699
1700 elem = builtin_type (gdbarch)->builtin_float;
1701 append_composite_type_field (t, "f", elem);
1702
1703 elem = builtin_type (gdbarch)->builtin_uint32;
1704 append_composite_type_field (t, "u", elem);
1705
1706 elem = builtin_type (gdbarch)->builtin_int32;
1707 append_composite_type_field (t, "s", elem);
1708
1709 tdep->vns_type = t;
1710 }
1711
1712 return tdep->vns_type;
1713}
1714
1715/* Return the type for an AdvSISD H register. */
1716
1717static struct type *
1718aarch64_vnh_type (struct gdbarch *gdbarch)
1719{
1720 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1721
1722 if (tdep->vnh_type == NULL)
1723 {
1724 struct type *t;
1725 struct type *elem;
1726
1727 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1728 TYPE_CODE_UNION);
1729
1730 elem = builtin_type (gdbarch)->builtin_uint16;
1731 append_composite_type_field (t, "u", elem);
1732
1733 elem = builtin_type (gdbarch)->builtin_int16;
1734 append_composite_type_field (t, "s", elem);
1735
1736 tdep->vnh_type = t;
1737 }
1738
1739 return tdep->vnh_type;
1740}
1741
1742/* Return the type for an AdvSISD B register. */
1743
1744static struct type *
1745aarch64_vnb_type (struct gdbarch *gdbarch)
1746{
1747 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1748
1749 if (tdep->vnb_type == NULL)
1750 {
1751 struct type *t;
1752 struct type *elem;
1753
1754 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1755 TYPE_CODE_UNION);
1756
1757 elem = builtin_type (gdbarch)->builtin_uint8;
1758 append_composite_type_field (t, "u", elem);
1759
1760 elem = builtin_type (gdbarch)->builtin_int8;
1761 append_composite_type_field (t, "s", elem);
1762
1763 tdep->vnb_type = t;
1764 }
1765
1766 return tdep->vnb_type;
1767}
1768
1769/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1770
1771static int
1772aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1773{
1774 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1775 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1776
1777 if (reg == AARCH64_DWARF_SP)
1778 return AARCH64_SP_REGNUM;
1779
1780 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1781 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1782
1783 return -1;
1784}
1785\f
1786
1787/* Implement the "print_insn" gdbarch method. */
1788
1789static int
1790aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1791{
1792 info->symbols = NULL;
6394c606 1793 return default_print_insn (memaddr, info);
07b287a0
MS		 1794}
1795
1796/* AArch64 BRK software debug mode instruction.
1797 Note that AArch64 code is always little-endian.
1798 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 1799constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 1800
04180708 1801typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 1802
1803/* Extract from an array REGS containing the (raw) register state a
1804 function return value of type TYPE, and copy that, in virtual
1805 format, into VALBUF. */
1806
1807static void
1808aarch64_extract_return_value (struct type *type, struct regcache *regs,
1809 gdb_byte *valbuf)
1810{
ac7936df 1811 struct gdbarch *gdbarch = regs->arch ();
07b287a0
MS		 1812 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1813
1814 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1815 {
1816 bfd_byte buf[V_REGISTER_SIZE];
1817 int len = TYPE_LENGTH (type);
1818
dca08e1f 1819 regs->cooked_read (AARCH64_V0_REGNUM, buf);
07b287a0
MS		 1820 memcpy (valbuf, buf, len);
1821 }
1822 else if (TYPE_CODE (type) == TYPE_CODE_INT
1823 || TYPE_CODE (type) == TYPE_CODE_CHAR
1824 || TYPE_CODE (type) == TYPE_CODE_BOOL
1825 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1826 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1827 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1828 {
1829 /* If the the type is a plain integer, then the access is
1830 straight-forward. Otherwise we have to play around a bit
1831 more. */
1832 int len = TYPE_LENGTH (type);
1833 int regno = AARCH64_X0_REGNUM;
1834 ULONGEST tmp;
1835
1836 while (len > 0)
1837 {
1838 /* By using store_unsigned_integer we avoid having to do
1839 anything special for small big-endian values. */
1840 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1841 store_unsigned_integer (valbuf,
1842 (len > X_REGISTER_SIZE
1843 ? X_REGISTER_SIZE : len), byte_order, tmp);
1844 len -= X_REGISTER_SIZE;
1845 valbuf += X_REGISTER_SIZE;
1846 }
1847 }
1848 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1849 {
1850 int regno = AARCH64_V0_REGNUM;
1851 bfd_byte buf[V_REGISTER_SIZE];
1852 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1853 int len = TYPE_LENGTH (target_type);
1854
dca08e1f 1855 regs->cooked_read (regno, buf);
07b287a0
MS		 1856 memcpy (valbuf, buf, len);
1857 valbuf += len;
dca08e1f 1858 regs->cooked_read (regno + 1, buf);
07b287a0
MS		 1859 memcpy (valbuf, buf, len);
1860 valbuf += len;
1861 }
cd635f74 1862 else if (is_hfa_or_hva (type))
07b287a0
MS		 1863 {
1864 int elements = TYPE_NFIELDS (type);
1865 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1866 int len = TYPE_LENGTH (member_type);
1867 int i;
1868
1869 for (i = 0; i < elements; i++)
1870 {
1871 int regno = AARCH64_V0_REGNUM + i;
db3516bb 1872 bfd_byte buf[V_REGISTER_SIZE];
07b287a0
MS		 1873
1874 if (aarch64_debug)
b277c936 1875 {
cd635f74 1876 debug_printf ("read HFA or HVA return value element %d from %s\n",
b277c936
PL		 1877 i + 1,
1878 gdbarch_register_name (gdbarch, regno));
1879 }
dca08e1f 1880 regs->cooked_read (regno, buf);
07b287a0
MS		 1881
1882 memcpy (valbuf, buf, len);
1883 valbuf += len;
1884 }
1885 }
238f2452
YQ		 1886 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1887 && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
1888 {
1889 /* Short vector is returned in V register. */
1890 gdb_byte buf[V_REGISTER_SIZE];
1891
dca08e1f 1892 regs->cooked_read (AARCH64_V0_REGNUM, buf);
238f2452
YQ		 1893 memcpy (valbuf, buf, TYPE_LENGTH (type));
1894 }
07b287a0
MS		 1895 else
1896 {
1897 /* For a structure or union the behaviour is as if the value had
1898 been stored to word-aligned memory and then loaded into
1899 registers with 64-bit load instruction(s). */
1900 int len = TYPE_LENGTH (type);
1901 int regno = AARCH64_X0_REGNUM;
1902 bfd_byte buf[X_REGISTER_SIZE];
1903
1904 while (len > 0)
1905 {
dca08e1f 1906 regs->cooked_read (regno++, buf);
07b287a0
MS		 1907 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1908 len -= X_REGISTER_SIZE;
1909 valbuf += X_REGISTER_SIZE;
1910 }
1911 }
1912}
1913
1914
1915/* Will a function return an aggregate type in memory or in a
1916 register? Return 0 if an aggregate type can be returned in a
1917 register, 1 if it must be returned in memory. */
1918
1919static int
1920aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1921{
f168693b 1922 type = check_typedef (type);
07b287a0 1923
cd635f74 1924 if (is_hfa_or_hva (type))
07b287a0 1925 {
cd635f74
YQ		 1926 /* v0-v7 are used to return values and one register is allocated
1927 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 1928 return 0;
1929 }
1930
1931 if (TYPE_LENGTH (type) > 16)
1932 {
1933 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1934 invisible reference. */
1935
1936 return 1;
1937 }
1938
1939 return 0;
1940}
1941
1942/* Write into appropriate registers a function return value of type
1943 TYPE, given in virtual format. */
1944
1945static void
1946aarch64_store_return_value (struct type *type, struct regcache *regs,
1947 const gdb_byte *valbuf)
1948{
ac7936df 1949 struct gdbarch *gdbarch = regs->arch ();
07b287a0
MS		 1950 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1951
1952 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1953 {
1954 bfd_byte buf[V_REGISTER_SIZE];
1955 int len = TYPE_LENGTH (type);
1956
1957 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
b66f5587 1958 regs->cooked_write (AARCH64_V0_REGNUM, buf);
07b287a0
MS		 1959 }
1960 else if (TYPE_CODE (type) == TYPE_CODE_INT
1961 || TYPE_CODE (type) == TYPE_CODE_CHAR
1962 || TYPE_CODE (type) == TYPE_CODE_BOOL
1963 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1964 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1965 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1966 {
1967 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1968 {
1969 /* Values of one word or less are zero/sign-extended and
1970 returned in r0. */
1971 bfd_byte tmpbuf[X_REGISTER_SIZE];
1972 LONGEST val = unpack_long (type, valbuf);
1973
1974 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 1975 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 1976 }
1977 else
1978 {
1979 /* Integral values greater than one word are stored in
1980 consecutive registers starting with r0. This will always
1981 be a multiple of the regiser size. */
1982 int len = TYPE_LENGTH (type);
1983 int regno = AARCH64_X0_REGNUM;
1984
1985 while (len > 0)
1986 {
b66f5587 1987 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 1988 len -= X_REGISTER_SIZE;
1989 valbuf += X_REGISTER_SIZE;
1990 }
1991 }
1992 }
cd635f74 1993 else if (is_hfa_or_hva (type))
07b287a0
MS		 1994 {
1995 int elements = TYPE_NFIELDS (type);
1996 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1997 int len = TYPE_LENGTH (member_type);
1998 int i;
1999
2000 for (i = 0; i < elements; i++)
2001 {
2002 int regno = AARCH64_V0_REGNUM + i;
d1be909e 2003 bfd_byte tmpbuf[V_REGISTER_SIZE];
07b287a0
MS		 2004
2005 if (aarch64_debug)
b277c936 2006 {
cd635f74 2007 debug_printf ("write HFA or HVA return value element %d to %s\n",
b277c936
PL		 2008 i + 1,
2009 gdbarch_register_name (gdbarch, regno));
2010 }
07b287a0
MS		 2011
2012 memcpy (tmpbuf, valbuf, len);
b66f5587 2013 regs->cooked_write (regno, tmpbuf);
07b287a0
MS		 2014 valbuf += len;
2015 }
2016 }
238f2452
YQ		 2017 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
2018 && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
2019 {
2020 /* Short vector. */
2021 gdb_byte buf[V_REGISTER_SIZE];
2022
2023 memcpy (buf, valbuf, TYPE_LENGTH (type));
b66f5587 2024 regs->cooked_write (AARCH64_V0_REGNUM, buf);
238f2452 2025 }
07b287a0
MS		 2026 else
2027 {
2028 /* For a structure or union the behaviour is as if the value had
2029 been stored to word-aligned memory and then loaded into
2030 registers with 64-bit load instruction(s). */
2031 int len = TYPE_LENGTH (type);
2032 int regno = AARCH64_X0_REGNUM;
2033 bfd_byte tmpbuf[X_REGISTER_SIZE];
2034
2035 while (len > 0)
2036 {
2037 memcpy (tmpbuf, valbuf,
2038 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2039 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2040 len -= X_REGISTER_SIZE;
2041 valbuf += X_REGISTER_SIZE;
2042 }
2043 }
2044}
2045
2046/* Implement the "return_value" gdbarch method. */
2047
2048static enum return_value_convention
2049aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2050 struct type *valtype, struct regcache *regcache,
2051 gdb_byte *readbuf, const gdb_byte *writebuf)
2052{
07b287a0
MS		 2053
2054 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2055 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2056 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2057 {
2058 if (aarch64_return_in_memory (gdbarch, valtype))
2059 {
2060 if (aarch64_debug)
b277c936 2061 debug_printf ("return value in memory\n");
07b287a0
MS		 2062 return RETURN_VALUE_STRUCT_CONVENTION;
2063 }
2064 }
2065
2066 if (writebuf)
2067 aarch64_store_return_value (valtype, regcache, writebuf);
2068
2069 if (readbuf)
2070 aarch64_extract_return_value (valtype, regcache, readbuf);
2071
2072 if (aarch64_debug)
b277c936 2073 debug_printf ("return value in registers\n");
07b287a0
MS		 2074
2075 return RETURN_VALUE_REGISTER_CONVENTION;
2076}
2077
2078/* Implement the "get_longjmp_target" gdbarch method. */
2079
2080static int
2081aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2082{
2083 CORE_ADDR jb_addr;
2084 gdb_byte buf[X_REGISTER_SIZE];
2085 struct gdbarch *gdbarch = get_frame_arch (frame);
2086 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2087 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2088
2089 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2090
2091 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2092 X_REGISTER_SIZE))
2093 return 0;
2094
2095 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2096 return 1;
2097}
ea873d8e
PL		 2098
2099/* Implement the "gen_return_address" gdbarch method. */
2100
2101static void
2102aarch64_gen_return_address (struct gdbarch *gdbarch,
2103 struct agent_expr *ax, struct axs_value *value,
2104 CORE_ADDR scope)
2105{
2106 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2107 value->kind = axs_lvalue_register;
2108 value->u.reg = AARCH64_LR_REGNUM;
2109}
07b287a0
MS		 2110\f
2111
2112/* Return the pseudo register name corresponding to register regnum. */
2113
2114static const char *
2115aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2116{
2117 static const char *const q_name[] =
2118 {
2119 "q0", "q1", "q2", "q3",
2120 "q4", "q5", "q6", "q7",
2121 "q8", "q9", "q10", "q11",
2122 "q12", "q13", "q14", "q15",
2123 "q16", "q17", "q18", "q19",
2124 "q20", "q21", "q22", "q23",
2125 "q24", "q25", "q26", "q27",
2126 "q28", "q29", "q30", "q31",
2127 };
2128
2129 static const char *const d_name[] =
2130 {
2131 "d0", "d1", "d2", "d3",
2132 "d4", "d5", "d6", "d7",
2133 "d8", "d9", "d10", "d11",
2134 "d12", "d13", "d14", "d15",
2135 "d16", "d17", "d18", "d19",
2136 "d20", "d21", "d22", "d23",
2137 "d24", "d25", "d26", "d27",
2138 "d28", "d29", "d30", "d31",
2139 };
2140
2141 static const char *const s_name[] =
2142 {
2143 "s0", "s1", "s2", "s3",
2144 "s4", "s5", "s6", "s7",
2145 "s8", "s9", "s10", "s11",
2146 "s12", "s13", "s14", "s15",
2147 "s16", "s17", "s18", "s19",
2148 "s20", "s21", "s22", "s23",
2149 "s24", "s25", "s26", "s27",
2150 "s28", "s29", "s30", "s31",
2151 };
2152
2153 static const char *const h_name[] =
2154 {
2155 "h0", "h1", "h2", "h3",
2156 "h4", "h5", "h6", "h7",
2157 "h8", "h9", "h10", "h11",
2158 "h12", "h13", "h14", "h15",
2159 "h16", "h17", "h18", "h19",
2160 "h20", "h21", "h22", "h23",
2161 "h24", "h25", "h26", "h27",
2162 "h28", "h29", "h30", "h31",
2163 };
2164
2165 static const char *const b_name[] =
2166 {
2167 "b0", "b1", "b2", "b3",
2168 "b4", "b5", "b6", "b7",
2169 "b8", "b9", "b10", "b11",
2170 "b12", "b13", "b14", "b15",
2171 "b16", "b17", "b18", "b19",
2172 "b20", "b21", "b22", "b23",
2173 "b24", "b25", "b26", "b27",
2174 "b28", "b29", "b30", "b31",
2175 };
2176
2177 regnum -= gdbarch_num_regs (gdbarch);
2178
2179 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2180 return q_name[regnum - AARCH64_Q0_REGNUM];
2181
2182 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2183 return d_name[regnum - AARCH64_D0_REGNUM];
2184
2185 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2186 return s_name[regnum - AARCH64_S0_REGNUM];
2187
2188 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2189 return h_name[regnum - AARCH64_H0_REGNUM];
2190
2191 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2192 return b_name[regnum - AARCH64_B0_REGNUM];
2193
2194 internal_error (__FILE__, __LINE__,
2195 _("aarch64_pseudo_register_name: bad register number %d"),
2196 regnum);
2197}
2198
2199/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2200
2201static struct type *
2202aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2203{
2204 regnum -= gdbarch_num_regs (gdbarch);
2205
2206 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2207 return aarch64_vnq_type (gdbarch);
2208
2209 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2210 return aarch64_vnd_type (gdbarch);
2211
2212 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2213 return aarch64_vns_type (gdbarch);
2214
2215 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2216 return aarch64_vnh_type (gdbarch);
2217
2218 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2219 return aarch64_vnb_type (gdbarch);
2220
2221 internal_error (__FILE__, __LINE__,
2222 _("aarch64_pseudo_register_type: bad register number %d"),
2223 regnum);
2224}
2225
2226/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2227
2228static int
2229aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2230 struct reggroup *group)
2231{
2232 regnum -= gdbarch_num_regs (gdbarch);
2233
2234 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2235 return group == all_reggroup || group == vector_reggroup;
2236 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2237 return (group == all_reggroup || group == vector_reggroup
2238 || group == float_reggroup);
2239 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2240 return (group == all_reggroup || group == vector_reggroup
2241 || group == float_reggroup);
2242 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2243 return group == all_reggroup || group == vector_reggroup;
2244 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2245 return group == all_reggroup || group == vector_reggroup;
2246
2247 return group == all_reggroup;
2248}
2249
3c5cd5c3
AH		 2250/* Helper for aarch64_pseudo_read_value. */
2251
2252static struct value *
2253aarch64_pseudo_read_value_1 (readable_regcache *regcache, int regnum_offset,
2254 int regsize, struct value *result_value)
2255{
2256 gdb_byte reg_buf[V_REGISTER_SIZE];
2257 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2258
2259 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2260 mark_value_bytes_unavailable (result_value, 0,
2261 TYPE_LENGTH (value_type (result_value)));
2262 else
2263 memcpy (value_contents_raw (result_value), reg_buf, regsize);
2264 return result_value;
2265 }
2266
07b287a0
MS		 2267/* Implement the "pseudo_register_read_value" gdbarch method. */
2268
2269static struct value *
3c5cd5c3 2270aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2271 int regnum)
2272{
3c5cd5c3 2273 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2274
07b287a0
MS		 2275 VALUE_LVAL (result_value) = lval_register;
2276 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2277
2278 regnum -= gdbarch_num_regs (gdbarch);
2279
2280 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
3c5cd5c3
AH		 2281 return aarch64_pseudo_read_value_1 (regcache, regnum - AARCH64_Q0_REGNUM,
2282 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2283
2284 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
3c5cd5c3
AH		 2285 return aarch64_pseudo_read_value_1 (regcache, regnum - AARCH64_D0_REGNUM,
2286 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2287
2288 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
3c5cd5c3
AH		 2289 return aarch64_pseudo_read_value_1 (regcache, regnum - AARCH64_S0_REGNUM,
2290 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2291
2292 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
3c5cd5c3
AH		 2293 return aarch64_pseudo_read_value_1 (regcache, regnum - AARCH64_H0_REGNUM,
2294 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2295
2296 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
3c5cd5c3
AH		 2297 return aarch64_pseudo_read_value_1 (regcache, regnum - AARCH64_B0_REGNUM,
2298 B_REGISTER_SIZE, result_value);
07b287a0
MS		 2299
2300 gdb_assert_not_reached ("regnum out of bound");
2301}
2302
3c5cd5c3 2303/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2304
2305static void
3c5cd5c3
AH		 2306aarch64_pseudo_write_1 (struct regcache *regcache, int regnum_offset,
2307 int regsize, const gdb_byte *buf)
07b287a0 2308{
d1be909e 2309 gdb_byte reg_buf[V_REGISTER_SIZE];
3c5cd5c3 2310 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0
MS		 2311
2312 /* Ensure the register buffer is zero, we want gdb writes of the
2313 various 'scalar' pseudo registers to behavior like architectural
2314 writes, register width bytes are written the remainder are set to
2315 zero. */
2316 memset (reg_buf, 0, sizeof (reg_buf));
2317
3c5cd5c3
AH		 2318 memcpy (reg_buf, buf, regsize);
2319 regcache->raw_write (v_regnum, reg_buf);
2320}
2321
2322/* Implement the "pseudo_register_write" gdbarch method. */
2323
2324static void
2325aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2326 int regnum, const gdb_byte *buf)
2327{
07b287a0
MS		 2328 regnum -= gdbarch_num_regs (gdbarch);
2329
2330 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
3c5cd5c3
AH		 2331 return aarch64_pseudo_write_1 (regcache, regnum - AARCH64_Q0_REGNUM,
2332 Q_REGISTER_SIZE, buf);
07b287a0
MS		 2333
2334 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
3c5cd5c3
AH		 2335 return aarch64_pseudo_write_1 (regcache, regnum - AARCH64_D0_REGNUM,
2336 D_REGISTER_SIZE, buf);
07b287a0
MS		 2337
2338 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
3c5cd5c3
AH		 2339 return aarch64_pseudo_write_1 (regcache, regnum - AARCH64_S0_REGNUM,
2340 S_REGISTER_SIZE, buf);
07b287a0
MS		 2341
2342 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
3c5cd5c3
AH		 2343 return aarch64_pseudo_write_1 (regcache, regnum - AARCH64_H0_REGNUM,
2344 H_REGISTER_SIZE, buf);
07b287a0
MS		 2345
2346 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
3c5cd5c3
AH		 2347 return aarch64_pseudo_write_1 (regcache, regnum - AARCH64_B0_REGNUM,
2348 B_REGISTER_SIZE, buf);
07b287a0
MS		 2349
2350 gdb_assert_not_reached ("regnum out of bound");
2351}
2352
07b287a0
MS		 2353/* Callback function for user_reg_add. */
2354
2355static struct value *
2356value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2357{
9a3c8263 2358 const int *reg_p = (const int *) baton;
07b287a0
MS		 2359
2360 return value_of_register (*reg_p, frame);
2361}
2362\f
2363
9404b58f
KM		 2364/* Implement the "software_single_step" gdbarch method, needed to
2365 single step through atomic sequences on AArch64. */
2366
a0ff9e1a 2367static std::vector<CORE_ADDR>
f5ea389a 2368aarch64_software_single_step (struct regcache *regcache)
9404b58f 2369{
ac7936df 2370 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2371 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2372 const int insn_size = 4;
2373 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2374 CORE_ADDR pc = regcache_read_pc (regcache);
9404b58f
KM		 2375 CORE_ADDR breaks[2] = { -1, -1 };
2376 CORE_ADDR loc = pc;
2377 CORE_ADDR closing_insn = 0;
2378 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2379 byte_order_for_code);
2380 int index;
2381 int insn_count;
2382 int bc_insn_count = 0; /* Conditional branch instruction count. */
2383 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2384 aarch64_inst inst;
2385
561a72d4 2386 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2387 return {};
9404b58f
KM		 2388
2389 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2390 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2391 return {};
9404b58f
KM		 2392
2393 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2394 {
9404b58f
KM		 2395 loc += insn_size;
2396 insn = read_memory_unsigned_integer (loc, insn_size,
2397 byte_order_for_code);
2398
561a72d4 2399 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2400 return {};
9404b58f 2401 /* Check if the instruction is a conditional branch. */
f77ee802 2402 if (inst.opcode->iclass == condbranch)
9404b58f 2403 {
f77ee802
YQ		 2404 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2405
9404b58f 2406 if (bc_insn_count >= 1)
a0ff9e1a 2407 return {};
9404b58f
KM		 2408
2409 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2410 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2411
2412 bc_insn_count++;
2413 last_breakpoint++;
2414 }
2415
2416 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2417 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2418 {
2419 closing_insn = loc;
2420 break;
2421 }
2422 }
2423
2424 /* We didn't find a closing Store Exclusive instruction, fall back. */
2425 if (!closing_insn)
a0ff9e1a 2426 return {};
9404b58f
KM		 2427
2428 /* Insert breakpoint after the end of the atomic sequence. */
2429 breaks[0] = loc + insn_size;
2430
2431 /* Check for duplicated breakpoints, and also check that the second
2432 breakpoint is not within the atomic sequence. */
2433 if (last_breakpoint
2434 && (breaks[1] == breaks[0]
2435 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2436 last_breakpoint = 0;
2437
a0ff9e1a
SM		 2438 std::vector<CORE_ADDR> next_pcs;
2439
9404b58f
KM		 2440 /* Insert the breakpoint at the end of the sequence, and one at the
2441 destination of the conditional branch, if it exists. */
2442 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2443 next_pcs.push_back (breaks[index]);
9404b58f 2444
93f9a11f 2445 return next_pcs;
9404b58f
KM		 2446}
2447
cfba9872 2448struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2449{
2450 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2451 is being displaced stepping. */
cfba9872 2452 int cond = 0;
b6542f81
YQ		 2453
2454 /* PC adjustment offset after displaced stepping. */
cfba9872 2455 int32_t pc_adjust = 0;
b6542f81
YQ		 2456};
2457
2458/* Data when visiting instructions for displaced stepping. */
2459
2460struct aarch64_displaced_step_data
2461{
2462 struct aarch64_insn_data base;
2463
2464 /* The address where the instruction will be executed at. */
2465 CORE_ADDR new_addr;
2466 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2467 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2468 /* Number of instructions in INSN_BUF. */
2469 unsigned insn_count;
2470 /* Registers when doing displaced stepping. */
2471 struct regcache *regs;
2472
cfba9872 2473 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2474};
2475
2476/* Implementation of aarch64_insn_visitor method "b". */
2477
2478static void
2479aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2480 struct aarch64_insn_data *data)
2481{
2482 struct aarch64_displaced_step_data *dsd
2483 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2484 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2485
2486 if (can_encode_int32 (new_offset, 28))
2487 {
2488 /* Emit B rather than BL, because executing BL on a new address
2489 will get the wrong address into LR. In order to avoid this,
2490 we emit B, and update LR if the instruction is BL. */
2491 emit_b (dsd->insn_buf, 0, new_offset);
2492 dsd->insn_count++;
2493 }
2494 else
2495 {
2496 /* Write NOP. */
2497 emit_nop (dsd->insn_buf);
2498 dsd->insn_count++;
2499 dsd->dsc->pc_adjust = offset;
2500 }
2501
2502 if (is_bl)
2503 {
2504 /* Update LR. */
2505 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2506 data->insn_addr + 4);
2507 }
2508}
2509
2510/* Implementation of aarch64_insn_visitor method "b_cond". */
2511
2512static void
2513aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2514 struct aarch64_insn_data *data)
2515{
2516 struct aarch64_displaced_step_data *dsd
2517 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2518
2519 /* GDB has to fix up PC after displaced step this instruction
2520 differently according to the condition is true or false. Instead
2521 of checking COND against conditional flags, we can use
2522 the following instructions, and GDB can tell how to fix up PC
2523 according to the PC value.
2524
2525 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2526 INSN1 ;
2527 TAKEN:
2528 INSN2
2529 */
2530
2531 emit_bcond (dsd->insn_buf, cond, 8);
2532 dsd->dsc->cond = 1;
2533 dsd->dsc->pc_adjust = offset;
2534 dsd->insn_count = 1;
2535}
2536
2537/* Dynamically allocate a new register. If we know the register
2538 statically, we should make it a global as above instead of using this
2539 helper function. */
2540
2541static struct aarch64_register
2542aarch64_register (unsigned num, int is64)
2543{
2544 return (struct aarch64_register) { num, is64 };
2545}
2546
2547/* Implementation of aarch64_insn_visitor method "cb". */
2548
2549static void
2550aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2551 const unsigned rn, int is64,
2552 struct aarch64_insn_data *data)
2553{
2554 struct aarch64_displaced_step_data *dsd
2555 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2556
2557 /* The offset is out of range for a compare and branch
2558 instruction. We can use the following instructions instead:
2559
2560 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2561 INSN1 ;
2562 TAKEN:
2563 INSN2
2564 */
2565 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2566 dsd->insn_count = 1;
2567 dsd->dsc->cond = 1;
2568 dsd->dsc->pc_adjust = offset;
2569}
2570
2571/* Implementation of aarch64_insn_visitor method "tb". */
2572
2573static void
2574aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2575 const unsigned rt, unsigned bit,
2576 struct aarch64_insn_data *data)
2577{
2578 struct aarch64_displaced_step_data *dsd
2579 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2580
2581 /* The offset is out of range for a test bit and branch
2582 instruction We can use the following instructions instead:
2583
2584 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2585 INSN1 ;
2586 TAKEN:
2587 INSN2
2588
2589 */
2590 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2591 dsd->insn_count = 1;
2592 dsd->dsc->cond = 1;
2593 dsd->dsc->pc_adjust = offset;
2594}
2595
2596/* Implementation of aarch64_insn_visitor method "adr". */
2597
2598static void
2599aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2600 const int is_adrp, struct aarch64_insn_data *data)
2601{
2602 struct aarch64_displaced_step_data *dsd
2603 = (struct aarch64_displaced_step_data *) data;
2604 /* We know exactly the address the ADR{P,} instruction will compute.
2605 We can just write it to the destination register. */
2606 CORE_ADDR address = data->insn_addr + offset;
2607
2608 if (is_adrp)
2609 {
2610 /* Clear the lower 12 bits of the offset to get the 4K page. */
2611 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2612 address & ~0xfff);
2613 }
2614 else
2615 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2616 address);
2617
2618 dsd->dsc->pc_adjust = 4;
2619 emit_nop (dsd->insn_buf);
2620 dsd->insn_count = 1;
2621}
2622
2623/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2624
2625static void
2626aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2627 const unsigned rt, const int is64,
2628 struct aarch64_insn_data *data)
2629{
2630 struct aarch64_displaced_step_data *dsd
2631 = (struct aarch64_displaced_step_data *) data;
2632 CORE_ADDR address = data->insn_addr + offset;
2633 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2634
2635 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2636 address);
2637
2638 if (is_sw)
2639 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2640 aarch64_register (rt, 1), zero);
2641 else
2642 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2643 aarch64_register (rt, 1), zero);
2644
2645 dsd->dsc->pc_adjust = 4;
2646}
2647
2648/* Implementation of aarch64_insn_visitor method "others". */
2649
2650static void
2651aarch64_displaced_step_others (const uint32_t insn,
2652 struct aarch64_insn_data *data)
2653{
2654 struct aarch64_displaced_step_data *dsd
2655 = (struct aarch64_displaced_step_data *) data;
2656
e1c587c3 2657 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2658 dsd->insn_count = 1;
2659
2660 if ((insn & 0xfffffc1f) == 0xd65f0000)
2661 {
2662 /* RET */
2663 dsd->dsc->pc_adjust = 0;
2664 }
2665 else
2666 dsd->dsc->pc_adjust = 4;
2667}
2668
2669static const struct aarch64_insn_visitor visitor =
2670{
2671 aarch64_displaced_step_b,
2672 aarch64_displaced_step_b_cond,
2673 aarch64_displaced_step_cb,
2674 aarch64_displaced_step_tb,
2675 aarch64_displaced_step_adr,
2676 aarch64_displaced_step_ldr_literal,
2677 aarch64_displaced_step_others,
2678};
2679
2680/* Implement the "displaced_step_copy_insn" gdbarch method. */
2681
2682struct displaced_step_closure *
2683aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2684 CORE_ADDR from, CORE_ADDR to,
2685 struct regcache *regs)
2686{
b6542f81
YQ		 2687 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2688 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2689 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2690 aarch64_inst inst;
2691
561a72d4 2692 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2693 return NULL;
b6542f81
YQ		 2694
2695 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2696 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2697 {
2698 /* We can't displaced step atomic sequences. */
2699 return NULL;
2700 }
2701
cfba9872
SM		 2702 std::unique_ptr<aarch64_displaced_step_closure> dsc
2703 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2704 dsd.base.insn_addr = from;
2705 dsd.new_addr = to;
2706 dsd.regs = regs;
cfba9872 2707 dsd.dsc = dsc.get ();
034f1a81 2708 dsd.insn_count = 0;
b6542f81
YQ		 2709 aarch64_relocate_instruction (insn, &visitor,
2710 (struct aarch64_insn_data *) &dsd);
2711 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2712
2713 if (dsd.insn_count != 0)
2714 {
2715 int i;
2716
2717 /* Instruction can be relocated to scratch pad. Copy
2718 relocated instruction(s) there. */
2719 for (i = 0; i < dsd.insn_count; i++)
2720 {
2721 if (debug_displaced)
2722 {
2723 debug_printf ("displaced: writing insn ");
2724 debug_printf ("%.8x", dsd.insn_buf[i]);
2725 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2726 }
2727 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2728 (ULONGEST) dsd.insn_buf[i]);
2729 }
2730 }
2731 else
2732 {
b6542f81
YQ		 2733 dsc = NULL;
2734 }
2735
cfba9872 2736 return dsc.release ();
b6542f81
YQ		 2737}
2738
2739/* Implement the "displaced_step_fixup" gdbarch method. */
2740
2741void
2742aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 2743 struct displaced_step_closure *dsc_,
b6542f81
YQ		 2744 CORE_ADDR from, CORE_ADDR to,
2745 struct regcache *regs)
2746{
cfba9872
SM		 2747 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2748
b6542f81
YQ		 2749 if (dsc->cond)
2750 {
2751 ULONGEST pc;
2752
2753 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2754 if (pc - to == 8)
2755 {
2756 /* Condition is true. */
2757 }
2758 else if (pc - to == 4)
2759 {
2760 /* Condition is false. */
2761 dsc->pc_adjust = 4;
2762 }
2763 else
2764 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2765 }
2766
2767 if (dsc->pc_adjust != 0)
2768 {
2769 if (debug_displaced)
2770 {
2771 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2772 paddress (gdbarch, from), dsc->pc_adjust);
2773 }
2774 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2775 from + dsc->pc_adjust);
2776 }
2777}
2778
2779/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2780
2781int
2782aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2783 struct displaced_step_closure *closure)
2784{
2785 return 1;
2786}
2787
95228a0d
AH		 2788/* Get the correct target description for the given VQ value.
2789 If VQ is zero then it is assumed SVE is not supported.
2790 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 2791
2792const target_desc *
39bfb937 2793aarch64_read_description (uint64_t vq)
da434ccb 2794{
95228a0d 2795 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 2796 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 2797 AARCH64_MAX_SVE_VQ);
2798
2799 struct target_desc *tdesc = tdesc_aarch64_list[vq];
da434ccb 2800
95228a0d
AH		 2801 if (tdesc == NULL)
2802 {
2803 tdesc = aarch64_create_target_description (vq);
2804 tdesc_aarch64_list[vq] = tdesc;
2805 }
da434ccb 2806
95228a0d 2807 return tdesc;
da434ccb
AH		 2808}
2809
ba2d2bb2
AH		 2810/* Return the VQ used when creating the target description TDESC. */
2811
1332a140 2812static uint64_t
ba2d2bb2
AH		 2813aarch64_get_tdesc_vq (const struct target_desc *tdesc)
2814{
2815 const struct tdesc_feature *feature_sve;
2816
2817 if (!tdesc_has_registers (tdesc))
2818 return 0;
2819
2820 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
2821
2822 if (feature_sve == nullptr)
2823 return 0;
2824
1332a140
AH		 2825 uint64_t vl = tdesc_register_size (feature_sve,
2826 aarch64_sve_register_names[0]);
ba2d2bb2
AH		 2827 return sve_vq_from_vl (vl);
2828}
2829
2830
07b287a0
MS		 2831/* Initialize the current architecture based on INFO. If possible,
2832 re-use an architecture from ARCHES, which is a list of
2833 architectures already created during this debugging session.
2834
2835 Called e.g. at program startup, when reading a core file, and when
2836 reading a binary file. */
2837
2838static struct gdbarch *
2839aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2840{
2841 struct gdbarch_tdep *tdep;
2842 struct gdbarch *gdbarch;
2843 struct gdbarch_list *best_arch;
2844 struct tdesc_arch_data *tdesc_data = NULL;
2845 const struct target_desc *tdesc = info.target_desc;
2846 int i;
07b287a0 2847 int valid_p = 1;
ba2d2bb2
AH		 2848 const struct tdesc_feature *feature_core;
2849 const struct tdesc_feature *feature_fpu;
2850 const struct tdesc_feature *feature_sve;
07b287a0
MS		 2851 int num_regs = 0;
2852 int num_pseudo_regs = 0;
2853
ba2d2bb2 2854 /* Ensure we always have a target description. */
07b287a0 2855 if (!tdesc_has_registers (tdesc))
ba2d2bb2 2856 tdesc = aarch64_read_description (0);
07b287a0
MS		 2857 gdb_assert (tdesc);
2858
ba2d2bb2
AH		 2859 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2860 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2861 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
07b287a0 2862
ba2d2bb2 2863 if (feature_core == NULL)
07b287a0
MS		 2864 return NULL;
2865
2866 tdesc_data = tdesc_data_alloc ();
2867
ba2d2bb2 2868 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 2869 and allocate their numbers. */
2870 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 2871 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
2872 AARCH64_X0_REGNUM + i,
2873 aarch64_r_register_names[i]);
07b287a0
MS		 2874
2875 num_regs = AARCH64_X0_REGNUM + i;
2876
ba2d2bb2
AH		 2877 /* Add the V registers. */
2878 if (feature_fpu != NULL)
07b287a0 2879 {
ba2d2bb2
AH		 2880 if (feature_sve != NULL)
2881 error (_("Program contains both fpu and SVE features."));
2882
2883 /* Validate the description provides the mandatory V registers
2884 and allocate their numbers. */
07b287a0 2885 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 2886 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
2887 AARCH64_V0_REGNUM + i,
2888 aarch64_v_register_names[i]);
07b287a0
MS		 2889
2890 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 2891 }
07b287a0 2892
ba2d2bb2
AH		 2893 /* Add the SVE registers. */
2894 if (feature_sve != NULL)
2895 {
2896 /* Validate the description provides the mandatory SVE registers
2897 and allocate their numbers. */
2898 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
2899 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
2900 AARCH64_SVE_Z0_REGNUM + i,
2901 aarch64_sve_register_names[i]);
2902
2903 num_regs = AARCH64_SVE_Z0_REGNUM + i;
2904 num_pseudo_regs += 32; /* add the Vn register pseudos. */
2905 }
2906
2907 if (feature_fpu != NULL || feature_sve != NULL)
2908 {
07b287a0
MS		 2909 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2910 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2911 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2912 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2913 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2914 }
2915
2916 if (!valid_p)
2917 {
2918 tdesc_data_cleanup (tdesc_data);
2919 return NULL;
2920 }
2921
2922 /* AArch64 code is always little-endian. */
2923 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2924
2925 /* If there is already a candidate, use it. */
2926 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2927 best_arch != NULL;
2928 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2929 {
2930 /* Found a match. */
2931 break;
2932 }
2933
2934 if (best_arch != NULL)
2935 {
2936 if (tdesc_data != NULL)
2937 tdesc_data_cleanup (tdesc_data);
2938 return best_arch->gdbarch;
2939 }
2940
8d749320 2941 tdep = XCNEW (struct gdbarch_tdep);
07b287a0
MS		 2942 gdbarch = gdbarch_alloc (&info, tdep);
2943
2944 /* This should be low enough for everything. */
2945 tdep->lowest_pc = 0x20;
2946 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2947 tdep->jb_elt_size = 8;
ba2d2bb2 2948 tdep->vq = aarch64_get_tdesc_vq (tdesc);
07b287a0
MS		 2949
2950 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2951 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2952
07b287a0
MS		 2953 /* Frame handling. */
2954 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2955 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2956 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2957
2958 /* Advance PC across function entry code. */
2959 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2960
2961 /* The stack grows downward. */
2962 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2963
2964 /* Breakpoint manipulation. */
04180708
YQ		 2965 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2966 aarch64_breakpoint::kind_from_pc);
2967 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2968 aarch64_breakpoint::bp_from_kind);
07b287a0 2969 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 2970 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 2971
2972 /* Information about registers, etc. */
2973 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2974 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2975 set_gdbarch_num_regs (gdbarch, num_regs);
2976
2977 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2978 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2979 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2980 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2981 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2982 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2983 aarch64_pseudo_register_reggroup_p);
2984
2985 /* ABI */
2986 set_gdbarch_short_bit (gdbarch, 16);
2987 set_gdbarch_int_bit (gdbarch, 32);
2988 set_gdbarch_float_bit (gdbarch, 32);
2989 set_gdbarch_double_bit (gdbarch, 64);
2990 set_gdbarch_long_double_bit (gdbarch, 128);
2991 set_gdbarch_long_bit (gdbarch, 64);
2992 set_gdbarch_long_long_bit (gdbarch, 64);
2993 set_gdbarch_ptr_bit (gdbarch, 64);
2994 set_gdbarch_char_signed (gdbarch, 0);
53375380 2995 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 2996 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2997 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2998 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2999
3000 /* Internal <-> external register number maps. */
3001 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3002
3003 /* Returning results. */
3004 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3005
3006 /* Disassembly. */
3007 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3008
3009 /* Virtual tables. */
3010 set_gdbarch_vbit_in_delta (gdbarch, 1);
3011
3012 /* Hook in the ABI-specific overrides, if they have been registered. */
3013 info.target_desc = tdesc;
0dba2a6c 3014 info.tdesc_data = tdesc_data;
07b287a0
MS		 3015 gdbarch_init_osabi (info, gdbarch);
3016
3017 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3018
3019 /* Add some default predicates. */
3020 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3021 dwarf2_append_unwinders (gdbarch);
3022 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3023
3024 frame_base_set_default (gdbarch, &aarch64_normal_base);
3025
3026 /* Now we have tuned the configuration, set a few final things,
3027 based on what the OS ABI has told us. */
3028
3029 if (tdep->jb_pc >= 0)
3030 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3031
ea873d8e
PL		 3032 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3033
07b287a0
MS		 3034 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3035
3036 /* Add standard register aliases. */
3037 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3038 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3039 value_of_aarch64_user_reg,
3040 &aarch64_register_aliases[i].regnum);
3041
3042 return gdbarch;
3043}
3044
3045static void
3046aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3047{
3048 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3049
3050 if (tdep == NULL)
3051 return;
3052
3053 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3054 paddress (gdbarch, tdep->lowest_pc));
3055}
3056
0d4c07af 3057#if GDB_SELF_TEST
1e2b521d
YQ		 3058namespace selftests
3059{
3060static void aarch64_process_record_test (void);
3061}
0d4c07af 3062#endif
1e2b521d 3063
07b287a0
MS		 3064void
3065_initialize_aarch64_tdep (void)
3066{
3067 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3068 aarch64_dump_tdep);
3069
07b287a0
MS		 3070 /* Debug this file's internals. */
3071 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3072Set AArch64 debugging."), _("\
3073Show AArch64 debugging."), _("\
3074When on, AArch64 specific debugging is enabled."),
3075 NULL,
3076 show_aarch64_debug,
3077 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3078
3079#if GDB_SELF_TEST
1526853e
SM		 3080 selftests::register_test ("aarch64-analyze-prologue",
3081 selftests::aarch64_analyze_prologue_test);
3082 selftests::register_test ("aarch64-process-record",
3083 selftests::aarch64_process_record_test);
6654d750 3084 selftests::record_xml_tdesc ("aarch64.xml",
95228a0d 3085 aarch64_create_target_description (0));
4d9a9006 3086#endif
07b287a0 3087}
99afc88b
OJ		 3088
3089/* AArch64 process record-replay related structures, defines etc. */
3090
99afc88b
OJ		 3091#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3092 do \
3093 { \
3094 unsigned int reg_len = LENGTH; \
3095 if (reg_len) \
3096 { \
3097 REGS = XNEWVEC (uint32_t, reg_len); \
3098 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3099 } \
3100 } \
3101 while (0)
3102
3103#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3104 do \
3105 { \
3106 unsigned int mem_len = LENGTH; \
3107 if (mem_len) \
3108 { \
3109 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3110 memcpy(&MEMS->len, &RECORD_BUF[0], \
3111 sizeof(struct aarch64_mem_r) * LENGTH); \
3112 } \
3113 } \
3114 while (0)
3115
3116/* AArch64 record/replay structures and enumerations. */
3117
3118struct aarch64_mem_r
3119{
3120 uint64_t len; /* Record length. */
3121 uint64_t addr; /* Memory address. */
3122};
3123
3124enum aarch64_record_result
3125{
3126 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3127 AARCH64_RECORD_UNSUPPORTED,
3128 AARCH64_RECORD_UNKNOWN
3129};
3130
3131typedef struct insn_decode_record_t
3132{
3133 struct gdbarch *gdbarch;
3134 struct regcache *regcache;
3135 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3136 uint32_t aarch64_insn; /* Insn to be recorded. */
3137 uint32_t mem_rec_count; /* Count of memory records. */
3138 uint32_t reg_rec_count; /* Count of register records. */
3139 uint32_t *aarch64_regs; /* Registers to be recorded. */
3140 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3141} insn_decode_record;
3142
3143/* Record handler for data processing - register instructions. */
3144
3145static unsigned int
3146aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3147{
3148 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3149 uint32_t record_buf[4];
3150
3151 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3152 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3153 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3154
3155 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3156 {
3157 uint8_t setflags;
3158
3159 /* Logical (shifted register). */
3160 if (insn_bits24_27 == 0x0a)
3161 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3162 /* Add/subtract. */
3163 else if (insn_bits24_27 == 0x0b)
3164 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3165 else
3166 return AARCH64_RECORD_UNKNOWN;
3167
3168 record_buf[0] = reg_rd;
3169 aarch64_insn_r->reg_rec_count = 1;
3170 if (setflags)
3171 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3172 }
3173 else
3174 {
3175 if (insn_bits24_27 == 0x0b)
3176 {
3177 /* Data-processing (3 source). */
3178 record_buf[0] = reg_rd;
3179 aarch64_insn_r->reg_rec_count = 1;
3180 }
3181 else if (insn_bits24_27 == 0x0a)
3182 {
3183 if (insn_bits21_23 == 0x00)
3184 {
3185 /* Add/subtract (with carry). */
3186 record_buf[0] = reg_rd;
3187 aarch64_insn_r->reg_rec_count = 1;
3188 if (bit (aarch64_insn_r->aarch64_insn, 29))
3189 {
3190 record_buf[1] = AARCH64_CPSR_REGNUM;
3191 aarch64_insn_r->reg_rec_count = 2;
3192 }
3193 }
3194 else if (insn_bits21_23 == 0x02)
3195 {
3196 /* Conditional compare (register) and conditional compare
3197 (immediate) instructions. */
3198 record_buf[0] = AARCH64_CPSR_REGNUM;
3199 aarch64_insn_r->reg_rec_count = 1;
3200 }
3201 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3202 {
3203 /* CConditional select. */
3204 /* Data-processing (2 source). */
3205 /* Data-processing (1 source). */
3206 record_buf[0] = reg_rd;
3207 aarch64_insn_r->reg_rec_count = 1;
3208 }
3209 else
3210 return AARCH64_RECORD_UNKNOWN;
3211 }
3212 }
3213
3214 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3215 record_buf);
3216 return AARCH64_RECORD_SUCCESS;
3217}
3218
3219/* Record handler for data processing - immediate instructions. */
3220
3221static unsigned int
3222aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3223{
78cc6c2d 3224 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3225 uint32_t record_buf[4];
3226
3227 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3228 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3229 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3230
3231 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3232 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3233 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3234 {
3235 record_buf[0] = reg_rd;
3236 aarch64_insn_r->reg_rec_count = 1;
3237 }
3238 else if (insn_bits24_27 == 0x01)
3239 {
3240 /* Add/Subtract (immediate). */
3241 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3242 record_buf[0] = reg_rd;
3243 aarch64_insn_r->reg_rec_count = 1;
3244 if (setflags)
3245 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3246 }
3247 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3248 {
3249 /* Logical (immediate). */
3250 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3251 record_buf[0] = reg_rd;
3252 aarch64_insn_r->reg_rec_count = 1;
3253 if (setflags)
3254 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3255 }
3256 else
3257 return AARCH64_RECORD_UNKNOWN;
3258
3259 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3260 record_buf);
3261 return AARCH64_RECORD_SUCCESS;
3262}
3263
3264/* Record handler for branch, exception generation and system instructions. */
3265
3266static unsigned int
3267aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3268{
3269 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3270 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3271 uint32_t record_buf[4];
3272
3273 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3274 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3275 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3276
3277 if (insn_bits28_31 == 0x0d)
3278 {
3279 /* Exception generation instructions. */
3280 if (insn_bits24_27 == 0x04)
3281 {
5d98d3cd
YQ		 3282 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3283 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3284 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3285 {
3286 ULONGEST svc_number;
3287
3288 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3289 &svc_number);
3290 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3291 svc_number);
3292 }
3293 else
3294 return AARCH64_RECORD_UNSUPPORTED;
3295 }
3296 /* System instructions. */
3297 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3298 {
3299 uint32_t reg_rt, reg_crn;
3300
3301 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3302 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3303
3304 /* Record rt in case of sysl and mrs instructions. */
3305 if (bit (aarch64_insn_r->aarch64_insn, 21))
3306 {
3307 record_buf[0] = reg_rt;
3308 aarch64_insn_r->reg_rec_count = 1;
3309 }
3310 /* Record cpsr for hint and msr(immediate) instructions. */
3311 else if (reg_crn == 0x02 || reg_crn == 0x04)
3312 {
3313 record_buf[0] = AARCH64_CPSR_REGNUM;
3314 aarch64_insn_r->reg_rec_count = 1;
3315 }
3316 }
3317 /* Unconditional branch (register). */
3318 else if((insn_bits24_27 & 0x0e) == 0x06)
3319 {
3320 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3321 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3322 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3323 }
3324 else
3325 return AARCH64_RECORD_UNKNOWN;
3326 }
3327 /* Unconditional branch (immediate). */
3328 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3329 {
3330 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3331 if (bit (aarch64_insn_r->aarch64_insn, 31))
3332 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3333 }
3334 else
3335 /* Compare & branch (immediate), Test & branch (immediate) and
3336 Conditional branch (immediate). */
3337 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3338
3339 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3340 record_buf);
3341 return AARCH64_RECORD_SUCCESS;
3342}
3343
3344/* Record handler for advanced SIMD load and store instructions. */
3345
3346static unsigned int
3347aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3348{
3349 CORE_ADDR address;
3350 uint64_t addr_offset = 0;
3351 uint32_t record_buf[24];
3352 uint64_t record_buf_mem[24];
3353 uint32_t reg_rn, reg_rt;
3354 uint32_t reg_index = 0, mem_index = 0;
3355 uint8_t opcode_bits, size_bits;
3356
3357 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3358 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3359 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3360 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3361 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3362
3363 if (record_debug)
b277c936 3364 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3365
3366 /* Load/store single structure. */
3367 if (bit (aarch64_insn_r->aarch64_insn, 24))
3368 {
3369 uint8_t sindex, scale, selem, esize, replicate = 0;
3370 scale = opcode_bits >> 2;
3371 selem = ((opcode_bits & 0x02) |
3372 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3373 switch (scale)
3374 {
3375 case 1:
3376 if (size_bits & 0x01)
3377 return AARCH64_RECORD_UNKNOWN;
3378 break;
3379 case 2:
3380 if ((size_bits >> 1) & 0x01)
3381 return AARCH64_RECORD_UNKNOWN;
3382 if (size_bits & 0x01)
3383 {
3384 if (!((opcode_bits >> 1) & 0x01))
3385 scale = 3;
3386 else
3387 return AARCH64_RECORD_UNKNOWN;
3388 }
3389 break;
3390 case 3:
3391 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3392 {
3393 scale = size_bits;
3394 replicate = 1;
3395 break;
3396 }
3397 else
3398 return AARCH64_RECORD_UNKNOWN;
3399 default:
3400 break;
3401 }
3402 esize = 8 << scale;
3403 if (replicate)
3404 for (sindex = 0; sindex < selem; sindex++)
3405 {
3406 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3407 reg_rt = (reg_rt + 1) % 32;
3408 }
3409 else
3410 {
3411 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3412 {
3413 if (bit (aarch64_insn_r->aarch64_insn, 22))
3414 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3415 else
3416 {
3417 record_buf_mem[mem_index++] = esize / 8;
3418 record_buf_mem[mem_index++] = address + addr_offset;
3419 }
3420 addr_offset = addr_offset + (esize / 8);
3421 reg_rt = (reg_rt + 1) % 32;
3422 }
99afc88b
OJ		 3423 }
3424 }
3425 /* Load/store multiple structure. */
3426 else
3427 {
3428 uint8_t selem, esize, rpt, elements;
3429 uint8_t eindex, rindex;
3430
3431 esize = 8 << size_bits;
3432 if (bit (aarch64_insn_r->aarch64_insn, 30))
3433 elements = 128 / esize;
3434 else
3435 elements = 64 / esize;
3436
3437 switch (opcode_bits)
3438 {
3439 /*LD/ST4 (4 Registers). */
3440 case 0:
3441 rpt = 1;
3442 selem = 4;
3443 break;
3444 /*LD/ST1 (4 Registers). */
3445 case 2:
3446 rpt = 4;
3447 selem = 1;
3448 break;
3449 /*LD/ST3 (3 Registers). */
3450 case 4:
3451 rpt = 1;
3452 selem = 3;
3453 break;
3454 /*LD/ST1 (3 Registers). */
3455 case 6:
3456 rpt = 3;
3457 selem = 1;
3458 break;
3459 /*LD/ST1 (1 Register). */
3460 case 7:
3461 rpt = 1;
3462 selem = 1;
3463 break;
3464 /*LD/ST2 (2 Registers). */
3465 case 8:
3466 rpt = 1;
3467 selem = 2;
3468 break;
3469 /*LD/ST1 (2 Registers). */
3470 case 10:
3471 rpt = 2;
3472 selem = 1;
3473 break;
3474 default:
3475 return AARCH64_RECORD_UNSUPPORTED;
3476 break;
3477 }
3478 for (rindex = 0; rindex < rpt; rindex++)
3479 for (eindex = 0; eindex < elements; eindex++)
3480 {
3481 uint8_t reg_tt, sindex;
3482 reg_tt = (reg_rt + rindex) % 32;
3483 for (sindex = 0; sindex < selem; sindex++)
3484 {
3485 if (bit (aarch64_insn_r->aarch64_insn, 22))
3486 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3487 else
3488 {
3489 record_buf_mem[mem_index++] = esize / 8;
3490 record_buf_mem[mem_index++] = address + addr_offset;
3491 }
3492 addr_offset = addr_offset + (esize / 8);
3493 reg_tt = (reg_tt + 1) % 32;
3494 }
3495 }
3496 }
3497
3498 if (bit (aarch64_insn_r->aarch64_insn, 23))
3499 record_buf[reg_index++] = reg_rn;
3500
3501 aarch64_insn_r->reg_rec_count = reg_index;
3502 aarch64_insn_r->mem_rec_count = mem_index / 2;
3503 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3504 record_buf_mem);
3505 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3506 record_buf);
3507 return AARCH64_RECORD_SUCCESS;
3508}
3509
3510/* Record handler for load and store instructions. */
3511
3512static unsigned int
3513aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3514{
3515 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3516 uint8_t insn_bit23, insn_bit21;
3517 uint8_t opc, size_bits, ld_flag, vector_flag;
3518 uint32_t reg_rn, reg_rt, reg_rt2;
3519 uint64_t datasize, offset;
3520 uint32_t record_buf[8];
3521 uint64_t record_buf_mem[8];
3522 CORE_ADDR address;
3523
3524 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3525 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3526 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3527 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3528 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3529 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3530 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3531 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3532 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3533 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3534 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3535
3536 /* Load/store exclusive. */
3537 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3538 {
3539 if (record_debug)
b277c936 3540 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3541
3542 if (ld_flag)
3543 {
3544 record_buf[0] = reg_rt;
3545 aarch64_insn_r->reg_rec_count = 1;
3546 if (insn_bit21)
3547 {
3548 record_buf[1] = reg_rt2;
3549 aarch64_insn_r->reg_rec_count = 2;
3550 }
3551 }
3552 else
3553 {
3554 if (insn_bit21)
3555 datasize = (8 << size_bits) * 2;
3556 else
3557 datasize = (8 << size_bits);
3558 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3559 &address);
3560 record_buf_mem[0] = datasize / 8;
3561 record_buf_mem[1] = address;
3562 aarch64_insn_r->mem_rec_count = 1;
3563 if (!insn_bit23)
3564 {
3565 /* Save register rs. */
3566 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3567 aarch64_insn_r->reg_rec_count = 1;
3568 }
3569 }
3570 }
3571 /* Load register (literal) instructions decoding. */
3572 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3573 {
3574 if (record_debug)
b277c936 3575 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3576 if (vector_flag)
3577 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3578 else
3579 record_buf[0] = reg_rt;
3580 aarch64_insn_r->reg_rec_count = 1;
3581 }
3582 /* All types of load/store pair instructions decoding. */
3583 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3584 {
3585 if (record_debug)
b277c936 3586 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3587
3588 if (ld_flag)
3589 {
3590 if (vector_flag)
3591 {
3592 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3593 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3594 }
3595 else
3596 {
3597 record_buf[0] = reg_rt;
3598 record_buf[1] = reg_rt2;
3599 }
3600 aarch64_insn_r->reg_rec_count = 2;
3601 }
3602 else
3603 {
3604 uint16_t imm7_off;
3605 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3606 if (!vector_flag)
3607 size_bits = size_bits >> 1;
3608 datasize = 8 << (2 + size_bits);
3609 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3610 offset = offset << (2 + size_bits);
3611 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3612 &address);
3613 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3614 {
3615 if (imm7_off & 0x40)
3616 address = address - offset;
3617 else
3618 address = address + offset;
3619 }
3620
3621 record_buf_mem[0] = datasize / 8;
3622 record_buf_mem[1] = address;
3623 record_buf_mem[2] = datasize / 8;
3624 record_buf_mem[3] = address + (datasize / 8);
3625 aarch64_insn_r->mem_rec_count = 2;
3626 }
3627 if (bit (aarch64_insn_r->aarch64_insn, 23))
3628 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3629 }
3630 /* Load/store register (unsigned immediate) instructions. */
3631 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3632 {
3633 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3634 if (!(opc >> 1))
33877125
YQ		 3635 {
3636 if (opc & 0x01)
3637 ld_flag = 0x01;
3638 else
3639 ld_flag = 0x0;
3640 }
99afc88b 3641 else
33877125 3642 {
1e2b521d
YQ		 3643 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3644 {
3645 /* PRFM (immediate) */
3646 return AARCH64_RECORD_SUCCESS;
3647 }
3648 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3649 {
3650 /* LDRSW (immediate) */
3651 ld_flag = 0x1;
3652 }
33877125 3653 else
1e2b521d
YQ		 3654 {
3655 if (opc & 0x01)
3656 ld_flag = 0x01;
3657 else
3658 ld_flag = 0x0;
3659 }
33877125 3660 }
99afc88b
OJ		 3661
3662 if (record_debug)
3663 {
b277c936
PL		 3664 debug_printf ("Process record: load/store (unsigned immediate):"
3665 " size %x V %d opc %x\n", size_bits, vector_flag,
3666 opc);
99afc88b
OJ		 3667 }
3668
3669 if (!ld_flag)
3670 {
3671 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3672 datasize = 8 << size_bits;
3673 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3674 &address);
3675 offset = offset << size_bits;
3676 address = address + offset;
3677
3678 record_buf_mem[0] = datasize >> 3;
3679 record_buf_mem[1] = address;
3680 aarch64_insn_r->mem_rec_count = 1;
3681 }
3682 else
3683 {
3684 if (vector_flag)
3685 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3686 else
3687 record_buf[0] = reg_rt;
3688 aarch64_insn_r->reg_rec_count = 1;
3689 }
3690 }
3691 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 3692 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3693 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 3694 {
3695 if (record_debug)
b277c936 3696 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 3697 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3698 if (!(opc >> 1))
3699 if (opc & 0x01)
3700 ld_flag = 0x01;
3701 else
3702 ld_flag = 0x0;
3703 else
3704 if (size_bits != 0x03)
3705 ld_flag = 0x01;
3706 else
3707 return AARCH64_RECORD_UNKNOWN;
3708
3709 if (!ld_flag)
3710 {
d9436c7c
PA		 3711 ULONGEST reg_rm_val;
3712
99afc88b
OJ		 3713 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3714 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
3715 if (bit (aarch64_insn_r->aarch64_insn, 12))
3716 offset = reg_rm_val << size_bits;
3717 else
3718 offset = reg_rm_val;
3719 datasize = 8 << size_bits;
3720 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3721 &address);
3722 address = address + offset;
3723 record_buf_mem[0] = datasize >> 3;
3724 record_buf_mem[1] = address;
3725 aarch64_insn_r->mem_rec_count = 1;
3726 }
3727 else
3728 {
3729 if (vector_flag)
3730 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3731 else
3732 record_buf[0] = reg_rt;
3733 aarch64_insn_r->reg_rec_count = 1;
3734 }
3735 }
3736 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 3737 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3738 && !insn_bit21)
99afc88b
OJ		 3739 {
3740 if (record_debug)
3741 {
b277c936
PL		 3742 debug_printf ("Process record: load/store "
3743 "(immediate and unprivileged)\n");
99afc88b
OJ		 3744 }
3745 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3746 if (!(opc >> 1))
3747 if (opc & 0x01)
3748 ld_flag = 0x01;
3749 else
3750 ld_flag = 0x0;
3751 else
3752 if (size_bits != 0x03)
3753 ld_flag = 0x01;
3754 else
3755 return AARCH64_RECORD_UNKNOWN;
3756
3757 if (!ld_flag)
3758 {
3759 uint16_t imm9_off;
3760 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3761 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3762 datasize = 8 << size_bits;
3763 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3764 &address);
3765 if (insn_bits10_11 != 0x01)
3766 {
3767 if (imm9_off & 0x0100)
3768 address = address - offset;
3769 else
3770 address = address + offset;
3771 }
3772 record_buf_mem[0] = datasize >> 3;
3773 record_buf_mem[1] = address;
3774 aarch64_insn_r->mem_rec_count = 1;
3775 }
3776 else
3777 {
3778 if (vector_flag)
3779 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3780 else
3781 record_buf[0] = reg_rt;
3782 aarch64_insn_r->reg_rec_count = 1;
3783 }
3784 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3785 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3786 }
3787 /* Advanced SIMD load/store instructions. */
3788 else
3789 return aarch64_record_asimd_load_store (aarch64_insn_r);
3790
3791 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3792 record_buf_mem);
3793 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3794 record_buf);
3795 return AARCH64_RECORD_SUCCESS;
3796}
3797
3798/* Record handler for data processing SIMD and floating point instructions. */
3799
3800static unsigned int
3801aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3802{
3803 uint8_t insn_bit21, opcode, rmode, reg_rd;
3804 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3805 uint8_t insn_bits11_14;
3806 uint32_t record_buf[2];
3807
3808 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3809 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3810 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3811 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3812 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3813 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3814 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3815 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3816 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3817
3818 if (record_debug)
b277c936 3819 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 3820
3821 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3822 {
3823 /* Floating point - fixed point conversion instructions. */
3824 if (!insn_bit21)
3825 {
3826 if (record_debug)
b277c936 3827 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 3828
3829 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3830 record_buf[0] = reg_rd;
3831 else
3832 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3833 }
3834 /* Floating point - conditional compare instructions. */
3835 else if (insn_bits10_11 == 0x01)
3836 {
3837 if (record_debug)
b277c936 3838 debug_printf ("FP - conditional compare");
99afc88b
OJ		 3839
3840 record_buf[0] = AARCH64_CPSR_REGNUM;
3841 }
3842 /* Floating point - data processing (2-source) and
3843 conditional select instructions. */
3844 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3845 {
3846 if (record_debug)
b277c936 3847 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 3848
3849 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3850 }
3851 else if (insn_bits10_11 == 0x00)
3852 {
3853 /* Floating point - immediate instructions. */
3854 if ((insn_bits12_15 & 0x01) == 0x01
3855 || (insn_bits12_15 & 0x07) == 0x04)
3856 {
3857 if (record_debug)
b277c936 3858 debug_printf ("FP - immediate");
99afc88b
OJ		 3859 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3860 }
3861 /* Floating point - compare instructions. */
3862 else if ((insn_bits12_15 & 0x03) == 0x02)
3863 {
3864 if (record_debug)
b277c936 3865 debug_printf ("FP - immediate");
99afc88b
OJ		 3866 record_buf[0] = AARCH64_CPSR_REGNUM;
3867 }
3868 /* Floating point - integer conversions instructions. */
f62fce35 3869 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 3870 {
3871 /* Convert float to integer instruction. */
3872 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3873 {
3874 if (record_debug)
b277c936 3875 debug_printf ("float to int conversion");
99afc88b
OJ		 3876
3877 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3878 }
3879 /* Convert integer to float instruction. */
3880 else if ((opcode >> 1) == 0x01 && !rmode)
3881 {
3882 if (record_debug)
b277c936 3883 debug_printf ("int to float conversion");
99afc88b
OJ		 3884
3885 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3886 }
3887 /* Move float to integer instruction. */
3888 else if ((opcode >> 1) == 0x03)
3889 {
3890 if (record_debug)
b277c936 3891 debug_printf ("move float to int");
99afc88b
OJ		 3892
3893 if (!(opcode & 0x01))
3894 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3895 else
3896 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3897 }
f62fce35
YQ		 3898 else
3899 return AARCH64_RECORD_UNKNOWN;
99afc88b 3900 }
f62fce35
YQ		 3901 else
3902 return AARCH64_RECORD_UNKNOWN;
99afc88b 3903 }
f62fce35
YQ		 3904 else
3905 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 3906 }
3907 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3908 {
3909 if (record_debug)
b277c936 3910 debug_printf ("SIMD copy");
99afc88b
OJ		 3911
3912 /* Advanced SIMD copy instructions. */
3913 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3914 && !bit (aarch64_insn_r->aarch64_insn, 15)
3915 && bit (aarch64_insn_r->aarch64_insn, 10))
3916 {
3917 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3918 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3919 else
3920 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3921 }
3922 else
3923 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3924 }
3925 /* All remaining floating point or advanced SIMD instructions. */
3926 else
3927 {
3928 if (record_debug)
b277c936 3929 debug_printf ("all remain");
99afc88b
OJ		 3930
3931 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3932 }
3933
3934 if (record_debug)
b277c936 3935 debug_printf ("\n");
99afc88b
OJ		 3936
3937 aarch64_insn_r->reg_rec_count++;
3938 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3939 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3940 record_buf);
3941 return AARCH64_RECORD_SUCCESS;
3942}
3943
3944/* Decodes insns type and invokes its record handler. */
3945
3946static unsigned int
3947aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3948{
3949 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3950
3951 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3952 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3953 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3954 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3955
3956 /* Data processing - immediate instructions. */
3957 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3958 return aarch64_record_data_proc_imm (aarch64_insn_r);
3959
3960 /* Branch, exception generation and system instructions. */
3961 if (ins_bit26 && !ins_bit27 && ins_bit28)
3962 return aarch64_record_branch_except_sys (aarch64_insn_r);
3963
3964 /* Load and store instructions. */
3965 if (!ins_bit25 && ins_bit27)
3966 return aarch64_record_load_store (aarch64_insn_r);
3967
3968 /* Data processing - register instructions. */
3969 if (ins_bit25 && !ins_bit26 && ins_bit27)
3970 return aarch64_record_data_proc_reg (aarch64_insn_r);
3971
3972 /* Data processing - SIMD and floating point instructions. */
3973 if (ins_bit25 && ins_bit26 && ins_bit27)
3974 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3975
3976 return AARCH64_RECORD_UNSUPPORTED;
3977}
3978
3979/* Cleans up local record registers and memory allocations. */
3980
3981static void
3982deallocate_reg_mem (insn_decode_record *record)
3983{
3984 xfree (record->aarch64_regs);
3985 xfree (record->aarch64_mems);
3986}
3987
1e2b521d
YQ		 3988#if GDB_SELF_TEST
3989namespace selftests {
3990
3991static void
3992aarch64_process_record_test (void)
3993{
3994 struct gdbarch_info info;
3995 uint32_t ret;
3996
3997 gdbarch_info_init (&info);
3998 info.bfd_arch_info = bfd_scan_arch ("aarch64");
3999
4000 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4001 SELF_CHECK (gdbarch != NULL);
4002
4003 insn_decode_record aarch64_record;
4004
4005 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4006 aarch64_record.regcache = NULL;
4007 aarch64_record.this_addr = 0;
4008 aarch64_record.gdbarch = gdbarch;
4009
4010 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4011 aarch64_record.aarch64_insn = 0xf9800020;
4012 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4013 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4014 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4015 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4016
4017 deallocate_reg_mem (&aarch64_record);
4018}
4019
4020} // namespace selftests
4021#endif /* GDB_SELF_TEST */
4022
99afc88b
OJ		 4023/* Parse the current instruction and record the values of the registers and
4024 memory that will be changed in current instruction to record_arch_list
4025 return -1 if something is wrong. */
4026
4027int
4028aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4029 CORE_ADDR insn_addr)
4030{
4031 uint32_t rec_no = 0;
4032 uint8_t insn_size = 4;
4033 uint32_t ret = 0;
99afc88b
OJ		 4034 gdb_byte buf[insn_size];
4035 insn_decode_record aarch64_record;
4036
4037 memset (&buf[0], 0, insn_size);
4038 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4039 target_read_memory (insn_addr, &buf[0], insn_size);
4040 aarch64_record.aarch64_insn
4041 = (uint32_t) extract_unsigned_integer (&buf[0],
4042 insn_size,
4043 gdbarch_byte_order (gdbarch));
4044 aarch64_record.regcache = regcache;
4045 aarch64_record.this_addr = insn_addr;
4046 aarch64_record.gdbarch = gdbarch;
4047
4048 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4049 if (ret == AARCH64_RECORD_UNSUPPORTED)
4050 {
4051 printf_unfiltered (_("Process record does not support instruction "
4052 "0x%0x at address %s.\n"),
4053 aarch64_record.aarch64_insn,
4054 paddress (gdbarch, insn_addr));
4055 ret = -1;
4056 }
4057
4058 if (0 == ret)
4059 {
4060 /* Record registers. */
4061 record_full_arch_list_add_reg (aarch64_record.regcache,
4062 AARCH64_PC_REGNUM);
4063 /* Always record register CPSR. */
4064 record_full_arch_list_add_reg (aarch64_record.regcache,
4065 AARCH64_CPSR_REGNUM);
4066 if (aarch64_record.aarch64_regs)
4067 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4068 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4069 aarch64_record.aarch64_regs[rec_no]))
4070 ret = -1;
4071
4072 /* Record memories. */
4073 if (aarch64_record.aarch64_mems)
4074 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4075 if (record_full_arch_list_add_mem
4076 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4077 aarch64_record.aarch64_mems[rec_no].len))
4078 ret = -1;
4079
4080 if (record_full_arch_list_add_end ())
4081 ret = -1;
4082 }
4083
4084 deallocate_reg_mem (&aarch64_record);
4085 return ret;
4086}
GDB Binutils - Deliverables
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