Commit | Line | Data |
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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
61baf725 | 3 | Copyright (C) 2009-2017 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
07b287a0 MS |
27 | #include "dis-asm.h" |
28 | #include "regcache.h" | |
29 | #include "reggroups.h" | |
30 | #include "doublest.h" | |
31 | #include "value.h" | |
32 | #include "arch-utils.h" | |
33 | #include "osabi.h" | |
34 | #include "frame-unwind.h" | |
35 | #include "frame-base.h" | |
36 | #include "trad-frame.h" | |
37 | #include "objfiles.h" | |
38 | #include "dwarf2-frame.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "prologue-value.h" | |
41 | #include "target-descriptions.h" | |
42 | #include "user-regs.h" | |
43 | #include "language.h" | |
44 | #include "infcall.h" | |
ea873d8e PL |
45 | #include "ax.h" |
46 | #include "ax-gdb.h" | |
4d9a9006 | 47 | #include "selftest.h" |
07b287a0 MS |
48 | |
49 | #include "aarch64-tdep.h" | |
50 | ||
51 | #include "elf-bfd.h" | |
52 | #include "elf/aarch64.h" | |
53 | ||
07b287a0 MS |
54 | #include "vec.h" |
55 | ||
99afc88b OJ |
56 | #include "record.h" |
57 | #include "record-full.h" | |
58 | ||
07b287a0 | 59 | #include "features/aarch64.c" |
07b287a0 | 60 | |
787749ea PL |
61 | #include "arch/aarch64-insn.h" |
62 | ||
f77ee802 | 63 | #include "opcode/aarch64.h" |
325fac50 | 64 | #include <algorithm> |
f77ee802 YQ |
65 | |
66 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
67 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
68 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
69 | ||
07b287a0 MS |
70 | /* Pseudo register base numbers. */ |
71 | #define AARCH64_Q0_REGNUM 0 | |
187f5d00 | 72 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT) |
07b287a0 MS |
73 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) |
74 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
75 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
76 | ||
77 | /* The standard register names, and all the valid aliases for them. */ | |
78 | static const struct | |
79 | { | |
80 | const char *const name; | |
81 | int regnum; | |
82 | } aarch64_register_aliases[] = | |
83 | { | |
84 | /* 64-bit register names. */ | |
85 | {"fp", AARCH64_FP_REGNUM}, | |
86 | {"lr", AARCH64_LR_REGNUM}, | |
87 | {"sp", AARCH64_SP_REGNUM}, | |
88 | ||
89 | /* 32-bit register names. */ | |
90 | {"w0", AARCH64_X0_REGNUM + 0}, | |
91 | {"w1", AARCH64_X0_REGNUM + 1}, | |
92 | {"w2", AARCH64_X0_REGNUM + 2}, | |
93 | {"w3", AARCH64_X0_REGNUM + 3}, | |
94 | {"w4", AARCH64_X0_REGNUM + 4}, | |
95 | {"w5", AARCH64_X0_REGNUM + 5}, | |
96 | {"w6", AARCH64_X0_REGNUM + 6}, | |
97 | {"w7", AARCH64_X0_REGNUM + 7}, | |
98 | {"w8", AARCH64_X0_REGNUM + 8}, | |
99 | {"w9", AARCH64_X0_REGNUM + 9}, | |
100 | {"w10", AARCH64_X0_REGNUM + 10}, | |
101 | {"w11", AARCH64_X0_REGNUM + 11}, | |
102 | {"w12", AARCH64_X0_REGNUM + 12}, | |
103 | {"w13", AARCH64_X0_REGNUM + 13}, | |
104 | {"w14", AARCH64_X0_REGNUM + 14}, | |
105 | {"w15", AARCH64_X0_REGNUM + 15}, | |
106 | {"w16", AARCH64_X0_REGNUM + 16}, | |
107 | {"w17", AARCH64_X0_REGNUM + 17}, | |
108 | {"w18", AARCH64_X0_REGNUM + 18}, | |
109 | {"w19", AARCH64_X0_REGNUM + 19}, | |
110 | {"w20", AARCH64_X0_REGNUM + 20}, | |
111 | {"w21", AARCH64_X0_REGNUM + 21}, | |
112 | {"w22", AARCH64_X0_REGNUM + 22}, | |
113 | {"w23", AARCH64_X0_REGNUM + 23}, | |
114 | {"w24", AARCH64_X0_REGNUM + 24}, | |
115 | {"w25", AARCH64_X0_REGNUM + 25}, | |
116 | {"w26", AARCH64_X0_REGNUM + 26}, | |
117 | {"w27", AARCH64_X0_REGNUM + 27}, | |
118 | {"w28", AARCH64_X0_REGNUM + 28}, | |
119 | {"w29", AARCH64_X0_REGNUM + 29}, | |
120 | {"w30", AARCH64_X0_REGNUM + 30}, | |
121 | ||
122 | /* specials */ | |
123 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
124 | {"ip1", AARCH64_X0_REGNUM + 17} | |
125 | }; | |
126 | ||
127 | /* The required core 'R' registers. */ | |
128 | static const char *const aarch64_r_register_names[] = | |
129 | { | |
130 | /* These registers must appear in consecutive RAW register number | |
131 | order and they must begin with AARCH64_X0_REGNUM! */ | |
132 | "x0", "x1", "x2", "x3", | |
133 | "x4", "x5", "x6", "x7", | |
134 | "x8", "x9", "x10", "x11", | |
135 | "x12", "x13", "x14", "x15", | |
136 | "x16", "x17", "x18", "x19", | |
137 | "x20", "x21", "x22", "x23", | |
138 | "x24", "x25", "x26", "x27", | |
139 | "x28", "x29", "x30", "sp", | |
140 | "pc", "cpsr" | |
141 | }; | |
142 | ||
143 | /* The FP/SIMD 'V' registers. */ | |
144 | static const char *const aarch64_v_register_names[] = | |
145 | { | |
146 | /* These registers must appear in consecutive RAW register number | |
147 | order and they must begin with AARCH64_V0_REGNUM! */ | |
148 | "v0", "v1", "v2", "v3", | |
149 | "v4", "v5", "v6", "v7", | |
150 | "v8", "v9", "v10", "v11", | |
151 | "v12", "v13", "v14", "v15", | |
152 | "v16", "v17", "v18", "v19", | |
153 | "v20", "v21", "v22", "v23", | |
154 | "v24", "v25", "v26", "v27", | |
155 | "v28", "v29", "v30", "v31", | |
156 | "fpsr", | |
157 | "fpcr" | |
158 | }; | |
159 | ||
160 | /* AArch64 prologue cache structure. */ | |
161 | struct aarch64_prologue_cache | |
162 | { | |
db634143 PL |
163 | /* The program counter at the start of the function. It is used to |
164 | identify this frame as a prologue frame. */ | |
165 | CORE_ADDR func; | |
166 | ||
167 | /* The program counter at the time this frame was created; i.e. where | |
168 | this function was called from. It is used to identify this frame as a | |
169 | stub frame. */ | |
170 | CORE_ADDR prev_pc; | |
171 | ||
07b287a0 MS |
172 | /* The stack pointer at the time this frame was created; i.e. the |
173 | caller's stack pointer when this function was called. It is used | |
174 | to identify this frame. */ | |
175 | CORE_ADDR prev_sp; | |
176 | ||
7dfa3edc PL |
177 | /* Is the target available to read from? */ |
178 | int available_p; | |
179 | ||
07b287a0 MS |
180 | /* The frame base for this frame is just prev_sp - frame size. |
181 | FRAMESIZE is the distance from the frame pointer to the | |
182 | initial stack pointer. */ | |
183 | int framesize; | |
184 | ||
185 | /* The register used to hold the frame pointer for this frame. */ | |
186 | int framereg; | |
187 | ||
188 | /* Saved register offsets. */ | |
189 | struct trad_frame_saved_reg *saved_regs; | |
190 | }; | |
191 | ||
07b287a0 MS |
192 | static void |
193 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
194 | struct cmd_list_element *c, const char *value) | |
195 | { | |
196 | fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value); | |
197 | } | |
198 | ||
ffdbe864 YQ |
199 | namespace { |
200 | ||
4d9a9006 YQ |
201 | /* Abstract instruction reader. */ |
202 | ||
203 | class abstract_instruction_reader | |
204 | { | |
205 | public: | |
206 | /* Read in one instruction. */ | |
207 | virtual ULONGEST read (CORE_ADDR memaddr, int len, | |
208 | enum bfd_endian byte_order) = 0; | |
209 | }; | |
210 | ||
211 | /* Instruction reader from real target. */ | |
212 | ||
213 | class instruction_reader : public abstract_instruction_reader | |
214 | { | |
215 | public: | |
216 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
217 | { | |
fc2f703e | 218 | return read_code_unsigned_integer (memaddr, len, byte_order); |
4d9a9006 YQ |
219 | } |
220 | }; | |
221 | ||
ffdbe864 YQ |
222 | } // namespace |
223 | ||
07b287a0 MS |
224 | /* Analyze a prologue, looking for a recognizable stack frame |
225 | and frame pointer. Scan until we encounter a store that could | |
226 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
227 | ||
228 | static CORE_ADDR | |
229 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
230 | CORE_ADDR start, CORE_ADDR limit, | |
4d9a9006 YQ |
231 | struct aarch64_prologue_cache *cache, |
232 | abstract_instruction_reader& reader) | |
07b287a0 MS |
233 | { |
234 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
235 | int i; | |
187f5d00 YQ |
236 | /* Track X registers and D registers in prologue. */ |
237 | pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT]; | |
07b287a0 MS |
238 | struct pv_area *stack; |
239 | struct cleanup *back_to; | |
240 | ||
187f5d00 | 241 | for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++) |
07b287a0 MS |
242 | regs[i] = pv_register (i, 0); |
243 | stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
244 | back_to = make_cleanup_free_pv_area (stack); | |
245 | ||
246 | for (; start < limit; start += 4) | |
247 | { | |
248 | uint32_t insn; | |
d9ebcbce | 249 | aarch64_inst inst; |
07b287a0 | 250 | |
4d9a9006 | 251 | insn = reader.read (start, 4, byte_order_for_code); |
07b287a0 | 252 | |
d9ebcbce YQ |
253 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
254 | break; | |
255 | ||
256 | if (inst.opcode->iclass == addsub_imm | |
257 | && (inst.opcode->op == OP_ADD | |
258 | || strcmp ("sub", inst.opcode->name) == 0)) | |
07b287a0 | 259 | { |
d9ebcbce YQ |
260 | unsigned rd = inst.operands[0].reg.regno; |
261 | unsigned rn = inst.operands[1].reg.regno; | |
262 | ||
263 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
264 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
265 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
266 | gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM); | |
267 | ||
268 | if (inst.opcode->op == OP_ADD) | |
269 | { | |
270 | regs[rd] = pv_add_constant (regs[rn], | |
271 | inst.operands[2].imm.value); | |
272 | } | |
273 | else | |
274 | { | |
275 | regs[rd] = pv_add_constant (regs[rn], | |
276 | -inst.operands[2].imm.value); | |
277 | } | |
278 | } | |
279 | else if (inst.opcode->iclass == pcreladdr | |
280 | && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP) | |
281 | { | |
282 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
283 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
284 | ||
285 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
07b287a0 | 286 | } |
d9ebcbce | 287 | else if (inst.opcode->iclass == branch_imm) |
07b287a0 MS |
288 | { |
289 | /* Stop analysis on branch. */ | |
290 | break; | |
291 | } | |
d9ebcbce | 292 | else if (inst.opcode->iclass == condbranch) |
07b287a0 MS |
293 | { |
294 | /* Stop analysis on branch. */ | |
295 | break; | |
296 | } | |
d9ebcbce | 297 | else if (inst.opcode->iclass == branch_reg) |
07b287a0 MS |
298 | { |
299 | /* Stop analysis on branch. */ | |
300 | break; | |
301 | } | |
d9ebcbce | 302 | else if (inst.opcode->iclass == compbranch) |
07b287a0 MS |
303 | { |
304 | /* Stop analysis on branch. */ | |
305 | break; | |
306 | } | |
d9ebcbce YQ |
307 | else if (inst.opcode->op == OP_MOVZ) |
308 | { | |
309 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
310 | regs[inst.operands[0].reg.regno] = pv_unknown (); | |
311 | } | |
312 | else if (inst.opcode->iclass == log_shift | |
313 | && strcmp (inst.opcode->name, "orr") == 0) | |
07b287a0 | 314 | { |
d9ebcbce YQ |
315 | unsigned rd = inst.operands[0].reg.regno; |
316 | unsigned rn = inst.operands[1].reg.regno; | |
317 | unsigned rm = inst.operands[2].reg.regno; | |
318 | ||
319 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
320 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn); | |
321 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT); | |
322 | ||
323 | if (inst.operands[2].shifter.amount == 0 | |
324 | && rn == AARCH64_SP_REGNUM) | |
07b287a0 MS |
325 | regs[rd] = regs[rm]; |
326 | else | |
327 | { | |
328 | if (aarch64_debug) | |
b277c936 PL |
329 | { |
330 | debug_printf ("aarch64: prologue analysis gave up " | |
0a0da556 | 331 | "addr=%s opcode=0x%x (orr x register)\n", |
b277c936 PL |
332 | core_addr_to_string_nz (start), insn); |
333 | } | |
07b287a0 MS |
334 | break; |
335 | } | |
336 | } | |
d9ebcbce | 337 | else if (inst.opcode->op == OP_STUR) |
07b287a0 | 338 | { |
d9ebcbce YQ |
339 | unsigned rt = inst.operands[0].reg.regno; |
340 | unsigned rn = inst.operands[1].addr.base_regno; | |
341 | int is64 | |
342 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
343 | ||
344 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
345 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); | |
346 | gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); | |
347 | gdb_assert (!inst.operands[1].addr.offset.is_reg); | |
348 | ||
349 | pv_area_store (stack, pv_add_constant (regs[rn], | |
350 | inst.operands[1].addr.offset.imm), | |
07b287a0 MS |
351 | is64 ? 8 : 4, regs[rt]); |
352 | } | |
d9ebcbce | 353 | else if ((inst.opcode->iclass == ldstpair_off |
03bcd739 YQ |
354 | || (inst.opcode->iclass == ldstpair_indexed |
355 | && inst.operands[2].addr.preind)) | |
d9ebcbce | 356 | && strcmp ("stp", inst.opcode->name) == 0) |
07b287a0 | 357 | { |
03bcd739 | 358 | /* STP with addressing mode Pre-indexed and Base register. */ |
187f5d00 YQ |
359 | unsigned rt1; |
360 | unsigned rt2; | |
d9ebcbce YQ |
361 | unsigned rn = inst.operands[2].addr.base_regno; |
362 | int32_t imm = inst.operands[2].addr.offset.imm; | |
363 | ||
187f5d00 YQ |
364 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
365 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
366 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2 | |
367 | || inst.operands[1].type == AARCH64_OPND_Ft2); | |
d9ebcbce YQ |
368 | gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7); |
369 | gdb_assert (!inst.operands[2].addr.offset.is_reg); | |
370 | ||
07b287a0 MS |
371 | /* If recording this store would invalidate the store area |
372 | (perhaps because rn is not known) then we should abandon | |
373 | further prologue analysis. */ | |
374 | if (pv_area_store_would_trash (stack, | |
375 | pv_add_constant (regs[rn], imm))) | |
376 | break; | |
377 | ||
378 | if (pv_area_store_would_trash (stack, | |
379 | pv_add_constant (regs[rn], imm + 8))) | |
380 | break; | |
381 | ||
187f5d00 YQ |
382 | rt1 = inst.operands[0].reg.regno; |
383 | rt2 = inst.operands[1].reg.regno; | |
384 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
385 | { | |
386 | /* Only bottom 64-bit of each V register (D register) need | |
387 | to be preserved. */ | |
388 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
389 | rt1 += AARCH64_X_REGISTER_COUNT; | |
390 | rt2 += AARCH64_X_REGISTER_COUNT; | |
391 | } | |
392 | ||
07b287a0 MS |
393 | pv_area_store (stack, pv_add_constant (regs[rn], imm), 8, |
394 | regs[rt1]); | |
395 | pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8, | |
396 | regs[rt2]); | |
14ac654f | 397 | |
d9ebcbce | 398 | if (inst.operands[2].addr.writeback) |
93d96012 | 399 | regs[rn] = pv_add_constant (regs[rn], imm); |
07b287a0 | 400 | |
07b287a0 | 401 | } |
432ec081 YQ |
402 | else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ |
403 | || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ | |
404 | && (inst.opcode->op == OP_STR_POS | |
405 | || inst.opcode->op == OP_STRF_POS))) | |
406 | && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM | |
407 | && strcmp ("str", inst.opcode->name) == 0) | |
408 | { | |
409 | /* STR (immediate) */ | |
410 | unsigned int rt = inst.operands[0].reg.regno; | |
411 | int32_t imm = inst.operands[1].addr.offset.imm; | |
412 | unsigned int rn = inst.operands[1].addr.base_regno; | |
413 | bool is64 | |
414 | = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); | |
415 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt | |
416 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
417 | ||
418 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
419 | { | |
420 | /* Only bottom 64-bit of each V register (D register) need | |
421 | to be preserved. */ | |
422 | gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); | |
423 | rt += AARCH64_X_REGISTER_COUNT; | |
424 | } | |
425 | ||
426 | pv_area_store (stack, pv_add_constant (regs[rn], imm), | |
427 | is64 ? 8 : 4, regs[rt]); | |
428 | if (inst.operands[1].addr.writeback) | |
429 | regs[rn] = pv_add_constant (regs[rn], imm); | |
430 | } | |
d9ebcbce | 431 | else if (inst.opcode->iclass == testbranch) |
07b287a0 MS |
432 | { |
433 | /* Stop analysis on branch. */ | |
434 | break; | |
435 | } | |
436 | else | |
437 | { | |
438 | if (aarch64_debug) | |
b277c936 | 439 | { |
0a0da556 | 440 | debug_printf ("aarch64: prologue analysis gave up addr=%s" |
b277c936 PL |
441 | " opcode=0x%x\n", |
442 | core_addr_to_string_nz (start), insn); | |
443 | } | |
07b287a0 MS |
444 | break; |
445 | } | |
446 | } | |
447 | ||
448 | if (cache == NULL) | |
449 | { | |
450 | do_cleanups (back_to); | |
451 | return start; | |
452 | } | |
453 | ||
454 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
455 | { | |
456 | /* Frame pointer is fp. Frame size is constant. */ | |
457 | cache->framereg = AARCH64_FP_REGNUM; | |
458 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
459 | } | |
460 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
461 | { | |
462 | /* Try the stack pointer. */ | |
463 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
464 | cache->framereg = AARCH64_SP_REGNUM; | |
465 | } | |
466 | else | |
467 | { | |
468 | /* We're just out of luck. We don't know where the frame is. */ | |
469 | cache->framereg = -1; | |
470 | cache->framesize = 0; | |
471 | } | |
472 | ||
473 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
474 | { | |
475 | CORE_ADDR offset; | |
476 | ||
477 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
478 | cache->saved_regs[i].addr = offset; | |
479 | } | |
480 | ||
187f5d00 YQ |
481 | for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++) |
482 | { | |
483 | int regnum = gdbarch_num_regs (gdbarch); | |
484 | CORE_ADDR offset; | |
485 | ||
486 | if (pv_area_find_reg (stack, gdbarch, i + AARCH64_X_REGISTER_COUNT, | |
487 | &offset)) | |
488 | cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset; | |
489 | } | |
490 | ||
07b287a0 MS |
491 | do_cleanups (back_to); |
492 | return start; | |
493 | } | |
494 | ||
4d9a9006 YQ |
495 | static CORE_ADDR |
496 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
497 | CORE_ADDR start, CORE_ADDR limit, | |
498 | struct aarch64_prologue_cache *cache) | |
499 | { | |
500 | instruction_reader reader; | |
501 | ||
502 | return aarch64_analyze_prologue (gdbarch, start, limit, cache, | |
503 | reader); | |
504 | } | |
505 | ||
506 | #if GDB_SELF_TEST | |
507 | ||
508 | namespace selftests { | |
509 | ||
510 | /* Instruction reader from manually cooked instruction sequences. */ | |
511 | ||
512 | class instruction_reader_test : public abstract_instruction_reader | |
513 | { | |
514 | public: | |
515 | template<size_t SIZE> | |
516 | explicit instruction_reader_test (const uint32_t (&insns)[SIZE]) | |
517 | : m_insns (insns), m_insns_size (SIZE) | |
518 | {} | |
519 | ||
520 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
521 | { | |
522 | SELF_CHECK (len == 4); | |
523 | SELF_CHECK (memaddr % 4 == 0); | |
524 | SELF_CHECK (memaddr / 4 < m_insns_size); | |
525 | ||
526 | return m_insns[memaddr / 4]; | |
527 | } | |
528 | ||
529 | private: | |
530 | const uint32_t *m_insns; | |
531 | size_t m_insns_size; | |
532 | }; | |
533 | ||
534 | static void | |
535 | aarch64_analyze_prologue_test (void) | |
536 | { | |
537 | struct gdbarch_info info; | |
538 | ||
539 | gdbarch_info_init (&info); | |
540 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
541 | ||
542 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
543 | SELF_CHECK (gdbarch != NULL); | |
544 | ||
545 | /* Test the simple prologue in which frame pointer is used. */ | |
546 | { | |
547 | struct aarch64_prologue_cache cache; | |
548 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
549 | ||
550 | static const uint32_t insns[] = { | |
551 | 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */ | |
552 | 0x910003fd, /* mov x29, sp */ | |
553 | 0x97ffffe6, /* bl 0x400580 */ | |
554 | }; | |
555 | instruction_reader_test reader (insns); | |
556 | ||
557 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
558 | SELF_CHECK (end == 4 * 2); | |
559 | ||
560 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
561 | SELF_CHECK (cache.framesize == 272); | |
562 | ||
563 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
564 | { | |
565 | if (i == AARCH64_FP_REGNUM) | |
566 | SELF_CHECK (cache.saved_regs[i].addr == -272); | |
567 | else if (i == AARCH64_LR_REGNUM) | |
568 | SELF_CHECK (cache.saved_regs[i].addr == -264); | |
569 | else | |
570 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
571 | } | |
572 | ||
573 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
574 | { | |
575 | int regnum = gdbarch_num_regs (gdbarch); | |
576 | ||
577 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
578 | == -1); | |
579 | } | |
580 | } | |
432ec081 YQ |
581 | |
582 | /* Test a prologue in which STR is used and frame pointer is not | |
583 | used. */ | |
584 | { | |
585 | struct aarch64_prologue_cache cache; | |
586 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
587 | ||
588 | static const uint32_t insns[] = { | |
589 | 0xf81d0ff3, /* str x19, [sp, #-48]! */ | |
590 | 0xb9002fe0, /* str w0, [sp, #44] */ | |
591 | 0xf90013e1, /* str x1, [sp, #32]*/ | |
592 | 0xfd000fe0, /* str d0, [sp, #24] */ | |
593 | 0xaa0203f3, /* mov x19, x2 */ | |
594 | 0xf94013e0, /* ldr x0, [sp, #32] */ | |
595 | }; | |
596 | instruction_reader_test reader (insns); | |
597 | ||
598 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
599 | ||
600 | SELF_CHECK (end == 4 * 5); | |
601 | ||
602 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
603 | SELF_CHECK (cache.framesize == 48); | |
604 | ||
605 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
606 | { | |
607 | if (i == 1) | |
608 | SELF_CHECK (cache.saved_regs[i].addr == -16); | |
609 | else if (i == 19) | |
610 | SELF_CHECK (cache.saved_regs[i].addr == -48); | |
611 | else | |
612 | SELF_CHECK (cache.saved_regs[i].addr == -1); | |
613 | } | |
614 | ||
615 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
616 | { | |
617 | int regnum = gdbarch_num_regs (gdbarch); | |
618 | ||
619 | if (i == 0) | |
620 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
621 | == -24); | |
622 | else | |
623 | SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr | |
624 | == -1); | |
625 | } | |
626 | } | |
4d9a9006 YQ |
627 | } |
628 | } // namespace selftests | |
629 | #endif /* GDB_SELF_TEST */ | |
630 | ||
07b287a0 MS |
631 | /* Implement the "skip_prologue" gdbarch method. */ |
632 | ||
633 | static CORE_ADDR | |
634 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
635 | { | |
07b287a0 | 636 | CORE_ADDR func_addr, limit_pc; |
07b287a0 MS |
637 | |
638 | /* See if we can determine the end of the prologue via the symbol | |
639 | table. If so, then return either PC, or the PC after the | |
640 | prologue, whichever is greater. */ | |
641 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
642 | { | |
643 | CORE_ADDR post_prologue_pc | |
644 | = skip_prologue_using_sal (gdbarch, func_addr); | |
645 | ||
646 | if (post_prologue_pc != 0) | |
325fac50 | 647 | return std::max (pc, post_prologue_pc); |
07b287a0 MS |
648 | } |
649 | ||
650 | /* Can't determine prologue from the symbol table, need to examine | |
651 | instructions. */ | |
652 | ||
653 | /* Find an upper limit on the function prologue using the debug | |
654 | information. If the debug information could not be used to | |
655 | provide that bound, then use an arbitrary large number as the | |
656 | upper bound. */ | |
657 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
658 | if (limit_pc == 0) | |
659 | limit_pc = pc + 128; /* Magic. */ | |
660 | ||
661 | /* Try disassembling prologue. */ | |
662 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
663 | } | |
664 | ||
665 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
666 | cache CACHE. */ | |
667 | ||
668 | static void | |
669 | aarch64_scan_prologue (struct frame_info *this_frame, | |
670 | struct aarch64_prologue_cache *cache) | |
671 | { | |
672 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
673 | CORE_ADDR prologue_start; | |
674 | CORE_ADDR prologue_end; | |
675 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
676 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
677 | ||
db634143 PL |
678 | cache->prev_pc = prev_pc; |
679 | ||
07b287a0 MS |
680 | /* Assume we do not find a frame. */ |
681 | cache->framereg = -1; | |
682 | cache->framesize = 0; | |
683 | ||
684 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
685 | &prologue_end)) | |
686 | { | |
687 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
688 | ||
689 | if (sal.line == 0) | |
690 | { | |
691 | /* No line info so use the current PC. */ | |
692 | prologue_end = prev_pc; | |
693 | } | |
694 | else if (sal.end < prologue_end) | |
695 | { | |
696 | /* The next line begins after the function end. */ | |
697 | prologue_end = sal.end; | |
698 | } | |
699 | ||
325fac50 | 700 | prologue_end = std::min (prologue_end, prev_pc); |
07b287a0 MS |
701 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
702 | } | |
703 | else | |
704 | { | |
705 | CORE_ADDR frame_loc; | |
07b287a0 MS |
706 | |
707 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
708 | if (frame_loc == 0) | |
709 | return; | |
710 | ||
711 | cache->framereg = AARCH64_FP_REGNUM; | |
712 | cache->framesize = 16; | |
713 | cache->saved_regs[29].addr = 0; | |
714 | cache->saved_regs[30].addr = 8; | |
715 | } | |
716 | } | |
717 | ||
7dfa3edc PL |
718 | /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This |
719 | function may throw an exception if the inferior's registers or memory is | |
720 | not available. */ | |
07b287a0 | 721 | |
7dfa3edc PL |
722 | static void |
723 | aarch64_make_prologue_cache_1 (struct frame_info *this_frame, | |
724 | struct aarch64_prologue_cache *cache) | |
07b287a0 | 725 | { |
07b287a0 MS |
726 | CORE_ADDR unwound_fp; |
727 | int reg; | |
728 | ||
07b287a0 MS |
729 | aarch64_scan_prologue (this_frame, cache); |
730 | ||
731 | if (cache->framereg == -1) | |
7dfa3edc | 732 | return; |
07b287a0 MS |
733 | |
734 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
735 | if (unwound_fp == 0) | |
7dfa3edc | 736 | return; |
07b287a0 MS |
737 | |
738 | cache->prev_sp = unwound_fp + cache->framesize; | |
739 | ||
740 | /* Calculate actual addresses of saved registers using offsets | |
741 | determined by aarch64_analyze_prologue. */ | |
742 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
743 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
744 | cache->saved_regs[reg].addr += cache->prev_sp; | |
745 | ||
db634143 PL |
746 | cache->func = get_frame_func (this_frame); |
747 | ||
7dfa3edc PL |
748 | cache->available_p = 1; |
749 | } | |
750 | ||
751 | /* Allocate and fill in *THIS_CACHE with information about the prologue of | |
752 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
753 | Return a pointer to the current aarch64_prologue_cache in | |
754 | *THIS_CACHE. */ | |
755 | ||
756 | static struct aarch64_prologue_cache * | |
757 | aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache) | |
758 | { | |
759 | struct aarch64_prologue_cache *cache; | |
760 | ||
761 | if (*this_cache != NULL) | |
9a3c8263 | 762 | return (struct aarch64_prologue_cache *) *this_cache; |
7dfa3edc PL |
763 | |
764 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
765 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
766 | *this_cache = cache; | |
767 | ||
768 | TRY | |
769 | { | |
770 | aarch64_make_prologue_cache_1 (this_frame, cache); | |
771 | } | |
772 | CATCH (ex, RETURN_MASK_ERROR) | |
773 | { | |
774 | if (ex.error != NOT_AVAILABLE_ERROR) | |
775 | throw_exception (ex); | |
776 | } | |
777 | END_CATCH | |
778 | ||
07b287a0 MS |
779 | return cache; |
780 | } | |
781 | ||
7dfa3edc PL |
782 | /* Implement the "stop_reason" frame_unwind method. */ |
783 | ||
784 | static enum unwind_stop_reason | |
785 | aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
786 | void **this_cache) | |
787 | { | |
788 | struct aarch64_prologue_cache *cache | |
789 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
790 | ||
791 | if (!cache->available_p) | |
792 | return UNWIND_UNAVAILABLE; | |
793 | ||
794 | /* Halt the backtrace at "_start". */ | |
795 | if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
796 | return UNWIND_OUTERMOST; | |
797 | ||
798 | /* We've hit a wall, stop. */ | |
799 | if (cache->prev_sp == 0) | |
800 | return UNWIND_OUTERMOST; | |
801 | ||
802 | return UNWIND_NO_REASON; | |
803 | } | |
804 | ||
07b287a0 MS |
805 | /* Our frame ID for a normal frame is the current function's starting |
806 | PC and the caller's SP when we were called. */ | |
807 | ||
808 | static void | |
809 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
810 | void **this_cache, struct frame_id *this_id) | |
811 | { | |
7c8edfae PL |
812 | struct aarch64_prologue_cache *cache |
813 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 | 814 | |
7dfa3edc PL |
815 | if (!cache->available_p) |
816 | *this_id = frame_id_build_unavailable_stack (cache->func); | |
817 | else | |
818 | *this_id = frame_id_build (cache->prev_sp, cache->func); | |
07b287a0 MS |
819 | } |
820 | ||
821 | /* Implement the "prev_register" frame_unwind method. */ | |
822 | ||
823 | static struct value * | |
824 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
825 | void **this_cache, int prev_regnum) | |
826 | { | |
7c8edfae PL |
827 | struct aarch64_prologue_cache *cache |
828 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
829 | |
830 | /* If we are asked to unwind the PC, then we need to return the LR | |
831 | instead. The prologue may save PC, but it will point into this | |
832 | frame's prologue, not the next frame's resume location. */ | |
833 | if (prev_regnum == AARCH64_PC_REGNUM) | |
834 | { | |
835 | CORE_ADDR lr; | |
836 | ||
837 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
838 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); | |
839 | } | |
840 | ||
841 | /* SP is generally not saved to the stack, but this frame is | |
842 | identified by the next frame's stack pointer at the time of the | |
843 | call. The value was already reconstructed into PREV_SP. */ | |
844 | /* | |
845 | +----------+ ^ | |
846 | | saved lr | | | |
847 | +->| saved fp |--+ | |
848 | | | | | |
849 | | | | <- Previous SP | |
850 | | +----------+ | |
851 | | | saved lr | | |
852 | +--| saved fp |<- FP | |
853 | | | | |
854 | | |<- SP | |
855 | +----------+ */ | |
856 | if (prev_regnum == AARCH64_SP_REGNUM) | |
857 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
858 | cache->prev_sp); | |
859 | ||
860 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
861 | prev_regnum); | |
862 | } | |
863 | ||
864 | /* AArch64 prologue unwinder. */ | |
865 | struct frame_unwind aarch64_prologue_unwind = | |
866 | { | |
867 | NORMAL_FRAME, | |
7dfa3edc | 868 | aarch64_prologue_frame_unwind_stop_reason, |
07b287a0 MS |
869 | aarch64_prologue_this_id, |
870 | aarch64_prologue_prev_register, | |
871 | NULL, | |
872 | default_frame_sniffer | |
873 | }; | |
874 | ||
8b61f75d PL |
875 | /* Allocate and fill in *THIS_CACHE with information about the prologue of |
876 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
877 | Return a pointer to the current aarch64_prologue_cache in | |
878 | *THIS_CACHE. */ | |
07b287a0 MS |
879 | |
880 | static struct aarch64_prologue_cache * | |
8b61f75d | 881 | aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache) |
07b287a0 | 882 | { |
07b287a0 | 883 | struct aarch64_prologue_cache *cache; |
8b61f75d PL |
884 | |
885 | if (*this_cache != NULL) | |
9a3c8263 | 886 | return (struct aarch64_prologue_cache *) *this_cache; |
07b287a0 MS |
887 | |
888 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
889 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
8b61f75d | 890 | *this_cache = cache; |
07b287a0 | 891 | |
02a2a705 PL |
892 | TRY |
893 | { | |
894 | cache->prev_sp = get_frame_register_unsigned (this_frame, | |
895 | AARCH64_SP_REGNUM); | |
896 | cache->prev_pc = get_frame_pc (this_frame); | |
897 | cache->available_p = 1; | |
898 | } | |
899 | CATCH (ex, RETURN_MASK_ERROR) | |
900 | { | |
901 | if (ex.error != NOT_AVAILABLE_ERROR) | |
902 | throw_exception (ex); | |
903 | } | |
904 | END_CATCH | |
07b287a0 MS |
905 | |
906 | return cache; | |
907 | } | |
908 | ||
02a2a705 PL |
909 | /* Implement the "stop_reason" frame_unwind method. */ |
910 | ||
911 | static enum unwind_stop_reason | |
912 | aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame, | |
913 | void **this_cache) | |
914 | { | |
915 | struct aarch64_prologue_cache *cache | |
916 | = aarch64_make_stub_cache (this_frame, this_cache); | |
917 | ||
918 | if (!cache->available_p) | |
919 | return UNWIND_UNAVAILABLE; | |
920 | ||
921 | return UNWIND_NO_REASON; | |
922 | } | |
923 | ||
07b287a0 MS |
924 | /* Our frame ID for a stub frame is the current SP and LR. */ |
925 | ||
926 | static void | |
927 | aarch64_stub_this_id (struct frame_info *this_frame, | |
928 | void **this_cache, struct frame_id *this_id) | |
929 | { | |
8b61f75d PL |
930 | struct aarch64_prologue_cache *cache |
931 | = aarch64_make_stub_cache (this_frame, this_cache); | |
07b287a0 | 932 | |
02a2a705 PL |
933 | if (cache->available_p) |
934 | *this_id = frame_id_build (cache->prev_sp, cache->prev_pc); | |
935 | else | |
936 | *this_id = frame_id_build_unavailable_stack (cache->prev_pc); | |
07b287a0 MS |
937 | } |
938 | ||
939 | /* Implement the "sniffer" frame_unwind method. */ | |
940 | ||
941 | static int | |
942 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
943 | struct frame_info *this_frame, | |
944 | void **this_prologue_cache) | |
945 | { | |
946 | CORE_ADDR addr_in_block; | |
947 | gdb_byte dummy[4]; | |
948 | ||
949 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 950 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
951 | /* We also use the stub winder if the target memory is unreadable |
952 | to avoid having the prologue unwinder trying to read it. */ | |
953 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
954 | return 1; | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
959 | /* AArch64 stub unwinder. */ | |
960 | struct frame_unwind aarch64_stub_unwind = | |
961 | { | |
962 | NORMAL_FRAME, | |
02a2a705 | 963 | aarch64_stub_frame_unwind_stop_reason, |
07b287a0 MS |
964 | aarch64_stub_this_id, |
965 | aarch64_prologue_prev_register, | |
966 | NULL, | |
967 | aarch64_stub_unwind_sniffer | |
968 | }; | |
969 | ||
970 | /* Return the frame base address of *THIS_FRAME. */ | |
971 | ||
972 | static CORE_ADDR | |
973 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
974 | { | |
7c8edfae PL |
975 | struct aarch64_prologue_cache *cache |
976 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
977 | |
978 | return cache->prev_sp - cache->framesize; | |
979 | } | |
980 | ||
981 | /* AArch64 default frame base information. */ | |
982 | struct frame_base aarch64_normal_base = | |
983 | { | |
984 | &aarch64_prologue_unwind, | |
985 | aarch64_normal_frame_base, | |
986 | aarch64_normal_frame_base, | |
987 | aarch64_normal_frame_base | |
988 | }; | |
989 | ||
990 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that | |
991 | dummy frame. The frame ID's base needs to match the TOS value | |
992 | saved by save_dummy_frame_tos () and returned from | |
993 | aarch64_push_dummy_call, and the PC needs to match the dummy | |
994 | frame's breakpoint. */ | |
995 | ||
996 | static struct frame_id | |
997 | aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
998 | { | |
999 | return frame_id_build (get_frame_register_unsigned (this_frame, | |
1000 | AARCH64_SP_REGNUM), | |
1001 | get_frame_pc (this_frame)); | |
1002 | } | |
1003 | ||
1004 | /* Implement the "unwind_pc" gdbarch method. */ | |
1005 | ||
1006 | static CORE_ADDR | |
1007 | aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1008 | { | |
1009 | CORE_ADDR pc | |
1010 | = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM); | |
1011 | ||
1012 | return pc; | |
1013 | } | |
1014 | ||
1015 | /* Implement the "unwind_sp" gdbarch method. */ | |
1016 | ||
1017 | static CORE_ADDR | |
1018 | aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1019 | { | |
1020 | return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1021 | } | |
1022 | ||
1023 | /* Return the value of the REGNUM register in the previous frame of | |
1024 | *THIS_FRAME. */ | |
1025 | ||
1026 | static struct value * | |
1027 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1028 | void **this_cache, int regnum) | |
1029 | { | |
07b287a0 MS |
1030 | CORE_ADDR lr; |
1031 | ||
1032 | switch (regnum) | |
1033 | { | |
1034 | case AARCH64_PC_REGNUM: | |
1035 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1036 | return frame_unwind_got_constant (this_frame, regnum, lr); | |
1037 | ||
1038 | default: | |
1039 | internal_error (__FILE__, __LINE__, | |
1040 | _("Unexpected register %d"), regnum); | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /* Implement the "init_reg" dwarf2_frame_ops method. */ | |
1045 | ||
1046 | static void | |
1047 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1048 | struct dwarf2_frame_state_reg *reg, | |
1049 | struct frame_info *this_frame) | |
1050 | { | |
1051 | switch (regnum) | |
1052 | { | |
1053 | case AARCH64_PC_REGNUM: | |
1054 | reg->how = DWARF2_FRAME_REG_FN; | |
1055 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
1056 | break; | |
1057 | case AARCH64_SP_REGNUM: | |
1058 | reg->how = DWARF2_FRAME_REG_CFA; | |
1059 | break; | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | /* When arguments must be pushed onto the stack, they go on in reverse | |
1064 | order. The code below implements a FILO (stack) to do this. */ | |
1065 | ||
1066 | typedef struct | |
1067 | { | |
c3c87445 YQ |
1068 | /* Value to pass on stack. It can be NULL if this item is for stack |
1069 | padding. */ | |
7c543f7b | 1070 | const gdb_byte *data; |
07b287a0 MS |
1071 | |
1072 | /* Size in bytes of value to pass on stack. */ | |
1073 | int len; | |
1074 | } stack_item_t; | |
1075 | ||
1076 | DEF_VEC_O (stack_item_t); | |
1077 | ||
1078 | /* Return the alignment (in bytes) of the given type. */ | |
1079 | ||
1080 | static int | |
1081 | aarch64_type_align (struct type *t) | |
1082 | { | |
1083 | int n; | |
1084 | int align; | |
1085 | int falign; | |
1086 | ||
1087 | t = check_typedef (t); | |
1088 | switch (TYPE_CODE (t)) | |
1089 | { | |
1090 | default: | |
1091 | /* Should never happen. */ | |
1092 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1093 | return 4; | |
1094 | ||
1095 | case TYPE_CODE_PTR: | |
1096 | case TYPE_CODE_ENUM: | |
1097 | case TYPE_CODE_INT: | |
1098 | case TYPE_CODE_FLT: | |
1099 | case TYPE_CODE_SET: | |
1100 | case TYPE_CODE_RANGE: | |
1101 | case TYPE_CODE_BITSTRING: | |
1102 | case TYPE_CODE_REF: | |
aa006118 | 1103 | case TYPE_CODE_RVALUE_REF: |
07b287a0 MS |
1104 | case TYPE_CODE_CHAR: |
1105 | case TYPE_CODE_BOOL: | |
1106 | return TYPE_LENGTH (t); | |
1107 | ||
1108 | case TYPE_CODE_ARRAY: | |
238f2452 YQ |
1109 | if (TYPE_VECTOR (t)) |
1110 | { | |
1111 | /* Use the natural alignment for vector types (the same for | |
1112 | scalar type), but the maximum alignment is 128-bit. */ | |
1113 | if (TYPE_LENGTH (t) > 16) | |
1114 | return 16; | |
1115 | else | |
1116 | return TYPE_LENGTH (t); | |
1117 | } | |
1118 | else | |
1119 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
07b287a0 MS |
1120 | case TYPE_CODE_COMPLEX: |
1121 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
1122 | ||
1123 | case TYPE_CODE_STRUCT: | |
1124 | case TYPE_CODE_UNION: | |
1125 | align = 1; | |
1126 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1127 | { | |
1128 | falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n)); | |
1129 | if (falign > align) | |
1130 | align = falign; | |
1131 | } | |
1132 | return align; | |
1133 | } | |
1134 | } | |
1135 | ||
cd635f74 YQ |
1136 | /* Return 1 if *TY is a homogeneous floating-point aggregate or |
1137 | homogeneous short-vector aggregate as defined in the AAPCS64 ABI | |
1138 | document; otherwise return 0. */ | |
07b287a0 MS |
1139 | |
1140 | static int | |
cd635f74 | 1141 | is_hfa_or_hva (struct type *ty) |
07b287a0 MS |
1142 | { |
1143 | switch (TYPE_CODE (ty)) | |
1144 | { | |
1145 | case TYPE_CODE_ARRAY: | |
1146 | { | |
1147 | struct type *target_ty = TYPE_TARGET_TYPE (ty); | |
238f2452 YQ |
1148 | |
1149 | if (TYPE_VECTOR (ty)) | |
1150 | return 0; | |
1151 | ||
cd635f74 YQ |
1152 | if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */ |
1153 | && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */ | |
1154 | || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */ | |
1155 | && TYPE_VECTOR (target_ty)))) | |
07b287a0 MS |
1156 | return 1; |
1157 | break; | |
1158 | } | |
1159 | ||
1160 | case TYPE_CODE_UNION: | |
1161 | case TYPE_CODE_STRUCT: | |
1162 | { | |
cd635f74 | 1163 | /* HFA or HVA has at most four members. */ |
07b287a0 MS |
1164 | if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4) |
1165 | { | |
1166 | struct type *member0_type; | |
1167 | ||
1168 | member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0)); | |
cd635f74 YQ |
1169 | if (TYPE_CODE (member0_type) == TYPE_CODE_FLT |
1170 | || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY | |
1171 | && TYPE_VECTOR (member0_type))) | |
07b287a0 MS |
1172 | { |
1173 | int i; | |
1174 | ||
1175 | for (i = 0; i < TYPE_NFIELDS (ty); i++) | |
1176 | { | |
1177 | struct type *member1_type; | |
1178 | ||
1179 | member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i)); | |
1180 | if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type) | |
1181 | || (TYPE_LENGTH (member0_type) | |
1182 | != TYPE_LENGTH (member1_type))) | |
1183 | return 0; | |
1184 | } | |
1185 | return 1; | |
1186 | } | |
1187 | } | |
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | default: | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | /* AArch64 function call information structure. */ | |
1199 | struct aarch64_call_info | |
1200 | { | |
1201 | /* the current argument number. */ | |
1202 | unsigned argnum; | |
1203 | ||
1204 | /* The next general purpose register number, equivalent to NGRN as | |
1205 | described in the AArch64 Procedure Call Standard. */ | |
1206 | unsigned ngrn; | |
1207 | ||
1208 | /* The next SIMD and floating point register number, equivalent to | |
1209 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
1210 | unsigned nsrn; | |
1211 | ||
1212 | /* The next stacked argument address, equivalent to NSAA as | |
1213 | described in the AArch64 Procedure Call Standard. */ | |
1214 | unsigned nsaa; | |
1215 | ||
1216 | /* Stack item vector. */ | |
1217 | VEC(stack_item_t) *si; | |
1218 | }; | |
1219 | ||
1220 | /* Pass a value in a sequence of consecutive X registers. The caller | |
1221 | is responsbile for ensuring sufficient registers are available. */ | |
1222 | ||
1223 | static void | |
1224 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1225 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1226 | struct value *arg) |
07b287a0 MS |
1227 | { |
1228 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1229 | int len = TYPE_LENGTH (type); | |
1230 | enum type_code typecode = TYPE_CODE (type); | |
1231 | int regnum = AARCH64_X0_REGNUM + info->ngrn; | |
8e80f9d1 | 1232 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1233 | |
1234 | info->argnum++; | |
1235 | ||
1236 | while (len > 0) | |
1237 | { | |
1238 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1239 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1240 | byte_order); | |
1241 | ||
1242 | ||
1243 | /* Adjust sub-word struct/union args when big-endian. */ | |
1244 | if (byte_order == BFD_ENDIAN_BIG | |
1245 | && partial_len < X_REGISTER_SIZE | |
1246 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1247 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1248 | ||
1249 | if (aarch64_debug) | |
b277c936 PL |
1250 | { |
1251 | debug_printf ("arg %d in %s = 0x%s\n", info->argnum, | |
1252 | gdbarch_register_name (gdbarch, regnum), | |
1253 | phex (regval, X_REGISTER_SIZE)); | |
1254 | } | |
07b287a0 MS |
1255 | regcache_cooked_write_unsigned (regcache, regnum, regval); |
1256 | len -= partial_len; | |
1257 | buf += partial_len; | |
1258 | regnum++; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* Attempt to marshall a value in a V register. Return 1 if | |
1263 | successful, or 0 if insufficient registers are available. This | |
1264 | function, unlike the equivalent pass_in_x() function does not | |
1265 | handle arguments spread across multiple registers. */ | |
1266 | ||
1267 | static int | |
1268 | pass_in_v (struct gdbarch *gdbarch, | |
1269 | struct regcache *regcache, | |
1270 | struct aarch64_call_info *info, | |
0735fddd | 1271 | int len, const bfd_byte *buf) |
07b287a0 MS |
1272 | { |
1273 | if (info->nsrn < 8) | |
1274 | { | |
07b287a0 | 1275 | int regnum = AARCH64_V0_REGNUM + info->nsrn; |
0735fddd | 1276 | gdb_byte reg[V_REGISTER_SIZE]; |
07b287a0 MS |
1277 | |
1278 | info->argnum++; | |
1279 | info->nsrn++; | |
1280 | ||
0735fddd YQ |
1281 | memset (reg, 0, sizeof (reg)); |
1282 | /* PCS C.1, the argument is allocated to the least significant | |
1283 | bits of V register. */ | |
1284 | memcpy (reg, buf, len); | |
1285 | regcache_cooked_write (regcache, regnum, reg); | |
1286 | ||
07b287a0 | 1287 | if (aarch64_debug) |
b277c936 PL |
1288 | { |
1289 | debug_printf ("arg %d in %s\n", info->argnum, | |
1290 | gdbarch_register_name (gdbarch, regnum)); | |
1291 | } | |
07b287a0 MS |
1292 | return 1; |
1293 | } | |
1294 | info->nsrn = 8; | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | /* Marshall an argument onto the stack. */ | |
1299 | ||
1300 | static void | |
1301 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1302 | struct value *arg) |
07b287a0 | 1303 | { |
8e80f9d1 | 1304 | const bfd_byte *buf = value_contents (arg); |
07b287a0 MS |
1305 | int len = TYPE_LENGTH (type); |
1306 | int align; | |
1307 | stack_item_t item; | |
1308 | ||
1309 | info->argnum++; | |
1310 | ||
1311 | align = aarch64_type_align (type); | |
1312 | ||
1313 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1314 | Natural alignment of the argument's type. */ | |
1315 | align = align_up (align, 8); | |
1316 | ||
1317 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1318 | if (align > 16) | |
1319 | align = 16; | |
1320 | ||
1321 | if (aarch64_debug) | |
b277c936 PL |
1322 | { |
1323 | debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len, | |
1324 | info->nsaa); | |
1325 | } | |
07b287a0 MS |
1326 | |
1327 | item.len = len; | |
1328 | item.data = buf; | |
1329 | VEC_safe_push (stack_item_t, info->si, &item); | |
1330 | ||
1331 | info->nsaa += len; | |
1332 | if (info->nsaa & (align - 1)) | |
1333 | { | |
1334 | /* Push stack alignment padding. */ | |
1335 | int pad = align - (info->nsaa & (align - 1)); | |
1336 | ||
1337 | item.len = pad; | |
c3c87445 | 1338 | item.data = NULL; |
07b287a0 MS |
1339 | |
1340 | VEC_safe_push (stack_item_t, info->si, &item); | |
1341 | info->nsaa += pad; | |
1342 | } | |
1343 | } | |
1344 | ||
1345 | /* Marshall an argument into a sequence of one or more consecutive X | |
1346 | registers or, if insufficient X registers are available then onto | |
1347 | the stack. */ | |
1348 | ||
1349 | static void | |
1350 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1351 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1352 | struct value *arg) |
07b287a0 MS |
1353 | { |
1354 | int len = TYPE_LENGTH (type); | |
1355 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1356 | ||
1357 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1358 | if (info->ngrn + nregs <= 8) | |
1359 | { | |
8e80f9d1 | 1360 | pass_in_x (gdbarch, regcache, info, type, arg); |
07b287a0 MS |
1361 | info->ngrn += nregs; |
1362 | } | |
1363 | else | |
1364 | { | |
1365 | info->ngrn = 8; | |
8e80f9d1 | 1366 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1367 | } |
1368 | } | |
1369 | ||
1370 | /* Pass a value in a V register, or on the stack if insufficient are | |
1371 | available. */ | |
1372 | ||
1373 | static void | |
1374 | pass_in_v_or_stack (struct gdbarch *gdbarch, | |
1375 | struct regcache *regcache, | |
1376 | struct aarch64_call_info *info, | |
1377 | struct type *type, | |
8e80f9d1 | 1378 | struct value *arg) |
07b287a0 | 1379 | { |
0735fddd YQ |
1380 | if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type), |
1381 | value_contents (arg))) | |
8e80f9d1 | 1382 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1383 | } |
1384 | ||
1385 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1386 | ||
1387 | static CORE_ADDR | |
1388 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1389 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1390 | int nargs, | |
1391 | struct value **args, CORE_ADDR sp, int struct_return, | |
1392 | CORE_ADDR struct_addr) | |
1393 | { | |
07b287a0 | 1394 | int argnum; |
07b287a0 MS |
1395 | struct aarch64_call_info info; |
1396 | struct type *func_type; | |
1397 | struct type *return_type; | |
1398 | int lang_struct_return; | |
1399 | ||
1400 | memset (&info, 0, sizeof (info)); | |
1401 | ||
1402 | /* We need to know what the type of the called function is in order | |
1403 | to determine the number of named/anonymous arguments for the | |
1404 | actual argument placement, and the return type in order to handle | |
1405 | return value correctly. | |
1406 | ||
1407 | The generic code above us views the decision of return in memory | |
1408 | or return in registers as a two stage processes. The language | |
1409 | handler is consulted first and may decide to return in memory (eg | |
1410 | class with copy constructor returned by value), this will cause | |
1411 | the generic code to allocate space AND insert an initial leading | |
1412 | argument. | |
1413 | ||
1414 | If the language code does not decide to pass in memory then the | |
1415 | target code is consulted. | |
1416 | ||
1417 | If the language code decides to pass in memory we want to move | |
1418 | the pointer inserted as the initial argument from the argument | |
1419 | list and into X8, the conventional AArch64 struct return pointer | |
1420 | register. | |
1421 | ||
1422 | This is slightly awkward, ideally the flag "lang_struct_return" | |
1423 | would be passed to the targets implementation of push_dummy_call. | |
1424 | Rather that change the target interface we call the language code | |
1425 | directly ourselves. */ | |
1426 | ||
1427 | func_type = check_typedef (value_type (function)); | |
1428 | ||
1429 | /* Dereference function pointer types. */ | |
1430 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
1431 | func_type = TYPE_TARGET_TYPE (func_type); | |
1432 | ||
1433 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
1434 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
1435 | ||
1436 | /* If language_pass_by_reference () returned true we will have been | |
1437 | given an additional initial argument, a hidden pointer to the | |
1438 | return slot in memory. */ | |
1439 | return_type = TYPE_TARGET_TYPE (func_type); | |
1440 | lang_struct_return = language_pass_by_reference (return_type); | |
1441 | ||
1442 | /* Set the return address. For the AArch64, the return breakpoint | |
1443 | is always at BP_ADDR. */ | |
1444 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1445 | ||
1446 | /* If we were given an initial argument for the return slot because | |
1447 | lang_struct_return was true, lose it. */ | |
1448 | if (lang_struct_return) | |
1449 | { | |
1450 | args++; | |
1451 | nargs--; | |
1452 | } | |
1453 | ||
1454 | /* The struct_return pointer occupies X8. */ | |
1455 | if (struct_return || lang_struct_return) | |
1456 | { | |
1457 | if (aarch64_debug) | |
b277c936 PL |
1458 | { |
1459 | debug_printf ("struct return in %s = 0x%s\n", | |
1460 | gdbarch_register_name (gdbarch, | |
1461 | AARCH64_STRUCT_RETURN_REGNUM), | |
1462 | paddress (gdbarch, struct_addr)); | |
1463 | } | |
07b287a0 MS |
1464 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, |
1465 | struct_addr); | |
1466 | } | |
1467 | ||
1468 | for (argnum = 0; argnum < nargs; argnum++) | |
1469 | { | |
1470 | struct value *arg = args[argnum]; | |
1471 | struct type *arg_type; | |
1472 | int len; | |
1473 | ||
1474 | arg_type = check_typedef (value_type (arg)); | |
1475 | len = TYPE_LENGTH (arg_type); | |
1476 | ||
1477 | switch (TYPE_CODE (arg_type)) | |
1478 | { | |
1479 | case TYPE_CODE_INT: | |
1480 | case TYPE_CODE_BOOL: | |
1481 | case TYPE_CODE_CHAR: | |
1482 | case TYPE_CODE_RANGE: | |
1483 | case TYPE_CODE_ENUM: | |
1484 | if (len < 4) | |
1485 | { | |
1486 | /* Promote to 32 bit integer. */ | |
1487 | if (TYPE_UNSIGNED (arg_type)) | |
1488 | arg_type = builtin_type (gdbarch)->builtin_uint32; | |
1489 | else | |
1490 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1491 | arg = value_cast (arg_type, arg); | |
1492 | } | |
8e80f9d1 | 1493 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1494 | break; |
1495 | ||
1496 | case TYPE_CODE_COMPLEX: | |
1497 | if (info.nsrn <= 6) | |
1498 | { | |
1499 | const bfd_byte *buf = value_contents (arg); | |
1500 | struct type *target_type = | |
1501 | check_typedef (TYPE_TARGET_TYPE (arg_type)); | |
1502 | ||
07b287a0 | 1503 | pass_in_v (gdbarch, regcache, &info, |
0735fddd YQ |
1504 | TYPE_LENGTH (target_type), buf); |
1505 | pass_in_v (gdbarch, regcache, &info, | |
1506 | TYPE_LENGTH (target_type), | |
07b287a0 MS |
1507 | buf + TYPE_LENGTH (target_type)); |
1508 | } | |
1509 | else | |
1510 | { | |
1511 | info.nsrn = 8; | |
8e80f9d1 | 1512 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1513 | } |
1514 | break; | |
1515 | case TYPE_CODE_FLT: | |
8e80f9d1 | 1516 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1517 | break; |
1518 | ||
1519 | case TYPE_CODE_STRUCT: | |
1520 | case TYPE_CODE_ARRAY: | |
1521 | case TYPE_CODE_UNION: | |
cd635f74 | 1522 | if (is_hfa_or_hva (arg_type)) |
07b287a0 MS |
1523 | { |
1524 | int elements = TYPE_NFIELDS (arg_type); | |
1525 | ||
1526 | /* Homogeneous Aggregates */ | |
1527 | if (info.nsrn + elements < 8) | |
1528 | { | |
1529 | int i; | |
1530 | ||
1531 | for (i = 0; i < elements; i++) | |
1532 | { | |
1533 | /* We know that we have sufficient registers | |
1534 | available therefore this will never fallback | |
1535 | to the stack. */ | |
1536 | struct value *field = | |
1537 | value_primitive_field (arg, 0, i, arg_type); | |
1538 | struct type *field_type = | |
1539 | check_typedef (value_type (field)); | |
1540 | ||
8e80f9d1 YQ |
1541 | pass_in_v_or_stack (gdbarch, regcache, &info, |
1542 | field_type, field); | |
07b287a0 MS |
1543 | } |
1544 | } | |
1545 | else | |
1546 | { | |
1547 | info.nsrn = 8; | |
8e80f9d1 | 1548 | pass_on_stack (&info, arg_type, arg); |
07b287a0 MS |
1549 | } |
1550 | } | |
238f2452 YQ |
1551 | else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY |
1552 | && TYPE_VECTOR (arg_type) && (len == 16 || len == 8)) | |
1553 | { | |
1554 | /* Short vector types are passed in V registers. */ | |
1555 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg); | |
1556 | } | |
07b287a0 MS |
1557 | else if (len > 16) |
1558 | { | |
1559 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1560 | invisible reference. */ | |
1561 | ||
1562 | /* Allocate aligned storage. */ | |
1563 | sp = align_down (sp - len, 16); | |
1564 | ||
1565 | /* Write the real data into the stack. */ | |
1566 | write_memory (sp, value_contents (arg), len); | |
1567 | ||
1568 | /* Construct the indirection. */ | |
1569 | arg_type = lookup_pointer_type (arg_type); | |
1570 | arg = value_from_pointer (arg_type, sp); | |
8e80f9d1 | 1571 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1572 | } |
1573 | else | |
1574 | /* PCS C.15 / C.18 multiple values pass. */ | |
8e80f9d1 | 1575 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1576 | break; |
1577 | ||
1578 | default: | |
8e80f9d1 | 1579 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1580 | break; |
1581 | } | |
1582 | } | |
1583 | ||
1584 | /* Make sure stack retains 16 byte alignment. */ | |
1585 | if (info.nsaa & 15) | |
1586 | sp -= 16 - (info.nsaa & 15); | |
1587 | ||
1588 | while (!VEC_empty (stack_item_t, info.si)) | |
1589 | { | |
1590 | stack_item_t *si = VEC_last (stack_item_t, info.si); | |
1591 | ||
1592 | sp -= si->len; | |
c3c87445 YQ |
1593 | if (si->data != NULL) |
1594 | write_memory (sp, si->data, si->len); | |
07b287a0 MS |
1595 | VEC_pop (stack_item_t, info.si); |
1596 | } | |
1597 | ||
1598 | VEC_free (stack_item_t, info.si); | |
1599 | ||
1600 | /* Finally, update the SP register. */ | |
1601 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1602 | ||
1603 | return sp; | |
1604 | } | |
1605 | ||
1606 | /* Implement the "frame_align" gdbarch method. */ | |
1607 | ||
1608 | static CORE_ADDR | |
1609 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1610 | { | |
1611 | /* Align the stack to sixteen bytes. */ | |
1612 | return sp & ~(CORE_ADDR) 15; | |
1613 | } | |
1614 | ||
1615 | /* Return the type for an AdvSISD Q register. */ | |
1616 | ||
1617 | static struct type * | |
1618 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
1619 | { | |
1620 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1621 | ||
1622 | if (tdep->vnq_type == NULL) | |
1623 | { | |
1624 | struct type *t; | |
1625 | struct type *elem; | |
1626 | ||
1627 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
1628 | TYPE_CODE_UNION); | |
1629 | ||
1630 | elem = builtin_type (gdbarch)->builtin_uint128; | |
1631 | append_composite_type_field (t, "u", elem); | |
1632 | ||
1633 | elem = builtin_type (gdbarch)->builtin_int128; | |
1634 | append_composite_type_field (t, "s", elem); | |
1635 | ||
1636 | tdep->vnq_type = t; | |
1637 | } | |
1638 | ||
1639 | return tdep->vnq_type; | |
1640 | } | |
1641 | ||
1642 | /* Return the type for an AdvSISD D register. */ | |
1643 | ||
1644 | static struct type * | |
1645 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
1646 | { | |
1647 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1648 | ||
1649 | if (tdep->vnd_type == NULL) | |
1650 | { | |
1651 | struct type *t; | |
1652 | struct type *elem; | |
1653 | ||
1654 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
1655 | TYPE_CODE_UNION); | |
1656 | ||
1657 | elem = builtin_type (gdbarch)->builtin_double; | |
1658 | append_composite_type_field (t, "f", elem); | |
1659 | ||
1660 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1661 | append_composite_type_field (t, "u", elem); | |
1662 | ||
1663 | elem = builtin_type (gdbarch)->builtin_int64; | |
1664 | append_composite_type_field (t, "s", elem); | |
1665 | ||
1666 | tdep->vnd_type = t; | |
1667 | } | |
1668 | ||
1669 | return tdep->vnd_type; | |
1670 | } | |
1671 | ||
1672 | /* Return the type for an AdvSISD S register. */ | |
1673 | ||
1674 | static struct type * | |
1675 | aarch64_vns_type (struct gdbarch *gdbarch) | |
1676 | { | |
1677 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1678 | ||
1679 | if (tdep->vns_type == NULL) | |
1680 | { | |
1681 | struct type *t; | |
1682 | struct type *elem; | |
1683 | ||
1684 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
1685 | TYPE_CODE_UNION); | |
1686 | ||
1687 | elem = builtin_type (gdbarch)->builtin_float; | |
1688 | append_composite_type_field (t, "f", elem); | |
1689 | ||
1690 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1691 | append_composite_type_field (t, "u", elem); | |
1692 | ||
1693 | elem = builtin_type (gdbarch)->builtin_int32; | |
1694 | append_composite_type_field (t, "s", elem); | |
1695 | ||
1696 | tdep->vns_type = t; | |
1697 | } | |
1698 | ||
1699 | return tdep->vns_type; | |
1700 | } | |
1701 | ||
1702 | /* Return the type for an AdvSISD H register. */ | |
1703 | ||
1704 | static struct type * | |
1705 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
1706 | { | |
1707 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1708 | ||
1709 | if (tdep->vnh_type == NULL) | |
1710 | { | |
1711 | struct type *t; | |
1712 | struct type *elem; | |
1713 | ||
1714 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
1715 | TYPE_CODE_UNION); | |
1716 | ||
1717 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1718 | append_composite_type_field (t, "u", elem); | |
1719 | ||
1720 | elem = builtin_type (gdbarch)->builtin_int16; | |
1721 | append_composite_type_field (t, "s", elem); | |
1722 | ||
1723 | tdep->vnh_type = t; | |
1724 | } | |
1725 | ||
1726 | return tdep->vnh_type; | |
1727 | } | |
1728 | ||
1729 | /* Return the type for an AdvSISD B register. */ | |
1730 | ||
1731 | static struct type * | |
1732 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
1733 | { | |
1734 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1735 | ||
1736 | if (tdep->vnb_type == NULL) | |
1737 | { | |
1738 | struct type *t; | |
1739 | struct type *elem; | |
1740 | ||
1741 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
1742 | TYPE_CODE_UNION); | |
1743 | ||
1744 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1745 | append_composite_type_field (t, "u", elem); | |
1746 | ||
1747 | elem = builtin_type (gdbarch)->builtin_int8; | |
1748 | append_composite_type_field (t, "s", elem); | |
1749 | ||
1750 | tdep->vnb_type = t; | |
1751 | } | |
1752 | ||
1753 | return tdep->vnb_type; | |
1754 | } | |
1755 | ||
1756 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ | |
1757 | ||
1758 | static int | |
1759 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1760 | { | |
1761 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) | |
1762 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
1763 | ||
1764 | if (reg == AARCH64_DWARF_SP) | |
1765 | return AARCH64_SP_REGNUM; | |
1766 | ||
1767 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) | |
1768 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
1769 | ||
1770 | return -1; | |
1771 | } | |
1772 | \f | |
1773 | ||
1774 | /* Implement the "print_insn" gdbarch method. */ | |
1775 | ||
1776 | static int | |
1777 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
1778 | { | |
1779 | info->symbols = NULL; | |
6394c606 | 1780 | return default_print_insn (memaddr, info); |
07b287a0 MS |
1781 | } |
1782 | ||
1783 | /* AArch64 BRK software debug mode instruction. | |
1784 | Note that AArch64 code is always little-endian. | |
1785 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
04180708 | 1786 | constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 | 1787 | |
04180708 | 1788 | typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint; |
07b287a0 MS |
1789 | |
1790 | /* Extract from an array REGS containing the (raw) register state a | |
1791 | function return value of type TYPE, and copy that, in virtual | |
1792 | format, into VALBUF. */ | |
1793 | ||
1794 | static void | |
1795 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
1796 | gdb_byte *valbuf) | |
1797 | { | |
1798 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
1799 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1800 | ||
1801 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1802 | { | |
1803 | bfd_byte buf[V_REGISTER_SIZE]; | |
1804 | int len = TYPE_LENGTH (type); | |
1805 | ||
1806 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1807 | memcpy (valbuf, buf, len); | |
1808 | } | |
1809 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1810 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1811 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1812 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 1813 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
1814 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
1815 | { | |
1816 | /* If the the type is a plain integer, then the access is | |
1817 | straight-forward. Otherwise we have to play around a bit | |
1818 | more. */ | |
1819 | int len = TYPE_LENGTH (type); | |
1820 | int regno = AARCH64_X0_REGNUM; | |
1821 | ULONGEST tmp; | |
1822 | ||
1823 | while (len > 0) | |
1824 | { | |
1825 | /* By using store_unsigned_integer we avoid having to do | |
1826 | anything special for small big-endian values. */ | |
1827 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
1828 | store_unsigned_integer (valbuf, | |
1829 | (len > X_REGISTER_SIZE | |
1830 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
1831 | len -= X_REGISTER_SIZE; | |
1832 | valbuf += X_REGISTER_SIZE; | |
1833 | } | |
1834 | } | |
1835 | else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX) | |
1836 | { | |
1837 | int regno = AARCH64_V0_REGNUM; | |
1838 | bfd_byte buf[V_REGISTER_SIZE]; | |
1839 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1840 | int len = TYPE_LENGTH (target_type); | |
1841 | ||
1842 | regcache_cooked_read (regs, regno, buf); | |
1843 | memcpy (valbuf, buf, len); | |
1844 | valbuf += len; | |
1845 | regcache_cooked_read (regs, regno + 1, buf); | |
1846 | memcpy (valbuf, buf, len); | |
1847 | valbuf += len; | |
1848 | } | |
cd635f74 | 1849 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
1850 | { |
1851 | int elements = TYPE_NFIELDS (type); | |
1852 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1853 | int len = TYPE_LENGTH (member_type); | |
1854 | int i; | |
1855 | ||
1856 | for (i = 0; i < elements; i++) | |
1857 | { | |
1858 | int regno = AARCH64_V0_REGNUM + i; | |
db3516bb | 1859 | bfd_byte buf[V_REGISTER_SIZE]; |
07b287a0 MS |
1860 | |
1861 | if (aarch64_debug) | |
b277c936 | 1862 | { |
cd635f74 | 1863 | debug_printf ("read HFA or HVA return value element %d from %s\n", |
b277c936 PL |
1864 | i + 1, |
1865 | gdbarch_register_name (gdbarch, regno)); | |
1866 | } | |
07b287a0 MS |
1867 | regcache_cooked_read (regs, regno, buf); |
1868 | ||
1869 | memcpy (valbuf, buf, len); | |
1870 | valbuf += len; | |
1871 | } | |
1872 | } | |
238f2452 YQ |
1873 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
1874 | && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8)) | |
1875 | { | |
1876 | /* Short vector is returned in V register. */ | |
1877 | gdb_byte buf[V_REGISTER_SIZE]; | |
1878 | ||
1879 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1880 | memcpy (valbuf, buf, TYPE_LENGTH (type)); | |
1881 | } | |
07b287a0 MS |
1882 | else |
1883 | { | |
1884 | /* For a structure or union the behaviour is as if the value had | |
1885 | been stored to word-aligned memory and then loaded into | |
1886 | registers with 64-bit load instruction(s). */ | |
1887 | int len = TYPE_LENGTH (type); | |
1888 | int regno = AARCH64_X0_REGNUM; | |
1889 | bfd_byte buf[X_REGISTER_SIZE]; | |
1890 | ||
1891 | while (len > 0) | |
1892 | { | |
1893 | regcache_cooked_read (regs, regno++, buf); | |
1894 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
1895 | len -= X_REGISTER_SIZE; | |
1896 | valbuf += X_REGISTER_SIZE; | |
1897 | } | |
1898 | } | |
1899 | } | |
1900 | ||
1901 | ||
1902 | /* Will a function return an aggregate type in memory or in a | |
1903 | register? Return 0 if an aggregate type can be returned in a | |
1904 | register, 1 if it must be returned in memory. */ | |
1905 | ||
1906 | static int | |
1907 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
1908 | { | |
f168693b | 1909 | type = check_typedef (type); |
07b287a0 | 1910 | |
cd635f74 | 1911 | if (is_hfa_or_hva (type)) |
07b287a0 | 1912 | { |
cd635f74 YQ |
1913 | /* v0-v7 are used to return values and one register is allocated |
1914 | for one member. However, HFA or HVA has at most four members. */ | |
07b287a0 MS |
1915 | return 0; |
1916 | } | |
1917 | ||
1918 | if (TYPE_LENGTH (type) > 16) | |
1919 | { | |
1920 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
1921 | invisible reference. */ | |
1922 | ||
1923 | return 1; | |
1924 | } | |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
1929 | /* Write into appropriate registers a function return value of type | |
1930 | TYPE, given in virtual format. */ | |
1931 | ||
1932 | static void | |
1933 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
1934 | const gdb_byte *valbuf) | |
1935 | { | |
1936 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
1937 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1938 | ||
1939 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1940 | { | |
1941 | bfd_byte buf[V_REGISTER_SIZE]; | |
1942 | int len = TYPE_LENGTH (type); | |
1943 | ||
1944 | memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
1945 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
1946 | } | |
1947 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1948 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1949 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1950 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
aa006118 | 1951 | || TYPE_IS_REFERENCE (type) |
07b287a0 MS |
1952 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
1953 | { | |
1954 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
1955 | { | |
1956 | /* Values of one word or less are zero/sign-extended and | |
1957 | returned in r0. */ | |
1958 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
1959 | LONGEST val = unpack_long (type, valbuf); | |
1960 | ||
1961 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
1962 | regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf); | |
1963 | } | |
1964 | else | |
1965 | { | |
1966 | /* Integral values greater than one word are stored in | |
1967 | consecutive registers starting with r0. This will always | |
1968 | be a multiple of the regiser size. */ | |
1969 | int len = TYPE_LENGTH (type); | |
1970 | int regno = AARCH64_X0_REGNUM; | |
1971 | ||
1972 | while (len > 0) | |
1973 | { | |
1974 | regcache_cooked_write (regs, regno++, valbuf); | |
1975 | len -= X_REGISTER_SIZE; | |
1976 | valbuf += X_REGISTER_SIZE; | |
1977 | } | |
1978 | } | |
1979 | } | |
cd635f74 | 1980 | else if (is_hfa_or_hva (type)) |
07b287a0 MS |
1981 | { |
1982 | int elements = TYPE_NFIELDS (type); | |
1983 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1984 | int len = TYPE_LENGTH (member_type); | |
1985 | int i; | |
1986 | ||
1987 | for (i = 0; i < elements; i++) | |
1988 | { | |
1989 | int regno = AARCH64_V0_REGNUM + i; | |
d1be909e | 1990 | bfd_byte tmpbuf[V_REGISTER_SIZE]; |
07b287a0 MS |
1991 | |
1992 | if (aarch64_debug) | |
b277c936 | 1993 | { |
cd635f74 | 1994 | debug_printf ("write HFA or HVA return value element %d to %s\n", |
b277c936 PL |
1995 | i + 1, |
1996 | gdbarch_register_name (gdbarch, regno)); | |
1997 | } | |
07b287a0 MS |
1998 | |
1999 | memcpy (tmpbuf, valbuf, len); | |
2000 | regcache_cooked_write (regs, regno, tmpbuf); | |
2001 | valbuf += len; | |
2002 | } | |
2003 | } | |
238f2452 YQ |
2004 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type) |
2005 | && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16)) | |
2006 | { | |
2007 | /* Short vector. */ | |
2008 | gdb_byte buf[V_REGISTER_SIZE]; | |
2009 | ||
2010 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
2011 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
2012 | } | |
07b287a0 MS |
2013 | else |
2014 | { | |
2015 | /* For a structure or union the behaviour is as if the value had | |
2016 | been stored to word-aligned memory and then loaded into | |
2017 | registers with 64-bit load instruction(s). */ | |
2018 | int len = TYPE_LENGTH (type); | |
2019 | int regno = AARCH64_X0_REGNUM; | |
2020 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2021 | ||
2022 | while (len > 0) | |
2023 | { | |
2024 | memcpy (tmpbuf, valbuf, | |
2025 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2026 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2027 | len -= X_REGISTER_SIZE; | |
2028 | valbuf += X_REGISTER_SIZE; | |
2029 | } | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | /* Implement the "return_value" gdbarch method. */ | |
2034 | ||
2035 | static enum return_value_convention | |
2036 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2037 | struct type *valtype, struct regcache *regcache, | |
2038 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2039 | { | |
07b287a0 MS |
2040 | |
2041 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2042 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2043 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2044 | { | |
2045 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2046 | { | |
2047 | if (aarch64_debug) | |
b277c936 | 2048 | debug_printf ("return value in memory\n"); |
07b287a0 MS |
2049 | return RETURN_VALUE_STRUCT_CONVENTION; |
2050 | } | |
2051 | } | |
2052 | ||
2053 | if (writebuf) | |
2054 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2055 | ||
2056 | if (readbuf) | |
2057 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2058 | ||
2059 | if (aarch64_debug) | |
b277c936 | 2060 | debug_printf ("return value in registers\n"); |
07b287a0 MS |
2061 | |
2062 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2063 | } | |
2064 | ||
2065 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2066 | ||
2067 | static int | |
2068 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2069 | { | |
2070 | CORE_ADDR jb_addr; | |
2071 | gdb_byte buf[X_REGISTER_SIZE]; | |
2072 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2073 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2074 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2075 | ||
2076 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2077 | ||
2078 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2079 | X_REGISTER_SIZE)) | |
2080 | return 0; | |
2081 | ||
2082 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2083 | return 1; | |
2084 | } | |
ea873d8e PL |
2085 | |
2086 | /* Implement the "gen_return_address" gdbarch method. */ | |
2087 | ||
2088 | static void | |
2089 | aarch64_gen_return_address (struct gdbarch *gdbarch, | |
2090 | struct agent_expr *ax, struct axs_value *value, | |
2091 | CORE_ADDR scope) | |
2092 | { | |
2093 | value->type = register_type (gdbarch, AARCH64_LR_REGNUM); | |
2094 | value->kind = axs_lvalue_register; | |
2095 | value->u.reg = AARCH64_LR_REGNUM; | |
2096 | } | |
07b287a0 MS |
2097 | \f |
2098 | ||
2099 | /* Return the pseudo register name corresponding to register regnum. */ | |
2100 | ||
2101 | static const char * | |
2102 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2103 | { | |
2104 | static const char *const q_name[] = | |
2105 | { | |
2106 | "q0", "q1", "q2", "q3", | |
2107 | "q4", "q5", "q6", "q7", | |
2108 | "q8", "q9", "q10", "q11", | |
2109 | "q12", "q13", "q14", "q15", | |
2110 | "q16", "q17", "q18", "q19", | |
2111 | "q20", "q21", "q22", "q23", | |
2112 | "q24", "q25", "q26", "q27", | |
2113 | "q28", "q29", "q30", "q31", | |
2114 | }; | |
2115 | ||
2116 | static const char *const d_name[] = | |
2117 | { | |
2118 | "d0", "d1", "d2", "d3", | |
2119 | "d4", "d5", "d6", "d7", | |
2120 | "d8", "d9", "d10", "d11", | |
2121 | "d12", "d13", "d14", "d15", | |
2122 | "d16", "d17", "d18", "d19", | |
2123 | "d20", "d21", "d22", "d23", | |
2124 | "d24", "d25", "d26", "d27", | |
2125 | "d28", "d29", "d30", "d31", | |
2126 | }; | |
2127 | ||
2128 | static const char *const s_name[] = | |
2129 | { | |
2130 | "s0", "s1", "s2", "s3", | |
2131 | "s4", "s5", "s6", "s7", | |
2132 | "s8", "s9", "s10", "s11", | |
2133 | "s12", "s13", "s14", "s15", | |
2134 | "s16", "s17", "s18", "s19", | |
2135 | "s20", "s21", "s22", "s23", | |
2136 | "s24", "s25", "s26", "s27", | |
2137 | "s28", "s29", "s30", "s31", | |
2138 | }; | |
2139 | ||
2140 | static const char *const h_name[] = | |
2141 | { | |
2142 | "h0", "h1", "h2", "h3", | |
2143 | "h4", "h5", "h6", "h7", | |
2144 | "h8", "h9", "h10", "h11", | |
2145 | "h12", "h13", "h14", "h15", | |
2146 | "h16", "h17", "h18", "h19", | |
2147 | "h20", "h21", "h22", "h23", | |
2148 | "h24", "h25", "h26", "h27", | |
2149 | "h28", "h29", "h30", "h31", | |
2150 | }; | |
2151 | ||
2152 | static const char *const b_name[] = | |
2153 | { | |
2154 | "b0", "b1", "b2", "b3", | |
2155 | "b4", "b5", "b6", "b7", | |
2156 | "b8", "b9", "b10", "b11", | |
2157 | "b12", "b13", "b14", "b15", | |
2158 | "b16", "b17", "b18", "b19", | |
2159 | "b20", "b21", "b22", "b23", | |
2160 | "b24", "b25", "b26", "b27", | |
2161 | "b28", "b29", "b30", "b31", | |
2162 | }; | |
2163 | ||
2164 | regnum -= gdbarch_num_regs (gdbarch); | |
2165 | ||
2166 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2167 | return q_name[regnum - AARCH64_Q0_REGNUM]; | |
2168 | ||
2169 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2170 | return d_name[regnum - AARCH64_D0_REGNUM]; | |
2171 | ||
2172 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2173 | return s_name[regnum - AARCH64_S0_REGNUM]; | |
2174 | ||
2175 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2176 | return h_name[regnum - AARCH64_H0_REGNUM]; | |
2177 | ||
2178 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2179 | return b_name[regnum - AARCH64_B0_REGNUM]; | |
2180 | ||
2181 | internal_error (__FILE__, __LINE__, | |
2182 | _("aarch64_pseudo_register_name: bad register number %d"), | |
2183 | regnum); | |
2184 | } | |
2185 | ||
2186 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2187 | ||
2188 | static struct type * | |
2189 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2190 | { | |
2191 | regnum -= gdbarch_num_regs (gdbarch); | |
2192 | ||
2193 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2194 | return aarch64_vnq_type (gdbarch); | |
2195 | ||
2196 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2197 | return aarch64_vnd_type (gdbarch); | |
2198 | ||
2199 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2200 | return aarch64_vns_type (gdbarch); | |
2201 | ||
2202 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2203 | return aarch64_vnh_type (gdbarch); | |
2204 | ||
2205 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2206 | return aarch64_vnb_type (gdbarch); | |
2207 | ||
2208 | internal_error (__FILE__, __LINE__, | |
2209 | _("aarch64_pseudo_register_type: bad register number %d"), | |
2210 | regnum); | |
2211 | } | |
2212 | ||
2213 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2214 | ||
2215 | static int | |
2216 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2217 | struct reggroup *group) | |
2218 | { | |
2219 | regnum -= gdbarch_num_regs (gdbarch); | |
2220 | ||
2221 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2222 | return group == all_reggroup || group == vector_reggroup; | |
2223 | else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2224 | return (group == all_reggroup || group == vector_reggroup | |
2225 | || group == float_reggroup); | |
2226 | else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2227 | return (group == all_reggroup || group == vector_reggroup | |
2228 | || group == float_reggroup); | |
2229 | else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2230 | return group == all_reggroup || group == vector_reggroup; | |
2231 | else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2232 | return group == all_reggroup || group == vector_reggroup; | |
2233 | ||
2234 | return group == all_reggroup; | |
2235 | } | |
2236 | ||
2237 | /* Implement the "pseudo_register_read_value" gdbarch method. */ | |
2238 | ||
2239 | static struct value * | |
2240 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, | |
2241 | struct regcache *regcache, | |
2242 | int regnum) | |
2243 | { | |
d1be909e | 2244 | gdb_byte reg_buf[V_REGISTER_SIZE]; |
07b287a0 MS |
2245 | struct value *result_value; |
2246 | gdb_byte *buf; | |
2247 | ||
2248 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
2249 | VALUE_LVAL (result_value) = lval_register; | |
2250 | VALUE_REGNUM (result_value) = regnum; | |
2251 | buf = value_contents_raw (result_value); | |
2252 | ||
2253 | regnum -= gdbarch_num_regs (gdbarch); | |
2254 | ||
2255 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2256 | { | |
2257 | enum register_status status; | |
2258 | unsigned v_regnum; | |
2259 | ||
2260 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2261 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2262 | if (status != REG_VALID) | |
2263 | mark_value_bytes_unavailable (result_value, 0, | |
2264 | TYPE_LENGTH (value_type (result_value))); | |
2265 | else | |
2266 | memcpy (buf, reg_buf, Q_REGISTER_SIZE); | |
2267 | return result_value; | |
2268 | } | |
2269 | ||
2270 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2271 | { | |
2272 | enum register_status status; | |
2273 | unsigned v_regnum; | |
2274 | ||
2275 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2276 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2277 | if (status != REG_VALID) | |
2278 | mark_value_bytes_unavailable (result_value, 0, | |
2279 | TYPE_LENGTH (value_type (result_value))); | |
2280 | else | |
2281 | memcpy (buf, reg_buf, D_REGISTER_SIZE); | |
2282 | return result_value; | |
2283 | } | |
2284 | ||
2285 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2286 | { | |
2287 | enum register_status status; | |
2288 | unsigned v_regnum; | |
2289 | ||
2290 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2291 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
4bcddace PL |
2292 | if (status != REG_VALID) |
2293 | mark_value_bytes_unavailable (result_value, 0, | |
2294 | TYPE_LENGTH (value_type (result_value))); | |
2295 | else | |
2296 | memcpy (buf, reg_buf, S_REGISTER_SIZE); | |
07b287a0 MS |
2297 | return result_value; |
2298 | } | |
2299 | ||
2300 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2301 | { | |
2302 | enum register_status status; | |
2303 | unsigned v_regnum; | |
2304 | ||
2305 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2306 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2307 | if (status != REG_VALID) | |
2308 | mark_value_bytes_unavailable (result_value, 0, | |
2309 | TYPE_LENGTH (value_type (result_value))); | |
2310 | else | |
2311 | memcpy (buf, reg_buf, H_REGISTER_SIZE); | |
2312 | return result_value; | |
2313 | } | |
2314 | ||
2315 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2316 | { | |
2317 | enum register_status status; | |
2318 | unsigned v_regnum; | |
2319 | ||
2320 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2321 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2322 | if (status != REG_VALID) | |
2323 | mark_value_bytes_unavailable (result_value, 0, | |
2324 | TYPE_LENGTH (value_type (result_value))); | |
2325 | else | |
2326 | memcpy (buf, reg_buf, B_REGISTER_SIZE); | |
2327 | return result_value; | |
2328 | } | |
2329 | ||
2330 | gdb_assert_not_reached ("regnum out of bound"); | |
2331 | } | |
2332 | ||
2333 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2334 | ||
2335 | static void | |
2336 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2337 | int regnum, const gdb_byte *buf) | |
2338 | { | |
d1be909e | 2339 | gdb_byte reg_buf[V_REGISTER_SIZE]; |
07b287a0 MS |
2340 | |
2341 | /* Ensure the register buffer is zero, we want gdb writes of the | |
2342 | various 'scalar' pseudo registers to behavior like architectural | |
2343 | writes, register width bytes are written the remainder are set to | |
2344 | zero. */ | |
2345 | memset (reg_buf, 0, sizeof (reg_buf)); | |
2346 | ||
2347 | regnum -= gdbarch_num_regs (gdbarch); | |
2348 | ||
2349 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2350 | { | |
2351 | /* pseudo Q registers */ | |
2352 | unsigned v_regnum; | |
2353 | ||
2354 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2355 | memcpy (reg_buf, buf, Q_REGISTER_SIZE); | |
2356 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2357 | return; | |
2358 | } | |
2359 | ||
2360 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2361 | { | |
2362 | /* pseudo D registers */ | |
2363 | unsigned v_regnum; | |
2364 | ||
2365 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2366 | memcpy (reg_buf, buf, D_REGISTER_SIZE); | |
2367 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2368 | return; | |
2369 | } | |
2370 | ||
2371 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2372 | { | |
2373 | unsigned v_regnum; | |
2374 | ||
2375 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2376 | memcpy (reg_buf, buf, S_REGISTER_SIZE); | |
2377 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2378 | return; | |
2379 | } | |
2380 | ||
2381 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2382 | { | |
2383 | /* pseudo H registers */ | |
2384 | unsigned v_regnum; | |
2385 | ||
2386 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2387 | memcpy (reg_buf, buf, H_REGISTER_SIZE); | |
2388 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2389 | return; | |
2390 | } | |
2391 | ||
2392 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2393 | { | |
2394 | /* pseudo B registers */ | |
2395 | unsigned v_regnum; | |
2396 | ||
2397 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2398 | memcpy (reg_buf, buf, B_REGISTER_SIZE); | |
2399 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2400 | return; | |
2401 | } | |
2402 | ||
2403 | gdb_assert_not_reached ("regnum out of bound"); | |
2404 | } | |
2405 | ||
07b287a0 MS |
2406 | /* Callback function for user_reg_add. */ |
2407 | ||
2408 | static struct value * | |
2409 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2410 | { | |
9a3c8263 | 2411 | const int *reg_p = (const int *) baton; |
07b287a0 MS |
2412 | |
2413 | return value_of_register (*reg_p, frame); | |
2414 | } | |
2415 | \f | |
2416 | ||
9404b58f KM |
2417 | /* Implement the "software_single_step" gdbarch method, needed to |
2418 | single step through atomic sequences on AArch64. */ | |
2419 | ||
a0ff9e1a | 2420 | static std::vector<CORE_ADDR> |
f5ea389a | 2421 | aarch64_software_single_step (struct regcache *regcache) |
9404b58f | 2422 | { |
0187a92f | 2423 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
9404b58f KM |
2424 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2425 | const int insn_size = 4; | |
2426 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
0187a92f | 2427 | CORE_ADDR pc = regcache_read_pc (regcache); |
9404b58f KM |
2428 | CORE_ADDR breaks[2] = { -1, -1 }; |
2429 | CORE_ADDR loc = pc; | |
2430 | CORE_ADDR closing_insn = 0; | |
2431 | uint32_t insn = read_memory_unsigned_integer (loc, insn_size, | |
2432 | byte_order_for_code); | |
2433 | int index; | |
2434 | int insn_count; | |
2435 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2436 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
f77ee802 YQ |
2437 | aarch64_inst inst; |
2438 | ||
43cdf5ae | 2439 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
a0ff9e1a | 2440 | return {}; |
9404b58f KM |
2441 | |
2442 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
f77ee802 | 2443 | if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) |
a0ff9e1a | 2444 | return {}; |
9404b58f KM |
2445 | |
2446 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2447 | { | |
9404b58f KM |
2448 | loc += insn_size; |
2449 | insn = read_memory_unsigned_integer (loc, insn_size, | |
2450 | byte_order_for_code); | |
2451 | ||
43cdf5ae | 2452 | if (aarch64_decode_insn (insn, &inst, 1) != 0) |
a0ff9e1a | 2453 | return {}; |
9404b58f | 2454 | /* Check if the instruction is a conditional branch. */ |
f77ee802 | 2455 | if (inst.opcode->iclass == condbranch) |
9404b58f | 2456 | { |
f77ee802 YQ |
2457 | gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); |
2458 | ||
9404b58f | 2459 | if (bc_insn_count >= 1) |
a0ff9e1a | 2460 | return {}; |
9404b58f KM |
2461 | |
2462 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
f77ee802 | 2463 | breaks[1] = loc + inst.operands[0].imm.value; |
9404b58f KM |
2464 | |
2465 | bc_insn_count++; | |
2466 | last_breakpoint++; | |
2467 | } | |
2468 | ||
2469 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
f77ee802 | 2470 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) |
9404b58f KM |
2471 | { |
2472 | closing_insn = loc; | |
2473 | break; | |
2474 | } | |
2475 | } | |
2476 | ||
2477 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
2478 | if (!closing_insn) | |
a0ff9e1a | 2479 | return {}; |
9404b58f KM |
2480 | |
2481 | /* Insert breakpoint after the end of the atomic sequence. */ | |
2482 | breaks[0] = loc + insn_size; | |
2483 | ||
2484 | /* Check for duplicated breakpoints, and also check that the second | |
2485 | breakpoint is not within the atomic sequence. */ | |
2486 | if (last_breakpoint | |
2487 | && (breaks[1] == breaks[0] | |
2488 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
2489 | last_breakpoint = 0; | |
2490 | ||
a0ff9e1a SM |
2491 | std::vector<CORE_ADDR> next_pcs; |
2492 | ||
9404b58f KM |
2493 | /* Insert the breakpoint at the end of the sequence, and one at the |
2494 | destination of the conditional branch, if it exists. */ | |
2495 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 2496 | next_pcs.push_back (breaks[index]); |
9404b58f | 2497 | |
93f9a11f | 2498 | return next_pcs; |
9404b58f KM |
2499 | } |
2500 | ||
b6542f81 YQ |
2501 | struct displaced_step_closure |
2502 | { | |
2503 | /* It is true when condition instruction, such as B.CON, TBZ, etc, | |
2504 | is being displaced stepping. */ | |
2505 | int cond; | |
2506 | ||
2507 | /* PC adjustment offset after displaced stepping. */ | |
2508 | int32_t pc_adjust; | |
2509 | }; | |
2510 | ||
2511 | /* Data when visiting instructions for displaced stepping. */ | |
2512 | ||
2513 | struct aarch64_displaced_step_data | |
2514 | { | |
2515 | struct aarch64_insn_data base; | |
2516 | ||
2517 | /* The address where the instruction will be executed at. */ | |
2518 | CORE_ADDR new_addr; | |
2519 | /* Buffer of instructions to be copied to NEW_ADDR to execute. */ | |
2520 | uint32_t insn_buf[DISPLACED_MODIFIED_INSNS]; | |
2521 | /* Number of instructions in INSN_BUF. */ | |
2522 | unsigned insn_count; | |
2523 | /* Registers when doing displaced stepping. */ | |
2524 | struct regcache *regs; | |
2525 | ||
2526 | struct displaced_step_closure *dsc; | |
2527 | }; | |
2528 | ||
2529 | /* Implementation of aarch64_insn_visitor method "b". */ | |
2530 | ||
2531 | static void | |
2532 | aarch64_displaced_step_b (const int is_bl, const int32_t offset, | |
2533 | struct aarch64_insn_data *data) | |
2534 | { | |
2535 | struct aarch64_displaced_step_data *dsd | |
2536 | = (struct aarch64_displaced_step_data *) data; | |
2ac09a5b | 2537 | int64_t new_offset = data->insn_addr - dsd->new_addr + offset; |
b6542f81 YQ |
2538 | |
2539 | if (can_encode_int32 (new_offset, 28)) | |
2540 | { | |
2541 | /* Emit B rather than BL, because executing BL on a new address | |
2542 | will get the wrong address into LR. In order to avoid this, | |
2543 | we emit B, and update LR if the instruction is BL. */ | |
2544 | emit_b (dsd->insn_buf, 0, new_offset); | |
2545 | dsd->insn_count++; | |
2546 | } | |
2547 | else | |
2548 | { | |
2549 | /* Write NOP. */ | |
2550 | emit_nop (dsd->insn_buf); | |
2551 | dsd->insn_count++; | |
2552 | dsd->dsc->pc_adjust = offset; | |
2553 | } | |
2554 | ||
2555 | if (is_bl) | |
2556 | { | |
2557 | /* Update LR. */ | |
2558 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
2559 | data->insn_addr + 4); | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | /* Implementation of aarch64_insn_visitor method "b_cond". */ | |
2564 | ||
2565 | static void | |
2566 | aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset, | |
2567 | struct aarch64_insn_data *data) | |
2568 | { | |
2569 | struct aarch64_displaced_step_data *dsd | |
2570 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2571 | |
2572 | /* GDB has to fix up PC after displaced step this instruction | |
2573 | differently according to the condition is true or false. Instead | |
2574 | of checking COND against conditional flags, we can use | |
2575 | the following instructions, and GDB can tell how to fix up PC | |
2576 | according to the PC value. | |
2577 | ||
2578 | B.COND TAKEN ; If cond is true, then jump to TAKEN. | |
2579 | INSN1 ; | |
2580 | TAKEN: | |
2581 | INSN2 | |
2582 | */ | |
2583 | ||
2584 | emit_bcond (dsd->insn_buf, cond, 8); | |
2585 | dsd->dsc->cond = 1; | |
2586 | dsd->dsc->pc_adjust = offset; | |
2587 | dsd->insn_count = 1; | |
2588 | } | |
2589 | ||
2590 | /* Dynamically allocate a new register. If we know the register | |
2591 | statically, we should make it a global as above instead of using this | |
2592 | helper function. */ | |
2593 | ||
2594 | static struct aarch64_register | |
2595 | aarch64_register (unsigned num, int is64) | |
2596 | { | |
2597 | return (struct aarch64_register) { num, is64 }; | |
2598 | } | |
2599 | ||
2600 | /* Implementation of aarch64_insn_visitor method "cb". */ | |
2601 | ||
2602 | static void | |
2603 | aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz, | |
2604 | const unsigned rn, int is64, | |
2605 | struct aarch64_insn_data *data) | |
2606 | { | |
2607 | struct aarch64_displaced_step_data *dsd | |
2608 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2609 | |
2610 | /* The offset is out of range for a compare and branch | |
2611 | instruction. We can use the following instructions instead: | |
2612 | ||
2613 | CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. | |
2614 | INSN1 ; | |
2615 | TAKEN: | |
2616 | INSN2 | |
2617 | */ | |
2618 | emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8); | |
2619 | dsd->insn_count = 1; | |
2620 | dsd->dsc->cond = 1; | |
2621 | dsd->dsc->pc_adjust = offset; | |
2622 | } | |
2623 | ||
2624 | /* Implementation of aarch64_insn_visitor method "tb". */ | |
2625 | ||
2626 | static void | |
2627 | aarch64_displaced_step_tb (const int32_t offset, int is_tbnz, | |
2628 | const unsigned rt, unsigned bit, | |
2629 | struct aarch64_insn_data *data) | |
2630 | { | |
2631 | struct aarch64_displaced_step_data *dsd | |
2632 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
2633 | |
2634 | /* The offset is out of range for a test bit and branch | |
2635 | instruction We can use the following instructions instead: | |
2636 | ||
2637 | TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. | |
2638 | INSN1 ; | |
2639 | TAKEN: | |
2640 | INSN2 | |
2641 | ||
2642 | */ | |
2643 | emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8); | |
2644 | dsd->insn_count = 1; | |
2645 | dsd->dsc->cond = 1; | |
2646 | dsd->dsc->pc_adjust = offset; | |
2647 | } | |
2648 | ||
2649 | /* Implementation of aarch64_insn_visitor method "adr". */ | |
2650 | ||
2651 | static void | |
2652 | aarch64_displaced_step_adr (const int32_t offset, const unsigned rd, | |
2653 | const int is_adrp, struct aarch64_insn_data *data) | |
2654 | { | |
2655 | struct aarch64_displaced_step_data *dsd | |
2656 | = (struct aarch64_displaced_step_data *) data; | |
2657 | /* We know exactly the address the ADR{P,} instruction will compute. | |
2658 | We can just write it to the destination register. */ | |
2659 | CORE_ADDR address = data->insn_addr + offset; | |
2660 | ||
2661 | if (is_adrp) | |
2662 | { | |
2663 | /* Clear the lower 12 bits of the offset to get the 4K page. */ | |
2664 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2665 | address & ~0xfff); | |
2666 | } | |
2667 | else | |
2668 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
2669 | address); | |
2670 | ||
2671 | dsd->dsc->pc_adjust = 4; | |
2672 | emit_nop (dsd->insn_buf); | |
2673 | dsd->insn_count = 1; | |
2674 | } | |
2675 | ||
2676 | /* Implementation of aarch64_insn_visitor method "ldr_literal". */ | |
2677 | ||
2678 | static void | |
2679 | aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw, | |
2680 | const unsigned rt, const int is64, | |
2681 | struct aarch64_insn_data *data) | |
2682 | { | |
2683 | struct aarch64_displaced_step_data *dsd | |
2684 | = (struct aarch64_displaced_step_data *) data; | |
2685 | CORE_ADDR address = data->insn_addr + offset; | |
2686 | struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 }; | |
2687 | ||
2688 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt, | |
2689 | address); | |
2690 | ||
2691 | if (is_sw) | |
2692 | dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1), | |
2693 | aarch64_register (rt, 1), zero); | |
2694 | else | |
2695 | dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64), | |
2696 | aarch64_register (rt, 1), zero); | |
2697 | ||
2698 | dsd->dsc->pc_adjust = 4; | |
2699 | } | |
2700 | ||
2701 | /* Implementation of aarch64_insn_visitor method "others". */ | |
2702 | ||
2703 | static void | |
2704 | aarch64_displaced_step_others (const uint32_t insn, | |
2705 | struct aarch64_insn_data *data) | |
2706 | { | |
2707 | struct aarch64_displaced_step_data *dsd | |
2708 | = (struct aarch64_displaced_step_data *) data; | |
2709 | ||
e1c587c3 | 2710 | aarch64_emit_insn (dsd->insn_buf, insn); |
b6542f81 YQ |
2711 | dsd->insn_count = 1; |
2712 | ||
2713 | if ((insn & 0xfffffc1f) == 0xd65f0000) | |
2714 | { | |
2715 | /* RET */ | |
2716 | dsd->dsc->pc_adjust = 0; | |
2717 | } | |
2718 | else | |
2719 | dsd->dsc->pc_adjust = 4; | |
2720 | } | |
2721 | ||
2722 | static const struct aarch64_insn_visitor visitor = | |
2723 | { | |
2724 | aarch64_displaced_step_b, | |
2725 | aarch64_displaced_step_b_cond, | |
2726 | aarch64_displaced_step_cb, | |
2727 | aarch64_displaced_step_tb, | |
2728 | aarch64_displaced_step_adr, | |
2729 | aarch64_displaced_step_ldr_literal, | |
2730 | aarch64_displaced_step_others, | |
2731 | }; | |
2732 | ||
2733 | /* Implement the "displaced_step_copy_insn" gdbarch method. */ | |
2734 | ||
2735 | struct displaced_step_closure * | |
2736 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
2737 | CORE_ADDR from, CORE_ADDR to, | |
2738 | struct regcache *regs) | |
2739 | { | |
2740 | struct displaced_step_closure *dsc = NULL; | |
2741 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2742 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); | |
2743 | struct aarch64_displaced_step_data dsd; | |
c86a40c6 YQ |
2744 | aarch64_inst inst; |
2745 | ||
2746 | if (aarch64_decode_insn (insn, &inst, 1) != 0) | |
2747 | return NULL; | |
b6542f81 YQ |
2748 | |
2749 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
c86a40c6 | 2750 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) |
b6542f81 YQ |
2751 | { |
2752 | /* We can't displaced step atomic sequences. */ | |
2753 | return NULL; | |
2754 | } | |
2755 | ||
2756 | dsc = XCNEW (struct displaced_step_closure); | |
2757 | dsd.base.insn_addr = from; | |
2758 | dsd.new_addr = to; | |
2759 | dsd.regs = regs; | |
2760 | dsd.dsc = dsc; | |
034f1a81 | 2761 | dsd.insn_count = 0; |
b6542f81 YQ |
2762 | aarch64_relocate_instruction (insn, &visitor, |
2763 | (struct aarch64_insn_data *) &dsd); | |
2764 | gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS); | |
2765 | ||
2766 | if (dsd.insn_count != 0) | |
2767 | { | |
2768 | int i; | |
2769 | ||
2770 | /* Instruction can be relocated to scratch pad. Copy | |
2771 | relocated instruction(s) there. */ | |
2772 | for (i = 0; i < dsd.insn_count; i++) | |
2773 | { | |
2774 | if (debug_displaced) | |
2775 | { | |
2776 | debug_printf ("displaced: writing insn "); | |
2777 | debug_printf ("%.8x", dsd.insn_buf[i]); | |
2778 | debug_printf (" at %s\n", paddress (gdbarch, to + i * 4)); | |
2779 | } | |
2780 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, | |
2781 | (ULONGEST) dsd.insn_buf[i]); | |
2782 | } | |
2783 | } | |
2784 | else | |
2785 | { | |
2786 | xfree (dsc); | |
2787 | dsc = NULL; | |
2788 | } | |
2789 | ||
2790 | return dsc; | |
2791 | } | |
2792 | ||
2793 | /* Implement the "displaced_step_fixup" gdbarch method. */ | |
2794 | ||
2795 | void | |
2796 | aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
2797 | struct displaced_step_closure *dsc, | |
2798 | CORE_ADDR from, CORE_ADDR to, | |
2799 | struct regcache *regs) | |
2800 | { | |
2801 | if (dsc->cond) | |
2802 | { | |
2803 | ULONGEST pc; | |
2804 | ||
2805 | regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc); | |
2806 | if (pc - to == 8) | |
2807 | { | |
2808 | /* Condition is true. */ | |
2809 | } | |
2810 | else if (pc - to == 4) | |
2811 | { | |
2812 | /* Condition is false. */ | |
2813 | dsc->pc_adjust = 4; | |
2814 | } | |
2815 | else | |
2816 | gdb_assert_not_reached ("Unexpected PC value after displaced stepping"); | |
2817 | } | |
2818 | ||
2819 | if (dsc->pc_adjust != 0) | |
2820 | { | |
2821 | if (debug_displaced) | |
2822 | { | |
2823 | debug_printf ("displaced: fixup: set PC to %s:%d\n", | |
2824 | paddress (gdbarch, from), dsc->pc_adjust); | |
2825 | } | |
2826 | regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM, | |
2827 | from + dsc->pc_adjust); | |
2828 | } | |
2829 | } | |
2830 | ||
2831 | /* Implement the "displaced_step_hw_singlestep" gdbarch method. */ | |
2832 | ||
2833 | int | |
2834 | aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
2835 | struct displaced_step_closure *closure) | |
2836 | { | |
2837 | return 1; | |
2838 | } | |
2839 | ||
07b287a0 MS |
2840 | /* Initialize the current architecture based on INFO. If possible, |
2841 | re-use an architecture from ARCHES, which is a list of | |
2842 | architectures already created during this debugging session. | |
2843 | ||
2844 | Called e.g. at program startup, when reading a core file, and when | |
2845 | reading a binary file. */ | |
2846 | ||
2847 | static struct gdbarch * | |
2848 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2849 | { | |
2850 | struct gdbarch_tdep *tdep; | |
2851 | struct gdbarch *gdbarch; | |
2852 | struct gdbarch_list *best_arch; | |
2853 | struct tdesc_arch_data *tdesc_data = NULL; | |
2854 | const struct target_desc *tdesc = info.target_desc; | |
2855 | int i; | |
07b287a0 MS |
2856 | int valid_p = 1; |
2857 | const struct tdesc_feature *feature; | |
2858 | int num_regs = 0; | |
2859 | int num_pseudo_regs = 0; | |
2860 | ||
2861 | /* Ensure we always have a target descriptor. */ | |
2862 | if (!tdesc_has_registers (tdesc)) | |
2863 | tdesc = tdesc_aarch64; | |
2864 | ||
2865 | gdb_assert (tdesc); | |
2866 | ||
2867 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core"); | |
2868 | ||
2869 | if (feature == NULL) | |
2870 | return NULL; | |
2871 | ||
2872 | tdesc_data = tdesc_data_alloc (); | |
2873 | ||
2874 | /* Validate the descriptor provides the mandatory core R registers | |
2875 | and allocate their numbers. */ | |
2876 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
2877 | valid_p &= | |
2878 | tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i, | |
2879 | aarch64_r_register_names[i]); | |
2880 | ||
2881 | num_regs = AARCH64_X0_REGNUM + i; | |
2882 | ||
2883 | /* Look for the V registers. */ | |
2884 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); | |
2885 | if (feature) | |
2886 | { | |
2887 | /* Validate the descriptor provides the mandatory V registers | |
2888 | and allocate their numbers. */ | |
2889 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) | |
2890 | valid_p &= | |
2891 | tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i, | |
2892 | aarch64_v_register_names[i]); | |
2893 | ||
2894 | num_regs = AARCH64_V0_REGNUM + i; | |
2895 | ||
2896 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ | |
2897 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
2898 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
2899 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
2900 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
2901 | } | |
2902 | ||
2903 | if (!valid_p) | |
2904 | { | |
2905 | tdesc_data_cleanup (tdesc_data); | |
2906 | return NULL; | |
2907 | } | |
2908 | ||
2909 | /* AArch64 code is always little-endian. */ | |
2910 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
2911 | ||
2912 | /* If there is already a candidate, use it. */ | |
2913 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2914 | best_arch != NULL; | |
2915 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2916 | { | |
2917 | /* Found a match. */ | |
2918 | break; | |
2919 | } | |
2920 | ||
2921 | if (best_arch != NULL) | |
2922 | { | |
2923 | if (tdesc_data != NULL) | |
2924 | tdesc_data_cleanup (tdesc_data); | |
2925 | return best_arch->gdbarch; | |
2926 | } | |
2927 | ||
8d749320 | 2928 | tdep = XCNEW (struct gdbarch_tdep); |
07b287a0 MS |
2929 | gdbarch = gdbarch_alloc (&info, tdep); |
2930 | ||
2931 | /* This should be low enough for everything. */ | |
2932 | tdep->lowest_pc = 0x20; | |
2933 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
2934 | tdep->jb_elt_size = 8; | |
2935 | ||
2936 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); | |
2937 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
2938 | ||
07b287a0 MS |
2939 | /* Frame handling. */ |
2940 | set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id); | |
2941 | set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc); | |
2942 | set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp); | |
2943 | ||
2944 | /* Advance PC across function entry code. */ | |
2945 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
2946 | ||
2947 | /* The stack grows downward. */ | |
2948 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2949 | ||
2950 | /* Breakpoint manipulation. */ | |
04180708 YQ |
2951 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
2952 | aarch64_breakpoint::kind_from_pc); | |
2953 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
2954 | aarch64_breakpoint::bp_from_kind); | |
07b287a0 | 2955 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 2956 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
2957 | |
2958 | /* Information about registers, etc. */ | |
2959 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
2960 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
2961 | set_gdbarch_num_regs (gdbarch, num_regs); | |
2962 | ||
2963 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
2964 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
2965 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
2966 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
2967 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
2968 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
2969 | aarch64_pseudo_register_reggroup_p); | |
2970 | ||
2971 | /* ABI */ | |
2972 | set_gdbarch_short_bit (gdbarch, 16); | |
2973 | set_gdbarch_int_bit (gdbarch, 32); | |
2974 | set_gdbarch_float_bit (gdbarch, 32); | |
2975 | set_gdbarch_double_bit (gdbarch, 64); | |
2976 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2977 | set_gdbarch_long_bit (gdbarch, 64); | |
2978 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2979 | set_gdbarch_ptr_bit (gdbarch, 64); | |
2980 | set_gdbarch_char_signed (gdbarch, 0); | |
53375380 | 2981 | set_gdbarch_wchar_signed (gdbarch, 0); |
07b287a0 MS |
2982 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
2983 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
2984 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2985 | ||
2986 | /* Internal <-> external register number maps. */ | |
2987 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
2988 | ||
2989 | /* Returning results. */ | |
2990 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
2991 | ||
2992 | /* Disassembly. */ | |
2993 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
2994 | ||
2995 | /* Virtual tables. */ | |
2996 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
2997 | ||
2998 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
2999 | info.target_desc = tdesc; | |
0dba2a6c | 3000 | info.tdesc_data = tdesc_data; |
07b287a0 MS |
3001 | gdbarch_init_osabi (info, gdbarch); |
3002 | ||
3003 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
3004 | ||
3005 | /* Add some default predicates. */ | |
3006 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
3007 | dwarf2_append_unwinders (gdbarch); | |
3008 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
3009 | ||
3010 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
3011 | ||
3012 | /* Now we have tuned the configuration, set a few final things, | |
3013 | based on what the OS ABI has told us. */ | |
3014 | ||
3015 | if (tdep->jb_pc >= 0) | |
3016 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
3017 | ||
ea873d8e PL |
3018 | set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address); |
3019 | ||
07b287a0 MS |
3020 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
3021 | ||
3022 | /* Add standard register aliases. */ | |
3023 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
3024 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
3025 | value_of_aarch64_user_reg, | |
3026 | &aarch64_register_aliases[i].regnum); | |
3027 | ||
3028 | return gdbarch; | |
3029 | } | |
3030 | ||
3031 | static void | |
3032 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3033 | { | |
3034 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3035 | ||
3036 | if (tdep == NULL) | |
3037 | return; | |
3038 | ||
3039 | fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), | |
3040 | paddress (gdbarch, tdep->lowest_pc)); | |
3041 | } | |
3042 | ||
0d4c07af | 3043 | #if GDB_SELF_TEST |
1e2b521d YQ |
3044 | namespace selftests |
3045 | { | |
3046 | static void aarch64_process_record_test (void); | |
3047 | } | |
0d4c07af | 3048 | #endif |
1e2b521d | 3049 | |
07b287a0 MS |
3050 | void |
3051 | _initialize_aarch64_tdep (void) | |
3052 | { | |
3053 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
3054 | aarch64_dump_tdep); | |
3055 | ||
3056 | initialize_tdesc_aarch64 (); | |
07b287a0 MS |
3057 | |
3058 | /* Debug this file's internals. */ | |
3059 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
3060 | Set AArch64 debugging."), _("\ | |
3061 | Show AArch64 debugging."), _("\ | |
3062 | When on, AArch64 specific debugging is enabled."), | |
3063 | NULL, | |
3064 | show_aarch64_debug, | |
3065 | &setdebuglist, &showdebuglist); | |
4d9a9006 YQ |
3066 | |
3067 | #if GDB_SELF_TEST | |
1526853e SM |
3068 | selftests::register_test ("aarch64-analyze-prologue", |
3069 | selftests::aarch64_analyze_prologue_test); | |
3070 | selftests::register_test ("aarch64-process-record", | |
3071 | selftests::aarch64_process_record_test); | |
4d9a9006 | 3072 | #endif |
07b287a0 | 3073 | } |
99afc88b OJ |
3074 | |
3075 | /* AArch64 process record-replay related structures, defines etc. */ | |
3076 | ||
99afc88b OJ |
3077 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ |
3078 | do \ | |
3079 | { \ | |
3080 | unsigned int reg_len = LENGTH; \ | |
3081 | if (reg_len) \ | |
3082 | { \ | |
3083 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
3084 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
3085 | } \ | |
3086 | } \ | |
3087 | while (0) | |
3088 | ||
3089 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
3090 | do \ | |
3091 | { \ | |
3092 | unsigned int mem_len = LENGTH; \ | |
3093 | if (mem_len) \ | |
3094 | { \ | |
3095 | MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \ | |
3096 | memcpy(&MEMS->len, &RECORD_BUF[0], \ | |
3097 | sizeof(struct aarch64_mem_r) * LENGTH); \ | |
3098 | } \ | |
3099 | } \ | |
3100 | while (0) | |
3101 | ||
3102 | /* AArch64 record/replay structures and enumerations. */ | |
3103 | ||
3104 | struct aarch64_mem_r | |
3105 | { | |
3106 | uint64_t len; /* Record length. */ | |
3107 | uint64_t addr; /* Memory address. */ | |
3108 | }; | |
3109 | ||
3110 | enum aarch64_record_result | |
3111 | { | |
3112 | AARCH64_RECORD_SUCCESS, | |
99afc88b OJ |
3113 | AARCH64_RECORD_UNSUPPORTED, |
3114 | AARCH64_RECORD_UNKNOWN | |
3115 | }; | |
3116 | ||
3117 | typedef struct insn_decode_record_t | |
3118 | { | |
3119 | struct gdbarch *gdbarch; | |
3120 | struct regcache *regcache; | |
3121 | CORE_ADDR this_addr; /* Address of insn to be recorded. */ | |
3122 | uint32_t aarch64_insn; /* Insn to be recorded. */ | |
3123 | uint32_t mem_rec_count; /* Count of memory records. */ | |
3124 | uint32_t reg_rec_count; /* Count of register records. */ | |
3125 | uint32_t *aarch64_regs; /* Registers to be recorded. */ | |
3126 | struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */ | |
3127 | } insn_decode_record; | |
3128 | ||
3129 | /* Record handler for data processing - register instructions. */ | |
3130 | ||
3131 | static unsigned int | |
3132 | aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r) | |
3133 | { | |
3134 | uint8_t reg_rd, insn_bits24_27, insn_bits21_23; | |
3135 | uint32_t record_buf[4]; | |
3136 | ||
3137 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3138 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3139 | insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23); | |
3140 | ||
3141 | if (!bit (aarch64_insn_r->aarch64_insn, 28)) | |
3142 | { | |
3143 | uint8_t setflags; | |
3144 | ||
3145 | /* Logical (shifted register). */ | |
3146 | if (insn_bits24_27 == 0x0a) | |
3147 | setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03); | |
3148 | /* Add/subtract. */ | |
3149 | else if (insn_bits24_27 == 0x0b) | |
3150 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3151 | else | |
3152 | return AARCH64_RECORD_UNKNOWN; | |
3153 | ||
3154 | record_buf[0] = reg_rd; | |
3155 | aarch64_insn_r->reg_rec_count = 1; | |
3156 | if (setflags) | |
3157 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3158 | } | |
3159 | else | |
3160 | { | |
3161 | if (insn_bits24_27 == 0x0b) | |
3162 | { | |
3163 | /* Data-processing (3 source). */ | |
3164 | record_buf[0] = reg_rd; | |
3165 | aarch64_insn_r->reg_rec_count = 1; | |
3166 | } | |
3167 | else if (insn_bits24_27 == 0x0a) | |
3168 | { | |
3169 | if (insn_bits21_23 == 0x00) | |
3170 | { | |
3171 | /* Add/subtract (with carry). */ | |
3172 | record_buf[0] = reg_rd; | |
3173 | aarch64_insn_r->reg_rec_count = 1; | |
3174 | if (bit (aarch64_insn_r->aarch64_insn, 29)) | |
3175 | { | |
3176 | record_buf[1] = AARCH64_CPSR_REGNUM; | |
3177 | aarch64_insn_r->reg_rec_count = 2; | |
3178 | } | |
3179 | } | |
3180 | else if (insn_bits21_23 == 0x02) | |
3181 | { | |
3182 | /* Conditional compare (register) and conditional compare | |
3183 | (immediate) instructions. */ | |
3184 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3185 | aarch64_insn_r->reg_rec_count = 1; | |
3186 | } | |
3187 | else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06) | |
3188 | { | |
3189 | /* CConditional select. */ | |
3190 | /* Data-processing (2 source). */ | |
3191 | /* Data-processing (1 source). */ | |
3192 | record_buf[0] = reg_rd; | |
3193 | aarch64_insn_r->reg_rec_count = 1; | |
3194 | } | |
3195 | else | |
3196 | return AARCH64_RECORD_UNKNOWN; | |
3197 | } | |
3198 | } | |
3199 | ||
3200 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3201 | record_buf); | |
3202 | return AARCH64_RECORD_SUCCESS; | |
3203 | } | |
3204 | ||
3205 | /* Record handler for data processing - immediate instructions. */ | |
3206 | ||
3207 | static unsigned int | |
3208 | aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r) | |
3209 | { | |
78cc6c2d | 3210 | uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; |
99afc88b OJ |
3211 | uint32_t record_buf[4]; |
3212 | ||
3213 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
99afc88b OJ |
3214 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); |
3215 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3216 | ||
3217 | if (insn_bits24_27 == 0x00 /* PC rel addressing. */ | |
3218 | || insn_bits24_27 == 0x03 /* Bitfield and Extract. */ | |
3219 | || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */ | |
3220 | { | |
3221 | record_buf[0] = reg_rd; | |
3222 | aarch64_insn_r->reg_rec_count = 1; | |
3223 | } | |
3224 | else if (insn_bits24_27 == 0x01) | |
3225 | { | |
3226 | /* Add/Subtract (immediate). */ | |
3227 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3228 | record_buf[0] = reg_rd; | |
3229 | aarch64_insn_r->reg_rec_count = 1; | |
3230 | if (setflags) | |
3231 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3232 | } | |
3233 | else if (insn_bits24_27 == 0x02 && !insn_bit23) | |
3234 | { | |
3235 | /* Logical (immediate). */ | |
3236 | setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03; | |
3237 | record_buf[0] = reg_rd; | |
3238 | aarch64_insn_r->reg_rec_count = 1; | |
3239 | if (setflags) | |
3240 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3241 | } | |
3242 | else | |
3243 | return AARCH64_RECORD_UNKNOWN; | |
3244 | ||
3245 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3246 | record_buf); | |
3247 | return AARCH64_RECORD_SUCCESS; | |
3248 | } | |
3249 | ||
3250 | /* Record handler for branch, exception generation and system instructions. */ | |
3251 | ||
3252 | static unsigned int | |
3253 | aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r) | |
3254 | { | |
3255 | struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch); | |
3256 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23; | |
3257 | uint32_t record_buf[4]; | |
3258 | ||
3259 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3260 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3261 | insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3262 | ||
3263 | if (insn_bits28_31 == 0x0d) | |
3264 | { | |
3265 | /* Exception generation instructions. */ | |
3266 | if (insn_bits24_27 == 0x04) | |
3267 | { | |
5d98d3cd YQ |
3268 | if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) |
3269 | && !bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3270 | && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01) | |
99afc88b OJ |
3271 | { |
3272 | ULONGEST svc_number; | |
3273 | ||
3274 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8, | |
3275 | &svc_number); | |
3276 | return tdep->aarch64_syscall_record (aarch64_insn_r->regcache, | |
3277 | svc_number); | |
3278 | } | |
3279 | else | |
3280 | return AARCH64_RECORD_UNSUPPORTED; | |
3281 | } | |
3282 | /* System instructions. */ | |
3283 | else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00) | |
3284 | { | |
3285 | uint32_t reg_rt, reg_crn; | |
3286 | ||
3287 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3288 | reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3289 | ||
3290 | /* Record rt in case of sysl and mrs instructions. */ | |
3291 | if (bit (aarch64_insn_r->aarch64_insn, 21)) | |
3292 | { | |
3293 | record_buf[0] = reg_rt; | |
3294 | aarch64_insn_r->reg_rec_count = 1; | |
3295 | } | |
3296 | /* Record cpsr for hint and msr(immediate) instructions. */ | |
3297 | else if (reg_crn == 0x02 || reg_crn == 0x04) | |
3298 | { | |
3299 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3300 | aarch64_insn_r->reg_rec_count = 1; | |
3301 | } | |
3302 | } | |
3303 | /* Unconditional branch (register). */ | |
3304 | else if((insn_bits24_27 & 0x0e) == 0x06) | |
3305 | { | |
3306 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3307 | if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01) | |
3308 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3309 | } | |
3310 | else | |
3311 | return AARCH64_RECORD_UNKNOWN; | |
3312 | } | |
3313 | /* Unconditional branch (immediate). */ | |
3314 | else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04) | |
3315 | { | |
3316 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3317 | if (bit (aarch64_insn_r->aarch64_insn, 31)) | |
3318 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3319 | } | |
3320 | else | |
3321 | /* Compare & branch (immediate), Test & branch (immediate) and | |
3322 | Conditional branch (immediate). */ | |
3323 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3324 | ||
3325 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3326 | record_buf); | |
3327 | return AARCH64_RECORD_SUCCESS; | |
3328 | } | |
3329 | ||
3330 | /* Record handler for advanced SIMD load and store instructions. */ | |
3331 | ||
3332 | static unsigned int | |
3333 | aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r) | |
3334 | { | |
3335 | CORE_ADDR address; | |
3336 | uint64_t addr_offset = 0; | |
3337 | uint32_t record_buf[24]; | |
3338 | uint64_t record_buf_mem[24]; | |
3339 | uint32_t reg_rn, reg_rt; | |
3340 | uint32_t reg_index = 0, mem_index = 0; | |
3341 | uint8_t opcode_bits, size_bits; | |
3342 | ||
3343 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3344 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3345 | size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3346 | opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3347 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); | |
3348 | ||
3349 | if (record_debug) | |
b277c936 | 3350 | debug_printf ("Process record: Advanced SIMD load/store\n"); |
99afc88b OJ |
3351 | |
3352 | /* Load/store single structure. */ | |
3353 | if (bit (aarch64_insn_r->aarch64_insn, 24)) | |
3354 | { | |
3355 | uint8_t sindex, scale, selem, esize, replicate = 0; | |
3356 | scale = opcode_bits >> 2; | |
3357 | selem = ((opcode_bits & 0x02) | | |
3358 | bit (aarch64_insn_r->aarch64_insn, 21)) + 1; | |
3359 | switch (scale) | |
3360 | { | |
3361 | case 1: | |
3362 | if (size_bits & 0x01) | |
3363 | return AARCH64_RECORD_UNKNOWN; | |
3364 | break; | |
3365 | case 2: | |
3366 | if ((size_bits >> 1) & 0x01) | |
3367 | return AARCH64_RECORD_UNKNOWN; | |
3368 | if (size_bits & 0x01) | |
3369 | { | |
3370 | if (!((opcode_bits >> 1) & 0x01)) | |
3371 | scale = 3; | |
3372 | else | |
3373 | return AARCH64_RECORD_UNKNOWN; | |
3374 | } | |
3375 | break; | |
3376 | case 3: | |
3377 | if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) | |
3378 | { | |
3379 | scale = size_bits; | |
3380 | replicate = 1; | |
3381 | break; | |
3382 | } | |
3383 | else | |
3384 | return AARCH64_RECORD_UNKNOWN; | |
3385 | default: | |
3386 | break; | |
3387 | } | |
3388 | esize = 8 << scale; | |
3389 | if (replicate) | |
3390 | for (sindex = 0; sindex < selem; sindex++) | |
3391 | { | |
3392 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3393 | reg_rt = (reg_rt + 1) % 32; | |
3394 | } | |
3395 | else | |
3396 | { | |
3397 | for (sindex = 0; sindex < selem; sindex++) | |
a2e3e93f SM |
3398 | { |
3399 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3400 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
3401 | else | |
3402 | { | |
3403 | record_buf_mem[mem_index++] = esize / 8; | |
3404 | record_buf_mem[mem_index++] = address + addr_offset; | |
3405 | } | |
3406 | addr_offset = addr_offset + (esize / 8); | |
3407 | reg_rt = (reg_rt + 1) % 32; | |
3408 | } | |
99afc88b OJ |
3409 | } |
3410 | } | |
3411 | /* Load/store multiple structure. */ | |
3412 | else | |
3413 | { | |
3414 | uint8_t selem, esize, rpt, elements; | |
3415 | uint8_t eindex, rindex; | |
3416 | ||
3417 | esize = 8 << size_bits; | |
3418 | if (bit (aarch64_insn_r->aarch64_insn, 30)) | |
3419 | elements = 128 / esize; | |
3420 | else | |
3421 | elements = 64 / esize; | |
3422 | ||
3423 | switch (opcode_bits) | |
3424 | { | |
3425 | /*LD/ST4 (4 Registers). */ | |
3426 | case 0: | |
3427 | rpt = 1; | |
3428 | selem = 4; | |
3429 | break; | |
3430 | /*LD/ST1 (4 Registers). */ | |
3431 | case 2: | |
3432 | rpt = 4; | |
3433 | selem = 1; | |
3434 | break; | |
3435 | /*LD/ST3 (3 Registers). */ | |
3436 | case 4: | |
3437 | rpt = 1; | |
3438 | selem = 3; | |
3439 | break; | |
3440 | /*LD/ST1 (3 Registers). */ | |
3441 | case 6: | |
3442 | rpt = 3; | |
3443 | selem = 1; | |
3444 | break; | |
3445 | /*LD/ST1 (1 Register). */ | |
3446 | case 7: | |
3447 | rpt = 1; | |
3448 | selem = 1; | |
3449 | break; | |
3450 | /*LD/ST2 (2 Registers). */ | |
3451 | case 8: | |
3452 | rpt = 1; | |
3453 | selem = 2; | |
3454 | break; | |
3455 | /*LD/ST1 (2 Registers). */ | |
3456 | case 10: | |
3457 | rpt = 2; | |
3458 | selem = 1; | |
3459 | break; | |
3460 | default: | |
3461 | return AARCH64_RECORD_UNSUPPORTED; | |
3462 | break; | |
3463 | } | |
3464 | for (rindex = 0; rindex < rpt; rindex++) | |
3465 | for (eindex = 0; eindex < elements; eindex++) | |
3466 | { | |
3467 | uint8_t reg_tt, sindex; | |
3468 | reg_tt = (reg_rt + rindex) % 32; | |
3469 | for (sindex = 0; sindex < selem; sindex++) | |
3470 | { | |
3471 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
3472 | record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; | |
3473 | else | |
3474 | { | |
3475 | record_buf_mem[mem_index++] = esize / 8; | |
3476 | record_buf_mem[mem_index++] = address + addr_offset; | |
3477 | } | |
3478 | addr_offset = addr_offset + (esize / 8); | |
3479 | reg_tt = (reg_tt + 1) % 32; | |
3480 | } | |
3481 | } | |
3482 | } | |
3483 | ||
3484 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3485 | record_buf[reg_index++] = reg_rn; | |
3486 | ||
3487 | aarch64_insn_r->reg_rec_count = reg_index; | |
3488 | aarch64_insn_r->mem_rec_count = mem_index / 2; | |
3489 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3490 | record_buf_mem); | |
3491 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3492 | record_buf); | |
3493 | return AARCH64_RECORD_SUCCESS; | |
3494 | } | |
3495 | ||
3496 | /* Record handler for load and store instructions. */ | |
3497 | ||
3498 | static unsigned int | |
3499 | aarch64_record_load_store (insn_decode_record *aarch64_insn_r) | |
3500 | { | |
3501 | uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; | |
3502 | uint8_t insn_bit23, insn_bit21; | |
3503 | uint8_t opc, size_bits, ld_flag, vector_flag; | |
3504 | uint32_t reg_rn, reg_rt, reg_rt2; | |
3505 | uint64_t datasize, offset; | |
3506 | uint32_t record_buf[8]; | |
3507 | uint64_t record_buf_mem[8]; | |
3508 | CORE_ADDR address; | |
3509 | ||
3510 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3511 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3512 | insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29); | |
3513 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3514 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); | |
3515 | ld_flag = bit (aarch64_insn_r->aarch64_insn, 22); | |
3516 | vector_flag = bit (aarch64_insn_r->aarch64_insn, 26); | |
3517 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3518 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
3519 | reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14); | |
3520 | size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31); | |
3521 | ||
3522 | /* Load/store exclusive. */ | |
3523 | if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00) | |
3524 | { | |
3525 | if (record_debug) | |
b277c936 | 3526 | debug_printf ("Process record: load/store exclusive\n"); |
99afc88b OJ |
3527 | |
3528 | if (ld_flag) | |
3529 | { | |
3530 | record_buf[0] = reg_rt; | |
3531 | aarch64_insn_r->reg_rec_count = 1; | |
3532 | if (insn_bit21) | |
3533 | { | |
3534 | record_buf[1] = reg_rt2; | |
3535 | aarch64_insn_r->reg_rec_count = 2; | |
3536 | } | |
3537 | } | |
3538 | else | |
3539 | { | |
3540 | if (insn_bit21) | |
3541 | datasize = (8 << size_bits) * 2; | |
3542 | else | |
3543 | datasize = (8 << size_bits); | |
3544 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3545 | &address); | |
3546 | record_buf_mem[0] = datasize / 8; | |
3547 | record_buf_mem[1] = address; | |
3548 | aarch64_insn_r->mem_rec_count = 1; | |
3549 | if (!insn_bit23) | |
3550 | { | |
3551 | /* Save register rs. */ | |
3552 | record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20); | |
3553 | aarch64_insn_r->reg_rec_count = 1; | |
3554 | } | |
3555 | } | |
3556 | } | |
3557 | /* Load register (literal) instructions decoding. */ | |
3558 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01) | |
3559 | { | |
3560 | if (record_debug) | |
b277c936 | 3561 | debug_printf ("Process record: load register (literal)\n"); |
99afc88b OJ |
3562 | if (vector_flag) |
3563 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3564 | else | |
3565 | record_buf[0] = reg_rt; | |
3566 | aarch64_insn_r->reg_rec_count = 1; | |
3567 | } | |
3568 | /* All types of load/store pair instructions decoding. */ | |
3569 | else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02) | |
3570 | { | |
3571 | if (record_debug) | |
b277c936 | 3572 | debug_printf ("Process record: load/store pair\n"); |
99afc88b OJ |
3573 | |
3574 | if (ld_flag) | |
3575 | { | |
3576 | if (vector_flag) | |
3577 | { | |
3578 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3579 | record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM; | |
3580 | } | |
3581 | else | |
3582 | { | |
3583 | record_buf[0] = reg_rt; | |
3584 | record_buf[1] = reg_rt2; | |
3585 | } | |
3586 | aarch64_insn_r->reg_rec_count = 2; | |
3587 | } | |
3588 | else | |
3589 | { | |
3590 | uint16_t imm7_off; | |
3591 | imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21); | |
3592 | if (!vector_flag) | |
3593 | size_bits = size_bits >> 1; | |
3594 | datasize = 8 << (2 + size_bits); | |
3595 | offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off; | |
3596 | offset = offset << (2 + size_bits); | |
3597 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3598 | &address); | |
3599 | if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23)) | |
3600 | { | |
3601 | if (imm7_off & 0x40) | |
3602 | address = address - offset; | |
3603 | else | |
3604 | address = address + offset; | |
3605 | } | |
3606 | ||
3607 | record_buf_mem[0] = datasize / 8; | |
3608 | record_buf_mem[1] = address; | |
3609 | record_buf_mem[2] = datasize / 8; | |
3610 | record_buf_mem[3] = address + (datasize / 8); | |
3611 | aarch64_insn_r->mem_rec_count = 2; | |
3612 | } | |
3613 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
3614 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3615 | } | |
3616 | /* Load/store register (unsigned immediate) instructions. */ | |
3617 | else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03) | |
3618 | { | |
3619 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3620 | if (!(opc >> 1)) | |
33877125 YQ |
3621 | { |
3622 | if (opc & 0x01) | |
3623 | ld_flag = 0x01; | |
3624 | else | |
3625 | ld_flag = 0x0; | |
3626 | } | |
99afc88b | 3627 | else |
33877125 | 3628 | { |
1e2b521d YQ |
3629 | if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2) |
3630 | { | |
3631 | /* PRFM (immediate) */ | |
3632 | return AARCH64_RECORD_SUCCESS; | |
3633 | } | |
3634 | else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2) | |
3635 | { | |
3636 | /* LDRSW (immediate) */ | |
3637 | ld_flag = 0x1; | |
3638 | } | |
33877125 | 3639 | else |
1e2b521d YQ |
3640 | { |
3641 | if (opc & 0x01) | |
3642 | ld_flag = 0x01; | |
3643 | else | |
3644 | ld_flag = 0x0; | |
3645 | } | |
33877125 | 3646 | } |
99afc88b OJ |
3647 | |
3648 | if (record_debug) | |
3649 | { | |
b277c936 PL |
3650 | debug_printf ("Process record: load/store (unsigned immediate):" |
3651 | " size %x V %d opc %x\n", size_bits, vector_flag, | |
3652 | opc); | |
99afc88b OJ |
3653 | } |
3654 | ||
3655 | if (!ld_flag) | |
3656 | { | |
3657 | offset = bits (aarch64_insn_r->aarch64_insn, 10, 21); | |
3658 | datasize = 8 << size_bits; | |
3659 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3660 | &address); | |
3661 | offset = offset << size_bits; | |
3662 | address = address + offset; | |
3663 | ||
3664 | record_buf_mem[0] = datasize >> 3; | |
3665 | record_buf_mem[1] = address; | |
3666 | aarch64_insn_r->mem_rec_count = 1; | |
3667 | } | |
3668 | else | |
3669 | { | |
3670 | if (vector_flag) | |
3671 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3672 | else | |
3673 | record_buf[0] = reg_rt; | |
3674 | aarch64_insn_r->reg_rec_count = 1; | |
3675 | } | |
3676 | } | |
3677 | /* Load/store register (register offset) instructions. */ | |
5d98d3cd YQ |
3678 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3679 | && insn_bits10_11 == 0x02 && insn_bit21) | |
99afc88b OJ |
3680 | { |
3681 | if (record_debug) | |
b277c936 | 3682 | debug_printf ("Process record: load/store (register offset)\n"); |
99afc88b OJ |
3683 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); |
3684 | if (!(opc >> 1)) | |
3685 | if (opc & 0x01) | |
3686 | ld_flag = 0x01; | |
3687 | else | |
3688 | ld_flag = 0x0; | |
3689 | else | |
3690 | if (size_bits != 0x03) | |
3691 | ld_flag = 0x01; | |
3692 | else | |
3693 | return AARCH64_RECORD_UNKNOWN; | |
3694 | ||
3695 | if (!ld_flag) | |
3696 | { | |
d9436c7c PA |
3697 | ULONGEST reg_rm_val; |
3698 | ||
99afc88b OJ |
3699 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, |
3700 | bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val); | |
3701 | if (bit (aarch64_insn_r->aarch64_insn, 12)) | |
3702 | offset = reg_rm_val << size_bits; | |
3703 | else | |
3704 | offset = reg_rm_val; | |
3705 | datasize = 8 << size_bits; | |
3706 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3707 | &address); | |
3708 | address = address + offset; | |
3709 | record_buf_mem[0] = datasize >> 3; | |
3710 | record_buf_mem[1] = address; | |
3711 | aarch64_insn_r->mem_rec_count = 1; | |
3712 | } | |
3713 | else | |
3714 | { | |
3715 | if (vector_flag) | |
3716 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3717 | else | |
3718 | record_buf[0] = reg_rt; | |
3719 | aarch64_insn_r->reg_rec_count = 1; | |
3720 | } | |
3721 | } | |
3722 | /* Load/store register (immediate and unprivileged) instructions. */ | |
5d98d3cd YQ |
3723 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
3724 | && !insn_bit21) | |
99afc88b OJ |
3725 | { |
3726 | if (record_debug) | |
3727 | { | |
b277c936 PL |
3728 | debug_printf ("Process record: load/store " |
3729 | "(immediate and unprivileged)\n"); | |
99afc88b OJ |
3730 | } |
3731 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3732 | if (!(opc >> 1)) | |
3733 | if (opc & 0x01) | |
3734 | ld_flag = 0x01; | |
3735 | else | |
3736 | ld_flag = 0x0; | |
3737 | else | |
3738 | if (size_bits != 0x03) | |
3739 | ld_flag = 0x01; | |
3740 | else | |
3741 | return AARCH64_RECORD_UNKNOWN; | |
3742 | ||
3743 | if (!ld_flag) | |
3744 | { | |
3745 | uint16_t imm9_off; | |
3746 | imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20); | |
3747 | offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off; | |
3748 | datasize = 8 << size_bits; | |
3749 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
3750 | &address); | |
3751 | if (insn_bits10_11 != 0x01) | |
3752 | { | |
3753 | if (imm9_off & 0x0100) | |
3754 | address = address - offset; | |
3755 | else | |
3756 | address = address + offset; | |
3757 | } | |
3758 | record_buf_mem[0] = datasize >> 3; | |
3759 | record_buf_mem[1] = address; | |
3760 | aarch64_insn_r->mem_rec_count = 1; | |
3761 | } | |
3762 | else | |
3763 | { | |
3764 | if (vector_flag) | |
3765 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
3766 | else | |
3767 | record_buf[0] = reg_rt; | |
3768 | aarch64_insn_r->reg_rec_count = 1; | |
3769 | } | |
3770 | if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) | |
3771 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; | |
3772 | } | |
3773 | /* Advanced SIMD load/store instructions. */ | |
3774 | else | |
3775 | return aarch64_record_asimd_load_store (aarch64_insn_r); | |
3776 | ||
3777 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
3778 | record_buf_mem); | |
3779 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3780 | record_buf); | |
3781 | return AARCH64_RECORD_SUCCESS; | |
3782 | } | |
3783 | ||
3784 | /* Record handler for data processing SIMD and floating point instructions. */ | |
3785 | ||
3786 | static unsigned int | |
3787 | aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) | |
3788 | { | |
3789 | uint8_t insn_bit21, opcode, rmode, reg_rd; | |
3790 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; | |
3791 | uint8_t insn_bits11_14; | |
3792 | uint32_t record_buf[2]; | |
3793 | ||
3794 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3795 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3796 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
3797 | insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3798 | insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); | |
3799 | opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); | |
3800 | rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); | |
3801 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3802 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
3803 | ||
3804 | if (record_debug) | |
b277c936 | 3805 | debug_printf ("Process record: data processing SIMD/FP: "); |
99afc88b OJ |
3806 | |
3807 | if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) | |
3808 | { | |
3809 | /* Floating point - fixed point conversion instructions. */ | |
3810 | if (!insn_bit21) | |
3811 | { | |
3812 | if (record_debug) | |
b277c936 | 3813 | debug_printf ("FP - fixed point conversion"); |
99afc88b OJ |
3814 | |
3815 | if ((opcode >> 1) == 0x0 && rmode == 0x03) | |
3816 | record_buf[0] = reg_rd; | |
3817 | else | |
3818 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3819 | } | |
3820 | /* Floating point - conditional compare instructions. */ | |
3821 | else if (insn_bits10_11 == 0x01) | |
3822 | { | |
3823 | if (record_debug) | |
b277c936 | 3824 | debug_printf ("FP - conditional compare"); |
99afc88b OJ |
3825 | |
3826 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3827 | } | |
3828 | /* Floating point - data processing (2-source) and | |
3829 | conditional select instructions. */ | |
3830 | else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) | |
3831 | { | |
3832 | if (record_debug) | |
b277c936 | 3833 | debug_printf ("FP - DP (2-source)"); |
99afc88b OJ |
3834 | |
3835 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3836 | } | |
3837 | else if (insn_bits10_11 == 0x00) | |
3838 | { | |
3839 | /* Floating point - immediate instructions. */ | |
3840 | if ((insn_bits12_15 & 0x01) == 0x01 | |
3841 | || (insn_bits12_15 & 0x07) == 0x04) | |
3842 | { | |
3843 | if (record_debug) | |
b277c936 | 3844 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3845 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; |
3846 | } | |
3847 | /* Floating point - compare instructions. */ | |
3848 | else if ((insn_bits12_15 & 0x03) == 0x02) | |
3849 | { | |
3850 | if (record_debug) | |
b277c936 | 3851 | debug_printf ("FP - immediate"); |
99afc88b OJ |
3852 | record_buf[0] = AARCH64_CPSR_REGNUM; |
3853 | } | |
3854 | /* Floating point - integer conversions instructions. */ | |
f62fce35 | 3855 | else if (insn_bits12_15 == 0x00) |
99afc88b OJ |
3856 | { |
3857 | /* Convert float to integer instruction. */ | |
3858 | if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) | |
3859 | { | |
3860 | if (record_debug) | |
b277c936 | 3861 | debug_printf ("float to int conversion"); |
99afc88b OJ |
3862 | |
3863 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3864 | } | |
3865 | /* Convert integer to float instruction. */ | |
3866 | else if ((opcode >> 1) == 0x01 && !rmode) | |
3867 | { | |
3868 | if (record_debug) | |
b277c936 | 3869 | debug_printf ("int to float conversion"); |
99afc88b OJ |
3870 | |
3871 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3872 | } | |
3873 | /* Move float to integer instruction. */ | |
3874 | else if ((opcode >> 1) == 0x03) | |
3875 | { | |
3876 | if (record_debug) | |
b277c936 | 3877 | debug_printf ("move float to int"); |
99afc88b OJ |
3878 | |
3879 | if (!(opcode & 0x01)) | |
3880 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3881 | else | |
3882 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3883 | } | |
f62fce35 YQ |
3884 | else |
3885 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 3886 | } |
f62fce35 YQ |
3887 | else |
3888 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b | 3889 | } |
f62fce35 YQ |
3890 | else |
3891 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
3892 | } |
3893 | else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) | |
3894 | { | |
3895 | if (record_debug) | |
b277c936 | 3896 | debug_printf ("SIMD copy"); |
99afc88b OJ |
3897 | |
3898 | /* Advanced SIMD copy instructions. */ | |
3899 | if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3900 | && !bit (aarch64_insn_r->aarch64_insn, 15) | |
3901 | && bit (aarch64_insn_r->aarch64_insn, 10)) | |
3902 | { | |
3903 | if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) | |
3904 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
3905 | else | |
3906 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3907 | } | |
3908 | else | |
3909 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3910 | } | |
3911 | /* All remaining floating point or advanced SIMD instructions. */ | |
3912 | else | |
3913 | { | |
3914 | if (record_debug) | |
b277c936 | 3915 | debug_printf ("all remain"); |
99afc88b OJ |
3916 | |
3917 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
3918 | } | |
3919 | ||
3920 | if (record_debug) | |
b277c936 | 3921 | debug_printf ("\n"); |
99afc88b OJ |
3922 | |
3923 | aarch64_insn_r->reg_rec_count++; | |
3924 | gdb_assert (aarch64_insn_r->reg_rec_count == 1); | |
3925 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3926 | record_buf); | |
3927 | return AARCH64_RECORD_SUCCESS; | |
3928 | } | |
3929 | ||
3930 | /* Decodes insns type and invokes its record handler. */ | |
3931 | ||
3932 | static unsigned int | |
3933 | aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r) | |
3934 | { | |
3935 | uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; | |
3936 | ||
3937 | ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25); | |
3938 | ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26); | |
3939 | ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27); | |
3940 | ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28); | |
3941 | ||
3942 | /* Data processing - immediate instructions. */ | |
3943 | if (!ins_bit26 && !ins_bit27 && ins_bit28) | |
3944 | return aarch64_record_data_proc_imm (aarch64_insn_r); | |
3945 | ||
3946 | /* Branch, exception generation and system instructions. */ | |
3947 | if (ins_bit26 && !ins_bit27 && ins_bit28) | |
3948 | return aarch64_record_branch_except_sys (aarch64_insn_r); | |
3949 | ||
3950 | /* Load and store instructions. */ | |
3951 | if (!ins_bit25 && ins_bit27) | |
3952 | return aarch64_record_load_store (aarch64_insn_r); | |
3953 | ||
3954 | /* Data processing - register instructions. */ | |
3955 | if (ins_bit25 && !ins_bit26 && ins_bit27) | |
3956 | return aarch64_record_data_proc_reg (aarch64_insn_r); | |
3957 | ||
3958 | /* Data processing - SIMD and floating point instructions. */ | |
3959 | if (ins_bit25 && ins_bit26 && ins_bit27) | |
3960 | return aarch64_record_data_proc_simd_fp (aarch64_insn_r); | |
3961 | ||
3962 | return AARCH64_RECORD_UNSUPPORTED; | |
3963 | } | |
3964 | ||
3965 | /* Cleans up local record registers and memory allocations. */ | |
3966 | ||
3967 | static void | |
3968 | deallocate_reg_mem (insn_decode_record *record) | |
3969 | { | |
3970 | xfree (record->aarch64_regs); | |
3971 | xfree (record->aarch64_mems); | |
3972 | } | |
3973 | ||
1e2b521d YQ |
3974 | #if GDB_SELF_TEST |
3975 | namespace selftests { | |
3976 | ||
3977 | static void | |
3978 | aarch64_process_record_test (void) | |
3979 | { | |
3980 | struct gdbarch_info info; | |
3981 | uint32_t ret; | |
3982 | ||
3983 | gdbarch_info_init (&info); | |
3984 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); | |
3985 | ||
3986 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
3987 | SELF_CHECK (gdbarch != NULL); | |
3988 | ||
3989 | insn_decode_record aarch64_record; | |
3990 | ||
3991 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
3992 | aarch64_record.regcache = NULL; | |
3993 | aarch64_record.this_addr = 0; | |
3994 | aarch64_record.gdbarch = gdbarch; | |
3995 | ||
3996 | /* 20 00 80 f9 prfm pldl1keep, [x1] */ | |
3997 | aarch64_record.aarch64_insn = 0xf9800020; | |
3998 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
3999 | SELF_CHECK (ret == AARCH64_RECORD_SUCCESS); | |
4000 | SELF_CHECK (aarch64_record.reg_rec_count == 0); | |
4001 | SELF_CHECK (aarch64_record.mem_rec_count == 0); | |
4002 | ||
4003 | deallocate_reg_mem (&aarch64_record); | |
4004 | } | |
4005 | ||
4006 | } // namespace selftests | |
4007 | #endif /* GDB_SELF_TEST */ | |
4008 | ||
99afc88b OJ |
4009 | /* Parse the current instruction and record the values of the registers and |
4010 | memory that will be changed in current instruction to record_arch_list | |
4011 | return -1 if something is wrong. */ | |
4012 | ||
4013 | int | |
4014 | aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
4015 | CORE_ADDR insn_addr) | |
4016 | { | |
4017 | uint32_t rec_no = 0; | |
4018 | uint8_t insn_size = 4; | |
4019 | uint32_t ret = 0; | |
99afc88b OJ |
4020 | gdb_byte buf[insn_size]; |
4021 | insn_decode_record aarch64_record; | |
4022 | ||
4023 | memset (&buf[0], 0, insn_size); | |
4024 | memset (&aarch64_record, 0, sizeof (insn_decode_record)); | |
4025 | target_read_memory (insn_addr, &buf[0], insn_size); | |
4026 | aarch64_record.aarch64_insn | |
4027 | = (uint32_t) extract_unsigned_integer (&buf[0], | |
4028 | insn_size, | |
4029 | gdbarch_byte_order (gdbarch)); | |
4030 | aarch64_record.regcache = regcache; | |
4031 | aarch64_record.this_addr = insn_addr; | |
4032 | aarch64_record.gdbarch = gdbarch; | |
4033 | ||
4034 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4035 | if (ret == AARCH64_RECORD_UNSUPPORTED) | |
4036 | { | |
4037 | printf_unfiltered (_("Process record does not support instruction " | |
4038 | "0x%0x at address %s.\n"), | |
4039 | aarch64_record.aarch64_insn, | |
4040 | paddress (gdbarch, insn_addr)); | |
4041 | ret = -1; | |
4042 | } | |
4043 | ||
4044 | if (0 == ret) | |
4045 | { | |
4046 | /* Record registers. */ | |
4047 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4048 | AARCH64_PC_REGNUM); | |
4049 | /* Always record register CPSR. */ | |
4050 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4051 | AARCH64_CPSR_REGNUM); | |
4052 | if (aarch64_record.aarch64_regs) | |
4053 | for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++) | |
4054 | if (record_full_arch_list_add_reg (aarch64_record.regcache, | |
4055 | aarch64_record.aarch64_regs[rec_no])) | |
4056 | ret = -1; | |
4057 | ||
4058 | /* Record memories. */ | |
4059 | if (aarch64_record.aarch64_mems) | |
4060 | for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++) | |
4061 | if (record_full_arch_list_add_mem | |
4062 | ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr, | |
4063 | aarch64_record.aarch64_mems[rec_no].len)) | |
4064 | ret = -1; | |
4065 | ||
4066 | if (record_full_arch_list_add_end ()) | |
4067 | ret = -1; | |
4068 | } | |
4069 | ||
4070 | deallocate_reg_mem (&aarch64_record); | |
4071 | return ret; | |
4072 | } |