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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
32d0add0 | 3 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
07b287a0 MS |
27 | #include "dis-asm.h" |
28 | #include "regcache.h" | |
29 | #include "reggroups.h" | |
30 | #include "doublest.h" | |
31 | #include "value.h" | |
32 | #include "arch-utils.h" | |
33 | #include "osabi.h" | |
34 | #include "frame-unwind.h" | |
35 | #include "frame-base.h" | |
36 | #include "trad-frame.h" | |
37 | #include "objfiles.h" | |
38 | #include "dwarf2-frame.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "prologue-value.h" | |
41 | #include "target-descriptions.h" | |
42 | #include "user-regs.h" | |
43 | #include "language.h" | |
44 | #include "infcall.h" | |
45 | ||
46 | #include "aarch64-tdep.h" | |
47 | ||
48 | #include "elf-bfd.h" | |
49 | #include "elf/aarch64.h" | |
50 | ||
07b287a0 MS |
51 | #include "vec.h" |
52 | ||
53 | #include "features/aarch64.c" | |
07b287a0 MS |
54 | |
55 | /* Pseudo register base numbers. */ | |
56 | #define AARCH64_Q0_REGNUM 0 | |
57 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32) | |
58 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) | |
59 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
60 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
61 | ||
62 | /* The standard register names, and all the valid aliases for them. */ | |
63 | static const struct | |
64 | { | |
65 | const char *const name; | |
66 | int regnum; | |
67 | } aarch64_register_aliases[] = | |
68 | { | |
69 | /* 64-bit register names. */ | |
70 | {"fp", AARCH64_FP_REGNUM}, | |
71 | {"lr", AARCH64_LR_REGNUM}, | |
72 | {"sp", AARCH64_SP_REGNUM}, | |
73 | ||
74 | /* 32-bit register names. */ | |
75 | {"w0", AARCH64_X0_REGNUM + 0}, | |
76 | {"w1", AARCH64_X0_REGNUM + 1}, | |
77 | {"w2", AARCH64_X0_REGNUM + 2}, | |
78 | {"w3", AARCH64_X0_REGNUM + 3}, | |
79 | {"w4", AARCH64_X0_REGNUM + 4}, | |
80 | {"w5", AARCH64_X0_REGNUM + 5}, | |
81 | {"w6", AARCH64_X0_REGNUM + 6}, | |
82 | {"w7", AARCH64_X0_REGNUM + 7}, | |
83 | {"w8", AARCH64_X0_REGNUM + 8}, | |
84 | {"w9", AARCH64_X0_REGNUM + 9}, | |
85 | {"w10", AARCH64_X0_REGNUM + 10}, | |
86 | {"w11", AARCH64_X0_REGNUM + 11}, | |
87 | {"w12", AARCH64_X0_REGNUM + 12}, | |
88 | {"w13", AARCH64_X0_REGNUM + 13}, | |
89 | {"w14", AARCH64_X0_REGNUM + 14}, | |
90 | {"w15", AARCH64_X0_REGNUM + 15}, | |
91 | {"w16", AARCH64_X0_REGNUM + 16}, | |
92 | {"w17", AARCH64_X0_REGNUM + 17}, | |
93 | {"w18", AARCH64_X0_REGNUM + 18}, | |
94 | {"w19", AARCH64_X0_REGNUM + 19}, | |
95 | {"w20", AARCH64_X0_REGNUM + 20}, | |
96 | {"w21", AARCH64_X0_REGNUM + 21}, | |
97 | {"w22", AARCH64_X0_REGNUM + 22}, | |
98 | {"w23", AARCH64_X0_REGNUM + 23}, | |
99 | {"w24", AARCH64_X0_REGNUM + 24}, | |
100 | {"w25", AARCH64_X0_REGNUM + 25}, | |
101 | {"w26", AARCH64_X0_REGNUM + 26}, | |
102 | {"w27", AARCH64_X0_REGNUM + 27}, | |
103 | {"w28", AARCH64_X0_REGNUM + 28}, | |
104 | {"w29", AARCH64_X0_REGNUM + 29}, | |
105 | {"w30", AARCH64_X0_REGNUM + 30}, | |
106 | ||
107 | /* specials */ | |
108 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
109 | {"ip1", AARCH64_X0_REGNUM + 17} | |
110 | }; | |
111 | ||
112 | /* The required core 'R' registers. */ | |
113 | static const char *const aarch64_r_register_names[] = | |
114 | { | |
115 | /* These registers must appear in consecutive RAW register number | |
116 | order and they must begin with AARCH64_X0_REGNUM! */ | |
117 | "x0", "x1", "x2", "x3", | |
118 | "x4", "x5", "x6", "x7", | |
119 | "x8", "x9", "x10", "x11", | |
120 | "x12", "x13", "x14", "x15", | |
121 | "x16", "x17", "x18", "x19", | |
122 | "x20", "x21", "x22", "x23", | |
123 | "x24", "x25", "x26", "x27", | |
124 | "x28", "x29", "x30", "sp", | |
125 | "pc", "cpsr" | |
126 | }; | |
127 | ||
128 | /* The FP/SIMD 'V' registers. */ | |
129 | static const char *const aarch64_v_register_names[] = | |
130 | { | |
131 | /* These registers must appear in consecutive RAW register number | |
132 | order and they must begin with AARCH64_V0_REGNUM! */ | |
133 | "v0", "v1", "v2", "v3", | |
134 | "v4", "v5", "v6", "v7", | |
135 | "v8", "v9", "v10", "v11", | |
136 | "v12", "v13", "v14", "v15", | |
137 | "v16", "v17", "v18", "v19", | |
138 | "v20", "v21", "v22", "v23", | |
139 | "v24", "v25", "v26", "v27", | |
140 | "v28", "v29", "v30", "v31", | |
141 | "fpsr", | |
142 | "fpcr" | |
143 | }; | |
144 | ||
145 | /* AArch64 prologue cache structure. */ | |
146 | struct aarch64_prologue_cache | |
147 | { | |
148 | /* The stack pointer at the time this frame was created; i.e. the | |
149 | caller's stack pointer when this function was called. It is used | |
150 | to identify this frame. */ | |
151 | CORE_ADDR prev_sp; | |
152 | ||
153 | /* The frame base for this frame is just prev_sp - frame size. | |
154 | FRAMESIZE is the distance from the frame pointer to the | |
155 | initial stack pointer. */ | |
156 | int framesize; | |
157 | ||
158 | /* The register used to hold the frame pointer for this frame. */ | |
159 | int framereg; | |
160 | ||
161 | /* Saved register offsets. */ | |
162 | struct trad_frame_saved_reg *saved_regs; | |
163 | }; | |
164 | ||
165 | /* Toggle this file's internal debugging dump. */ | |
166 | static int aarch64_debug; | |
167 | ||
168 | static void | |
169 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
170 | struct cmd_list_element *c, const char *value) | |
171 | { | |
172 | fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value); | |
173 | } | |
174 | ||
175 | /* Extract a signed value from a bit field within an instruction | |
176 | encoding. | |
177 | ||
178 | INSN is the instruction opcode. | |
179 | ||
180 | WIDTH specifies the width of the bit field to extract (in bits). | |
181 | ||
182 | OFFSET specifies the least significant bit of the field where bits | |
183 | are numbered zero counting from least to most significant. */ | |
184 | ||
185 | static int32_t | |
186 | extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset) | |
187 | { | |
188 | unsigned shift_l = sizeof (int32_t) * 8 - (offset + width); | |
189 | unsigned shift_r = sizeof (int32_t) * 8 - width; | |
190 | ||
191 | return ((int32_t) insn << shift_l) >> shift_r; | |
192 | } | |
193 | ||
194 | /* Determine if specified bits within an instruction opcode matches a | |
195 | specific pattern. | |
196 | ||
197 | INSN is the instruction opcode. | |
198 | ||
199 | MASK specifies the bits within the opcode that are to be tested | |
200 | agsinst for a match with PATTERN. */ | |
201 | ||
202 | static int | |
203 | decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern) | |
204 | { | |
205 | return (insn & mask) == pattern; | |
206 | } | |
207 | ||
208 | /* Decode an opcode if it represents an immediate ADD or SUB instruction. | |
209 | ||
210 | ADDR specifies the address of the opcode. | |
211 | INSN specifies the opcode to test. | |
212 | RD receives the 'rd' field from the decoded instruction. | |
213 | RN receives the 'rn' field from the decoded instruction. | |
214 | ||
215 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
216 | static int | |
217 | decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn, | |
218 | int32_t *imm) | |
219 | { | |
220 | if ((insn & 0x9f000000) == 0x91000000) | |
221 | { | |
222 | unsigned shift; | |
223 | unsigned op_is_sub; | |
224 | ||
225 | *rd = (insn >> 0) & 0x1f; | |
226 | *rn = (insn >> 5) & 0x1f; | |
227 | *imm = (insn >> 10) & 0xfff; | |
228 | shift = (insn >> 22) & 0x3; | |
229 | op_is_sub = (insn >> 30) & 0x1; | |
230 | ||
231 | switch (shift) | |
232 | { | |
233 | case 0: | |
234 | break; | |
235 | case 1: | |
236 | *imm <<= 12; | |
237 | break; | |
238 | default: | |
239 | /* UNDEFINED */ | |
240 | return 0; | |
241 | } | |
242 | ||
243 | if (op_is_sub) | |
244 | *imm = -*imm; | |
245 | ||
246 | if (aarch64_debug) | |
247 | fprintf_unfiltered (gdb_stdlog, | |
248 | "decode: 0x%s 0x%x add x%u, x%u, #%d\n", | |
249 | core_addr_to_string_nz (addr), insn, *rd, *rn, | |
250 | *imm); | |
251 | return 1; | |
252 | } | |
253 | return 0; | |
254 | } | |
255 | ||
256 | /* Decode an opcode if it represents an ADRP instruction. | |
257 | ||
258 | ADDR specifies the address of the opcode. | |
259 | INSN specifies the opcode to test. | |
260 | RD receives the 'rd' field from the decoded instruction. | |
261 | ||
262 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
263 | ||
264 | static int | |
265 | decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd) | |
266 | { | |
267 | if (decode_masked_match (insn, 0x9f000000, 0x90000000)) | |
268 | { | |
269 | *rd = (insn >> 0) & 0x1f; | |
270 | ||
271 | if (aarch64_debug) | |
272 | fprintf_unfiltered (gdb_stdlog, | |
273 | "decode: 0x%s 0x%x adrp x%u, #?\n", | |
274 | core_addr_to_string_nz (addr), insn, *rd); | |
275 | return 1; | |
276 | } | |
277 | return 0; | |
278 | } | |
279 | ||
280 | /* Decode an opcode if it represents an branch immediate or branch | |
281 | and link immediate instruction. | |
282 | ||
283 | ADDR specifies the address of the opcode. | |
284 | INSN specifies the opcode to test. | |
285 | LINK receives the 'link' bit from the decoded instruction. | |
286 | OFFSET receives the immediate offset from the decoded instruction. | |
287 | ||
288 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
289 | ||
290 | static int | |
291 | decode_b (CORE_ADDR addr, uint32_t insn, unsigned *link, int32_t *offset) | |
292 | { | |
293 | /* b 0001 01ii iiii iiii iiii iiii iiii iiii */ | |
294 | /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */ | |
295 | if (decode_masked_match (insn, 0x7c000000, 0x14000000)) | |
296 | { | |
297 | *link = insn >> 31; | |
298 | *offset = extract_signed_bitfield (insn, 26, 0) << 2; | |
299 | ||
300 | if (aarch64_debug) | |
301 | fprintf_unfiltered (gdb_stdlog, | |
302 | "decode: 0x%s 0x%x %s 0x%s\n", | |
303 | core_addr_to_string_nz (addr), insn, | |
304 | *link ? "bl" : "b", | |
305 | core_addr_to_string_nz (addr + *offset)); | |
306 | ||
307 | return 1; | |
308 | } | |
309 | return 0; | |
310 | } | |
311 | ||
312 | /* Decode an opcode if it represents a conditional branch instruction. | |
313 | ||
314 | ADDR specifies the address of the opcode. | |
315 | INSN specifies the opcode to test. | |
316 | COND receives the branch condition field from the decoded | |
317 | instruction. | |
318 | OFFSET receives the immediate offset from the decoded instruction. | |
319 | ||
320 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
321 | ||
322 | static int | |
323 | decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset) | |
324 | { | |
325 | if (decode_masked_match (insn, 0xfe000000, 0x54000000)) | |
326 | { | |
327 | *cond = (insn >> 0) & 0xf; | |
328 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
329 | ||
330 | if (aarch64_debug) | |
331 | fprintf_unfiltered (gdb_stdlog, | |
332 | "decode: 0x%s 0x%x b<%u> 0x%s\n", | |
333 | core_addr_to_string_nz (addr), insn, *cond, | |
334 | core_addr_to_string_nz (addr + *offset)); | |
335 | return 1; | |
336 | } | |
337 | return 0; | |
338 | } | |
339 | ||
340 | /* Decode an opcode if it represents a branch via register instruction. | |
341 | ||
342 | ADDR specifies the address of the opcode. | |
343 | INSN specifies the opcode to test. | |
344 | LINK receives the 'link' bit from the decoded instruction. | |
345 | RN receives the 'rn' field from the decoded instruction. | |
346 | ||
347 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
348 | ||
349 | static int | |
350 | decode_br (CORE_ADDR addr, uint32_t insn, unsigned *link, unsigned *rn) | |
351 | { | |
352 | /* 8 4 0 6 2 8 4 0 */ | |
353 | /* blr 110101100011111100000000000rrrrr */ | |
354 | /* br 110101100001111100000000000rrrrr */ | |
355 | if (decode_masked_match (insn, 0xffdffc1f, 0xd61f0000)) | |
356 | { | |
357 | *link = (insn >> 21) & 1; | |
358 | *rn = (insn >> 5) & 0x1f; | |
359 | ||
360 | if (aarch64_debug) | |
361 | fprintf_unfiltered (gdb_stdlog, | |
362 | "decode: 0x%s 0x%x %s 0x%x\n", | |
363 | core_addr_to_string_nz (addr), insn, | |
364 | *link ? "blr" : "br", *rn); | |
365 | ||
366 | return 1; | |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
371 | /* Decode an opcode if it represents a CBZ or CBNZ instruction. | |
372 | ||
373 | ADDR specifies the address of the opcode. | |
374 | INSN specifies the opcode to test. | |
375 | IS64 receives the 'sf' field from the decoded instruction. | |
376 | OP receives the 'op' field from the decoded instruction. | |
377 | RN receives the 'rn' field from the decoded instruction. | |
378 | OFFSET receives the 'imm19' field from the decoded instruction. | |
379 | ||
380 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
381 | ||
382 | static int | |
383 | decode_cb (CORE_ADDR addr, | |
384 | uint32_t insn, int *is64, unsigned *op, unsigned *rn, | |
385 | int32_t *offset) | |
386 | { | |
387 | if (decode_masked_match (insn, 0x7e000000, 0x34000000)) | |
388 | { | |
389 | /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
390 | /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
391 | ||
392 | *rn = (insn >> 0) & 0x1f; | |
393 | *is64 = (insn >> 31) & 0x1; | |
394 | *op = (insn >> 24) & 0x1; | |
395 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
396 | ||
397 | if (aarch64_debug) | |
398 | fprintf_unfiltered (gdb_stdlog, | |
399 | "decode: 0x%s 0x%x %s 0x%s\n", | |
400 | core_addr_to_string_nz (addr), insn, | |
401 | *op ? "cbnz" : "cbz", | |
402 | core_addr_to_string_nz (addr + *offset)); | |
403 | return 1; | |
404 | } | |
405 | return 0; | |
406 | } | |
407 | ||
408 | /* Decode an opcode if it represents a ERET instruction. | |
409 | ||
410 | ADDR specifies the address of the opcode. | |
411 | INSN specifies the opcode to test. | |
412 | ||
413 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
414 | ||
415 | static int | |
416 | decode_eret (CORE_ADDR addr, uint32_t insn) | |
417 | { | |
418 | /* eret 1101 0110 1001 1111 0000 0011 1110 0000 */ | |
419 | if (insn == 0xd69f03e0) | |
420 | { | |
421 | if (aarch64_debug) | |
422 | fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n", | |
423 | core_addr_to_string_nz (addr), insn); | |
424 | return 1; | |
425 | } | |
426 | return 0; | |
427 | } | |
428 | ||
429 | /* Decode an opcode if it represents a MOVZ instruction. | |
430 | ||
431 | ADDR specifies the address of the opcode. | |
432 | INSN specifies the opcode to test. | |
433 | RD receives the 'rd' field from the decoded instruction. | |
434 | ||
435 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
436 | ||
437 | static int | |
438 | decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd) | |
439 | { | |
440 | if (decode_masked_match (insn, 0xff800000, 0x52800000)) | |
441 | { | |
442 | *rd = (insn >> 0) & 0x1f; | |
443 | ||
444 | if (aarch64_debug) | |
445 | fprintf_unfiltered (gdb_stdlog, | |
446 | "decode: 0x%s 0x%x movz x%u, #?\n", | |
447 | core_addr_to_string_nz (addr), insn, *rd); | |
448 | return 1; | |
449 | } | |
450 | return 0; | |
451 | } | |
452 | ||
453 | /* Decode an opcode if it represents a ORR (shifted register) | |
454 | instruction. | |
455 | ||
456 | ADDR specifies the address of the opcode. | |
457 | INSN specifies the opcode to test. | |
458 | RD receives the 'rd' field from the decoded instruction. | |
459 | RN receives the 'rn' field from the decoded instruction. | |
460 | RM receives the 'rm' field from the decoded instruction. | |
461 | IMM receives the 'imm6' field from the decoded instruction. | |
462 | ||
463 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
464 | ||
465 | static int | |
466 | decode_orr_shifted_register_x (CORE_ADDR addr, | |
467 | uint32_t insn, unsigned *rd, unsigned *rn, | |
468 | unsigned *rm, int32_t *imm) | |
469 | { | |
470 | if (decode_masked_match (insn, 0xff200000, 0xaa000000)) | |
471 | { | |
472 | *rd = (insn >> 0) & 0x1f; | |
473 | *rn = (insn >> 5) & 0x1f; | |
474 | *rm = (insn >> 16) & 0x1f; | |
475 | *imm = (insn >> 10) & 0x3f; | |
476 | ||
477 | if (aarch64_debug) | |
478 | fprintf_unfiltered (gdb_stdlog, | |
479 | "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n", | |
480 | core_addr_to_string_nz (addr), insn, *rd, | |
481 | *rn, *rm, *imm); | |
482 | return 1; | |
483 | } | |
484 | return 0; | |
485 | } | |
486 | ||
487 | /* Decode an opcode if it represents a RET instruction. | |
488 | ||
489 | ADDR specifies the address of the opcode. | |
490 | INSN specifies the opcode to test. | |
491 | RN receives the 'rn' field from the decoded instruction. | |
492 | ||
493 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
494 | ||
495 | static int | |
496 | decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn) | |
497 | { | |
498 | if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000)) | |
499 | { | |
500 | *rn = (insn >> 5) & 0x1f; | |
501 | if (aarch64_debug) | |
502 | fprintf_unfiltered (gdb_stdlog, | |
503 | "decode: 0x%s 0x%x ret x%u\n", | |
504 | core_addr_to_string_nz (addr), insn, *rn); | |
505 | return 1; | |
506 | } | |
507 | return 0; | |
508 | } | |
509 | ||
510 | /* Decode an opcode if it represents the following instruction: | |
511 | STP rt, rt2, [rn, #imm] | |
512 | ||
513 | ADDR specifies the address of the opcode. | |
514 | INSN specifies the opcode to test. | |
515 | RT1 receives the 'rt' field from the decoded instruction. | |
516 | RT2 receives the 'rt2' field from the decoded instruction. | |
517 | RN receives the 'rn' field from the decoded instruction. | |
518 | IMM receives the 'imm' field from the decoded instruction. | |
519 | ||
520 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
521 | ||
522 | static int | |
523 | decode_stp_offset (CORE_ADDR addr, | |
524 | uint32_t insn, | |
525 | unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm) | |
526 | { | |
527 | if (decode_masked_match (insn, 0xffc00000, 0xa9000000)) | |
528 | { | |
529 | *rt1 = (insn >> 0) & 0x1f; | |
530 | *rn = (insn >> 5) & 0x1f; | |
531 | *rt2 = (insn >> 10) & 0x1f; | |
532 | *imm = extract_signed_bitfield (insn, 7, 15); | |
533 | *imm <<= 3; | |
534 | ||
535 | if (aarch64_debug) | |
536 | fprintf_unfiltered (gdb_stdlog, | |
537 | "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n", | |
538 | core_addr_to_string_nz (addr), insn, | |
539 | *rt1, *rt2, *rn, *imm); | |
540 | return 1; | |
541 | } | |
542 | return 0; | |
543 | } | |
544 | ||
545 | /* Decode an opcode if it represents the following instruction: | |
546 | STP rt, rt2, [rn, #imm]! | |
547 | ||
548 | ADDR specifies the address of the opcode. | |
549 | INSN specifies the opcode to test. | |
550 | RT1 receives the 'rt' field from the decoded instruction. | |
551 | RT2 receives the 'rt2' field from the decoded instruction. | |
552 | RN receives the 'rn' field from the decoded instruction. | |
553 | IMM receives the 'imm' field from the decoded instruction. | |
554 | ||
555 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
556 | ||
557 | static int | |
558 | decode_stp_offset_wb (CORE_ADDR addr, | |
559 | uint32_t insn, | |
560 | unsigned *rt1, unsigned *rt2, unsigned *rn, | |
561 | int32_t *imm) | |
562 | { | |
563 | if (decode_masked_match (insn, 0xffc00000, 0xa9800000)) | |
564 | { | |
565 | *rt1 = (insn >> 0) & 0x1f; | |
566 | *rn = (insn >> 5) & 0x1f; | |
567 | *rt2 = (insn >> 10) & 0x1f; | |
568 | *imm = extract_signed_bitfield (insn, 7, 15); | |
569 | *imm <<= 3; | |
570 | ||
571 | if (aarch64_debug) | |
572 | fprintf_unfiltered (gdb_stdlog, | |
573 | "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n", | |
574 | core_addr_to_string_nz (addr), insn, | |
575 | *rt1, *rt2, *rn, *imm); | |
576 | return 1; | |
577 | } | |
578 | return 0; | |
579 | } | |
580 | ||
581 | /* Decode an opcode if it represents the following instruction: | |
582 | STUR rt, [rn, #imm] | |
583 | ||
584 | ADDR specifies the address of the opcode. | |
585 | INSN specifies the opcode to test. | |
586 | IS64 receives size field from the decoded instruction. | |
587 | RT receives the 'rt' field from the decoded instruction. | |
588 | RN receives the 'rn' field from the decoded instruction. | |
589 | IMM receives the 'imm' field from the decoded instruction. | |
590 | ||
591 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
592 | ||
593 | static int | |
594 | decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt, | |
595 | unsigned *rn, int32_t *imm) | |
596 | { | |
597 | if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000)) | |
598 | { | |
599 | *is64 = (insn >> 30) & 1; | |
600 | *rt = (insn >> 0) & 0x1f; | |
601 | *rn = (insn >> 5) & 0x1f; | |
602 | *imm = extract_signed_bitfield (insn, 9, 12); | |
603 | ||
604 | if (aarch64_debug) | |
605 | fprintf_unfiltered (gdb_stdlog, | |
606 | "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n", | |
607 | core_addr_to_string_nz (addr), insn, | |
608 | *is64 ? 'x' : 'w', *rt, *rn, *imm); | |
609 | return 1; | |
610 | } | |
611 | return 0; | |
612 | } | |
613 | ||
614 | /* Decode an opcode if it represents a TB or TBNZ instruction. | |
615 | ||
616 | ADDR specifies the address of the opcode. | |
617 | INSN specifies the opcode to test. | |
618 | OP receives the 'op' field from the decoded instruction. | |
619 | BIT receives the bit position field from the decoded instruction. | |
620 | RT receives 'rt' field from the decoded instruction. | |
621 | IMM receives 'imm' field from the decoded instruction. | |
622 | ||
623 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
624 | ||
625 | static int | |
626 | decode_tb (CORE_ADDR addr, | |
627 | uint32_t insn, unsigned *op, unsigned *bit, unsigned *rt, | |
628 | int32_t *imm) | |
629 | { | |
630 | if (decode_masked_match (insn, 0x7e000000, 0x36000000)) | |
631 | { | |
632 | /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */ | |
633 | /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */ | |
634 | ||
635 | *rt = (insn >> 0) & 0x1f; | |
636 | *op = insn & (1 << 24); | |
637 | *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f); | |
638 | *imm = extract_signed_bitfield (insn, 14, 5) << 2; | |
639 | ||
640 | if (aarch64_debug) | |
641 | fprintf_unfiltered (gdb_stdlog, | |
642 | "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n", | |
643 | core_addr_to_string_nz (addr), insn, | |
644 | *op ? "tbnz" : "tbz", *rt, *bit, | |
645 | core_addr_to_string_nz (addr + *imm)); | |
646 | return 1; | |
647 | } | |
648 | return 0; | |
649 | } | |
650 | ||
651 | /* Analyze a prologue, looking for a recognizable stack frame | |
652 | and frame pointer. Scan until we encounter a store that could | |
653 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
654 | ||
655 | static CORE_ADDR | |
656 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
657 | CORE_ADDR start, CORE_ADDR limit, | |
658 | struct aarch64_prologue_cache *cache) | |
659 | { | |
660 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
661 | int i; | |
662 | pv_t regs[AARCH64_X_REGISTER_COUNT]; | |
663 | struct pv_area *stack; | |
664 | struct cleanup *back_to; | |
665 | ||
666 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
667 | regs[i] = pv_register (i, 0); | |
668 | stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
669 | back_to = make_cleanup_free_pv_area (stack); | |
670 | ||
671 | for (; start < limit; start += 4) | |
672 | { | |
673 | uint32_t insn; | |
674 | unsigned rd; | |
675 | unsigned rn; | |
676 | unsigned rm; | |
677 | unsigned rt; | |
678 | unsigned rt1; | |
679 | unsigned rt2; | |
680 | int op_is_sub; | |
681 | int32_t imm; | |
682 | unsigned cond; | |
96b32e50 | 683 | int is64; |
07b287a0 MS |
684 | unsigned is_link; |
685 | unsigned op; | |
686 | unsigned bit; | |
687 | int32_t offset; | |
688 | ||
689 | insn = read_memory_unsigned_integer (start, 4, byte_order_for_code); | |
690 | ||
691 | if (decode_add_sub_imm (start, insn, &rd, &rn, &imm)) | |
692 | regs[rd] = pv_add_constant (regs[rn], imm); | |
693 | else if (decode_adrp (start, insn, &rd)) | |
694 | regs[rd] = pv_unknown (); | |
695 | else if (decode_b (start, insn, &is_link, &offset)) | |
696 | { | |
697 | /* Stop analysis on branch. */ | |
698 | break; | |
699 | } | |
700 | else if (decode_bcond (start, insn, &cond, &offset)) | |
701 | { | |
702 | /* Stop analysis on branch. */ | |
703 | break; | |
704 | } | |
705 | else if (decode_br (start, insn, &is_link, &rn)) | |
706 | { | |
707 | /* Stop analysis on branch. */ | |
708 | break; | |
709 | } | |
710 | else if (decode_cb (start, insn, &is64, &op, &rn, &offset)) | |
711 | { | |
712 | /* Stop analysis on branch. */ | |
713 | break; | |
714 | } | |
715 | else if (decode_eret (start, insn)) | |
716 | { | |
717 | /* Stop analysis on branch. */ | |
718 | break; | |
719 | } | |
720 | else if (decode_movz (start, insn, &rd)) | |
721 | regs[rd] = pv_unknown (); | |
722 | else | |
723 | if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm)) | |
724 | { | |
725 | if (imm == 0 && rn == 31) | |
726 | regs[rd] = regs[rm]; | |
727 | else | |
728 | { | |
729 | if (aarch64_debug) | |
730 | fprintf_unfiltered | |
731 | (gdb_stdlog, | |
732 | "aarch64: prologue analysis gave up addr=0x%s " | |
733 | "opcode=0x%x (orr x register)\n", | |
734 | core_addr_to_string_nz (start), | |
735 | insn); | |
736 | break; | |
737 | } | |
738 | } | |
739 | else if (decode_ret (start, insn, &rn)) | |
740 | { | |
741 | /* Stop analysis on branch. */ | |
742 | break; | |
743 | } | |
744 | else if (decode_stur (start, insn, &is64, &rt, &rn, &offset)) | |
745 | { | |
746 | pv_area_store (stack, pv_add_constant (regs[rn], offset), | |
747 | is64 ? 8 : 4, regs[rt]); | |
748 | } | |
749 | else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm)) | |
750 | { | |
751 | /* If recording this store would invalidate the store area | |
752 | (perhaps because rn is not known) then we should abandon | |
753 | further prologue analysis. */ | |
754 | if (pv_area_store_would_trash (stack, | |
755 | pv_add_constant (regs[rn], imm))) | |
756 | break; | |
757 | ||
758 | if (pv_area_store_would_trash (stack, | |
759 | pv_add_constant (regs[rn], imm + 8))) | |
760 | break; | |
761 | ||
762 | pv_area_store (stack, pv_add_constant (regs[rn], imm), 8, | |
763 | regs[rt1]); | |
764 | pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8, | |
765 | regs[rt2]); | |
766 | } | |
767 | else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm)) | |
768 | { | |
769 | /* If recording this store would invalidate the store area | |
770 | (perhaps because rn is not known) then we should abandon | |
771 | further prologue analysis. */ | |
772 | if (pv_area_store_would_trash (stack, | |
14ac654f MS |
773 | pv_add_constant (regs[rn], imm))) |
774 | break; | |
775 | ||
776 | if (pv_area_store_would_trash (stack, | |
07b287a0 MS |
777 | pv_add_constant (regs[rn], imm + 8))) |
778 | break; | |
779 | ||
780 | pv_area_store (stack, pv_add_constant (regs[rn], imm), 8, | |
781 | regs[rt1]); | |
782 | pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8, | |
783 | regs[rt2]); | |
784 | regs[rn] = pv_add_constant (regs[rn], imm); | |
785 | } | |
786 | else if (decode_tb (start, insn, &op, &bit, &rn, &offset)) | |
787 | { | |
788 | /* Stop analysis on branch. */ | |
789 | break; | |
790 | } | |
791 | else | |
792 | { | |
793 | if (aarch64_debug) | |
794 | fprintf_unfiltered (gdb_stdlog, | |
795 | "aarch64: prologue analysis gave up addr=0x%s" | |
796 | " opcode=0x%x\n", | |
797 | core_addr_to_string_nz (start), insn); | |
798 | break; | |
799 | } | |
800 | } | |
801 | ||
802 | if (cache == NULL) | |
803 | { | |
804 | do_cleanups (back_to); | |
805 | return start; | |
806 | } | |
807 | ||
808 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
809 | { | |
810 | /* Frame pointer is fp. Frame size is constant. */ | |
811 | cache->framereg = AARCH64_FP_REGNUM; | |
812 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
813 | } | |
814 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
815 | { | |
816 | /* Try the stack pointer. */ | |
817 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
818 | cache->framereg = AARCH64_SP_REGNUM; | |
819 | } | |
820 | else | |
821 | { | |
822 | /* We're just out of luck. We don't know where the frame is. */ | |
823 | cache->framereg = -1; | |
824 | cache->framesize = 0; | |
825 | } | |
826 | ||
827 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
828 | { | |
829 | CORE_ADDR offset; | |
830 | ||
831 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
832 | cache->saved_regs[i].addr = offset; | |
833 | } | |
834 | ||
835 | do_cleanups (back_to); | |
836 | return start; | |
837 | } | |
838 | ||
839 | /* Implement the "skip_prologue" gdbarch method. */ | |
840 | ||
841 | static CORE_ADDR | |
842 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
843 | { | |
844 | unsigned long inst; | |
845 | CORE_ADDR skip_pc; | |
846 | CORE_ADDR func_addr, limit_pc; | |
847 | struct symtab_and_line sal; | |
848 | ||
849 | /* See if we can determine the end of the prologue via the symbol | |
850 | table. If so, then return either PC, or the PC after the | |
851 | prologue, whichever is greater. */ | |
852 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
853 | { | |
854 | CORE_ADDR post_prologue_pc | |
855 | = skip_prologue_using_sal (gdbarch, func_addr); | |
856 | ||
857 | if (post_prologue_pc != 0) | |
858 | return max (pc, post_prologue_pc); | |
859 | } | |
860 | ||
861 | /* Can't determine prologue from the symbol table, need to examine | |
862 | instructions. */ | |
863 | ||
864 | /* Find an upper limit on the function prologue using the debug | |
865 | information. If the debug information could not be used to | |
866 | provide that bound, then use an arbitrary large number as the | |
867 | upper bound. */ | |
868 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
869 | if (limit_pc == 0) | |
870 | limit_pc = pc + 128; /* Magic. */ | |
871 | ||
872 | /* Try disassembling prologue. */ | |
873 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
874 | } | |
875 | ||
876 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
877 | cache CACHE. */ | |
878 | ||
879 | static void | |
880 | aarch64_scan_prologue (struct frame_info *this_frame, | |
881 | struct aarch64_prologue_cache *cache) | |
882 | { | |
883 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
884 | CORE_ADDR prologue_start; | |
885 | CORE_ADDR prologue_end; | |
886 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
887 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
888 | ||
889 | /* Assume we do not find a frame. */ | |
890 | cache->framereg = -1; | |
891 | cache->framesize = 0; | |
892 | ||
893 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
894 | &prologue_end)) | |
895 | { | |
896 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
897 | ||
898 | if (sal.line == 0) | |
899 | { | |
900 | /* No line info so use the current PC. */ | |
901 | prologue_end = prev_pc; | |
902 | } | |
903 | else if (sal.end < prologue_end) | |
904 | { | |
905 | /* The next line begins after the function end. */ | |
906 | prologue_end = sal.end; | |
907 | } | |
908 | ||
909 | prologue_end = min (prologue_end, prev_pc); | |
910 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); | |
911 | } | |
912 | else | |
913 | { | |
914 | CORE_ADDR frame_loc; | |
915 | LONGEST saved_fp; | |
916 | LONGEST saved_lr; | |
917 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
918 | ||
919 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
920 | if (frame_loc == 0) | |
921 | return; | |
922 | ||
923 | cache->framereg = AARCH64_FP_REGNUM; | |
924 | cache->framesize = 16; | |
925 | cache->saved_regs[29].addr = 0; | |
926 | cache->saved_regs[30].addr = 8; | |
927 | } | |
928 | } | |
929 | ||
930 | /* Allocate an aarch64_prologue_cache and fill it with information | |
931 | about the prologue of *THIS_FRAME. */ | |
932 | ||
933 | static struct aarch64_prologue_cache * | |
934 | aarch64_make_prologue_cache (struct frame_info *this_frame) | |
935 | { | |
936 | struct aarch64_prologue_cache *cache; | |
937 | CORE_ADDR unwound_fp; | |
938 | int reg; | |
939 | ||
940 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
941 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
942 | ||
943 | aarch64_scan_prologue (this_frame, cache); | |
944 | ||
945 | if (cache->framereg == -1) | |
946 | return cache; | |
947 | ||
948 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
949 | if (unwound_fp == 0) | |
950 | return cache; | |
951 | ||
952 | cache->prev_sp = unwound_fp + cache->framesize; | |
953 | ||
954 | /* Calculate actual addresses of saved registers using offsets | |
955 | determined by aarch64_analyze_prologue. */ | |
956 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
957 | if (trad_frame_addr_p (cache->saved_regs, reg)) | |
958 | cache->saved_regs[reg].addr += cache->prev_sp; | |
959 | ||
960 | return cache; | |
961 | } | |
962 | ||
963 | /* Our frame ID for a normal frame is the current function's starting | |
964 | PC and the caller's SP when we were called. */ | |
965 | ||
966 | static void | |
967 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
968 | void **this_cache, struct frame_id *this_id) | |
969 | { | |
970 | struct aarch64_prologue_cache *cache; | |
971 | struct frame_id id; | |
972 | CORE_ADDR pc, func; | |
973 | ||
974 | if (*this_cache == NULL) | |
975 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
976 | cache = *this_cache; | |
977 | ||
978 | /* This is meant to halt the backtrace at "_start". */ | |
979 | pc = get_frame_pc (this_frame); | |
980 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
981 | return; | |
982 | ||
983 | /* If we've hit a wall, stop. */ | |
984 | if (cache->prev_sp == 0) | |
985 | return; | |
986 | ||
987 | func = get_frame_func (this_frame); | |
988 | id = frame_id_build (cache->prev_sp, func); | |
989 | *this_id = id; | |
990 | } | |
991 | ||
992 | /* Implement the "prev_register" frame_unwind method. */ | |
993 | ||
994 | static struct value * | |
995 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
996 | void **this_cache, int prev_regnum) | |
997 | { | |
998 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
999 | struct aarch64_prologue_cache *cache; | |
1000 | ||
1001 | if (*this_cache == NULL) | |
1002 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
1003 | cache = *this_cache; | |
1004 | ||
1005 | /* If we are asked to unwind the PC, then we need to return the LR | |
1006 | instead. The prologue may save PC, but it will point into this | |
1007 | frame's prologue, not the next frame's resume location. */ | |
1008 | if (prev_regnum == AARCH64_PC_REGNUM) | |
1009 | { | |
1010 | CORE_ADDR lr; | |
1011 | ||
1012 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1013 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); | |
1014 | } | |
1015 | ||
1016 | /* SP is generally not saved to the stack, but this frame is | |
1017 | identified by the next frame's stack pointer at the time of the | |
1018 | call. The value was already reconstructed into PREV_SP. */ | |
1019 | /* | |
1020 | +----------+ ^ | |
1021 | | saved lr | | | |
1022 | +->| saved fp |--+ | |
1023 | | | | | |
1024 | | | | <- Previous SP | |
1025 | | +----------+ | |
1026 | | | saved lr | | |
1027 | +--| saved fp |<- FP | |
1028 | | | | |
1029 | | |<- SP | |
1030 | +----------+ */ | |
1031 | if (prev_regnum == AARCH64_SP_REGNUM) | |
1032 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
1033 | cache->prev_sp); | |
1034 | ||
1035 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
1036 | prev_regnum); | |
1037 | } | |
1038 | ||
1039 | /* AArch64 prologue unwinder. */ | |
1040 | struct frame_unwind aarch64_prologue_unwind = | |
1041 | { | |
1042 | NORMAL_FRAME, | |
1043 | default_frame_unwind_stop_reason, | |
1044 | aarch64_prologue_this_id, | |
1045 | aarch64_prologue_prev_register, | |
1046 | NULL, | |
1047 | default_frame_sniffer | |
1048 | }; | |
1049 | ||
1050 | /* Allocate an aarch64_prologue_cache and fill it with information | |
1051 | about the prologue of *THIS_FRAME. */ | |
1052 | ||
1053 | static struct aarch64_prologue_cache * | |
1054 | aarch64_make_stub_cache (struct frame_info *this_frame) | |
1055 | { | |
1056 | int reg; | |
1057 | struct aarch64_prologue_cache *cache; | |
1058 | CORE_ADDR unwound_fp; | |
1059 | ||
1060 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1061 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1062 | ||
1063 | cache->prev_sp | |
1064 | = get_frame_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1065 | ||
1066 | return cache; | |
1067 | } | |
1068 | ||
1069 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1070 | ||
1071 | static void | |
1072 | aarch64_stub_this_id (struct frame_info *this_frame, | |
1073 | void **this_cache, struct frame_id *this_id) | |
1074 | { | |
1075 | struct aarch64_prologue_cache *cache; | |
1076 | ||
1077 | if (*this_cache == NULL) | |
1078 | *this_cache = aarch64_make_stub_cache (this_frame); | |
1079 | cache = *this_cache; | |
1080 | ||
1081 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); | |
1082 | } | |
1083 | ||
1084 | /* Implement the "sniffer" frame_unwind method. */ | |
1085 | ||
1086 | static int | |
1087 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
1088 | struct frame_info *this_frame, | |
1089 | void **this_prologue_cache) | |
1090 | { | |
1091 | CORE_ADDR addr_in_block; | |
1092 | gdb_byte dummy[4]; | |
1093 | ||
1094 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 1095 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
1096 | /* We also use the stub winder if the target memory is unreadable |
1097 | to avoid having the prologue unwinder trying to read it. */ | |
1098 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
1099 | return 1; | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /* AArch64 stub unwinder. */ | |
1105 | struct frame_unwind aarch64_stub_unwind = | |
1106 | { | |
1107 | NORMAL_FRAME, | |
1108 | default_frame_unwind_stop_reason, | |
1109 | aarch64_stub_this_id, | |
1110 | aarch64_prologue_prev_register, | |
1111 | NULL, | |
1112 | aarch64_stub_unwind_sniffer | |
1113 | }; | |
1114 | ||
1115 | /* Return the frame base address of *THIS_FRAME. */ | |
1116 | ||
1117 | static CORE_ADDR | |
1118 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
1119 | { | |
1120 | struct aarch64_prologue_cache *cache; | |
1121 | ||
1122 | if (*this_cache == NULL) | |
1123 | *this_cache = aarch64_make_prologue_cache (this_frame); | |
1124 | cache = *this_cache; | |
1125 | ||
1126 | return cache->prev_sp - cache->framesize; | |
1127 | } | |
1128 | ||
1129 | /* AArch64 default frame base information. */ | |
1130 | struct frame_base aarch64_normal_base = | |
1131 | { | |
1132 | &aarch64_prologue_unwind, | |
1133 | aarch64_normal_frame_base, | |
1134 | aarch64_normal_frame_base, | |
1135 | aarch64_normal_frame_base | |
1136 | }; | |
1137 | ||
1138 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that | |
1139 | dummy frame. The frame ID's base needs to match the TOS value | |
1140 | saved by save_dummy_frame_tos () and returned from | |
1141 | aarch64_push_dummy_call, and the PC needs to match the dummy | |
1142 | frame's breakpoint. */ | |
1143 | ||
1144 | static struct frame_id | |
1145 | aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1146 | { | |
1147 | return frame_id_build (get_frame_register_unsigned (this_frame, | |
1148 | AARCH64_SP_REGNUM), | |
1149 | get_frame_pc (this_frame)); | |
1150 | } | |
1151 | ||
1152 | /* Implement the "unwind_pc" gdbarch method. */ | |
1153 | ||
1154 | static CORE_ADDR | |
1155 | aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1156 | { | |
1157 | CORE_ADDR pc | |
1158 | = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM); | |
1159 | ||
1160 | return pc; | |
1161 | } | |
1162 | ||
1163 | /* Implement the "unwind_sp" gdbarch method. */ | |
1164 | ||
1165 | static CORE_ADDR | |
1166 | aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1167 | { | |
1168 | return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM); | |
1169 | } | |
1170 | ||
1171 | /* Return the value of the REGNUM register in the previous frame of | |
1172 | *THIS_FRAME. */ | |
1173 | ||
1174 | static struct value * | |
1175 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1176 | void **this_cache, int regnum) | |
1177 | { | |
1178 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1179 | CORE_ADDR lr; | |
1180 | ||
1181 | switch (regnum) | |
1182 | { | |
1183 | case AARCH64_PC_REGNUM: | |
1184 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
1185 | return frame_unwind_got_constant (this_frame, regnum, lr); | |
1186 | ||
1187 | default: | |
1188 | internal_error (__FILE__, __LINE__, | |
1189 | _("Unexpected register %d"), regnum); | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | /* Implement the "init_reg" dwarf2_frame_ops method. */ | |
1194 | ||
1195 | static void | |
1196 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1197 | struct dwarf2_frame_state_reg *reg, | |
1198 | struct frame_info *this_frame) | |
1199 | { | |
1200 | switch (regnum) | |
1201 | { | |
1202 | case AARCH64_PC_REGNUM: | |
1203 | reg->how = DWARF2_FRAME_REG_FN; | |
1204 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
1205 | break; | |
1206 | case AARCH64_SP_REGNUM: | |
1207 | reg->how = DWARF2_FRAME_REG_CFA; | |
1208 | break; | |
1209 | } | |
1210 | } | |
1211 | ||
1212 | /* When arguments must be pushed onto the stack, they go on in reverse | |
1213 | order. The code below implements a FILO (stack) to do this. */ | |
1214 | ||
1215 | typedef struct | |
1216 | { | |
1217 | /* Value to pass on stack. */ | |
1218 | const void *data; | |
1219 | ||
1220 | /* Size in bytes of value to pass on stack. */ | |
1221 | int len; | |
1222 | } stack_item_t; | |
1223 | ||
1224 | DEF_VEC_O (stack_item_t); | |
1225 | ||
1226 | /* Return the alignment (in bytes) of the given type. */ | |
1227 | ||
1228 | static int | |
1229 | aarch64_type_align (struct type *t) | |
1230 | { | |
1231 | int n; | |
1232 | int align; | |
1233 | int falign; | |
1234 | ||
1235 | t = check_typedef (t); | |
1236 | switch (TYPE_CODE (t)) | |
1237 | { | |
1238 | default: | |
1239 | /* Should never happen. */ | |
1240 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1241 | return 4; | |
1242 | ||
1243 | case TYPE_CODE_PTR: | |
1244 | case TYPE_CODE_ENUM: | |
1245 | case TYPE_CODE_INT: | |
1246 | case TYPE_CODE_FLT: | |
1247 | case TYPE_CODE_SET: | |
1248 | case TYPE_CODE_RANGE: | |
1249 | case TYPE_CODE_BITSTRING: | |
1250 | case TYPE_CODE_REF: | |
1251 | case TYPE_CODE_CHAR: | |
1252 | case TYPE_CODE_BOOL: | |
1253 | return TYPE_LENGTH (t); | |
1254 | ||
1255 | case TYPE_CODE_ARRAY: | |
1256 | case TYPE_CODE_COMPLEX: | |
1257 | return aarch64_type_align (TYPE_TARGET_TYPE (t)); | |
1258 | ||
1259 | case TYPE_CODE_STRUCT: | |
1260 | case TYPE_CODE_UNION: | |
1261 | align = 1; | |
1262 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1263 | { | |
1264 | falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n)); | |
1265 | if (falign > align) | |
1266 | align = falign; | |
1267 | } | |
1268 | return align; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* Return 1 if *TY is a homogeneous floating-point aggregate as | |
1273 | defined in the AAPCS64 ABI document; otherwise return 0. */ | |
1274 | ||
1275 | static int | |
1276 | is_hfa (struct type *ty) | |
1277 | { | |
1278 | switch (TYPE_CODE (ty)) | |
1279 | { | |
1280 | case TYPE_CODE_ARRAY: | |
1281 | { | |
1282 | struct type *target_ty = TYPE_TARGET_TYPE (ty); | |
1283 | if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4) | |
1284 | return 1; | |
1285 | break; | |
1286 | } | |
1287 | ||
1288 | case TYPE_CODE_UNION: | |
1289 | case TYPE_CODE_STRUCT: | |
1290 | { | |
1291 | if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4) | |
1292 | { | |
1293 | struct type *member0_type; | |
1294 | ||
1295 | member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0)); | |
1296 | if (TYPE_CODE (member0_type) == TYPE_CODE_FLT) | |
1297 | { | |
1298 | int i; | |
1299 | ||
1300 | for (i = 0; i < TYPE_NFIELDS (ty); i++) | |
1301 | { | |
1302 | struct type *member1_type; | |
1303 | ||
1304 | member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i)); | |
1305 | if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type) | |
1306 | || (TYPE_LENGTH (member0_type) | |
1307 | != TYPE_LENGTH (member1_type))) | |
1308 | return 0; | |
1309 | } | |
1310 | return 1; | |
1311 | } | |
1312 | } | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | default: | |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
1323 | /* AArch64 function call information structure. */ | |
1324 | struct aarch64_call_info | |
1325 | { | |
1326 | /* the current argument number. */ | |
1327 | unsigned argnum; | |
1328 | ||
1329 | /* The next general purpose register number, equivalent to NGRN as | |
1330 | described in the AArch64 Procedure Call Standard. */ | |
1331 | unsigned ngrn; | |
1332 | ||
1333 | /* The next SIMD and floating point register number, equivalent to | |
1334 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
1335 | unsigned nsrn; | |
1336 | ||
1337 | /* The next stacked argument address, equivalent to NSAA as | |
1338 | described in the AArch64 Procedure Call Standard. */ | |
1339 | unsigned nsaa; | |
1340 | ||
1341 | /* Stack item vector. */ | |
1342 | VEC(stack_item_t) *si; | |
1343 | }; | |
1344 | ||
1345 | /* Pass a value in a sequence of consecutive X registers. The caller | |
1346 | is responsbile for ensuring sufficient registers are available. */ | |
1347 | ||
1348 | static void | |
1349 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1350 | struct aarch64_call_info *info, struct type *type, | |
1351 | const bfd_byte *buf) | |
1352 | { | |
1353 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1354 | int len = TYPE_LENGTH (type); | |
1355 | enum type_code typecode = TYPE_CODE (type); | |
1356 | int regnum = AARCH64_X0_REGNUM + info->ngrn; | |
1357 | ||
1358 | info->argnum++; | |
1359 | ||
1360 | while (len > 0) | |
1361 | { | |
1362 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1363 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1364 | byte_order); | |
1365 | ||
1366 | ||
1367 | /* Adjust sub-word struct/union args when big-endian. */ | |
1368 | if (byte_order == BFD_ENDIAN_BIG | |
1369 | && partial_len < X_REGISTER_SIZE | |
1370 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1371 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1372 | ||
1373 | if (aarch64_debug) | |
1374 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
1375 | info->argnum, | |
1376 | gdbarch_register_name (gdbarch, regnum), | |
1377 | phex (regval, X_REGISTER_SIZE)); | |
1378 | regcache_cooked_write_unsigned (regcache, regnum, regval); | |
1379 | len -= partial_len; | |
1380 | buf += partial_len; | |
1381 | regnum++; | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | /* Attempt to marshall a value in a V register. Return 1 if | |
1386 | successful, or 0 if insufficient registers are available. This | |
1387 | function, unlike the equivalent pass_in_x() function does not | |
1388 | handle arguments spread across multiple registers. */ | |
1389 | ||
1390 | static int | |
1391 | pass_in_v (struct gdbarch *gdbarch, | |
1392 | struct regcache *regcache, | |
1393 | struct aarch64_call_info *info, | |
1394 | const bfd_byte *buf) | |
1395 | { | |
1396 | if (info->nsrn < 8) | |
1397 | { | |
1398 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1399 | int regnum = AARCH64_V0_REGNUM + info->nsrn; | |
1400 | ||
1401 | info->argnum++; | |
1402 | info->nsrn++; | |
1403 | ||
1404 | regcache_cooked_write (regcache, regnum, buf); | |
1405 | if (aarch64_debug) | |
1406 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s\n", | |
1407 | info->argnum, | |
1408 | gdbarch_register_name (gdbarch, regnum)); | |
1409 | return 1; | |
1410 | } | |
1411 | info->nsrn = 8; | |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | /* Marshall an argument onto the stack. */ | |
1416 | ||
1417 | static void | |
1418 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
1419 | const bfd_byte *buf) | |
1420 | { | |
1421 | int len = TYPE_LENGTH (type); | |
1422 | int align; | |
1423 | stack_item_t item; | |
1424 | ||
1425 | info->argnum++; | |
1426 | ||
1427 | align = aarch64_type_align (type); | |
1428 | ||
1429 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1430 | Natural alignment of the argument's type. */ | |
1431 | align = align_up (align, 8); | |
1432 | ||
1433 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1434 | if (align > 16) | |
1435 | align = 16; | |
1436 | ||
1437 | if (aarch64_debug) | |
1438 | fprintf_unfiltered (gdb_stdlog, "arg %d len=%d @ sp + %d\n", | |
1439 | info->argnum, len, info->nsaa); | |
1440 | ||
1441 | item.len = len; | |
1442 | item.data = buf; | |
1443 | VEC_safe_push (stack_item_t, info->si, &item); | |
1444 | ||
1445 | info->nsaa += len; | |
1446 | if (info->nsaa & (align - 1)) | |
1447 | { | |
1448 | /* Push stack alignment padding. */ | |
1449 | int pad = align - (info->nsaa & (align - 1)); | |
1450 | ||
1451 | item.len = pad; | |
1452 | item.data = buf; | |
1453 | ||
1454 | VEC_safe_push (stack_item_t, info->si, &item); | |
1455 | info->nsaa += pad; | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | /* Marshall an argument into a sequence of one or more consecutive X | |
1460 | registers or, if insufficient X registers are available then onto | |
1461 | the stack. */ | |
1462 | ||
1463 | static void | |
1464 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1465 | struct aarch64_call_info *info, struct type *type, | |
1466 | const bfd_byte *buf) | |
1467 | { | |
1468 | int len = TYPE_LENGTH (type); | |
1469 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1470 | ||
1471 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1472 | if (info->ngrn + nregs <= 8) | |
1473 | { | |
1474 | pass_in_x (gdbarch, regcache, info, type, buf); | |
1475 | info->ngrn += nregs; | |
1476 | } | |
1477 | else | |
1478 | { | |
1479 | info->ngrn = 8; | |
1480 | pass_on_stack (info, type, buf); | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | /* Pass a value in a V register, or on the stack if insufficient are | |
1485 | available. */ | |
1486 | ||
1487 | static void | |
1488 | pass_in_v_or_stack (struct gdbarch *gdbarch, | |
1489 | struct regcache *regcache, | |
1490 | struct aarch64_call_info *info, | |
1491 | struct type *type, | |
1492 | const bfd_byte *buf) | |
1493 | { | |
1494 | if (!pass_in_v (gdbarch, regcache, info, buf)) | |
1495 | pass_on_stack (info, type, buf); | |
1496 | } | |
1497 | ||
1498 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1499 | ||
1500 | static CORE_ADDR | |
1501 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1502 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1503 | int nargs, | |
1504 | struct value **args, CORE_ADDR sp, int struct_return, | |
1505 | CORE_ADDR struct_addr) | |
1506 | { | |
1507 | int nstack = 0; | |
1508 | int argnum; | |
1509 | int x_argreg; | |
1510 | int v_argreg; | |
1511 | struct aarch64_call_info info; | |
1512 | struct type *func_type; | |
1513 | struct type *return_type; | |
1514 | int lang_struct_return; | |
1515 | ||
1516 | memset (&info, 0, sizeof (info)); | |
1517 | ||
1518 | /* We need to know what the type of the called function is in order | |
1519 | to determine the number of named/anonymous arguments for the | |
1520 | actual argument placement, and the return type in order to handle | |
1521 | return value correctly. | |
1522 | ||
1523 | The generic code above us views the decision of return in memory | |
1524 | or return in registers as a two stage processes. The language | |
1525 | handler is consulted first and may decide to return in memory (eg | |
1526 | class with copy constructor returned by value), this will cause | |
1527 | the generic code to allocate space AND insert an initial leading | |
1528 | argument. | |
1529 | ||
1530 | If the language code does not decide to pass in memory then the | |
1531 | target code is consulted. | |
1532 | ||
1533 | If the language code decides to pass in memory we want to move | |
1534 | the pointer inserted as the initial argument from the argument | |
1535 | list and into X8, the conventional AArch64 struct return pointer | |
1536 | register. | |
1537 | ||
1538 | This is slightly awkward, ideally the flag "lang_struct_return" | |
1539 | would be passed to the targets implementation of push_dummy_call. | |
1540 | Rather that change the target interface we call the language code | |
1541 | directly ourselves. */ | |
1542 | ||
1543 | func_type = check_typedef (value_type (function)); | |
1544 | ||
1545 | /* Dereference function pointer types. */ | |
1546 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
1547 | func_type = TYPE_TARGET_TYPE (func_type); | |
1548 | ||
1549 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
1550 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
1551 | ||
1552 | /* If language_pass_by_reference () returned true we will have been | |
1553 | given an additional initial argument, a hidden pointer to the | |
1554 | return slot in memory. */ | |
1555 | return_type = TYPE_TARGET_TYPE (func_type); | |
1556 | lang_struct_return = language_pass_by_reference (return_type); | |
1557 | ||
1558 | /* Set the return address. For the AArch64, the return breakpoint | |
1559 | is always at BP_ADDR. */ | |
1560 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1561 | ||
1562 | /* If we were given an initial argument for the return slot because | |
1563 | lang_struct_return was true, lose it. */ | |
1564 | if (lang_struct_return) | |
1565 | { | |
1566 | args++; | |
1567 | nargs--; | |
1568 | } | |
1569 | ||
1570 | /* The struct_return pointer occupies X8. */ | |
1571 | if (struct_return || lang_struct_return) | |
1572 | { | |
1573 | if (aarch64_debug) | |
1574 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
1575 | gdbarch_register_name | |
1576 | (gdbarch, | |
1577 | AARCH64_STRUCT_RETURN_REGNUM), | |
1578 | paddress (gdbarch, struct_addr)); | |
1579 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, | |
1580 | struct_addr); | |
1581 | } | |
1582 | ||
1583 | for (argnum = 0; argnum < nargs; argnum++) | |
1584 | { | |
1585 | struct value *arg = args[argnum]; | |
1586 | struct type *arg_type; | |
1587 | int len; | |
1588 | ||
1589 | arg_type = check_typedef (value_type (arg)); | |
1590 | len = TYPE_LENGTH (arg_type); | |
1591 | ||
1592 | switch (TYPE_CODE (arg_type)) | |
1593 | { | |
1594 | case TYPE_CODE_INT: | |
1595 | case TYPE_CODE_BOOL: | |
1596 | case TYPE_CODE_CHAR: | |
1597 | case TYPE_CODE_RANGE: | |
1598 | case TYPE_CODE_ENUM: | |
1599 | if (len < 4) | |
1600 | { | |
1601 | /* Promote to 32 bit integer. */ | |
1602 | if (TYPE_UNSIGNED (arg_type)) | |
1603 | arg_type = builtin_type (gdbarch)->builtin_uint32; | |
1604 | else | |
1605 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1606 | arg = value_cast (arg_type, arg); | |
1607 | } | |
1608 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1609 | value_contents (arg)); | |
1610 | break; | |
1611 | ||
1612 | case TYPE_CODE_COMPLEX: | |
1613 | if (info.nsrn <= 6) | |
1614 | { | |
1615 | const bfd_byte *buf = value_contents (arg); | |
1616 | struct type *target_type = | |
1617 | check_typedef (TYPE_TARGET_TYPE (arg_type)); | |
1618 | ||
1619 | pass_in_v (gdbarch, regcache, &info, buf); | |
1620 | pass_in_v (gdbarch, regcache, &info, | |
1621 | buf + TYPE_LENGTH (target_type)); | |
1622 | } | |
1623 | else | |
1624 | { | |
1625 | info.nsrn = 8; | |
1626 | pass_on_stack (&info, arg_type, value_contents (arg)); | |
1627 | } | |
1628 | break; | |
1629 | case TYPE_CODE_FLT: | |
1630 | pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, | |
1631 | value_contents (arg)); | |
1632 | break; | |
1633 | ||
1634 | case TYPE_CODE_STRUCT: | |
1635 | case TYPE_CODE_ARRAY: | |
1636 | case TYPE_CODE_UNION: | |
1637 | if (is_hfa (arg_type)) | |
1638 | { | |
1639 | int elements = TYPE_NFIELDS (arg_type); | |
1640 | ||
1641 | /* Homogeneous Aggregates */ | |
1642 | if (info.nsrn + elements < 8) | |
1643 | { | |
1644 | int i; | |
1645 | ||
1646 | for (i = 0; i < elements; i++) | |
1647 | { | |
1648 | /* We know that we have sufficient registers | |
1649 | available therefore this will never fallback | |
1650 | to the stack. */ | |
1651 | struct value *field = | |
1652 | value_primitive_field (arg, 0, i, arg_type); | |
1653 | struct type *field_type = | |
1654 | check_typedef (value_type (field)); | |
1655 | ||
1656 | pass_in_v_or_stack (gdbarch, regcache, &info, field_type, | |
1657 | value_contents_writeable (field)); | |
1658 | } | |
1659 | } | |
1660 | else | |
1661 | { | |
1662 | info.nsrn = 8; | |
1663 | pass_on_stack (&info, arg_type, value_contents (arg)); | |
1664 | } | |
1665 | } | |
1666 | else if (len > 16) | |
1667 | { | |
1668 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1669 | invisible reference. */ | |
1670 | ||
1671 | /* Allocate aligned storage. */ | |
1672 | sp = align_down (sp - len, 16); | |
1673 | ||
1674 | /* Write the real data into the stack. */ | |
1675 | write_memory (sp, value_contents (arg), len); | |
1676 | ||
1677 | /* Construct the indirection. */ | |
1678 | arg_type = lookup_pointer_type (arg_type); | |
1679 | arg = value_from_pointer (arg_type, sp); | |
1680 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1681 | value_contents (arg)); | |
1682 | } | |
1683 | else | |
1684 | /* PCS C.15 / C.18 multiple values pass. */ | |
1685 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1686 | value_contents (arg)); | |
1687 | break; | |
1688 | ||
1689 | default: | |
1690 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, | |
1691 | value_contents (arg)); | |
1692 | break; | |
1693 | } | |
1694 | } | |
1695 | ||
1696 | /* Make sure stack retains 16 byte alignment. */ | |
1697 | if (info.nsaa & 15) | |
1698 | sp -= 16 - (info.nsaa & 15); | |
1699 | ||
1700 | while (!VEC_empty (stack_item_t, info.si)) | |
1701 | { | |
1702 | stack_item_t *si = VEC_last (stack_item_t, info.si); | |
1703 | ||
1704 | sp -= si->len; | |
1705 | write_memory (sp, si->data, si->len); | |
1706 | VEC_pop (stack_item_t, info.si); | |
1707 | } | |
1708 | ||
1709 | VEC_free (stack_item_t, info.si); | |
1710 | ||
1711 | /* Finally, update the SP register. */ | |
1712 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1713 | ||
1714 | return sp; | |
1715 | } | |
1716 | ||
1717 | /* Implement the "frame_align" gdbarch method. */ | |
1718 | ||
1719 | static CORE_ADDR | |
1720 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1721 | { | |
1722 | /* Align the stack to sixteen bytes. */ | |
1723 | return sp & ~(CORE_ADDR) 15; | |
1724 | } | |
1725 | ||
1726 | /* Return the type for an AdvSISD Q register. */ | |
1727 | ||
1728 | static struct type * | |
1729 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
1730 | { | |
1731 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1732 | ||
1733 | if (tdep->vnq_type == NULL) | |
1734 | { | |
1735 | struct type *t; | |
1736 | struct type *elem; | |
1737 | ||
1738 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
1739 | TYPE_CODE_UNION); | |
1740 | ||
1741 | elem = builtin_type (gdbarch)->builtin_uint128; | |
1742 | append_composite_type_field (t, "u", elem); | |
1743 | ||
1744 | elem = builtin_type (gdbarch)->builtin_int128; | |
1745 | append_composite_type_field (t, "s", elem); | |
1746 | ||
1747 | tdep->vnq_type = t; | |
1748 | } | |
1749 | ||
1750 | return tdep->vnq_type; | |
1751 | } | |
1752 | ||
1753 | /* Return the type for an AdvSISD D register. */ | |
1754 | ||
1755 | static struct type * | |
1756 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
1757 | { | |
1758 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1759 | ||
1760 | if (tdep->vnd_type == NULL) | |
1761 | { | |
1762 | struct type *t; | |
1763 | struct type *elem; | |
1764 | ||
1765 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
1766 | TYPE_CODE_UNION); | |
1767 | ||
1768 | elem = builtin_type (gdbarch)->builtin_double; | |
1769 | append_composite_type_field (t, "f", elem); | |
1770 | ||
1771 | elem = builtin_type (gdbarch)->builtin_uint64; | |
1772 | append_composite_type_field (t, "u", elem); | |
1773 | ||
1774 | elem = builtin_type (gdbarch)->builtin_int64; | |
1775 | append_composite_type_field (t, "s", elem); | |
1776 | ||
1777 | tdep->vnd_type = t; | |
1778 | } | |
1779 | ||
1780 | return tdep->vnd_type; | |
1781 | } | |
1782 | ||
1783 | /* Return the type for an AdvSISD S register. */ | |
1784 | ||
1785 | static struct type * | |
1786 | aarch64_vns_type (struct gdbarch *gdbarch) | |
1787 | { | |
1788 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1789 | ||
1790 | if (tdep->vns_type == NULL) | |
1791 | { | |
1792 | struct type *t; | |
1793 | struct type *elem; | |
1794 | ||
1795 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
1796 | TYPE_CODE_UNION); | |
1797 | ||
1798 | elem = builtin_type (gdbarch)->builtin_float; | |
1799 | append_composite_type_field (t, "f", elem); | |
1800 | ||
1801 | elem = builtin_type (gdbarch)->builtin_uint32; | |
1802 | append_composite_type_field (t, "u", elem); | |
1803 | ||
1804 | elem = builtin_type (gdbarch)->builtin_int32; | |
1805 | append_composite_type_field (t, "s", elem); | |
1806 | ||
1807 | tdep->vns_type = t; | |
1808 | } | |
1809 | ||
1810 | return tdep->vns_type; | |
1811 | } | |
1812 | ||
1813 | /* Return the type for an AdvSISD H register. */ | |
1814 | ||
1815 | static struct type * | |
1816 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
1817 | { | |
1818 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1819 | ||
1820 | if (tdep->vnh_type == NULL) | |
1821 | { | |
1822 | struct type *t; | |
1823 | struct type *elem; | |
1824 | ||
1825 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
1826 | TYPE_CODE_UNION); | |
1827 | ||
1828 | elem = builtin_type (gdbarch)->builtin_uint16; | |
1829 | append_composite_type_field (t, "u", elem); | |
1830 | ||
1831 | elem = builtin_type (gdbarch)->builtin_int16; | |
1832 | append_composite_type_field (t, "s", elem); | |
1833 | ||
1834 | tdep->vnh_type = t; | |
1835 | } | |
1836 | ||
1837 | return tdep->vnh_type; | |
1838 | } | |
1839 | ||
1840 | /* Return the type for an AdvSISD B register. */ | |
1841 | ||
1842 | static struct type * | |
1843 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
1844 | { | |
1845 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1846 | ||
1847 | if (tdep->vnb_type == NULL) | |
1848 | { | |
1849 | struct type *t; | |
1850 | struct type *elem; | |
1851 | ||
1852 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
1853 | TYPE_CODE_UNION); | |
1854 | ||
1855 | elem = builtin_type (gdbarch)->builtin_uint8; | |
1856 | append_composite_type_field (t, "u", elem); | |
1857 | ||
1858 | elem = builtin_type (gdbarch)->builtin_int8; | |
1859 | append_composite_type_field (t, "s", elem); | |
1860 | ||
1861 | tdep->vnb_type = t; | |
1862 | } | |
1863 | ||
1864 | return tdep->vnb_type; | |
1865 | } | |
1866 | ||
1867 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ | |
1868 | ||
1869 | static int | |
1870 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1871 | { | |
1872 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) | |
1873 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
1874 | ||
1875 | if (reg == AARCH64_DWARF_SP) | |
1876 | return AARCH64_SP_REGNUM; | |
1877 | ||
1878 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) | |
1879 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
1880 | ||
1881 | return -1; | |
1882 | } | |
1883 | \f | |
1884 | ||
1885 | /* Implement the "print_insn" gdbarch method. */ | |
1886 | ||
1887 | static int | |
1888 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
1889 | { | |
1890 | info->symbols = NULL; | |
1891 | return print_insn_aarch64 (memaddr, info); | |
1892 | } | |
1893 | ||
1894 | /* AArch64 BRK software debug mode instruction. | |
1895 | Note that AArch64 code is always little-endian. | |
1896 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
948f8e3d | 1897 | static const gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 MS |
1898 | |
1899 | /* Implement the "breakpoint_from_pc" gdbarch method. */ | |
1900 | ||
948f8e3d | 1901 | static const gdb_byte * |
07b287a0 MS |
1902 | aarch64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
1903 | int *lenptr) | |
1904 | { | |
1905 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1906 | ||
1907 | *lenptr = sizeof (aarch64_default_breakpoint); | |
1908 | return aarch64_default_breakpoint; | |
1909 | } | |
1910 | ||
1911 | /* Extract from an array REGS containing the (raw) register state a | |
1912 | function return value of type TYPE, and copy that, in virtual | |
1913 | format, into VALBUF. */ | |
1914 | ||
1915 | static void | |
1916 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
1917 | gdb_byte *valbuf) | |
1918 | { | |
1919 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
1920 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1921 | ||
1922 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1923 | { | |
1924 | bfd_byte buf[V_REGISTER_SIZE]; | |
1925 | int len = TYPE_LENGTH (type); | |
1926 | ||
1927 | regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf); | |
1928 | memcpy (valbuf, buf, len); | |
1929 | } | |
1930 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
1931 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
1932 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
1933 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
1934 | || TYPE_CODE (type) == TYPE_CODE_REF | |
1935 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
1936 | { | |
1937 | /* If the the type is a plain integer, then the access is | |
1938 | straight-forward. Otherwise we have to play around a bit | |
1939 | more. */ | |
1940 | int len = TYPE_LENGTH (type); | |
1941 | int regno = AARCH64_X0_REGNUM; | |
1942 | ULONGEST tmp; | |
1943 | ||
1944 | while (len > 0) | |
1945 | { | |
1946 | /* By using store_unsigned_integer we avoid having to do | |
1947 | anything special for small big-endian values. */ | |
1948 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
1949 | store_unsigned_integer (valbuf, | |
1950 | (len > X_REGISTER_SIZE | |
1951 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
1952 | len -= X_REGISTER_SIZE; | |
1953 | valbuf += X_REGISTER_SIZE; | |
1954 | } | |
1955 | } | |
1956 | else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX) | |
1957 | { | |
1958 | int regno = AARCH64_V0_REGNUM; | |
1959 | bfd_byte buf[V_REGISTER_SIZE]; | |
1960 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1961 | int len = TYPE_LENGTH (target_type); | |
1962 | ||
1963 | regcache_cooked_read (regs, regno, buf); | |
1964 | memcpy (valbuf, buf, len); | |
1965 | valbuf += len; | |
1966 | regcache_cooked_read (regs, regno + 1, buf); | |
1967 | memcpy (valbuf, buf, len); | |
1968 | valbuf += len; | |
1969 | } | |
1970 | else if (is_hfa (type)) | |
1971 | { | |
1972 | int elements = TYPE_NFIELDS (type); | |
1973 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1974 | int len = TYPE_LENGTH (member_type); | |
1975 | int i; | |
1976 | ||
1977 | for (i = 0; i < elements; i++) | |
1978 | { | |
1979 | int regno = AARCH64_V0_REGNUM + i; | |
1980 | bfd_byte buf[X_REGISTER_SIZE]; | |
1981 | ||
1982 | if (aarch64_debug) | |
1983 | fprintf_unfiltered (gdb_stdlog, | |
1984 | "read HFA return value element %d from %s\n", | |
1985 | i + 1, | |
1986 | gdbarch_register_name (gdbarch, regno)); | |
1987 | regcache_cooked_read (regs, regno, buf); | |
1988 | ||
1989 | memcpy (valbuf, buf, len); | |
1990 | valbuf += len; | |
1991 | } | |
1992 | } | |
1993 | else | |
1994 | { | |
1995 | /* For a structure or union the behaviour is as if the value had | |
1996 | been stored to word-aligned memory and then loaded into | |
1997 | registers with 64-bit load instruction(s). */ | |
1998 | int len = TYPE_LENGTH (type); | |
1999 | int regno = AARCH64_X0_REGNUM; | |
2000 | bfd_byte buf[X_REGISTER_SIZE]; | |
2001 | ||
2002 | while (len > 0) | |
2003 | { | |
2004 | regcache_cooked_read (regs, regno++, buf); | |
2005 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2006 | len -= X_REGISTER_SIZE; | |
2007 | valbuf += X_REGISTER_SIZE; | |
2008 | } | |
2009 | } | |
2010 | } | |
2011 | ||
2012 | ||
2013 | /* Will a function return an aggregate type in memory or in a | |
2014 | register? Return 0 if an aggregate type can be returned in a | |
2015 | register, 1 if it must be returned in memory. */ | |
2016 | ||
2017 | static int | |
2018 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
2019 | { | |
2020 | int nRc; | |
2021 | enum type_code code; | |
2022 | ||
2023 | CHECK_TYPEDEF (type); | |
2024 | ||
2025 | /* In the AArch64 ABI, "integer" like aggregate types are returned | |
2026 | in registers. For an aggregate type to be integer like, its size | |
2027 | must be less than or equal to 4 * X_REGISTER_SIZE. */ | |
2028 | ||
2029 | if (is_hfa (type)) | |
2030 | { | |
2031 | /* PCS B.5 If the argument is a Named HFA, then the argument is | |
2032 | used unmodified. */ | |
2033 | return 0; | |
2034 | } | |
2035 | ||
2036 | if (TYPE_LENGTH (type) > 16) | |
2037 | { | |
2038 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
2039 | invisible reference. */ | |
2040 | ||
2041 | return 1; | |
2042 | } | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | /* Write into appropriate registers a function return value of type | |
2048 | TYPE, given in virtual format. */ | |
2049 | ||
2050 | static void | |
2051 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
2052 | const gdb_byte *valbuf) | |
2053 | { | |
2054 | struct gdbarch *gdbarch = get_regcache_arch (regs); | |
2055 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2056 | ||
2057 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2058 | { | |
2059 | bfd_byte buf[V_REGISTER_SIZE]; | |
2060 | int len = TYPE_LENGTH (type); | |
2061 | ||
2062 | memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
2063 | regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf); | |
2064 | } | |
2065 | else if (TYPE_CODE (type) == TYPE_CODE_INT | |
2066 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2067 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2068 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2069 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2070 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2071 | { | |
2072 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
2073 | { | |
2074 | /* Values of one word or less are zero/sign-extended and | |
2075 | returned in r0. */ | |
2076 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2077 | LONGEST val = unpack_long (type, valbuf); | |
2078 | ||
2079 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
2080 | regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf); | |
2081 | } | |
2082 | else | |
2083 | { | |
2084 | /* Integral values greater than one word are stored in | |
2085 | consecutive registers starting with r0. This will always | |
2086 | be a multiple of the regiser size. */ | |
2087 | int len = TYPE_LENGTH (type); | |
2088 | int regno = AARCH64_X0_REGNUM; | |
2089 | ||
2090 | while (len > 0) | |
2091 | { | |
2092 | regcache_cooked_write (regs, regno++, valbuf); | |
2093 | len -= X_REGISTER_SIZE; | |
2094 | valbuf += X_REGISTER_SIZE; | |
2095 | } | |
2096 | } | |
2097 | } | |
2098 | else if (is_hfa (type)) | |
2099 | { | |
2100 | int elements = TYPE_NFIELDS (type); | |
2101 | struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2102 | int len = TYPE_LENGTH (member_type); | |
2103 | int i; | |
2104 | ||
2105 | for (i = 0; i < elements; i++) | |
2106 | { | |
2107 | int regno = AARCH64_V0_REGNUM + i; | |
2108 | bfd_byte tmpbuf[MAX_REGISTER_SIZE]; | |
2109 | ||
2110 | if (aarch64_debug) | |
2111 | fprintf_unfiltered (gdb_stdlog, | |
2112 | "write HFA return value element %d to %s\n", | |
2113 | i + 1, | |
2114 | gdbarch_register_name (gdbarch, regno)); | |
2115 | ||
2116 | memcpy (tmpbuf, valbuf, len); | |
2117 | regcache_cooked_write (regs, regno, tmpbuf); | |
2118 | valbuf += len; | |
2119 | } | |
2120 | } | |
2121 | else | |
2122 | { | |
2123 | /* For a structure or union the behaviour is as if the value had | |
2124 | been stored to word-aligned memory and then loaded into | |
2125 | registers with 64-bit load instruction(s). */ | |
2126 | int len = TYPE_LENGTH (type); | |
2127 | int regno = AARCH64_X0_REGNUM; | |
2128 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2129 | ||
2130 | while (len > 0) | |
2131 | { | |
2132 | memcpy (tmpbuf, valbuf, | |
2133 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
2134 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2135 | len -= X_REGISTER_SIZE; | |
2136 | valbuf += X_REGISTER_SIZE; | |
2137 | } | |
2138 | } | |
2139 | } | |
2140 | ||
2141 | /* Implement the "return_value" gdbarch method. */ | |
2142 | ||
2143 | static enum return_value_convention | |
2144 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2145 | struct type *valtype, struct regcache *regcache, | |
2146 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2147 | { | |
2148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2149 | ||
2150 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
2151 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2152 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2153 | { | |
2154 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2155 | { | |
2156 | if (aarch64_debug) | |
2157 | fprintf_unfiltered (gdb_stdlog, "return value in memory\n"); | |
2158 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2159 | } | |
2160 | } | |
2161 | ||
2162 | if (writebuf) | |
2163 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2164 | ||
2165 | if (readbuf) | |
2166 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2167 | ||
2168 | if (aarch64_debug) | |
2169 | fprintf_unfiltered (gdb_stdlog, "return value in registers\n"); | |
2170 | ||
2171 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2172 | } | |
2173 | ||
2174 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2175 | ||
2176 | static int | |
2177 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2178 | { | |
2179 | CORE_ADDR jb_addr; | |
2180 | gdb_byte buf[X_REGISTER_SIZE]; | |
2181 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2182 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2183 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2184 | ||
2185 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2186 | ||
2187 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2188 | X_REGISTER_SIZE)) | |
2189 | return 0; | |
2190 | ||
2191 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2192 | return 1; | |
2193 | } | |
2194 | \f | |
2195 | ||
2196 | /* Return the pseudo register name corresponding to register regnum. */ | |
2197 | ||
2198 | static const char * | |
2199 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2200 | { | |
2201 | static const char *const q_name[] = | |
2202 | { | |
2203 | "q0", "q1", "q2", "q3", | |
2204 | "q4", "q5", "q6", "q7", | |
2205 | "q8", "q9", "q10", "q11", | |
2206 | "q12", "q13", "q14", "q15", | |
2207 | "q16", "q17", "q18", "q19", | |
2208 | "q20", "q21", "q22", "q23", | |
2209 | "q24", "q25", "q26", "q27", | |
2210 | "q28", "q29", "q30", "q31", | |
2211 | }; | |
2212 | ||
2213 | static const char *const d_name[] = | |
2214 | { | |
2215 | "d0", "d1", "d2", "d3", | |
2216 | "d4", "d5", "d6", "d7", | |
2217 | "d8", "d9", "d10", "d11", | |
2218 | "d12", "d13", "d14", "d15", | |
2219 | "d16", "d17", "d18", "d19", | |
2220 | "d20", "d21", "d22", "d23", | |
2221 | "d24", "d25", "d26", "d27", | |
2222 | "d28", "d29", "d30", "d31", | |
2223 | }; | |
2224 | ||
2225 | static const char *const s_name[] = | |
2226 | { | |
2227 | "s0", "s1", "s2", "s3", | |
2228 | "s4", "s5", "s6", "s7", | |
2229 | "s8", "s9", "s10", "s11", | |
2230 | "s12", "s13", "s14", "s15", | |
2231 | "s16", "s17", "s18", "s19", | |
2232 | "s20", "s21", "s22", "s23", | |
2233 | "s24", "s25", "s26", "s27", | |
2234 | "s28", "s29", "s30", "s31", | |
2235 | }; | |
2236 | ||
2237 | static const char *const h_name[] = | |
2238 | { | |
2239 | "h0", "h1", "h2", "h3", | |
2240 | "h4", "h5", "h6", "h7", | |
2241 | "h8", "h9", "h10", "h11", | |
2242 | "h12", "h13", "h14", "h15", | |
2243 | "h16", "h17", "h18", "h19", | |
2244 | "h20", "h21", "h22", "h23", | |
2245 | "h24", "h25", "h26", "h27", | |
2246 | "h28", "h29", "h30", "h31", | |
2247 | }; | |
2248 | ||
2249 | static const char *const b_name[] = | |
2250 | { | |
2251 | "b0", "b1", "b2", "b3", | |
2252 | "b4", "b5", "b6", "b7", | |
2253 | "b8", "b9", "b10", "b11", | |
2254 | "b12", "b13", "b14", "b15", | |
2255 | "b16", "b17", "b18", "b19", | |
2256 | "b20", "b21", "b22", "b23", | |
2257 | "b24", "b25", "b26", "b27", | |
2258 | "b28", "b29", "b30", "b31", | |
2259 | }; | |
2260 | ||
2261 | regnum -= gdbarch_num_regs (gdbarch); | |
2262 | ||
2263 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2264 | return q_name[regnum - AARCH64_Q0_REGNUM]; | |
2265 | ||
2266 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2267 | return d_name[regnum - AARCH64_D0_REGNUM]; | |
2268 | ||
2269 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2270 | return s_name[regnum - AARCH64_S0_REGNUM]; | |
2271 | ||
2272 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2273 | return h_name[regnum - AARCH64_H0_REGNUM]; | |
2274 | ||
2275 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2276 | return b_name[regnum - AARCH64_B0_REGNUM]; | |
2277 | ||
2278 | internal_error (__FILE__, __LINE__, | |
2279 | _("aarch64_pseudo_register_name: bad register number %d"), | |
2280 | regnum); | |
2281 | } | |
2282 | ||
2283 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2284 | ||
2285 | static struct type * | |
2286 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2287 | { | |
2288 | regnum -= gdbarch_num_regs (gdbarch); | |
2289 | ||
2290 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2291 | return aarch64_vnq_type (gdbarch); | |
2292 | ||
2293 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2294 | return aarch64_vnd_type (gdbarch); | |
2295 | ||
2296 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2297 | return aarch64_vns_type (gdbarch); | |
2298 | ||
2299 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2300 | return aarch64_vnh_type (gdbarch); | |
2301 | ||
2302 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2303 | return aarch64_vnb_type (gdbarch); | |
2304 | ||
2305 | internal_error (__FILE__, __LINE__, | |
2306 | _("aarch64_pseudo_register_type: bad register number %d"), | |
2307 | regnum); | |
2308 | } | |
2309 | ||
2310 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2311 | ||
2312 | static int | |
2313 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2314 | struct reggroup *group) | |
2315 | { | |
2316 | regnum -= gdbarch_num_regs (gdbarch); | |
2317 | ||
2318 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2319 | return group == all_reggroup || group == vector_reggroup; | |
2320 | else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2321 | return (group == all_reggroup || group == vector_reggroup | |
2322 | || group == float_reggroup); | |
2323 | else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2324 | return (group == all_reggroup || group == vector_reggroup | |
2325 | || group == float_reggroup); | |
2326 | else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2327 | return group == all_reggroup || group == vector_reggroup; | |
2328 | else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2329 | return group == all_reggroup || group == vector_reggroup; | |
2330 | ||
2331 | return group == all_reggroup; | |
2332 | } | |
2333 | ||
2334 | /* Implement the "pseudo_register_read_value" gdbarch method. */ | |
2335 | ||
2336 | static struct value * | |
2337 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, | |
2338 | struct regcache *regcache, | |
2339 | int regnum) | |
2340 | { | |
2341 | gdb_byte reg_buf[MAX_REGISTER_SIZE]; | |
2342 | struct value *result_value; | |
2343 | gdb_byte *buf; | |
2344 | ||
2345 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
2346 | VALUE_LVAL (result_value) = lval_register; | |
2347 | VALUE_REGNUM (result_value) = regnum; | |
2348 | buf = value_contents_raw (result_value); | |
2349 | ||
2350 | regnum -= gdbarch_num_regs (gdbarch); | |
2351 | ||
2352 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2353 | { | |
2354 | enum register_status status; | |
2355 | unsigned v_regnum; | |
2356 | ||
2357 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2358 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2359 | if (status != REG_VALID) | |
2360 | mark_value_bytes_unavailable (result_value, 0, | |
2361 | TYPE_LENGTH (value_type (result_value))); | |
2362 | else | |
2363 | memcpy (buf, reg_buf, Q_REGISTER_SIZE); | |
2364 | return result_value; | |
2365 | } | |
2366 | ||
2367 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2368 | { | |
2369 | enum register_status status; | |
2370 | unsigned v_regnum; | |
2371 | ||
2372 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2373 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2374 | if (status != REG_VALID) | |
2375 | mark_value_bytes_unavailable (result_value, 0, | |
2376 | TYPE_LENGTH (value_type (result_value))); | |
2377 | else | |
2378 | memcpy (buf, reg_buf, D_REGISTER_SIZE); | |
2379 | return result_value; | |
2380 | } | |
2381 | ||
2382 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2383 | { | |
2384 | enum register_status status; | |
2385 | unsigned v_regnum; | |
2386 | ||
2387 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2388 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2389 | memcpy (buf, reg_buf, S_REGISTER_SIZE); | |
2390 | return result_value; | |
2391 | } | |
2392 | ||
2393 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2394 | { | |
2395 | enum register_status status; | |
2396 | unsigned v_regnum; | |
2397 | ||
2398 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2399 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2400 | if (status != REG_VALID) | |
2401 | mark_value_bytes_unavailable (result_value, 0, | |
2402 | TYPE_LENGTH (value_type (result_value))); | |
2403 | else | |
2404 | memcpy (buf, reg_buf, H_REGISTER_SIZE); | |
2405 | return result_value; | |
2406 | } | |
2407 | ||
2408 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2409 | { | |
2410 | enum register_status status; | |
2411 | unsigned v_regnum; | |
2412 | ||
2413 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2414 | status = regcache_raw_read (regcache, v_regnum, reg_buf); | |
2415 | if (status != REG_VALID) | |
2416 | mark_value_bytes_unavailable (result_value, 0, | |
2417 | TYPE_LENGTH (value_type (result_value))); | |
2418 | else | |
2419 | memcpy (buf, reg_buf, B_REGISTER_SIZE); | |
2420 | return result_value; | |
2421 | } | |
2422 | ||
2423 | gdb_assert_not_reached ("regnum out of bound"); | |
2424 | } | |
2425 | ||
2426 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2427 | ||
2428 | static void | |
2429 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2430 | int regnum, const gdb_byte *buf) | |
2431 | { | |
2432 | gdb_byte reg_buf[MAX_REGISTER_SIZE]; | |
2433 | ||
2434 | /* Ensure the register buffer is zero, we want gdb writes of the | |
2435 | various 'scalar' pseudo registers to behavior like architectural | |
2436 | writes, register width bytes are written the remainder are set to | |
2437 | zero. */ | |
2438 | memset (reg_buf, 0, sizeof (reg_buf)); | |
2439 | ||
2440 | regnum -= gdbarch_num_regs (gdbarch); | |
2441 | ||
2442 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
2443 | { | |
2444 | /* pseudo Q registers */ | |
2445 | unsigned v_regnum; | |
2446 | ||
2447 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM; | |
2448 | memcpy (reg_buf, buf, Q_REGISTER_SIZE); | |
2449 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2450 | return; | |
2451 | } | |
2452 | ||
2453 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
2454 | { | |
2455 | /* pseudo D registers */ | |
2456 | unsigned v_regnum; | |
2457 | ||
2458 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM; | |
2459 | memcpy (reg_buf, buf, D_REGISTER_SIZE); | |
2460 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2461 | return; | |
2462 | } | |
2463 | ||
2464 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
2465 | { | |
2466 | unsigned v_regnum; | |
2467 | ||
2468 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM; | |
2469 | memcpy (reg_buf, buf, S_REGISTER_SIZE); | |
2470 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2471 | return; | |
2472 | } | |
2473 | ||
2474 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
2475 | { | |
2476 | /* pseudo H registers */ | |
2477 | unsigned v_regnum; | |
2478 | ||
2479 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM; | |
2480 | memcpy (reg_buf, buf, H_REGISTER_SIZE); | |
2481 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2482 | return; | |
2483 | } | |
2484 | ||
2485 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
2486 | { | |
2487 | /* pseudo B registers */ | |
2488 | unsigned v_regnum; | |
2489 | ||
2490 | v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM; | |
2491 | memcpy (reg_buf, buf, B_REGISTER_SIZE); | |
2492 | regcache_raw_write (regcache, v_regnum, reg_buf); | |
2493 | return; | |
2494 | } | |
2495 | ||
2496 | gdb_assert_not_reached ("regnum out of bound"); | |
2497 | } | |
2498 | ||
07b287a0 MS |
2499 | /* Callback function for user_reg_add. */ |
2500 | ||
2501 | static struct value * | |
2502 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2503 | { | |
2504 | const int *reg_p = baton; | |
2505 | ||
2506 | return value_of_register (*reg_p, frame); | |
2507 | } | |
2508 | \f | |
2509 | ||
9404b58f KM |
2510 | /* Implement the "software_single_step" gdbarch method, needed to |
2511 | single step through atomic sequences on AArch64. */ | |
2512 | ||
2513 | static int | |
2514 | aarch64_software_single_step (struct frame_info *frame) | |
2515 | { | |
2516 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2517 | struct address_space *aspace = get_frame_address_space (frame); | |
2518 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
2519 | const int insn_size = 4; | |
2520 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2521 | CORE_ADDR pc = get_frame_pc (frame); | |
2522 | CORE_ADDR breaks[2] = { -1, -1 }; | |
2523 | CORE_ADDR loc = pc; | |
2524 | CORE_ADDR closing_insn = 0; | |
2525 | uint32_t insn = read_memory_unsigned_integer (loc, insn_size, | |
2526 | byte_order_for_code); | |
2527 | int index; | |
2528 | int insn_count; | |
2529 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2530 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2531 | ||
2532 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
2533 | if (!decode_masked_match (insn, 0x3fc00000, 0x08400000)) | |
2534 | return 0; | |
2535 | ||
2536 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2537 | { | |
2538 | int32_t offset; | |
2539 | unsigned cond; | |
2540 | ||
2541 | loc += insn_size; | |
2542 | insn = read_memory_unsigned_integer (loc, insn_size, | |
2543 | byte_order_for_code); | |
2544 | ||
2545 | /* Check if the instruction is a conditional branch. */ | |
2546 | if (decode_bcond (loc, insn, &cond, &offset)) | |
2547 | { | |
2548 | if (bc_insn_count >= 1) | |
2549 | return 0; | |
2550 | ||
2551 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
2552 | breaks[1] = loc + offset; | |
2553 | ||
2554 | bc_insn_count++; | |
2555 | last_breakpoint++; | |
2556 | } | |
2557 | ||
2558 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
2559 | if (decode_masked_match (insn, 0x3fc00000, 0x08000000)) | |
2560 | { | |
2561 | closing_insn = loc; | |
2562 | break; | |
2563 | } | |
2564 | } | |
2565 | ||
2566 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
2567 | if (!closing_insn) | |
2568 | return 0; | |
2569 | ||
2570 | /* Insert breakpoint after the end of the atomic sequence. */ | |
2571 | breaks[0] = loc + insn_size; | |
2572 | ||
2573 | /* Check for duplicated breakpoints, and also check that the second | |
2574 | breakpoint is not within the atomic sequence. */ | |
2575 | if (last_breakpoint | |
2576 | && (breaks[1] == breaks[0] | |
2577 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
2578 | last_breakpoint = 0; | |
2579 | ||
2580 | /* Insert the breakpoint at the end of the sequence, and one at the | |
2581 | destination of the conditional branch, if it exists. */ | |
2582 | for (index = 0; index <= last_breakpoint; index++) | |
2583 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
2584 | ||
2585 | return 1; | |
2586 | } | |
2587 | ||
07b287a0 MS |
2588 | /* Initialize the current architecture based on INFO. If possible, |
2589 | re-use an architecture from ARCHES, which is a list of | |
2590 | architectures already created during this debugging session. | |
2591 | ||
2592 | Called e.g. at program startup, when reading a core file, and when | |
2593 | reading a binary file. */ | |
2594 | ||
2595 | static struct gdbarch * | |
2596 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2597 | { | |
2598 | struct gdbarch_tdep *tdep; | |
2599 | struct gdbarch *gdbarch; | |
2600 | struct gdbarch_list *best_arch; | |
2601 | struct tdesc_arch_data *tdesc_data = NULL; | |
2602 | const struct target_desc *tdesc = info.target_desc; | |
2603 | int i; | |
2604 | int have_fpa_registers = 1; | |
2605 | int valid_p = 1; | |
2606 | const struct tdesc_feature *feature; | |
2607 | int num_regs = 0; | |
2608 | int num_pseudo_regs = 0; | |
2609 | ||
2610 | /* Ensure we always have a target descriptor. */ | |
2611 | if (!tdesc_has_registers (tdesc)) | |
2612 | tdesc = tdesc_aarch64; | |
2613 | ||
2614 | gdb_assert (tdesc); | |
2615 | ||
2616 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core"); | |
2617 | ||
2618 | if (feature == NULL) | |
2619 | return NULL; | |
2620 | ||
2621 | tdesc_data = tdesc_data_alloc (); | |
2622 | ||
2623 | /* Validate the descriptor provides the mandatory core R registers | |
2624 | and allocate their numbers. */ | |
2625 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
2626 | valid_p &= | |
2627 | tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i, | |
2628 | aarch64_r_register_names[i]); | |
2629 | ||
2630 | num_regs = AARCH64_X0_REGNUM + i; | |
2631 | ||
2632 | /* Look for the V registers. */ | |
2633 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); | |
2634 | if (feature) | |
2635 | { | |
2636 | /* Validate the descriptor provides the mandatory V registers | |
2637 | and allocate their numbers. */ | |
2638 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) | |
2639 | valid_p &= | |
2640 | tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i, | |
2641 | aarch64_v_register_names[i]); | |
2642 | ||
2643 | num_regs = AARCH64_V0_REGNUM + i; | |
2644 | ||
2645 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ | |
2646 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
2647 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
2648 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
2649 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
2650 | } | |
2651 | ||
2652 | if (!valid_p) | |
2653 | { | |
2654 | tdesc_data_cleanup (tdesc_data); | |
2655 | return NULL; | |
2656 | } | |
2657 | ||
2658 | /* AArch64 code is always little-endian. */ | |
2659 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
2660 | ||
2661 | /* If there is already a candidate, use it. */ | |
2662 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
2663 | best_arch != NULL; | |
2664 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
2665 | { | |
2666 | /* Found a match. */ | |
2667 | break; | |
2668 | } | |
2669 | ||
2670 | if (best_arch != NULL) | |
2671 | { | |
2672 | if (tdesc_data != NULL) | |
2673 | tdesc_data_cleanup (tdesc_data); | |
2674 | return best_arch->gdbarch; | |
2675 | } | |
2676 | ||
2677 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
2678 | gdbarch = gdbarch_alloc (&info, tdep); | |
2679 | ||
2680 | /* This should be low enough for everything. */ | |
2681 | tdep->lowest_pc = 0x20; | |
2682 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
2683 | tdep->jb_elt_size = 8; | |
2684 | ||
2685 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); | |
2686 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
2687 | ||
07b287a0 MS |
2688 | /* Frame handling. */ |
2689 | set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id); | |
2690 | set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc); | |
2691 | set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp); | |
2692 | ||
2693 | /* Advance PC across function entry code. */ | |
2694 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
2695 | ||
2696 | /* The stack grows downward. */ | |
2697 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2698 | ||
2699 | /* Breakpoint manipulation. */ | |
2700 | set_gdbarch_breakpoint_from_pc (gdbarch, aarch64_breakpoint_from_pc); | |
07b287a0 | 2701 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 2702 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
2703 | |
2704 | /* Information about registers, etc. */ | |
2705 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
2706 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
2707 | set_gdbarch_num_regs (gdbarch, num_regs); | |
2708 | ||
2709 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
2710 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
2711 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
2712 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
2713 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
2714 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
2715 | aarch64_pseudo_register_reggroup_p); | |
2716 | ||
2717 | /* ABI */ | |
2718 | set_gdbarch_short_bit (gdbarch, 16); | |
2719 | set_gdbarch_int_bit (gdbarch, 32); | |
2720 | set_gdbarch_float_bit (gdbarch, 32); | |
2721 | set_gdbarch_double_bit (gdbarch, 64); | |
2722 | set_gdbarch_long_double_bit (gdbarch, 128); | |
2723 | set_gdbarch_long_bit (gdbarch, 64); | |
2724 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2725 | set_gdbarch_ptr_bit (gdbarch, 64); | |
2726 | set_gdbarch_char_signed (gdbarch, 0); | |
2727 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
2728 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
2729 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); | |
2730 | ||
2731 | /* Internal <-> external register number maps. */ | |
2732 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
2733 | ||
2734 | /* Returning results. */ | |
2735 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
2736 | ||
2737 | /* Disassembly. */ | |
2738 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
2739 | ||
2740 | /* Virtual tables. */ | |
2741 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
2742 | ||
2743 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
2744 | info.target_desc = tdesc; | |
2745 | info.tdep_info = (void *) tdesc_data; | |
2746 | gdbarch_init_osabi (info, gdbarch); | |
2747 | ||
2748 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
2749 | ||
2750 | /* Add some default predicates. */ | |
2751 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
2752 | dwarf2_append_unwinders (gdbarch); | |
2753 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
2754 | ||
2755 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
2756 | ||
2757 | /* Now we have tuned the configuration, set a few final things, | |
2758 | based on what the OS ABI has told us. */ | |
2759 | ||
2760 | if (tdep->jb_pc >= 0) | |
2761 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
2762 | ||
2763 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
2764 | ||
2765 | /* Add standard register aliases. */ | |
2766 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
2767 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
2768 | value_of_aarch64_user_reg, | |
2769 | &aarch64_register_aliases[i].regnum); | |
2770 | ||
2771 | return gdbarch; | |
2772 | } | |
2773 | ||
2774 | static void | |
2775 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
2776 | { | |
2777 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2778 | ||
2779 | if (tdep == NULL) | |
2780 | return; | |
2781 | ||
2782 | fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), | |
2783 | paddress (gdbarch, tdep->lowest_pc)); | |
2784 | } | |
2785 | ||
2786 | /* Suppress warning from -Wmissing-prototypes. */ | |
2787 | extern initialize_file_ftype _initialize_aarch64_tdep; | |
2788 | ||
2789 | void | |
2790 | _initialize_aarch64_tdep (void) | |
2791 | { | |
2792 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
2793 | aarch64_dump_tdep); | |
2794 | ||
2795 | initialize_tdesc_aarch64 (); | |
07b287a0 MS |
2796 | |
2797 | /* Debug this file's internals. */ | |
2798 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
2799 | Set AArch64 debugging."), _("\ | |
2800 | Show AArch64 debugging."), _("\ | |
2801 | When on, AArch64 specific debugging is enabled."), | |
2802 | NULL, | |
2803 | show_aarch64_debug, | |
2804 | &setdebuglist, &showdebuglist); | |
2805 | } |