Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
7b6bb8da JB |
4 | 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
615967cb | 23 | #include "doublest.h" |
c906108c | 24 | #include "frame.h" |
d2427a71 RH |
25 | #include "frame-unwind.h" |
26 | #include "frame-base.h" | |
baa490c4 | 27 | #include "dwarf2-frame.h" |
c906108c SS |
28 | #include "inferior.h" |
29 | #include "symtab.h" | |
30 | #include "value.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
33 | #include "dis-asm.h" | |
34 | #include "symfile.h" | |
35 | #include "objfiles.h" | |
36 | #include "gdb_string.h" | |
c5f0f3d0 | 37 | #include "linespec.h" |
4e052eda | 38 | #include "regcache.h" |
615967cb | 39 | #include "reggroups.h" |
dc129d82 | 40 | #include "arch-utils.h" |
4be87837 | 41 | #include "osabi.h" |
fe898f56 | 42 | #include "block.h" |
7d9b040b | 43 | #include "infcall.h" |
07ea644b | 44 | #include "trad-frame.h" |
dc129d82 JT |
45 | |
46 | #include "elf-bfd.h" | |
47 | ||
48 | #include "alpha-tdep.h" | |
49 | ||
3a48e6ff JG |
50 | /* Instruction decoding. The notations for registers, immediates and |
51 | opcodes are the same as the one used in Compaq's Alpha architecture | |
52 | handbook. */ | |
53 | ||
54 | #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26) | |
55 | ||
56 | /* Memory instruction format */ | |
57 | #define MEM_RA(insn) ((insn & 0x03e00000) >> 21) | |
58 | #define MEM_RB(insn) ((insn & 0x001f0000) >> 16) | |
59 | #define MEM_DISP(insn) \ | |
60 | (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff)) | |
61 | ||
62 | static const int lda_opcode = 0x08; | |
63 | static const int stq_opcode = 0x2d; | |
64 | ||
65 | /* Branch instruction format */ | |
66 | #define BR_RA(insn) MEM_RA(insn) | |
67 | ||
46ad3598 | 68 | static const int br_opcode = 0x30; |
3a48e6ff JG |
69 | static const int bne_opcode = 0x3d; |
70 | ||
71 | /* Operate instruction format */ | |
72 | #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5) | |
73 | #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000) | |
74 | #define OPR_RA(insn) MEM_RA(insn) | |
75 | #define OPR_RC(insn) ((insn & 0x1f)) | |
76 | #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13) | |
77 | ||
78 | static const int subq_opcode = 0x10; | |
79 | static const int subq_function = 0x29; | |
80 | ||
c906108c | 81 | \f |
515921d7 JB |
82 | /* Return the name of the REGNO register. |
83 | ||
84 | An empty name corresponds to a register number that used to | |
0963b4bd | 85 | be used for a virtual register. That virtual register has |
515921d7 JB |
86 | been removed, but the index is still reserved to maintain |
87 | compatibility with existing remote alpha targets. */ | |
88 | ||
fa88f677 | 89 | static const char * |
d93859e2 | 90 | alpha_register_name (struct gdbarch *gdbarch, int regno) |
636a6dfc | 91 | { |
5ab84872 | 92 | static const char * const register_names[] = |
636a6dfc JT |
93 | { |
94 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", | |
95 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", | |
96 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", | |
97 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", | |
98 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
99 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
100 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
101 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", | |
44d88583 | 102 | "pc", "", "unique" |
636a6dfc JT |
103 | }; |
104 | ||
105 | if (regno < 0) | |
5ab84872 | 106 | return NULL; |
e8d2d628 | 107 | if (regno >= ARRAY_SIZE(register_names)) |
5ab84872 RH |
108 | return NULL; |
109 | return register_names[regno]; | |
636a6dfc | 110 | } |
d734c450 | 111 | |
dc129d82 | 112 | static int |
64a3914f | 113 | alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 114 | { |
4a1be8d2 | 115 | return (strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
116 | } |
117 | ||
dc129d82 | 118 | static int |
64a3914f | 119 | alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 120 | { |
515921d7 | 121 | return (regno == ALPHA_ZERO_REGNUM |
64a3914f | 122 | || strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
123 | } |
124 | ||
dc129d82 | 125 | static struct type * |
c483c494 | 126 | alpha_register_type (struct gdbarch *gdbarch, int regno) |
0d056799 | 127 | { |
72667056 | 128 | if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) |
0dfff4cb | 129 | return builtin_type (gdbarch)->builtin_data_ptr; |
72667056 | 130 | if (regno == ALPHA_PC_REGNUM) |
0dfff4cb | 131 | return builtin_type (gdbarch)->builtin_func_ptr; |
72667056 RH |
132 | |
133 | /* Don't need to worry about little vs big endian until | |
134 | some jerk tries to port to alpha-unicosmk. */ | |
b38b6be2 | 135 | if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) |
27067745 | 136 | return builtin_type (gdbarch)->builtin_double; |
72667056 | 137 | |
df4df182 | 138 | return builtin_type (gdbarch)->builtin_int64; |
0d056799 | 139 | } |
f8453e34 | 140 | |
615967cb RH |
141 | /* Is REGNUM a member of REGGROUP? */ |
142 | ||
143 | static int | |
144 | alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
145 | struct reggroup *group) | |
146 | { | |
147 | /* Filter out any registers eliminated, but whose regnum is | |
148 | reserved for backward compatibility, e.g. the vfp. */ | |
ec7cc0e8 UW |
149 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
150 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
615967cb RH |
151 | return 0; |
152 | ||
df4a182b RH |
153 | if (group == all_reggroup) |
154 | return 1; | |
155 | ||
156 | /* Zero should not be saved or restored. Technically it is a general | |
157 | register (just as $f31 would be a float if we represented it), but | |
158 | there's no point displaying it during "info regs", so leave it out | |
159 | of all groups except for "all". */ | |
160 | if (regnum == ALPHA_ZERO_REGNUM) | |
161 | return 0; | |
162 | ||
163 | /* All other registers are saved and restored. */ | |
164 | if (group == save_reggroup || group == restore_reggroup) | |
615967cb RH |
165 | return 1; |
166 | ||
167 | /* All other groups are non-overlapping. */ | |
168 | ||
169 | /* Since this is really a PALcode memory slot... */ | |
170 | if (regnum == ALPHA_UNIQUE_REGNUM) | |
171 | return group == system_reggroup; | |
172 | ||
173 | /* Force the FPCR to be considered part of the floating point state. */ | |
174 | if (regnum == ALPHA_FPCR_REGNUM) | |
175 | return group == float_reggroup; | |
176 | ||
177 | if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31) | |
178 | return group == float_reggroup; | |
179 | else | |
180 | return group == general_reggroup; | |
181 | } | |
182 | ||
c483c494 RH |
183 | /* The following represents exactly the conversion performed by |
184 | the LDS instruction. This applies to both single-precision | |
185 | floating point and 32-bit integers. */ | |
186 | ||
187 | static void | |
e17a4113 | 188 | alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 189 | { |
e17a4113 UW |
190 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
191 | ULONGEST mem = extract_unsigned_integer (in, 4, byte_order); | |
c483c494 RH |
192 | ULONGEST frac = (mem >> 0) & 0x7fffff; |
193 | ULONGEST sign = (mem >> 31) & 1; | |
194 | ULONGEST exp_msb = (mem >> 30) & 1; | |
195 | ULONGEST exp_low = (mem >> 23) & 0x7f; | |
196 | ULONGEST exp, reg; | |
197 | ||
198 | exp = (exp_msb << 10) | exp_low; | |
199 | if (exp_msb) | |
200 | { | |
201 | if (exp_low == 0x7f) | |
202 | exp = 0x7ff; | |
203 | } | |
204 | else | |
205 | { | |
206 | if (exp_low != 0x00) | |
207 | exp |= 0x380; | |
208 | } | |
209 | ||
210 | reg = (sign << 63) | (exp << 52) | (frac << 29); | |
e17a4113 | 211 | store_unsigned_integer (out, 8, byte_order, reg); |
c483c494 RH |
212 | } |
213 | ||
214 | /* Similarly, this represents exactly the conversion performed by | |
215 | the STS instruction. */ | |
216 | ||
39efb398 | 217 | static void |
e17a4113 | 218 | alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 219 | { |
e17a4113 | 220 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c483c494 RH |
221 | ULONGEST reg, mem; |
222 | ||
e17a4113 | 223 | reg = extract_unsigned_integer (in, 8, byte_order); |
c483c494 | 224 | mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); |
e17a4113 | 225 | store_unsigned_integer (out, 4, byte_order, mem); |
c483c494 RH |
226 | } |
227 | ||
d2427a71 RH |
228 | /* The alpha needs a conversion between register and memory format if the |
229 | register is a floating point register and memory format is float, as the | |
230 | register format must be double or memory format is an integer with 4 | |
231 | bytes or less, as the representation of integers in floating point | |
0963b4bd | 232 | registers is different. */ |
d2427a71 | 233 | |
c483c494 | 234 | static int |
0963b4bd MS |
235 | alpha_convert_register_p (struct gdbarch *gdbarch, int regno, |
236 | struct type *type) | |
14696584 | 237 | { |
83acabca DJ |
238 | return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 |
239 | && TYPE_LENGTH (type) != 8); | |
14696584 RH |
240 | } |
241 | ||
8dccd430 | 242 | static int |
ff2e87ac | 243 | alpha_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
244 | struct type *valtype, gdb_byte *out, |
245 | int *optimizedp, int *unavailablep) | |
5868c862 | 246 | { |
8dccd430 | 247 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2a1ce6ec MK |
248 | gdb_byte in[MAX_REGISTER_SIZE]; |
249 | ||
8dccd430 PA |
250 | /* Convert to TYPE. */ |
251 | if (!get_frame_register_bytes (frame, regnum, 0, | |
252 | register_size (gdbarch, regnum), | |
253 | in, optimizedp, unavailablep)) | |
254 | return 0; | |
255 | ||
256 | if (TYPE_LENGTH (valtype) == 4) | |
d2427a71 | 257 | { |
8dccd430 PA |
258 | alpha_sts (gdbarch, out, in); |
259 | *optimizedp = *unavailablep = 0; | |
260 | return 1; | |
d2427a71 | 261 | } |
8dccd430 PA |
262 | |
263 | error (_("Cannot retrieve value from floating point register")); | |
d2427a71 | 264 | } |
5868c862 | 265 | |
d2427a71 | 266 | static void |
ff2e87ac | 267 | alpha_value_to_register (struct frame_info *frame, int regnum, |
5b819568 | 268 | struct type *valtype, const gdb_byte *in) |
d2427a71 | 269 | { |
2a1ce6ec MK |
270 | gdb_byte out[MAX_REGISTER_SIZE]; |
271 | ||
c483c494 | 272 | switch (TYPE_LENGTH (valtype)) |
d2427a71 | 273 | { |
c483c494 | 274 | case 4: |
e17a4113 | 275 | alpha_lds (get_frame_arch (frame), out, in); |
c483c494 | 276 | break; |
c483c494 | 277 | default: |
323e0a4a | 278 | error (_("Cannot store value in floating point register")); |
d2427a71 | 279 | } |
ff2e87ac | 280 | put_frame_register (frame, regnum, out); |
5868c862 JT |
281 | } |
282 | ||
d2427a71 RH |
283 | \f |
284 | /* The alpha passes the first six arguments in the registers, the rest on | |
c88e30c0 RH |
285 | the stack. The register arguments are stored in ARG_REG_BUFFER, and |
286 | then moved into the register file; this simplifies the passing of a | |
287 | large struct which extends from the registers to the stack, plus avoids | |
288 | three ptrace invocations per word. | |
289 | ||
290 | We don't bother tracking which register values should go in integer | |
291 | regs or fp regs; we load the same values into both. | |
292 | ||
d2427a71 RH |
293 | If the called function is returning a structure, the address of the |
294 | structure to be returned is passed as a hidden first argument. */ | |
c906108c | 295 | |
d2427a71 | 296 | static CORE_ADDR |
7d9b040b | 297 | alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
c88e30c0 RH |
298 | struct regcache *regcache, CORE_ADDR bp_addr, |
299 | int nargs, struct value **args, CORE_ADDR sp, | |
300 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 301 | { |
e17a4113 | 302 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d2427a71 RH |
303 | int i; |
304 | int accumulate_size = struct_return ? 8 : 0; | |
d2427a71 | 305 | struct alpha_arg |
c906108c | 306 | { |
f42a0a33 | 307 | const gdb_byte *contents; |
d2427a71 RH |
308 | int len; |
309 | int offset; | |
310 | }; | |
c88e30c0 RH |
311 | struct alpha_arg *alpha_args |
312 | = (struct alpha_arg *) alloca (nargs * sizeof (struct alpha_arg)); | |
52f0bd74 | 313 | struct alpha_arg *m_arg; |
2a1ce6ec | 314 | gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; |
d2427a71 | 315 | int required_arg_regs; |
7d9b040b | 316 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 317 | |
c88e30c0 RH |
318 | /* The ABI places the address of the called function in T12. */ |
319 | regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr); | |
320 | ||
321 | /* Set the return address register to point to the entry point | |
322 | of the program, where a breakpoint lies in wait. */ | |
323 | regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr); | |
324 | ||
325 | /* Lay out the arguments in memory. */ | |
d2427a71 RH |
326 | for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++) |
327 | { | |
328 | struct value *arg = args[i]; | |
4991999e | 329 | struct type *arg_type = check_typedef (value_type (arg)); |
c88e30c0 | 330 | |
d2427a71 RH |
331 | /* Cast argument to long if necessary as the compiler does it too. */ |
332 | switch (TYPE_CODE (arg_type)) | |
c906108c | 333 | { |
d2427a71 RH |
334 | case TYPE_CODE_INT: |
335 | case TYPE_CODE_BOOL: | |
336 | case TYPE_CODE_CHAR: | |
337 | case TYPE_CODE_RANGE: | |
338 | case TYPE_CODE_ENUM: | |
0ede8eca | 339 | if (TYPE_LENGTH (arg_type) == 4) |
d2427a71 | 340 | { |
0ede8eca RH |
341 | /* 32-bit values must be sign-extended to 64 bits |
342 | even if the base data type is unsigned. */ | |
df4df182 | 343 | arg_type = builtin_type (gdbarch)->builtin_int32; |
0ede8eca RH |
344 | arg = value_cast (arg_type, arg); |
345 | } | |
346 | if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE) | |
347 | { | |
df4df182 | 348 | arg_type = builtin_type (gdbarch)->builtin_int64; |
d2427a71 RH |
349 | arg = value_cast (arg_type, arg); |
350 | } | |
351 | break; | |
7b5e1cb3 | 352 | |
c88e30c0 RH |
353 | case TYPE_CODE_FLT: |
354 | /* "float" arguments loaded in registers must be passed in | |
355 | register format, aka "double". */ | |
356 | if (accumulate_size < sizeof (arg_reg_buffer) | |
357 | && TYPE_LENGTH (arg_type) == 4) | |
358 | { | |
27067745 | 359 | arg_type = builtin_type (gdbarch)->builtin_double; |
c88e30c0 RH |
360 | arg = value_cast (arg_type, arg); |
361 | } | |
362 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
363 | invisible reference. No one else uses this data type. */ | |
364 | else if (TYPE_LENGTH (arg_type) == 16) | |
365 | { | |
366 | /* Allocate aligned storage. */ | |
367 | sp = (sp & -16) - 16; | |
368 | ||
369 | /* Write the real data into the stack. */ | |
0fd88904 | 370 | write_memory (sp, value_contents (arg), 16); |
c88e30c0 RH |
371 | |
372 | /* Construct the indirection. */ | |
373 | arg_type = lookup_pointer_type (arg_type); | |
374 | arg = value_from_pointer (arg_type, sp); | |
375 | } | |
376 | break; | |
7b5e1cb3 RH |
377 | |
378 | case TYPE_CODE_COMPLEX: | |
379 | /* ??? The ABI says that complex values are passed as two | |
380 | separate scalar values. This distinction only matters | |
381 | for complex float. However, GCC does not implement this. */ | |
382 | ||
383 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
384 | invisible reference. */ | |
385 | if (TYPE_LENGTH (arg_type) == 32) | |
386 | { | |
387 | /* Allocate aligned storage. */ | |
388 | sp = (sp & -16) - 16; | |
389 | ||
390 | /* Write the real data into the stack. */ | |
0fd88904 | 391 | write_memory (sp, value_contents (arg), 32); |
7b5e1cb3 RH |
392 | |
393 | /* Construct the indirection. */ | |
394 | arg_type = lookup_pointer_type (arg_type); | |
395 | arg = value_from_pointer (arg_type, sp); | |
396 | } | |
397 | break; | |
398 | ||
d2427a71 RH |
399 | default: |
400 | break; | |
c906108c | 401 | } |
d2427a71 RH |
402 | m_arg->len = TYPE_LENGTH (arg_type); |
403 | m_arg->offset = accumulate_size; | |
404 | accumulate_size = (accumulate_size + m_arg->len + 7) & ~7; | |
f42a0a33 | 405 | m_arg->contents = value_contents (arg); |
c906108c SS |
406 | } |
407 | ||
d2427a71 RH |
408 | /* Determine required argument register loads, loading an argument register |
409 | is expensive as it uses three ptrace calls. */ | |
410 | required_arg_regs = accumulate_size / 8; | |
411 | if (required_arg_regs > ALPHA_NUM_ARG_REGS) | |
412 | required_arg_regs = ALPHA_NUM_ARG_REGS; | |
c906108c | 413 | |
d2427a71 | 414 | /* Make room for the arguments on the stack. */ |
c88e30c0 RH |
415 | if (accumulate_size < sizeof(arg_reg_buffer)) |
416 | accumulate_size = 0; | |
417 | else | |
418 | accumulate_size -= sizeof(arg_reg_buffer); | |
d2427a71 | 419 | sp -= accumulate_size; |
c906108c | 420 | |
c88e30c0 | 421 | /* Keep sp aligned to a multiple of 16 as the ABI requires. */ |
d2427a71 | 422 | sp &= ~15; |
c906108c | 423 | |
d2427a71 RH |
424 | /* `Push' arguments on the stack. */ |
425 | for (i = nargs; m_arg--, --i >= 0;) | |
c906108c | 426 | { |
f42a0a33 | 427 | const gdb_byte *contents = m_arg->contents; |
c88e30c0 RH |
428 | int offset = m_arg->offset; |
429 | int len = m_arg->len; | |
430 | ||
431 | /* Copy the bytes destined for registers into arg_reg_buffer. */ | |
432 | if (offset < sizeof(arg_reg_buffer)) | |
433 | { | |
434 | if (offset + len <= sizeof(arg_reg_buffer)) | |
435 | { | |
436 | memcpy (arg_reg_buffer + offset, contents, len); | |
437 | continue; | |
438 | } | |
439 | else | |
440 | { | |
441 | int tlen = sizeof(arg_reg_buffer) - offset; | |
442 | memcpy (arg_reg_buffer + offset, contents, tlen); | |
443 | offset += tlen; | |
444 | contents += tlen; | |
445 | len -= tlen; | |
446 | } | |
447 | } | |
448 | ||
449 | /* Everything else goes to the stack. */ | |
450 | write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len); | |
c906108c | 451 | } |
c88e30c0 | 452 | if (struct_return) |
e17a4113 UW |
453 | store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, |
454 | byte_order, struct_addr); | |
c906108c | 455 | |
d2427a71 RH |
456 | /* Load the argument registers. */ |
457 | for (i = 0; i < required_arg_regs; i++) | |
458 | { | |
09cc52fd RH |
459 | regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i, |
460 | arg_reg_buffer + i*ALPHA_REGISTER_SIZE); | |
461 | regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i, | |
462 | arg_reg_buffer + i*ALPHA_REGISTER_SIZE); | |
d2427a71 | 463 | } |
c906108c | 464 | |
09cc52fd RH |
465 | /* Finally, update the stack pointer. */ |
466 | regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp); | |
467 | ||
c88e30c0 | 468 | return sp; |
c906108c SS |
469 | } |
470 | ||
5ec2bb99 RH |
471 | /* Extract from REGCACHE the value about to be returned from a function |
472 | and copy it into VALBUF. */ | |
d2427a71 | 473 | |
dc129d82 | 474 | static void |
5ec2bb99 | 475 | alpha_extract_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 476 | gdb_byte *valbuf) |
140f9984 | 477 | { |
e17a4113 UW |
478 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
479 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7b5e1cb3 | 480 | int length = TYPE_LENGTH (valtype); |
2a1ce6ec | 481 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 RH |
482 | ULONGEST l; |
483 | ||
484 | switch (TYPE_CODE (valtype)) | |
485 | { | |
486 | case TYPE_CODE_FLT: | |
7b5e1cb3 | 487 | switch (length) |
5ec2bb99 RH |
488 | { |
489 | case 4: | |
490 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer); | |
e17a4113 | 491 | alpha_sts (gdbarch, valbuf, raw_buffer); |
5ec2bb99 RH |
492 | break; |
493 | ||
494 | case 8: | |
495 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
496 | break; | |
497 | ||
24064b5c RH |
498 | case 16: |
499 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
500 | read_memory (l, valbuf, 16); | |
501 | break; | |
502 | ||
5ec2bb99 | 503 | default: |
0963b4bd MS |
504 | internal_error (__FILE__, __LINE__, |
505 | _("unknown floating point width")); | |
5ec2bb99 RH |
506 | } |
507 | break; | |
508 | ||
7b5e1cb3 RH |
509 | case TYPE_CODE_COMPLEX: |
510 | switch (length) | |
511 | { | |
512 | case 8: | |
513 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
514 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
515 | break; | |
516 | ||
517 | case 16: | |
518 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
2a1ce6ec | 519 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); |
7b5e1cb3 RH |
520 | break; |
521 | ||
522 | case 32: | |
523 | regcache_cooked_read_signed (regcache, ALPHA_V0_REGNUM, &l); | |
524 | read_memory (l, valbuf, 32); | |
525 | break; | |
526 | ||
527 | default: | |
0963b4bd MS |
528 | internal_error (__FILE__, __LINE__, |
529 | _("unknown floating point width")); | |
7b5e1cb3 RH |
530 | } |
531 | break; | |
532 | ||
5ec2bb99 RH |
533 | default: |
534 | /* Assume everything else degenerates to an integer. */ | |
535 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
e17a4113 | 536 | store_unsigned_integer (valbuf, length, byte_order, l); |
5ec2bb99 RH |
537 | break; |
538 | } | |
140f9984 JT |
539 | } |
540 | ||
5ec2bb99 RH |
541 | /* Insert the given value into REGCACHE as if it was being |
542 | returned by a function. */ | |
0d056799 | 543 | |
d2427a71 | 544 | static void |
5ec2bb99 | 545 | alpha_store_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 546 | const gdb_byte *valbuf) |
c906108c | 547 | { |
df4df182 | 548 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
d2427a71 | 549 | int length = TYPE_LENGTH (valtype); |
2a1ce6ec | 550 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 | 551 | ULONGEST l; |
d2427a71 | 552 | |
5ec2bb99 | 553 | switch (TYPE_CODE (valtype)) |
c906108c | 554 | { |
5ec2bb99 RH |
555 | case TYPE_CODE_FLT: |
556 | switch (length) | |
557 | { | |
558 | case 4: | |
e17a4113 | 559 | alpha_lds (gdbarch, raw_buffer, valbuf); |
f75d70cc RH |
560 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer); |
561 | break; | |
5ec2bb99 RH |
562 | |
563 | case 8: | |
564 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
565 | break; | |
566 | ||
24064b5c RH |
567 | case 16: |
568 | /* FIXME: 128-bit long doubles are returned like structures: | |
569 | by writing into indirect storage provided by the caller | |
570 | as the first argument. */ | |
323e0a4a | 571 | error (_("Cannot set a 128-bit long double return value.")); |
24064b5c | 572 | |
5ec2bb99 | 573 | default: |
0963b4bd MS |
574 | internal_error (__FILE__, __LINE__, |
575 | _("unknown floating point width")); | |
5ec2bb99 RH |
576 | } |
577 | break; | |
d2427a71 | 578 | |
7b5e1cb3 RH |
579 | case TYPE_CODE_COMPLEX: |
580 | switch (length) | |
581 | { | |
582 | case 8: | |
583 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
584 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
585 | break; | |
586 | ||
587 | case 16: | |
588 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
2a1ce6ec | 589 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); |
7b5e1cb3 RH |
590 | break; |
591 | ||
592 | case 32: | |
593 | /* FIXME: 128-bit long doubles are returned like structures: | |
594 | by writing into indirect storage provided by the caller | |
595 | as the first argument. */ | |
323e0a4a | 596 | error (_("Cannot set a 128-bit long double return value.")); |
7b5e1cb3 RH |
597 | |
598 | default: | |
0963b4bd MS |
599 | internal_error (__FILE__, __LINE__, |
600 | _("unknown floating point width")); | |
7b5e1cb3 RH |
601 | } |
602 | break; | |
603 | ||
5ec2bb99 RH |
604 | default: |
605 | /* Assume everything else degenerates to an integer. */ | |
0ede8eca RH |
606 | /* 32-bit values must be sign-extended to 64 bits |
607 | even if the base data type is unsigned. */ | |
608 | if (length == 4) | |
df4df182 | 609 | valtype = builtin_type (gdbarch)->builtin_int32; |
5ec2bb99 RH |
610 | l = unpack_long (valtype, valbuf); |
611 | regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); | |
612 | break; | |
613 | } | |
c906108c SS |
614 | } |
615 | ||
9823e921 | 616 | static enum return_value_convention |
c055b101 CV |
617 | alpha_return_value (struct gdbarch *gdbarch, struct type *func_type, |
618 | struct type *type, struct regcache *regcache, | |
619 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
9823e921 RH |
620 | { |
621 | enum type_code code = TYPE_CODE (type); | |
622 | ||
623 | if ((code == TYPE_CODE_STRUCT | |
624 | || code == TYPE_CODE_UNION | |
625 | || code == TYPE_CODE_ARRAY) | |
626 | && gdbarch_tdep (gdbarch)->return_in_memory (type)) | |
627 | { | |
628 | if (readbuf) | |
629 | { | |
630 | ULONGEST addr; | |
631 | regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr); | |
632 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
633 | } | |
634 | ||
635 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
636 | } | |
637 | ||
638 | if (readbuf) | |
639 | alpha_extract_return_value (type, regcache, readbuf); | |
640 | if (writebuf) | |
641 | alpha_store_return_value (type, regcache, writebuf); | |
642 | ||
643 | return RETURN_VALUE_REGISTER_CONVENTION; | |
644 | } | |
645 | ||
646 | static int | |
647 | alpha_return_in_memory_always (struct type *type) | |
648 | { | |
649 | return 1; | |
650 | } | |
d2427a71 | 651 | \f |
2a1ce6ec | 652 | static const gdb_byte * |
67d57894 | 653 | alpha_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 654 | { |
2a1ce6ec | 655 | static const gdb_byte break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ |
c906108c | 656 | |
2a1ce6ec MK |
657 | *len = sizeof(break_insn); |
658 | return break_insn; | |
d2427a71 | 659 | } |
c906108c | 660 | |
d2427a71 RH |
661 | \f |
662 | /* This returns the PC of the first insn after the prologue. | |
663 | If we can't find the prologue, then return 0. */ | |
c906108c | 664 | |
d2427a71 RH |
665 | CORE_ADDR |
666 | alpha_after_prologue (CORE_ADDR pc) | |
c906108c | 667 | { |
d2427a71 RH |
668 | struct symtab_and_line sal; |
669 | CORE_ADDR func_addr, func_end; | |
c906108c | 670 | |
d2427a71 | 671 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c5aa993b | 672 | return 0; |
c906108c | 673 | |
d2427a71 RH |
674 | sal = find_pc_line (func_addr, 0); |
675 | if (sal.end < func_end) | |
676 | return sal.end; | |
c5aa993b | 677 | |
d2427a71 RH |
678 | /* The line after the prologue is after the end of the function. In this |
679 | case, tell the caller to find the prologue the hard way. */ | |
680 | return 0; | |
c906108c SS |
681 | } |
682 | ||
d2427a71 RH |
683 | /* Read an instruction from memory at PC, looking through breakpoints. */ |
684 | ||
685 | unsigned int | |
e17a4113 | 686 | alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 687 | { |
e17a4113 | 688 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e8d2d628 | 689 | gdb_byte buf[ALPHA_INSN_SIZE]; |
d2427a71 | 690 | int status; |
c5aa993b | 691 | |
8defab1a | 692 | status = target_read_memory (pc, buf, sizeof (buf)); |
d2427a71 RH |
693 | if (status) |
694 | memory_error (status, pc); | |
e17a4113 | 695 | return extract_unsigned_integer (buf, sizeof (buf), byte_order); |
d2427a71 | 696 | } |
c5aa993b | 697 | |
d2427a71 RH |
698 | /* To skip prologues, I use this predicate. Returns either PC itself |
699 | if the code at PC does not look like a function prologue; otherwise | |
700 | returns an address that (if we're lucky) follows the prologue. If | |
701 | LENIENT, then we must skip everything which is involved in setting | |
702 | up the frame (it's OK to skip more, just so long as we don't skip | |
703 | anything which might clobber the registers which are being saved. */ | |
c906108c | 704 | |
d2427a71 | 705 | static CORE_ADDR |
6093d2eb | 706 | alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 RH |
707 | { |
708 | unsigned long inst; | |
709 | int offset; | |
710 | CORE_ADDR post_prologue_pc; | |
e8d2d628 | 711 | gdb_byte buf[ALPHA_INSN_SIZE]; |
c906108c | 712 | |
d2427a71 RH |
713 | /* Silently return the unaltered pc upon memory errors. |
714 | This could happen on OSF/1 if decode_line_1 tries to skip the | |
715 | prologue for quickstarted shared library functions when the | |
716 | shared library is not yet mapped in. | |
717 | Reading target memory is slow over serial lines, so we perform | |
718 | this check only if the target has shared libraries (which all | |
719 | Alpha targets do). */ | |
e8d2d628 | 720 | if (target_read_memory (pc, buf, sizeof (buf))) |
d2427a71 | 721 | return pc; |
c906108c | 722 | |
d2427a71 RH |
723 | /* See if we can determine the end of the prologue via the symbol table. |
724 | If so, then return either PC, or the PC after the prologue, whichever | |
725 | is greater. */ | |
c906108c | 726 | |
d2427a71 RH |
727 | post_prologue_pc = alpha_after_prologue (pc); |
728 | if (post_prologue_pc != 0) | |
729 | return max (pc, post_prologue_pc); | |
c906108c | 730 | |
d2427a71 RH |
731 | /* Can't determine prologue from the symbol table, need to examine |
732 | instructions. */ | |
dc1b0db2 | 733 | |
0963b4bd | 734 | /* Skip the typical prologue instructions. These are the stack adjustment |
d2427a71 RH |
735 | instruction and the instructions that save registers on the stack |
736 | or in the gcc frame. */ | |
e8d2d628 | 737 | for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE) |
d2427a71 | 738 | { |
e17a4113 | 739 | inst = alpha_read_insn (gdbarch, pc + offset); |
c906108c | 740 | |
d2427a71 RH |
741 | if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */ |
742 | continue; | |
743 | if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */ | |
744 | continue; | |
745 | if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ | |
746 | continue; | |
747 | if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */ | |
748 | continue; | |
c906108c | 749 | |
d2427a71 RH |
750 | if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */ |
751 | || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */ | |
752 | && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */ | |
753 | continue; | |
c906108c | 754 | |
d2427a71 RH |
755 | if (inst == 0x47de040f) /* bis sp,sp,fp */ |
756 | continue; | |
757 | if (inst == 0x47fe040f) /* bis zero,sp,fp */ | |
758 | continue; | |
c906108c | 759 | |
d2427a71 | 760 | break; |
c906108c | 761 | } |
d2427a71 RH |
762 | return pc + offset; |
763 | } | |
c906108c | 764 | |
46ad3598 UW |
765 | \f |
766 | static const int ldl_l_opcode = 0x2a; | |
767 | static const int ldq_l_opcode = 0x2b; | |
768 | static const int stl_c_opcode = 0x2e; | |
769 | static const int stq_c_opcode = 0x2f; | |
770 | ||
771 | /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L | |
772 | instruction and ending with a STL_C/STQ_C instruction. If such a sequence | |
773 | is found, attempt to step through it. A breakpoint is placed at the end of | |
774 | the sequence. */ | |
775 | ||
776 | int | |
777 | alpha_deal_with_atomic_sequence (struct frame_info *frame) | |
778 | { | |
779 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
780 | struct address_space *aspace = get_frame_address_space (frame); | |
781 | CORE_ADDR pc = get_frame_pc (frame); | |
782 | CORE_ADDR breaks[2] = {-1, -1}; | |
783 | CORE_ADDR loc = pc; | |
784 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ | |
785 | unsigned int insn = alpha_read_insn (gdbarch, loc); | |
786 | int insn_count; | |
787 | int index; | |
788 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
789 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
790 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
791 | ||
792 | /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ | |
793 | if (INSN_OPCODE (insn) != ldl_l_opcode | |
794 | && INSN_OPCODE (insn) != ldq_l_opcode) | |
795 | return 0; | |
796 | ||
797 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
798 | instructions. */ | |
799 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
800 | { | |
801 | loc += ALPHA_INSN_SIZE; | |
802 | insn = alpha_read_insn (gdbarch, loc); | |
803 | ||
804 | /* Assume that there is at most one branch in the atomic | |
805 | sequence. If a branch is found, put a breakpoint in | |
806 | its destination address. */ | |
807 | if (INSN_OPCODE (insn) >= br_opcode) | |
808 | { | |
809 | int immediate = (insn & 0x001fffff) << 2; | |
810 | ||
811 | immediate = (immediate ^ 0x400000) - 0x400000; | |
812 | ||
813 | if (bc_insn_count >= 1) | |
814 | return 0; /* More than one branch found, fallback | |
815 | to the standard single-step code. */ | |
816 | ||
817 | breaks[1] = loc + ALPHA_INSN_SIZE + immediate; | |
818 | ||
819 | bc_insn_count++; | |
820 | last_breakpoint++; | |
821 | } | |
822 | ||
823 | if (INSN_OPCODE (insn) == stl_c_opcode | |
824 | || INSN_OPCODE (insn) == stq_c_opcode) | |
825 | break; | |
826 | } | |
827 | ||
828 | /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ | |
829 | if (INSN_OPCODE (insn) != stl_c_opcode | |
830 | && INSN_OPCODE (insn) != stq_c_opcode) | |
831 | return 0; | |
832 | ||
833 | closing_insn = loc; | |
834 | loc += ALPHA_INSN_SIZE; | |
835 | ||
836 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
837 | breaks[0] = loc; | |
838 | ||
839 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
840 | placed (branch instruction's destination) anywhere in sequence. */ | |
841 | if (last_breakpoint | |
842 | && (breaks[1] == breaks[0] | |
843 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
844 | last_breakpoint = 0; | |
845 | ||
846 | /* Effectively inserts the breakpoints. */ | |
847 | for (index = 0; index <= last_breakpoint; index++) | |
848 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | |
849 | ||
850 | return 1; | |
851 | } | |
852 | ||
d2427a71 RH |
853 | \f |
854 | /* Figure out where the longjmp will land. | |
855 | We expect the first arg to be a pointer to the jmp_buf structure from | |
856 | which we extract the PC (JB_PC) that we will land at. The PC is copied | |
857 | into the "pc". This routine returns true on success. */ | |
c906108c SS |
858 | |
859 | static int | |
60ade65d | 860 | alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 861 | { |
e17a4113 UW |
862 | struct gdbarch *gdbarch = get_frame_arch (frame); |
863 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
864 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d2427a71 | 865 | CORE_ADDR jb_addr; |
2a1ce6ec | 866 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
c906108c | 867 | |
60ade65d | 868 | jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM); |
c906108c | 869 | |
d2427a71 RH |
870 | if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size), |
871 | raw_buffer, tdep->jb_elt_size)) | |
c906108c | 872 | return 0; |
d2427a71 | 873 | |
e17a4113 | 874 | *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order); |
d2427a71 | 875 | return 1; |
c906108c SS |
876 | } |
877 | ||
d2427a71 RH |
878 | \f |
879 | /* Frame unwinder for signal trampolines. We use alpha tdep bits that | |
880 | describe the location and shape of the sigcontext structure. After | |
881 | that, all registers are in memory, so it's easy. */ | |
882 | /* ??? Shouldn't we be able to do this generically, rather than with | |
883 | OSABI data specific to Alpha? */ | |
884 | ||
885 | struct alpha_sigtramp_unwind_cache | |
c906108c | 886 | { |
d2427a71 RH |
887 | CORE_ADDR sigcontext_addr; |
888 | }; | |
c906108c | 889 | |
d2427a71 | 890 | static struct alpha_sigtramp_unwind_cache * |
6834c9bb | 891 | alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
d2427a71 RH |
892 | void **this_prologue_cache) |
893 | { | |
894 | struct alpha_sigtramp_unwind_cache *info; | |
895 | struct gdbarch_tdep *tdep; | |
c906108c | 896 | |
d2427a71 RH |
897 | if (*this_prologue_cache) |
898 | return *this_prologue_cache; | |
c906108c | 899 | |
d2427a71 RH |
900 | info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); |
901 | *this_prologue_cache = info; | |
c906108c | 902 | |
6834c9bb JB |
903 | tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
904 | info->sigcontext_addr = tdep->sigcontext_addr (this_frame); | |
c906108c | 905 | |
d2427a71 | 906 | return info; |
c906108c SS |
907 | } |
908 | ||
138e7be5 MK |
909 | /* Return the address of REGNUM in a sigtramp frame. Since this is |
910 | all arithmetic, it doesn't seem worthwhile to cache it. */ | |
c5aa993b | 911 | |
d2427a71 | 912 | static CORE_ADDR |
be8626e0 MD |
913 | alpha_sigtramp_register_address (struct gdbarch *gdbarch, |
914 | CORE_ADDR sigcontext_addr, int regnum) | |
d2427a71 | 915 | { |
be8626e0 | 916 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
138e7be5 MK |
917 | |
918 | if (regnum >= 0 && regnum < 32) | |
919 | return sigcontext_addr + tdep->sc_regs_offset + regnum * 8; | |
920 | else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32) | |
921 | return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8; | |
922 | else if (regnum == ALPHA_PC_REGNUM) | |
923 | return sigcontext_addr + tdep->sc_pc_offset; | |
c5aa993b | 924 | |
d2427a71 | 925 | return 0; |
c906108c SS |
926 | } |
927 | ||
d2427a71 RH |
928 | /* Given a GDB frame, determine the address of the calling function's |
929 | frame. This will be used to create a new GDB frame struct. */ | |
140f9984 | 930 | |
dc129d82 | 931 | static void |
6834c9bb | 932 | alpha_sigtramp_frame_this_id (struct frame_info *this_frame, |
d2427a71 RH |
933 | void **this_prologue_cache, |
934 | struct frame_id *this_id) | |
c906108c | 935 | { |
6834c9bb | 936 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
be8626e0 | 937 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d2427a71 | 938 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 939 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 RH |
940 | CORE_ADDR stack_addr, code_addr; |
941 | ||
942 | /* If the OSABI couldn't locate the sigcontext, give up. */ | |
943 | if (info->sigcontext_addr == 0) | |
944 | return; | |
945 | ||
946 | /* If we have dynamic signal trampolines, find their start. | |
947 | If we do not, then we must assume there is a symbol record | |
948 | that can provide the start address. */ | |
d2427a71 | 949 | if (tdep->dynamic_sigtramp_offset) |
c906108c | 950 | { |
d2427a71 | 951 | int offset; |
6834c9bb | 952 | code_addr = get_frame_pc (this_frame); |
e17a4113 | 953 | offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr); |
d2427a71 RH |
954 | if (offset >= 0) |
955 | code_addr -= offset; | |
c906108c | 956 | else |
d2427a71 | 957 | code_addr = 0; |
c906108c | 958 | } |
d2427a71 | 959 | else |
6834c9bb | 960 | code_addr = get_frame_func (this_frame); |
c906108c | 961 | |
d2427a71 | 962 | /* The stack address is trivially read from the sigcontext. */ |
be8626e0 | 963 | stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr, |
d2427a71 | 964 | ALPHA_SP_REGNUM); |
6834c9bb | 965 | stack_addr = get_frame_memory_unsigned (this_frame, stack_addr, |
b21fd293 | 966 | ALPHA_REGISTER_SIZE); |
c906108c | 967 | |
d2427a71 | 968 | *this_id = frame_id_build (stack_addr, code_addr); |
c906108c SS |
969 | } |
970 | ||
d2427a71 | 971 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
c906108c | 972 | |
6834c9bb JB |
973 | static struct value * |
974 | alpha_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
975 | void **this_prologue_cache, int regnum) | |
c906108c | 976 | { |
d2427a71 | 977 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 978 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 | 979 | CORE_ADDR addr; |
c906108c | 980 | |
d2427a71 | 981 | if (info->sigcontext_addr != 0) |
c906108c | 982 | { |
d2427a71 | 983 | /* All integer and fp registers are stored in memory. */ |
6834c9bb | 984 | addr = alpha_sigtramp_register_address (get_frame_arch (this_frame), |
be8626e0 | 985 | info->sigcontext_addr, regnum); |
d2427a71 | 986 | if (addr != 0) |
6834c9bb | 987 | return frame_unwind_got_memory (this_frame, regnum, addr); |
c906108c SS |
988 | } |
989 | ||
d2427a71 RH |
990 | /* This extra register may actually be in the sigcontext, but our |
991 | current description of it in alpha_sigtramp_frame_unwind_cache | |
992 | doesn't include it. Too bad. Fall back on whatever's in the | |
993 | outer frame. */ | |
6834c9bb | 994 | return frame_unwind_got_register (this_frame, regnum, regnum); |
d2427a71 | 995 | } |
c906108c | 996 | |
6834c9bb JB |
997 | static int |
998 | alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
999 | struct frame_info *this_frame, | |
1000 | void **this_prologue_cache) | |
d2427a71 | 1001 | { |
6834c9bb JB |
1002 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1003 | CORE_ADDR pc = get_frame_pc (this_frame); | |
d2427a71 | 1004 | char *name; |
c906108c | 1005 | |
f2524b93 AC |
1006 | /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead |
1007 | look at tramp-frame.h and other simplier per-architecture | |
1008 | sigtramp unwinders. */ | |
1009 | ||
1010 | /* We shouldn't even bother to try if the OSABI didn't register a | |
1011 | sigcontext_addr handler or pc_in_sigtramp hander. */ | |
ec7cc0e8 | 1012 | if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL) |
6834c9bb | 1013 | return 0; |
ec7cc0e8 | 1014 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL) |
6834c9bb | 1015 | return 0; |
c906108c | 1016 | |
d2427a71 RH |
1017 | /* Otherwise we should be in a signal frame. */ |
1018 | find_pc_partial_function (pc, &name, NULL, NULL); | |
e17a4113 | 1019 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name)) |
6834c9bb | 1020 | return 1; |
c906108c | 1021 | |
6834c9bb | 1022 | return 0; |
c906108c | 1023 | } |
6834c9bb JB |
1024 | |
1025 | static const struct frame_unwind alpha_sigtramp_frame_unwind = { | |
1026 | SIGTRAMP_FRAME, | |
8fbca658 | 1027 | default_frame_unwind_stop_reason, |
6834c9bb JB |
1028 | alpha_sigtramp_frame_this_id, |
1029 | alpha_sigtramp_frame_prev_register, | |
1030 | NULL, | |
1031 | alpha_sigtramp_frame_sniffer | |
1032 | }; | |
1033 | ||
d2427a71 | 1034 | \f |
c906108c | 1035 | |
d2427a71 RH |
1036 | /* Heuristic_proc_start may hunt through the text section for a long |
1037 | time across a 2400 baud serial line. Allows the user to limit this | |
1038 | search. */ | |
1039 | static unsigned int heuristic_fence_post = 0; | |
c906108c | 1040 | |
d2427a71 RH |
1041 | /* Attempt to locate the start of the function containing PC. We assume that |
1042 | the previous function ends with an about_to_return insn. Not foolproof by | |
1043 | any means, since gcc is happy to put the epilogue in the middle of a | |
1044 | function. But we're guessing anyway... */ | |
c906108c | 1045 | |
d2427a71 | 1046 | static CORE_ADDR |
be8626e0 | 1047 | alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 | 1048 | { |
be8626e0 | 1049 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d2427a71 RH |
1050 | CORE_ADDR last_non_nop = pc; |
1051 | CORE_ADDR fence = pc - heuristic_fence_post; | |
1052 | CORE_ADDR orig_pc = pc; | |
fbe586ae | 1053 | CORE_ADDR func; |
d6b48e9c | 1054 | struct inferior *inf; |
9e0b60a8 | 1055 | |
d2427a71 RH |
1056 | if (pc == 0) |
1057 | return 0; | |
9e0b60a8 | 1058 | |
fbe586ae RH |
1059 | /* First see if we can find the start of the function from minimal |
1060 | symbol information. This can succeed with a binary that doesn't | |
1061 | have debug info, but hasn't been stripped. */ | |
1062 | func = get_pc_function_start (pc); | |
1063 | if (func) | |
1064 | return func; | |
1065 | ||
d2427a71 RH |
1066 | if (heuristic_fence_post == UINT_MAX |
1067 | || fence < tdep->vm_min_address) | |
1068 | fence = tdep->vm_min_address; | |
c906108c | 1069 | |
d2427a71 RH |
1070 | /* Search back for previous return; also stop at a 0, which might be |
1071 | seen for instance before the start of a code section. Don't include | |
1072 | nops, since this usually indicates padding between functions. */ | |
e8d2d628 | 1073 | for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE) |
c906108c | 1074 | { |
e17a4113 | 1075 | unsigned int insn = alpha_read_insn (gdbarch, pc); |
d2427a71 | 1076 | switch (insn) |
c906108c | 1077 | { |
d2427a71 RH |
1078 | case 0: /* invalid insn */ |
1079 | case 0x6bfa8001: /* ret $31,($26),1 */ | |
1080 | return last_non_nop; | |
1081 | ||
1082 | case 0x2ffe0000: /* unop: ldq_u $31,0($30) */ | |
1083 | case 0x47ff041f: /* nop: bis $31,$31,$31 */ | |
1084 | break; | |
1085 | ||
1086 | default: | |
1087 | last_non_nop = pc; | |
1088 | break; | |
c906108c | 1089 | } |
d2427a71 | 1090 | } |
c906108c | 1091 | |
d6b48e9c PA |
1092 | inf = current_inferior (); |
1093 | ||
d2427a71 RH |
1094 | /* It's not clear to me why we reach this point when stopping quietly, |
1095 | but with this test, at least we don't print out warnings for every | |
1096 | child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 1097 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
d2427a71 RH |
1098 | { |
1099 | static int blurb_printed = 0; | |
c906108c | 1100 | |
d2427a71 | 1101 | if (fence == tdep->vm_min_address) |
323e0a4a | 1102 | warning (_("Hit beginning of text section without finding \ |
5af949e3 | 1103 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1104 | else |
323e0a4a | 1105 | warning (_("Hit heuristic-fence-post without finding \ |
5af949e3 | 1106 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1107 | |
d2427a71 RH |
1108 | if (!blurb_printed) |
1109 | { | |
323e0a4a | 1110 | printf_filtered (_("\ |
d2427a71 RH |
1111 | This warning occurs if you are debugging a function without any symbols\n\ |
1112 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
1113 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
1114 | \n\ | |
1115 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
323e0a4a | 1116 | (more likely) you have encountered a bug in GDB.\n")); |
d2427a71 RH |
1117 | blurb_printed = 1; |
1118 | } | |
1119 | } | |
c906108c | 1120 | |
d2427a71 RH |
1121 | return 0; |
1122 | } | |
c906108c | 1123 | |
07ea644b MD |
1124 | /* Fallback alpha frame unwinder. Uses instruction scanning and knows |
1125 | something about the traditional layout of alpha stack frames. */ | |
1126 | ||
1127 | struct alpha_heuristic_unwind_cache | |
1128 | { | |
1129 | CORE_ADDR vfp; | |
1130 | CORE_ADDR start_pc; | |
1131 | struct trad_frame_saved_reg *saved_regs; | |
1132 | int return_reg; | |
1133 | }; | |
1134 | ||
3a48e6ff JG |
1135 | /* If a probing loop sequence starts at PC, simulate it and compute |
1136 | FRAME_SIZE and PC after its execution. Otherwise, return with PC and | |
1137 | FRAME_SIZE unchanged. */ | |
1138 | ||
1139 | static void | |
1140 | alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc, | |
1141 | int *frame_size) | |
1142 | { | |
1143 | CORE_ADDR cur_pc = *pc; | |
1144 | int cur_frame_size = *frame_size; | |
1145 | int nb_of_iterations, reg_index, reg_probe; | |
1146 | unsigned int insn; | |
1147 | ||
1148 | /* The following pattern is recognized as a probing loop: | |
1149 | ||
1150 | lda REG_INDEX,NB_OF_ITERATIONS | |
1151 | lda REG_PROBE,<immediate>(sp) | |
1152 | ||
1153 | LOOP_START: | |
1154 | stq zero,<immediate>(REG_PROBE) | |
1155 | subq REG_INDEX,0x1,REG_INDEX | |
1156 | lda REG_PROBE,<immediate>(REG_PROBE) | |
1157 | bne REG_INDEX, LOOP_START | |
1158 | ||
1159 | lda sp,<immediate>(REG_PROBE) | |
1160 | ||
1161 | If anything different is found, the function returns without | |
1162 | changing PC and FRAME_SIZE. Otherwise, PC will point immediately | |
0963b4bd | 1163 | after this sequence, and FRAME_SIZE will be updated. */ |
3a48e6ff JG |
1164 | |
1165 | /* lda REG_INDEX,NB_OF_ITERATIONS */ | |
1166 | ||
1167 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1168 | if (INSN_OPCODE (insn) != lda_opcode) | |
1169 | return; | |
1170 | reg_index = MEM_RA (insn); | |
1171 | nb_of_iterations = MEM_DISP (insn); | |
1172 | ||
1173 | /* lda REG_PROBE,<immediate>(sp) */ | |
1174 | ||
1175 | cur_pc += ALPHA_INSN_SIZE; | |
1176 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1177 | if (INSN_OPCODE (insn) != lda_opcode | |
1178 | || MEM_RB (insn) != ALPHA_SP_REGNUM) | |
1179 | return; | |
1180 | reg_probe = MEM_RA (insn); | |
1181 | cur_frame_size -= MEM_DISP (insn); | |
1182 | ||
1183 | /* stq zero,<immediate>(REG_PROBE) */ | |
1184 | ||
1185 | cur_pc += ALPHA_INSN_SIZE; | |
1186 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1187 | if (INSN_OPCODE (insn) != stq_opcode | |
1188 | || MEM_RA (insn) != 0x1f | |
1189 | || MEM_RB (insn) != reg_probe) | |
1190 | return; | |
1191 | ||
1192 | /* subq REG_INDEX,0x1,REG_INDEX */ | |
1193 | ||
1194 | cur_pc += ALPHA_INSN_SIZE; | |
1195 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1196 | if (INSN_OPCODE (insn) != subq_opcode | |
1197 | || !OPR_HAS_IMMEDIATE (insn) | |
1198 | || OPR_FUNCTION (insn) != subq_function | |
1199 | || OPR_LIT(insn) != 1 | |
1200 | || OPR_RA (insn) != reg_index | |
1201 | || OPR_RC (insn) != reg_index) | |
1202 | return; | |
1203 | ||
1204 | /* lda REG_PROBE,<immediate>(REG_PROBE) */ | |
1205 | ||
1206 | cur_pc += ALPHA_INSN_SIZE; | |
1207 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1208 | if (INSN_OPCODE (insn) != lda_opcode | |
1209 | || MEM_RA (insn) != reg_probe | |
1210 | || MEM_RB (insn) != reg_probe) | |
1211 | return; | |
1212 | cur_frame_size -= MEM_DISP (insn) * nb_of_iterations; | |
1213 | ||
1214 | /* bne REG_INDEX, LOOP_START */ | |
1215 | ||
1216 | cur_pc += ALPHA_INSN_SIZE; | |
1217 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1218 | if (INSN_OPCODE (insn) != bne_opcode | |
1219 | || MEM_RA (insn) != reg_index) | |
1220 | return; | |
1221 | ||
1222 | /* lda sp,<immediate>(REG_PROBE) */ | |
1223 | ||
1224 | cur_pc += ALPHA_INSN_SIZE; | |
1225 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1226 | if (INSN_OPCODE (insn) != lda_opcode | |
1227 | || MEM_RA (insn) != ALPHA_SP_REGNUM | |
1228 | || MEM_RB (insn) != reg_probe) | |
1229 | return; | |
1230 | cur_frame_size -= MEM_DISP (insn); | |
1231 | ||
1232 | *pc = cur_pc; | |
1233 | *frame_size = cur_frame_size; | |
1234 | } | |
1235 | ||
fbe586ae | 1236 | static struct alpha_heuristic_unwind_cache * |
6834c9bb | 1237 | alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame, |
d2427a71 RH |
1238 | void **this_prologue_cache, |
1239 | CORE_ADDR start_pc) | |
1240 | { | |
6834c9bb | 1241 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
d2427a71 RH |
1242 | struct alpha_heuristic_unwind_cache *info; |
1243 | ULONGEST val; | |
1244 | CORE_ADDR limit_pc, cur_pc; | |
1245 | int frame_reg, frame_size, return_reg, reg; | |
c906108c | 1246 | |
d2427a71 RH |
1247 | if (*this_prologue_cache) |
1248 | return *this_prologue_cache; | |
c906108c | 1249 | |
d2427a71 RH |
1250 | info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); |
1251 | *this_prologue_cache = info; | |
6834c9bb | 1252 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1253 | |
6834c9bb | 1254 | limit_pc = get_frame_pc (this_frame); |
d2427a71 | 1255 | if (start_pc == 0) |
be8626e0 | 1256 | start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc); |
d2427a71 | 1257 | info->start_pc = start_pc; |
c906108c | 1258 | |
d2427a71 RH |
1259 | frame_reg = ALPHA_SP_REGNUM; |
1260 | frame_size = 0; | |
1261 | return_reg = -1; | |
c906108c | 1262 | |
d2427a71 RH |
1263 | /* If we've identified a likely place to start, do code scanning. */ |
1264 | if (start_pc != 0) | |
c5aa993b | 1265 | { |
d2427a71 RH |
1266 | /* Limit the forward search to 50 instructions. */ |
1267 | if (start_pc + 200 < limit_pc) | |
1268 | limit_pc = start_pc + 200; | |
c5aa993b | 1269 | |
e8d2d628 | 1270 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE) |
d2427a71 | 1271 | { |
e17a4113 | 1272 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1273 | |
d2427a71 RH |
1274 | if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ |
1275 | { | |
1276 | if (word & 0x8000) | |
1277 | { | |
1278 | /* Consider only the first stack allocation instruction | |
0963b4bd | 1279 | to contain the static size of the frame. */ |
d2427a71 RH |
1280 | if (frame_size == 0) |
1281 | frame_size = (-word) & 0xffff; | |
1282 | } | |
1283 | else | |
1284 | { | |
1285 | /* Exit loop if a positive stack adjustment is found, which | |
1286 | usually means that the stack cleanup code in the function | |
1287 | epilogue is reached. */ | |
1288 | break; | |
1289 | } | |
1290 | } | |
1291 | else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ | |
1292 | { | |
1293 | reg = (word & 0x03e00000) >> 21; | |
1294 | ||
d15bfd3a AC |
1295 | /* Ignore this instruction if we have already encountered |
1296 | an instruction saving the same register earlier in the | |
1297 | function code. The current instruction does not tell | |
1298 | us where the original value upon function entry is saved. | |
1299 | All it says is that the function we are scanning reused | |
1300 | that register for some computation of its own, and is now | |
1301 | saving its result. */ | |
07ea644b | 1302 | if (trad_frame_addr_p(info->saved_regs, reg)) |
d15bfd3a AC |
1303 | continue; |
1304 | ||
d2427a71 RH |
1305 | if (reg == 31) |
1306 | continue; | |
1307 | ||
1308 | /* Do not compute the address where the register was saved yet, | |
1309 | because we don't know yet if the offset will need to be | |
1310 | relative to $sp or $fp (we can not compute the address | |
1311 | relative to $sp if $sp is updated during the execution of | |
1312 | the current subroutine, for instance when doing some alloca). | |
1313 | So just store the offset for the moment, and compute the | |
1314 | address later when we know whether this frame has a frame | |
1315 | pointer or not. */ | |
1316 | /* Hack: temporarily add one, so that the offset is non-zero | |
1317 | and we can tell which registers have save offsets below. */ | |
07ea644b | 1318 | info->saved_regs[reg].addr = (word & 0xffff) + 1; |
d2427a71 RH |
1319 | |
1320 | /* Starting with OSF/1-3.2C, the system libraries are shipped | |
1321 | without local symbols, but they still contain procedure | |
1322 | descriptors without a symbol reference. GDB is currently | |
1323 | unable to find these procedure descriptors and uses | |
1324 | heuristic_proc_desc instead. | |
1325 | As some low level compiler support routines (__div*, __add*) | |
1326 | use a non-standard return address register, we have to | |
1327 | add some heuristics to determine the return address register, | |
1328 | or stepping over these routines will fail. | |
1329 | Usually the return address register is the first register | |
1330 | saved on the stack, but assembler optimization might | |
1331 | rearrange the register saves. | |
1332 | So we recognize only a few registers (t7, t9, ra) within | |
1333 | the procedure prologue as valid return address registers. | |
1334 | If we encounter a return instruction, we extract the | |
7a9dd1b2 | 1335 | return address register from it. |
d2427a71 RH |
1336 | |
1337 | FIXME: Rewriting GDB to access the procedure descriptors, | |
0963b4bd MS |
1338 | e.g. via the minimal symbol table, might obviate this |
1339 | hack. */ | |
d2427a71 RH |
1340 | if (return_reg == -1 |
1341 | && cur_pc < (start_pc + 80) | |
1342 | && (reg == ALPHA_T7_REGNUM | |
1343 | || reg == ALPHA_T9_REGNUM | |
1344 | || reg == ALPHA_RA_REGNUM)) | |
1345 | return_reg = reg; | |
1346 | } | |
1347 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1348 | return_reg = (word >> 16) & 0x1f; | |
1349 | else if (word == 0x47de040f) /* bis sp,sp,fp */ | |
1350 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
1351 | else if (word == 0x47fe040f) /* bis zero,sp,fp */ | |
1352 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
3a48e6ff JG |
1353 | |
1354 | alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size); | |
d2427a71 | 1355 | } |
c5aa993b | 1356 | |
d2427a71 RH |
1357 | /* If we haven't found a valid return address register yet, keep |
1358 | searching in the procedure prologue. */ | |
1359 | if (return_reg == -1) | |
1360 | { | |
1361 | while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80)) | |
1362 | { | |
e17a4113 | 1363 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1364 | |
d2427a71 RH |
1365 | if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ |
1366 | { | |
1367 | reg = (word & 0x03e00000) >> 21; | |
1368 | if (reg == ALPHA_T7_REGNUM | |
1369 | || reg == ALPHA_T9_REGNUM | |
1370 | || reg == ALPHA_RA_REGNUM) | |
1371 | { | |
1372 | return_reg = reg; | |
1373 | break; | |
1374 | } | |
1375 | } | |
1376 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1377 | { | |
1378 | return_reg = (word >> 16) & 0x1f; | |
1379 | break; | |
1380 | } | |
85b32d22 | 1381 | |
e8d2d628 | 1382 | cur_pc += ALPHA_INSN_SIZE; |
d2427a71 RH |
1383 | } |
1384 | } | |
c906108c | 1385 | } |
c906108c | 1386 | |
d2427a71 RH |
1387 | /* Failing that, do default to the customary RA. */ |
1388 | if (return_reg == -1) | |
1389 | return_reg = ALPHA_RA_REGNUM; | |
1390 | info->return_reg = return_reg; | |
f8453e34 | 1391 | |
6834c9bb | 1392 | val = get_frame_register_unsigned (this_frame, frame_reg); |
d2427a71 | 1393 | info->vfp = val + frame_size; |
c906108c | 1394 | |
d2427a71 RH |
1395 | /* Convert offsets to absolute addresses. See above about adding |
1396 | one to the offsets to make all detected offsets non-zero. */ | |
1397 | for (reg = 0; reg < ALPHA_NUM_REGS; ++reg) | |
07ea644b MD |
1398 | if (trad_frame_addr_p(info->saved_regs, reg)) |
1399 | info->saved_regs[reg].addr += val - 1; | |
d2427a71 | 1400 | |
bfd66dd9 JB |
1401 | /* The stack pointer of the previous frame is computed by popping |
1402 | the current stack frame. */ | |
1403 | if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM)) | |
1404 | trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp); | |
1405 | ||
d2427a71 | 1406 | return info; |
c906108c | 1407 | } |
c906108c | 1408 | |
d2427a71 RH |
1409 | /* Given a GDB frame, determine the address of the calling function's |
1410 | frame. This will be used to create a new GDB frame struct. */ | |
1411 | ||
fbe586ae | 1412 | static void |
6834c9bb JB |
1413 | alpha_heuristic_frame_this_id (struct frame_info *this_frame, |
1414 | void **this_prologue_cache, | |
1415 | struct frame_id *this_id) | |
c906108c | 1416 | { |
d2427a71 | 1417 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1418 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1419 | |
d2427a71 | 1420 | *this_id = frame_id_build (info->vfp, info->start_pc); |
c906108c SS |
1421 | } |
1422 | ||
d2427a71 RH |
1423 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
1424 | ||
6834c9bb JB |
1425 | static struct value * |
1426 | alpha_heuristic_frame_prev_register (struct frame_info *this_frame, | |
1427 | void **this_prologue_cache, int regnum) | |
c906108c | 1428 | { |
d2427a71 | 1429 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1430 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
d2427a71 RH |
1431 | |
1432 | /* The PC of the previous frame is stored in the link register of | |
1433 | the current frame. Frob regnum so that we pull the value from | |
1434 | the correct place. */ | |
1435 | if (regnum == ALPHA_PC_REGNUM) | |
1436 | regnum = info->return_reg; | |
1437 | ||
6834c9bb | 1438 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
95b80706 JT |
1439 | } |
1440 | ||
d2427a71 RH |
1441 | static const struct frame_unwind alpha_heuristic_frame_unwind = { |
1442 | NORMAL_FRAME, | |
8fbca658 | 1443 | default_frame_unwind_stop_reason, |
d2427a71 | 1444 | alpha_heuristic_frame_this_id, |
6834c9bb JB |
1445 | alpha_heuristic_frame_prev_register, |
1446 | NULL, | |
1447 | default_frame_sniffer | |
d2427a71 | 1448 | }; |
c906108c | 1449 | |
fbe586ae | 1450 | static CORE_ADDR |
6834c9bb | 1451 | alpha_heuristic_frame_base_address (struct frame_info *this_frame, |
d2427a71 | 1452 | void **this_prologue_cache) |
c906108c | 1453 | { |
d2427a71 | 1454 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1455 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1456 | |
d2427a71 | 1457 | return info->vfp; |
c906108c SS |
1458 | } |
1459 | ||
d2427a71 RH |
1460 | static const struct frame_base alpha_heuristic_frame_base = { |
1461 | &alpha_heuristic_frame_unwind, | |
1462 | alpha_heuristic_frame_base_address, | |
1463 | alpha_heuristic_frame_base_address, | |
1464 | alpha_heuristic_frame_base_address | |
1465 | }; | |
1466 | ||
c906108c | 1467 | /* Just like reinit_frame_cache, but with the right arguments to be |
d2427a71 | 1468 | callable as an sfunc. Used by the "set heuristic-fence-post" command. */ |
c906108c SS |
1469 | |
1470 | static void | |
fba45db2 | 1471 | reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c) |
c906108c SS |
1472 | { |
1473 | reinit_frame_cache (); | |
1474 | } | |
1475 | ||
d2427a71 | 1476 | \f |
d2427a71 RH |
1477 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1478 | dummy frame. The frame ID's base needs to match the TOS value | |
1479 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1480 | breakpoint. */ | |
d734c450 | 1481 | |
d2427a71 | 1482 | static struct frame_id |
6834c9bb | 1483 | alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
0d056799 | 1484 | { |
d2427a71 | 1485 | ULONGEST base; |
6834c9bb JB |
1486 | base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM); |
1487 | return frame_id_build (base, get_frame_pc (this_frame)); | |
0d056799 JT |
1488 | } |
1489 | ||
dc129d82 | 1490 | static CORE_ADDR |
d2427a71 | 1491 | alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
accc6d1f | 1492 | { |
d2427a71 | 1493 | ULONGEST pc; |
11411de3 | 1494 | pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM); |
d2427a71 | 1495 | return pc; |
accc6d1f JT |
1496 | } |
1497 | ||
98a8e1e5 RH |
1498 | \f |
1499 | /* Helper routines for alpha*-nat.c files to move register sets to and | |
1500 | from core files. The UNIQUE pointer is allowed to be NULL, as most | |
1501 | targets don't supply this value in their core files. */ | |
1502 | ||
1503 | void | |
390c1522 UW |
1504 | alpha_supply_int_regs (struct regcache *regcache, int regno, |
1505 | const void *r0_r30, const void *pc, const void *unique) | |
98a8e1e5 | 1506 | { |
2a1ce6ec | 1507 | const gdb_byte *regs = r0_r30; |
98a8e1e5 RH |
1508 | int i; |
1509 | ||
1510 | for (i = 0; i < 31; ++i) | |
1511 | if (regno == i || regno == -1) | |
390c1522 | 1512 | regcache_raw_supply (regcache, i, regs + i * 8); |
98a8e1e5 RH |
1513 | |
1514 | if (regno == ALPHA_ZERO_REGNUM || regno == -1) | |
4a1be8d2 PA |
1515 | { |
1516 | const gdb_byte zero[8] = { 0 }; | |
1517 | ||
1518 | regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero); | |
1519 | } | |
98a8e1e5 RH |
1520 | |
1521 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
390c1522 | 1522 | regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1523 | |
1524 | if (regno == ALPHA_UNIQUE_REGNUM || regno == -1) | |
390c1522 | 1525 | regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1526 | } |
1527 | ||
1528 | void | |
390c1522 UW |
1529 | alpha_fill_int_regs (const struct regcache *regcache, |
1530 | int regno, void *r0_r30, void *pc, void *unique) | |
98a8e1e5 | 1531 | { |
2a1ce6ec | 1532 | gdb_byte *regs = r0_r30; |
98a8e1e5 RH |
1533 | int i; |
1534 | ||
1535 | for (i = 0; i < 31; ++i) | |
1536 | if (regno == i || regno == -1) | |
390c1522 | 1537 | regcache_raw_collect (regcache, i, regs + i * 8); |
98a8e1e5 RH |
1538 | |
1539 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
390c1522 | 1540 | regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1541 | |
1542 | if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1)) | |
390c1522 | 1543 | regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1544 | } |
1545 | ||
1546 | void | |
390c1522 UW |
1547 | alpha_supply_fp_regs (struct regcache *regcache, int regno, |
1548 | const void *f0_f30, const void *fpcr) | |
98a8e1e5 | 1549 | { |
2a1ce6ec | 1550 | const gdb_byte *regs = f0_f30; |
98a8e1e5 RH |
1551 | int i; |
1552 | ||
1553 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1554 | if (regno == i || regno == -1) | |
390c1522 | 1555 | regcache_raw_supply (regcache, i, |
2a1ce6ec | 1556 | regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1557 | |
1558 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
390c1522 | 1559 | regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1560 | } |
1561 | ||
1562 | void | |
390c1522 UW |
1563 | alpha_fill_fp_regs (const struct regcache *regcache, |
1564 | int regno, void *f0_f30, void *fpcr) | |
98a8e1e5 | 1565 | { |
2a1ce6ec | 1566 | gdb_byte *regs = f0_f30; |
98a8e1e5 RH |
1567 | int i; |
1568 | ||
1569 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1570 | if (regno == i || regno == -1) | |
390c1522 | 1571 | regcache_raw_collect (regcache, i, |
2a1ce6ec | 1572 | regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1573 | |
1574 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
390c1522 | 1575 | regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1576 | } |
1577 | ||
d2427a71 | 1578 | \f |
0de94d4b JB |
1579 | |
1580 | /* Return nonzero if the G_floating register value in REG is equal to | |
1581 | zero for FP control instructions. */ | |
1582 | ||
1583 | static int | |
1584 | fp_register_zero_p (LONGEST reg) | |
1585 | { | |
1586 | /* Check that all bits except the sign bit are zero. */ | |
1587 | const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1; | |
1588 | ||
1589 | return ((reg & zero_mask) == 0); | |
1590 | } | |
1591 | ||
1592 | /* Return the value of the sign bit for the G_floating register | |
1593 | value held in REG. */ | |
1594 | ||
1595 | static int | |
1596 | fp_register_sign_bit (LONGEST reg) | |
1597 | { | |
1598 | const LONGEST sign_mask = (LONGEST) 1 << 63; | |
1599 | ||
1600 | return ((reg & sign_mask) != 0); | |
1601 | } | |
1602 | ||
ec32e4be JT |
1603 | /* alpha_software_single_step() is called just before we want to resume |
1604 | the inferior, if we want to single-step it but there is no hardware | |
1605 | or kernel single-step support (NetBSD on Alpha, for example). We find | |
e0cd558a | 1606 | the target of the coming instruction and breakpoint it. */ |
ec32e4be JT |
1607 | |
1608 | static CORE_ADDR | |
0b1b3e42 | 1609 | alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) |
ec32e4be | 1610 | { |
e17a4113 | 1611 | struct gdbarch *gdbarch = get_frame_arch (frame); |
ec32e4be JT |
1612 | unsigned int insn; |
1613 | unsigned int op; | |
551e4f2e | 1614 | int regno; |
ec32e4be JT |
1615 | int offset; |
1616 | LONGEST rav; | |
1617 | ||
e17a4113 | 1618 | insn = alpha_read_insn (gdbarch, pc); |
ec32e4be | 1619 | |
0963b4bd | 1620 | /* Opcode is top 6 bits. */ |
ec32e4be JT |
1621 | op = (insn >> 26) & 0x3f; |
1622 | ||
1623 | if (op == 0x1a) | |
1624 | { | |
1625 | /* Jump format: target PC is: | |
1626 | RB & ~3 */ | |
0b1b3e42 | 1627 | return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3); |
ec32e4be JT |
1628 | } |
1629 | ||
1630 | if ((op & 0x30) == 0x30) | |
1631 | { | |
1632 | /* Branch format: target PC is: | |
1633 | (new PC) + (4 * sext(displacement)) */ | |
f8bf5763 PM |
1634 | if (op == 0x30 /* BR */ |
1635 | || op == 0x34) /* BSR */ | |
ec32e4be JT |
1636 | { |
1637 | branch_taken: | |
1638 | offset = (insn & 0x001fffff); | |
1639 | if (offset & 0x00100000) | |
1640 | offset |= 0xffe00000; | |
e8d2d628 MK |
1641 | offset *= ALPHA_INSN_SIZE; |
1642 | return (pc + ALPHA_INSN_SIZE + offset); | |
ec32e4be JT |
1643 | } |
1644 | ||
1645 | /* Need to determine if branch is taken; read RA. */ | |
551e4f2e JB |
1646 | regno = (insn >> 21) & 0x1f; |
1647 | switch (op) | |
1648 | { | |
1649 | case 0x31: /* FBEQ */ | |
1650 | case 0x36: /* FBGE */ | |
1651 | case 0x37: /* FBGT */ | |
1652 | case 0x33: /* FBLE */ | |
1653 | case 0x32: /* FBLT */ | |
1654 | case 0x35: /* FBNE */ | |
e17a4113 | 1655 | regno += gdbarch_fp0_regnum (gdbarch); |
551e4f2e JB |
1656 | } |
1657 | ||
0b1b3e42 | 1658 | rav = get_frame_register_signed (frame, regno); |
0de94d4b | 1659 | |
ec32e4be JT |
1660 | switch (op) |
1661 | { | |
1662 | case 0x38: /* BLBC */ | |
1663 | if ((rav & 1) == 0) | |
1664 | goto branch_taken; | |
1665 | break; | |
1666 | case 0x3c: /* BLBS */ | |
1667 | if (rav & 1) | |
1668 | goto branch_taken; | |
1669 | break; | |
1670 | case 0x39: /* BEQ */ | |
1671 | if (rav == 0) | |
1672 | goto branch_taken; | |
1673 | break; | |
1674 | case 0x3d: /* BNE */ | |
1675 | if (rav != 0) | |
1676 | goto branch_taken; | |
1677 | break; | |
1678 | case 0x3a: /* BLT */ | |
1679 | if (rav < 0) | |
1680 | goto branch_taken; | |
1681 | break; | |
1682 | case 0x3b: /* BLE */ | |
1683 | if (rav <= 0) | |
1684 | goto branch_taken; | |
1685 | break; | |
1686 | case 0x3f: /* BGT */ | |
1687 | if (rav > 0) | |
1688 | goto branch_taken; | |
1689 | break; | |
1690 | case 0x3e: /* BGE */ | |
1691 | if (rav >= 0) | |
1692 | goto branch_taken; | |
1693 | break; | |
d2427a71 | 1694 | |
0de94d4b JB |
1695 | /* Floating point branches. */ |
1696 | ||
1697 | case 0x31: /* FBEQ */ | |
1698 | if (fp_register_zero_p (rav)) | |
1699 | goto branch_taken; | |
1700 | break; | |
1701 | case 0x36: /* FBGE */ | |
1702 | if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav)) | |
1703 | goto branch_taken; | |
1704 | break; | |
1705 | case 0x37: /* FBGT */ | |
1706 | if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav)) | |
1707 | goto branch_taken; | |
1708 | break; | |
1709 | case 0x33: /* FBLE */ | |
1710 | if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav)) | |
1711 | goto branch_taken; | |
1712 | break; | |
1713 | case 0x32: /* FBLT */ | |
1714 | if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav)) | |
1715 | goto branch_taken; | |
1716 | break; | |
1717 | case 0x35: /* FBNE */ | |
1718 | if (! fp_register_zero_p (rav)) | |
1719 | goto branch_taken; | |
1720 | break; | |
ec32e4be JT |
1721 | } |
1722 | } | |
1723 | ||
1724 | /* Not a branch or branch not taken; target PC is: | |
1725 | pc + 4 */ | |
e8d2d628 | 1726 | return (pc + ALPHA_INSN_SIZE); |
ec32e4be JT |
1727 | } |
1728 | ||
e6590a1b | 1729 | int |
0b1b3e42 | 1730 | alpha_software_single_step (struct frame_info *frame) |
ec32e4be | 1731 | { |
a6d9a66e | 1732 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 1733 | struct address_space *aspace = get_frame_address_space (frame); |
e0cd558a | 1734 | CORE_ADDR pc, next_pc; |
ec32e4be | 1735 | |
0b1b3e42 UW |
1736 | pc = get_frame_pc (frame); |
1737 | next_pc = alpha_next_pc (frame, pc); | |
ec32e4be | 1738 | |
6c95b8df | 1739 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 1740 | return 1; |
c906108c SS |
1741 | } |
1742 | ||
dc129d82 | 1743 | \f |
dc129d82 JT |
1744 | /* Initialize the current architecture based on INFO. If possible, re-use an |
1745 | architecture from ARCHES, which is a list of architectures already created | |
1746 | during this debugging session. | |
1747 | ||
1748 | Called e.g. at program startup, when reading a core file, and when reading | |
1749 | a binary file. */ | |
1750 | ||
1751 | static struct gdbarch * | |
1752 | alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1753 | { | |
1754 | struct gdbarch_tdep *tdep; | |
1755 | struct gdbarch *gdbarch; | |
dc129d82 JT |
1756 | |
1757 | /* Try to determine the ABI of the object we are loading. */ | |
4be87837 | 1758 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
dc129d82 | 1759 | { |
4be87837 DJ |
1760 | /* If it's an ECOFF file, assume it's OSF/1. */ |
1761 | if (bfd_get_flavour (info.abfd) == bfd_target_ecoff_flavour) | |
aff87235 | 1762 | info.osabi = GDB_OSABI_OSF1; |
dc129d82 JT |
1763 | } |
1764 | ||
1765 | /* Find a candidate among extant architectures. */ | |
4be87837 DJ |
1766 | arches = gdbarch_list_lookup_by_info (arches, &info); |
1767 | if (arches != NULL) | |
1768 | return arches->gdbarch; | |
dc129d82 JT |
1769 | |
1770 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
1771 | gdbarch = gdbarch_alloc (&info, tdep); | |
1772 | ||
d2427a71 RH |
1773 | /* Lowest text address. This is used by heuristic_proc_start() |
1774 | to decide when to stop looking. */ | |
594706e6 | 1775 | tdep->vm_min_address = (CORE_ADDR) 0x120000000LL; |
d9b023cc | 1776 | |
36a6271d | 1777 | tdep->dynamic_sigtramp_offset = NULL; |
5868c862 | 1778 | tdep->sigcontext_addr = NULL; |
138e7be5 MK |
1779 | tdep->sc_pc_offset = 2 * 8; |
1780 | tdep->sc_regs_offset = 4 * 8; | |
1781 | tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8; | |
36a6271d | 1782 | |
0963b4bd | 1783 | tdep->jb_pc = -1; /* longjmp support not enabled by default. */ |
accc6d1f | 1784 | |
9823e921 RH |
1785 | tdep->return_in_memory = alpha_return_in_memory_always; |
1786 | ||
dc129d82 JT |
1787 | /* Type sizes */ |
1788 | set_gdbarch_short_bit (gdbarch, 16); | |
1789 | set_gdbarch_int_bit (gdbarch, 32); | |
1790 | set_gdbarch_long_bit (gdbarch, 64); | |
1791 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1792 | set_gdbarch_float_bit (gdbarch, 32); | |
1793 | set_gdbarch_double_bit (gdbarch, 64); | |
1794 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1795 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1796 | ||
1797 | /* Register info */ | |
1798 | set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS); | |
1799 | set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM); | |
dc129d82 JT |
1800 | set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); |
1801 | set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); | |
1802 | ||
1803 | set_gdbarch_register_name (gdbarch, alpha_register_name); | |
c483c494 | 1804 | set_gdbarch_register_type (gdbarch, alpha_register_type); |
dc129d82 JT |
1805 | |
1806 | set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); | |
1807 | set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); | |
1808 | ||
c483c494 RH |
1809 | set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p); |
1810 | set_gdbarch_register_to_value (gdbarch, alpha_register_to_value); | |
1811 | set_gdbarch_value_to_register (gdbarch, alpha_value_to_register); | |
dc129d82 | 1812 | |
615967cb RH |
1813 | set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p); |
1814 | ||
d2427a71 | 1815 | /* Prologue heuristics. */ |
dc129d82 JT |
1816 | set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); |
1817 | ||
5ef165c2 RH |
1818 | /* Disassembler. */ |
1819 | set_gdbarch_print_insn (gdbarch, print_insn_alpha); | |
1820 | ||
d2427a71 | 1821 | /* Call info. */ |
dc129d82 | 1822 | |
9823e921 | 1823 | set_gdbarch_return_value (gdbarch, alpha_return_value); |
dc129d82 JT |
1824 | |
1825 | /* Settings for calling functions in the inferior. */ | |
c88e30c0 | 1826 | set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call); |
d2427a71 RH |
1827 | |
1828 | /* Methods for saving / extracting a dummy frame's ID. */ | |
6834c9bb | 1829 | set_gdbarch_dummy_id (gdbarch, alpha_dummy_id); |
d2427a71 RH |
1830 | |
1831 | /* Return the unwound PC value. */ | |
1832 | set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc); | |
dc129d82 JT |
1833 | |
1834 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
36a6271d | 1835 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
dc129d82 | 1836 | |
95b80706 | 1837 | set_gdbarch_breakpoint_from_pc (gdbarch, alpha_breakpoint_from_pc); |
e8d2d628 | 1838 | set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); |
9d519230 | 1839 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
95b80706 | 1840 | |
46ad3598 UW |
1841 | /* Handles single stepping of atomic sequences. */ |
1842 | set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence); | |
1843 | ||
44dffaac | 1844 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 1845 | gdbarch_init_osabi (info, gdbarch); |
44dffaac | 1846 | |
accc6d1f JT |
1847 | /* Now that we have tuned the configuration, set a few final things |
1848 | based on what the OS ABI has told us. */ | |
1849 | ||
1850 | if (tdep->jb_pc >= 0) | |
1851 | set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target); | |
1852 | ||
6834c9bb JB |
1853 | frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind); |
1854 | frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind); | |
dc129d82 | 1855 | |
d2427a71 | 1856 | frame_base_set_default (gdbarch, &alpha_heuristic_frame_base); |
accc6d1f | 1857 | |
d2427a71 | 1858 | return gdbarch; |
dc129d82 JT |
1859 | } |
1860 | ||
baa490c4 RH |
1861 | void |
1862 | alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
1863 | { | |
6834c9bb | 1864 | dwarf2_append_unwinders (gdbarch); |
336d1bba | 1865 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
baa490c4 RH |
1866 | } |
1867 | ||
a78f21af AC |
1868 | extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */ |
1869 | ||
c906108c | 1870 | void |
fba45db2 | 1871 | _initialize_alpha_tdep (void) |
c906108c SS |
1872 | { |
1873 | struct cmd_list_element *c; | |
1874 | ||
d2427a71 | 1875 | gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); |
c906108c SS |
1876 | |
1877 | /* Let the user set the fence post for heuristic_proc_start. */ | |
1878 | ||
1879 | /* We really would like to have both "0" and "unlimited" work, but | |
1880 | command.c doesn't deal with that. So make it a var_zinteger | |
1881 | because the user can always use "999999" or some such for unlimited. */ | |
edefbb7c AC |
1882 | /* We need to throw away the frame cache when we set this, since it |
1883 | might change our ability to get backtraces. */ | |
1884 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, | |
7915a72c AC |
1885 | &heuristic_fence_post, _("\ |
1886 | Set the distance searched for the start of a function."), _("\ | |
1887 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
1888 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
1889 | program for the start of a function. This command sets the distance of the\n\ | |
323e0a4a | 1890 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 1891 | reinit_frame_cache_sfunc, |
0963b4bd MS |
1892 | NULL, /* FIXME: i18n: The distance searched for |
1893 | the start of a function is \"%d\". */ | |
edefbb7c | 1894 | &setlist, &showlist); |
c906108c | 1895 | } |