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c906108c | 1 | /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. |
0fd88904 | 2 | |
61baf725 | 3 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
d2427a71 RH |
22 | #include "frame-unwind.h" |
23 | #include "frame-base.h" | |
baa490c4 | 24 | #include "dwarf2-frame.h" |
c906108c SS |
25 | #include "inferior.h" |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
30 | #include "dis-asm.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
c5f0f3d0 | 33 | #include "linespec.h" |
4e052eda | 34 | #include "regcache.h" |
615967cb | 35 | #include "reggroups.h" |
dc129d82 | 36 | #include "arch-utils.h" |
4be87837 | 37 | #include "osabi.h" |
fe898f56 | 38 | #include "block.h" |
7d9b040b | 39 | #include "infcall.h" |
07ea644b | 40 | #include "trad-frame.h" |
dc129d82 JT |
41 | |
42 | #include "elf-bfd.h" | |
43 | ||
44 | #include "alpha-tdep.h" | |
325fac50 | 45 | #include <algorithm> |
dc129d82 | 46 | |
3a48e6ff JG |
47 | /* Instruction decoding. The notations for registers, immediates and |
48 | opcodes are the same as the one used in Compaq's Alpha architecture | |
49 | handbook. */ | |
50 | ||
51 | #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26) | |
52 | ||
53 | /* Memory instruction format */ | |
54 | #define MEM_RA(insn) ((insn & 0x03e00000) >> 21) | |
55 | #define MEM_RB(insn) ((insn & 0x001f0000) >> 16) | |
56 | #define MEM_DISP(insn) \ | |
57 | (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff)) | |
58 | ||
59 | static const int lda_opcode = 0x08; | |
60 | static const int stq_opcode = 0x2d; | |
61 | ||
62 | /* Branch instruction format */ | |
63 | #define BR_RA(insn) MEM_RA(insn) | |
64 | ||
46ad3598 | 65 | static const int br_opcode = 0x30; |
3a48e6ff JG |
66 | static const int bne_opcode = 0x3d; |
67 | ||
68 | /* Operate instruction format */ | |
69 | #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5) | |
70 | #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000) | |
71 | #define OPR_RA(insn) MEM_RA(insn) | |
72 | #define OPR_RC(insn) ((insn & 0x1f)) | |
73 | #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13) | |
74 | ||
75 | static const int subq_opcode = 0x10; | |
76 | static const int subq_function = 0x29; | |
77 | ||
c906108c | 78 | \f |
515921d7 JB |
79 | /* Return the name of the REGNO register. |
80 | ||
81 | An empty name corresponds to a register number that used to | |
0963b4bd | 82 | be used for a virtual register. That virtual register has |
515921d7 JB |
83 | been removed, but the index is still reserved to maintain |
84 | compatibility with existing remote alpha targets. */ | |
85 | ||
fa88f677 | 86 | static const char * |
d93859e2 | 87 | alpha_register_name (struct gdbarch *gdbarch, int regno) |
636a6dfc | 88 | { |
5ab84872 | 89 | static const char * const register_names[] = |
636a6dfc JT |
90 | { |
91 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", | |
92 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", | |
93 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", | |
94 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", | |
95 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
96 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
97 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
98 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", | |
44d88583 | 99 | "pc", "", "unique" |
636a6dfc JT |
100 | }; |
101 | ||
102 | if (regno < 0) | |
5ab84872 | 103 | return NULL; |
e8d2d628 | 104 | if (regno >= ARRAY_SIZE(register_names)) |
5ab84872 RH |
105 | return NULL; |
106 | return register_names[regno]; | |
636a6dfc | 107 | } |
d734c450 | 108 | |
dc129d82 | 109 | static int |
64a3914f | 110 | alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 111 | { |
4a1be8d2 | 112 | return (strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
113 | } |
114 | ||
dc129d82 | 115 | static int |
64a3914f | 116 | alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) |
d734c450 | 117 | { |
515921d7 | 118 | return (regno == ALPHA_ZERO_REGNUM |
64a3914f | 119 | || strlen (alpha_register_name (gdbarch, regno)) == 0); |
d734c450 JT |
120 | } |
121 | ||
dc129d82 | 122 | static struct type * |
c483c494 | 123 | alpha_register_type (struct gdbarch *gdbarch, int regno) |
0d056799 | 124 | { |
72667056 | 125 | if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) |
0dfff4cb | 126 | return builtin_type (gdbarch)->builtin_data_ptr; |
72667056 | 127 | if (regno == ALPHA_PC_REGNUM) |
0dfff4cb | 128 | return builtin_type (gdbarch)->builtin_func_ptr; |
72667056 RH |
129 | |
130 | /* Don't need to worry about little vs big endian until | |
131 | some jerk tries to port to alpha-unicosmk. */ | |
b38b6be2 | 132 | if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) |
27067745 | 133 | return builtin_type (gdbarch)->builtin_double; |
72667056 | 134 | |
df4df182 | 135 | return builtin_type (gdbarch)->builtin_int64; |
0d056799 | 136 | } |
f8453e34 | 137 | |
615967cb RH |
138 | /* Is REGNUM a member of REGGROUP? */ |
139 | ||
140 | static int | |
141 | alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
142 | struct reggroup *group) | |
143 | { | |
144 | /* Filter out any registers eliminated, but whose regnum is | |
145 | reserved for backward compatibility, e.g. the vfp. */ | |
ec7cc0e8 UW |
146 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
147 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
615967cb RH |
148 | return 0; |
149 | ||
df4a182b RH |
150 | if (group == all_reggroup) |
151 | return 1; | |
152 | ||
153 | /* Zero should not be saved or restored. Technically it is a general | |
154 | register (just as $f31 would be a float if we represented it), but | |
155 | there's no point displaying it during "info regs", so leave it out | |
156 | of all groups except for "all". */ | |
157 | if (regnum == ALPHA_ZERO_REGNUM) | |
158 | return 0; | |
159 | ||
160 | /* All other registers are saved and restored. */ | |
161 | if (group == save_reggroup || group == restore_reggroup) | |
615967cb RH |
162 | return 1; |
163 | ||
164 | /* All other groups are non-overlapping. */ | |
165 | ||
166 | /* Since this is really a PALcode memory slot... */ | |
167 | if (regnum == ALPHA_UNIQUE_REGNUM) | |
168 | return group == system_reggroup; | |
169 | ||
170 | /* Force the FPCR to be considered part of the floating point state. */ | |
171 | if (regnum == ALPHA_FPCR_REGNUM) | |
172 | return group == float_reggroup; | |
173 | ||
174 | if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31) | |
175 | return group == float_reggroup; | |
176 | else | |
177 | return group == general_reggroup; | |
178 | } | |
179 | ||
c483c494 RH |
180 | /* The following represents exactly the conversion performed by |
181 | the LDS instruction. This applies to both single-precision | |
182 | floating point and 32-bit integers. */ | |
183 | ||
184 | static void | |
e17a4113 | 185 | alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 186 | { |
e17a4113 | 187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9a3c8263 SM |
188 | ULONGEST mem |
189 | = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order); | |
c483c494 RH |
190 | ULONGEST frac = (mem >> 0) & 0x7fffff; |
191 | ULONGEST sign = (mem >> 31) & 1; | |
192 | ULONGEST exp_msb = (mem >> 30) & 1; | |
193 | ULONGEST exp_low = (mem >> 23) & 0x7f; | |
194 | ULONGEST exp, reg; | |
195 | ||
196 | exp = (exp_msb << 10) | exp_low; | |
197 | if (exp_msb) | |
198 | { | |
199 | if (exp_low == 0x7f) | |
200 | exp = 0x7ff; | |
201 | } | |
202 | else | |
203 | { | |
204 | if (exp_low != 0x00) | |
205 | exp |= 0x380; | |
206 | } | |
207 | ||
208 | reg = (sign << 63) | (exp << 52) | (frac << 29); | |
9a3c8263 | 209 | store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg); |
c483c494 RH |
210 | } |
211 | ||
212 | /* Similarly, this represents exactly the conversion performed by | |
213 | the STS instruction. */ | |
214 | ||
39efb398 | 215 | static void |
e17a4113 | 216 | alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) |
c483c494 | 217 | { |
e17a4113 | 218 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c483c494 RH |
219 | ULONGEST reg, mem; |
220 | ||
9a3c8263 | 221 | reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order); |
c483c494 | 222 | mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); |
9a3c8263 | 223 | store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem); |
c483c494 RH |
224 | } |
225 | ||
d2427a71 RH |
226 | /* The alpha needs a conversion between register and memory format if the |
227 | register is a floating point register and memory format is float, as the | |
228 | register format must be double or memory format is an integer with 4 | |
68fce50f | 229 | bytes, as the representation of integers in floating point |
0963b4bd | 230 | registers is different. */ |
d2427a71 | 231 | |
c483c494 | 232 | static int |
0963b4bd MS |
233 | alpha_convert_register_p (struct gdbarch *gdbarch, int regno, |
234 | struct type *type) | |
14696584 | 235 | { |
83acabca | 236 | return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 |
68fce50f | 237 | && TYPE_LENGTH (type) == 4); |
14696584 RH |
238 | } |
239 | ||
8dccd430 | 240 | static int |
ff2e87ac | 241 | alpha_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
242 | struct type *valtype, gdb_byte *out, |
243 | int *optimizedp, int *unavailablep) | |
5868c862 | 244 | { |
8dccd430 | 245 | struct gdbarch *gdbarch = get_frame_arch (frame); |
fbe654c8 | 246 | struct value *value = get_frame_register_value (frame, regnum); |
2a1ce6ec | 247 | |
fbe654c8 AH |
248 | gdb_assert (value != NULL); |
249 | *optimizedp = value_optimized_out (value); | |
250 | *unavailablep = !value_entirely_available (value); | |
251 | ||
252 | if (*optimizedp || *unavailablep) | |
253 | { | |
254 | release_value (value); | |
255 | value_free (value); | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /* Convert to VALTYPE. */ | |
8dccd430 | 260 | |
68fce50f | 261 | gdb_assert (TYPE_LENGTH (valtype) == 4); |
fbe654c8 AH |
262 | alpha_sts (gdbarch, out, value_contents_all (value)); |
263 | ||
264 | release_value (value); | |
265 | value_free (value); | |
68fce50f | 266 | return 1; |
d2427a71 | 267 | } |
5868c862 | 268 | |
d2427a71 | 269 | static void |
ff2e87ac | 270 | alpha_value_to_register (struct frame_info *frame, int regnum, |
5b819568 | 271 | struct type *valtype, const gdb_byte *in) |
d2427a71 | 272 | { |
fbe654c8 | 273 | gdb_byte out[ALPHA_REGISTER_SIZE]; |
2a1ce6ec | 274 | |
68fce50f | 275 | gdb_assert (TYPE_LENGTH (valtype) == 4); |
fbe654c8 AH |
276 | gdb_assert (register_size (get_frame_arch (frame), regnum) |
277 | <= ALPHA_REGISTER_SIZE); | |
68fce50f YQ |
278 | alpha_lds (get_frame_arch (frame), out, in); |
279 | ||
ff2e87ac | 280 | put_frame_register (frame, regnum, out); |
5868c862 JT |
281 | } |
282 | ||
d2427a71 RH |
283 | \f |
284 | /* The alpha passes the first six arguments in the registers, the rest on | |
c88e30c0 RH |
285 | the stack. The register arguments are stored in ARG_REG_BUFFER, and |
286 | then moved into the register file; this simplifies the passing of a | |
287 | large struct which extends from the registers to the stack, plus avoids | |
288 | three ptrace invocations per word. | |
289 | ||
290 | We don't bother tracking which register values should go in integer | |
291 | regs or fp regs; we load the same values into both. | |
292 | ||
d2427a71 RH |
293 | If the called function is returning a structure, the address of the |
294 | structure to be returned is passed as a hidden first argument. */ | |
c906108c | 295 | |
d2427a71 | 296 | static CORE_ADDR |
7d9b040b | 297 | alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
c88e30c0 RH |
298 | struct regcache *regcache, CORE_ADDR bp_addr, |
299 | int nargs, struct value **args, CORE_ADDR sp, | |
300 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 301 | { |
e17a4113 | 302 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d2427a71 RH |
303 | int i; |
304 | int accumulate_size = struct_return ? 8 : 0; | |
d2427a71 | 305 | struct alpha_arg |
c906108c | 306 | { |
f42a0a33 | 307 | const gdb_byte *contents; |
d2427a71 RH |
308 | int len; |
309 | int offset; | |
310 | }; | |
8d749320 | 311 | struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs); |
52f0bd74 | 312 | struct alpha_arg *m_arg; |
2a1ce6ec | 313 | gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; |
d2427a71 | 314 | int required_arg_regs; |
7d9b040b | 315 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 316 | |
c88e30c0 RH |
317 | /* The ABI places the address of the called function in T12. */ |
318 | regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr); | |
319 | ||
320 | /* Set the return address register to point to the entry point | |
321 | of the program, where a breakpoint lies in wait. */ | |
322 | regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr); | |
323 | ||
324 | /* Lay out the arguments in memory. */ | |
d2427a71 RH |
325 | for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++) |
326 | { | |
327 | struct value *arg = args[i]; | |
4991999e | 328 | struct type *arg_type = check_typedef (value_type (arg)); |
c88e30c0 | 329 | |
d2427a71 RH |
330 | /* Cast argument to long if necessary as the compiler does it too. */ |
331 | switch (TYPE_CODE (arg_type)) | |
c906108c | 332 | { |
d2427a71 RH |
333 | case TYPE_CODE_INT: |
334 | case TYPE_CODE_BOOL: | |
335 | case TYPE_CODE_CHAR: | |
336 | case TYPE_CODE_RANGE: | |
337 | case TYPE_CODE_ENUM: | |
0ede8eca | 338 | if (TYPE_LENGTH (arg_type) == 4) |
d2427a71 | 339 | { |
0ede8eca RH |
340 | /* 32-bit values must be sign-extended to 64 bits |
341 | even if the base data type is unsigned. */ | |
df4df182 | 342 | arg_type = builtin_type (gdbarch)->builtin_int32; |
0ede8eca RH |
343 | arg = value_cast (arg_type, arg); |
344 | } | |
345 | if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE) | |
346 | { | |
df4df182 | 347 | arg_type = builtin_type (gdbarch)->builtin_int64; |
d2427a71 RH |
348 | arg = value_cast (arg_type, arg); |
349 | } | |
350 | break; | |
7b5e1cb3 | 351 | |
c88e30c0 RH |
352 | case TYPE_CODE_FLT: |
353 | /* "float" arguments loaded in registers must be passed in | |
354 | register format, aka "double". */ | |
355 | if (accumulate_size < sizeof (arg_reg_buffer) | |
356 | && TYPE_LENGTH (arg_type) == 4) | |
357 | { | |
27067745 | 358 | arg_type = builtin_type (gdbarch)->builtin_double; |
c88e30c0 RH |
359 | arg = value_cast (arg_type, arg); |
360 | } | |
361 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
362 | invisible reference. No one else uses this data type. */ | |
363 | else if (TYPE_LENGTH (arg_type) == 16) | |
364 | { | |
365 | /* Allocate aligned storage. */ | |
366 | sp = (sp & -16) - 16; | |
367 | ||
368 | /* Write the real data into the stack. */ | |
0fd88904 | 369 | write_memory (sp, value_contents (arg), 16); |
c88e30c0 RH |
370 | |
371 | /* Construct the indirection. */ | |
372 | arg_type = lookup_pointer_type (arg_type); | |
373 | arg = value_from_pointer (arg_type, sp); | |
374 | } | |
375 | break; | |
7b5e1cb3 RH |
376 | |
377 | case TYPE_CODE_COMPLEX: | |
378 | /* ??? The ABI says that complex values are passed as two | |
379 | separate scalar values. This distinction only matters | |
380 | for complex float. However, GCC does not implement this. */ | |
381 | ||
382 | /* Tru64 5.1 has a 128-bit long double, and passes this by | |
383 | invisible reference. */ | |
384 | if (TYPE_LENGTH (arg_type) == 32) | |
385 | { | |
386 | /* Allocate aligned storage. */ | |
387 | sp = (sp & -16) - 16; | |
388 | ||
389 | /* Write the real data into the stack. */ | |
0fd88904 | 390 | write_memory (sp, value_contents (arg), 32); |
7b5e1cb3 RH |
391 | |
392 | /* Construct the indirection. */ | |
393 | arg_type = lookup_pointer_type (arg_type); | |
394 | arg = value_from_pointer (arg_type, sp); | |
395 | } | |
396 | break; | |
397 | ||
d2427a71 RH |
398 | default: |
399 | break; | |
c906108c | 400 | } |
d2427a71 RH |
401 | m_arg->len = TYPE_LENGTH (arg_type); |
402 | m_arg->offset = accumulate_size; | |
403 | accumulate_size = (accumulate_size + m_arg->len + 7) & ~7; | |
f42a0a33 | 404 | m_arg->contents = value_contents (arg); |
c906108c SS |
405 | } |
406 | ||
d2427a71 RH |
407 | /* Determine required argument register loads, loading an argument register |
408 | is expensive as it uses three ptrace calls. */ | |
409 | required_arg_regs = accumulate_size / 8; | |
410 | if (required_arg_regs > ALPHA_NUM_ARG_REGS) | |
411 | required_arg_regs = ALPHA_NUM_ARG_REGS; | |
c906108c | 412 | |
d2427a71 | 413 | /* Make room for the arguments on the stack. */ |
c88e30c0 RH |
414 | if (accumulate_size < sizeof(arg_reg_buffer)) |
415 | accumulate_size = 0; | |
416 | else | |
417 | accumulate_size -= sizeof(arg_reg_buffer); | |
d2427a71 | 418 | sp -= accumulate_size; |
c906108c | 419 | |
c88e30c0 | 420 | /* Keep sp aligned to a multiple of 16 as the ABI requires. */ |
d2427a71 | 421 | sp &= ~15; |
c906108c | 422 | |
d2427a71 RH |
423 | /* `Push' arguments on the stack. */ |
424 | for (i = nargs; m_arg--, --i >= 0;) | |
c906108c | 425 | { |
f42a0a33 | 426 | const gdb_byte *contents = m_arg->contents; |
c88e30c0 RH |
427 | int offset = m_arg->offset; |
428 | int len = m_arg->len; | |
429 | ||
430 | /* Copy the bytes destined for registers into arg_reg_buffer. */ | |
431 | if (offset < sizeof(arg_reg_buffer)) | |
432 | { | |
433 | if (offset + len <= sizeof(arg_reg_buffer)) | |
434 | { | |
435 | memcpy (arg_reg_buffer + offset, contents, len); | |
436 | continue; | |
437 | } | |
438 | else | |
439 | { | |
440 | int tlen = sizeof(arg_reg_buffer) - offset; | |
441 | memcpy (arg_reg_buffer + offset, contents, tlen); | |
442 | offset += tlen; | |
443 | contents += tlen; | |
444 | len -= tlen; | |
445 | } | |
446 | } | |
447 | ||
448 | /* Everything else goes to the stack. */ | |
449 | write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len); | |
c906108c | 450 | } |
c88e30c0 | 451 | if (struct_return) |
e17a4113 UW |
452 | store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, |
453 | byte_order, struct_addr); | |
c906108c | 454 | |
d2427a71 RH |
455 | /* Load the argument registers. */ |
456 | for (i = 0; i < required_arg_regs; i++) | |
457 | { | |
09cc52fd RH |
458 | regcache_cooked_write (regcache, ALPHA_A0_REGNUM + i, |
459 | arg_reg_buffer + i*ALPHA_REGISTER_SIZE); | |
460 | regcache_cooked_write (regcache, ALPHA_FPA0_REGNUM + i, | |
461 | arg_reg_buffer + i*ALPHA_REGISTER_SIZE); | |
d2427a71 | 462 | } |
c906108c | 463 | |
09cc52fd RH |
464 | /* Finally, update the stack pointer. */ |
465 | regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp); | |
466 | ||
c88e30c0 | 467 | return sp; |
c906108c SS |
468 | } |
469 | ||
5ec2bb99 RH |
470 | /* Extract from REGCACHE the value about to be returned from a function |
471 | and copy it into VALBUF. */ | |
d2427a71 | 472 | |
dc129d82 | 473 | static void |
5ec2bb99 | 474 | alpha_extract_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 475 | gdb_byte *valbuf) |
140f9984 | 476 | { |
ac7936df | 477 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 478 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2a1ce6ec | 479 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 RH |
480 | ULONGEST l; |
481 | ||
482 | switch (TYPE_CODE (valtype)) | |
483 | { | |
484 | case TYPE_CODE_FLT: | |
744a8059 | 485 | switch (TYPE_LENGTH (valtype)) |
5ec2bb99 RH |
486 | { |
487 | case 4: | |
488 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer); | |
e17a4113 | 489 | alpha_sts (gdbarch, valbuf, raw_buffer); |
5ec2bb99 RH |
490 | break; |
491 | ||
492 | case 8: | |
493 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
494 | break; | |
495 | ||
24064b5c RH |
496 | case 16: |
497 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
498 | read_memory (l, valbuf, 16); | |
499 | break; | |
500 | ||
5ec2bb99 | 501 | default: |
0963b4bd MS |
502 | internal_error (__FILE__, __LINE__, |
503 | _("unknown floating point width")); | |
5ec2bb99 RH |
504 | } |
505 | break; | |
506 | ||
7b5e1cb3 | 507 | case TYPE_CODE_COMPLEX: |
744a8059 | 508 | switch (TYPE_LENGTH (valtype)) |
7b5e1cb3 RH |
509 | { |
510 | case 8: | |
511 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
512 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
513 | break; | |
514 | ||
515 | case 16: | |
516 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, valbuf); | |
2a1ce6ec | 517 | regcache_cooked_read (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); |
7b5e1cb3 RH |
518 | break; |
519 | ||
520 | case 32: | |
a9933661 | 521 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); |
7b5e1cb3 RH |
522 | read_memory (l, valbuf, 32); |
523 | break; | |
524 | ||
525 | default: | |
0963b4bd MS |
526 | internal_error (__FILE__, __LINE__, |
527 | _("unknown floating point width")); | |
7b5e1cb3 RH |
528 | } |
529 | break; | |
530 | ||
5ec2bb99 RH |
531 | default: |
532 | /* Assume everything else degenerates to an integer. */ | |
533 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); | |
744a8059 | 534 | store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l); |
5ec2bb99 RH |
535 | break; |
536 | } | |
140f9984 JT |
537 | } |
538 | ||
5ec2bb99 RH |
539 | /* Insert the given value into REGCACHE as if it was being |
540 | returned by a function. */ | |
0d056799 | 541 | |
d2427a71 | 542 | static void |
5ec2bb99 | 543 | alpha_store_return_value (struct type *valtype, struct regcache *regcache, |
5b819568 | 544 | const gdb_byte *valbuf) |
c906108c | 545 | { |
ac7936df | 546 | struct gdbarch *gdbarch = regcache->arch (); |
2a1ce6ec | 547 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
5ec2bb99 | 548 | ULONGEST l; |
d2427a71 | 549 | |
5ec2bb99 | 550 | switch (TYPE_CODE (valtype)) |
c906108c | 551 | { |
5ec2bb99 | 552 | case TYPE_CODE_FLT: |
744a8059 | 553 | switch (TYPE_LENGTH (valtype)) |
5ec2bb99 RH |
554 | { |
555 | case 4: | |
e17a4113 | 556 | alpha_lds (gdbarch, raw_buffer, valbuf); |
f75d70cc RH |
557 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, raw_buffer); |
558 | break; | |
5ec2bb99 RH |
559 | |
560 | case 8: | |
561 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
562 | break; | |
563 | ||
24064b5c RH |
564 | case 16: |
565 | /* FIXME: 128-bit long doubles are returned like structures: | |
566 | by writing into indirect storage provided by the caller | |
567 | as the first argument. */ | |
323e0a4a | 568 | error (_("Cannot set a 128-bit long double return value.")); |
24064b5c | 569 | |
5ec2bb99 | 570 | default: |
0963b4bd MS |
571 | internal_error (__FILE__, __LINE__, |
572 | _("unknown floating point width")); | |
5ec2bb99 RH |
573 | } |
574 | break; | |
d2427a71 | 575 | |
7b5e1cb3 | 576 | case TYPE_CODE_COMPLEX: |
744a8059 | 577 | switch (TYPE_LENGTH (valtype)) |
7b5e1cb3 RH |
578 | { |
579 | case 8: | |
580 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ | |
581 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
582 | break; | |
583 | ||
584 | case 16: | |
585 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM, valbuf); | |
2a1ce6ec | 586 | regcache_cooked_write (regcache, ALPHA_FP0_REGNUM + 1, valbuf + 8); |
7b5e1cb3 RH |
587 | break; |
588 | ||
589 | case 32: | |
590 | /* FIXME: 128-bit long doubles are returned like structures: | |
591 | by writing into indirect storage provided by the caller | |
592 | as the first argument. */ | |
323e0a4a | 593 | error (_("Cannot set a 128-bit long double return value.")); |
7b5e1cb3 RH |
594 | |
595 | default: | |
0963b4bd MS |
596 | internal_error (__FILE__, __LINE__, |
597 | _("unknown floating point width")); | |
7b5e1cb3 RH |
598 | } |
599 | break; | |
600 | ||
5ec2bb99 RH |
601 | default: |
602 | /* Assume everything else degenerates to an integer. */ | |
0ede8eca RH |
603 | /* 32-bit values must be sign-extended to 64 bits |
604 | even if the base data type is unsigned. */ | |
744a8059 | 605 | if (TYPE_LENGTH (valtype) == 4) |
df4df182 | 606 | valtype = builtin_type (gdbarch)->builtin_int32; |
5ec2bb99 RH |
607 | l = unpack_long (valtype, valbuf); |
608 | regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); | |
609 | break; | |
610 | } | |
c906108c SS |
611 | } |
612 | ||
9823e921 | 613 | static enum return_value_convention |
6a3a010b | 614 | alpha_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
615 | struct type *type, struct regcache *regcache, |
616 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
9823e921 RH |
617 | { |
618 | enum type_code code = TYPE_CODE (type); | |
619 | ||
620 | if ((code == TYPE_CODE_STRUCT | |
621 | || code == TYPE_CODE_UNION | |
622 | || code == TYPE_CODE_ARRAY) | |
623 | && gdbarch_tdep (gdbarch)->return_in_memory (type)) | |
624 | { | |
625 | if (readbuf) | |
626 | { | |
627 | ULONGEST addr; | |
628 | regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr); | |
629 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
630 | } | |
631 | ||
632 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
633 | } | |
634 | ||
635 | if (readbuf) | |
636 | alpha_extract_return_value (type, regcache, readbuf); | |
637 | if (writebuf) | |
638 | alpha_store_return_value (type, regcache, writebuf); | |
639 | ||
640 | return RETURN_VALUE_REGISTER_CONVENTION; | |
641 | } | |
642 | ||
643 | static int | |
644 | alpha_return_in_memory_always (struct type *type) | |
645 | { | |
646 | return 1; | |
647 | } | |
d2427a71 | 648 | \f |
c906108c | 649 | |
04180708 | 650 | constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ |
598cc9dc | 651 | |
04180708 | 652 | typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint; |
c906108c | 653 | |
d2427a71 RH |
654 | \f |
655 | /* This returns the PC of the first insn after the prologue. | |
656 | If we can't find the prologue, then return 0. */ | |
c906108c | 657 | |
d2427a71 RH |
658 | CORE_ADDR |
659 | alpha_after_prologue (CORE_ADDR pc) | |
c906108c | 660 | { |
d2427a71 RH |
661 | struct symtab_and_line sal; |
662 | CORE_ADDR func_addr, func_end; | |
c906108c | 663 | |
d2427a71 | 664 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c5aa993b | 665 | return 0; |
c906108c | 666 | |
d2427a71 RH |
667 | sal = find_pc_line (func_addr, 0); |
668 | if (sal.end < func_end) | |
669 | return sal.end; | |
c5aa993b | 670 | |
d2427a71 RH |
671 | /* The line after the prologue is after the end of the function. In this |
672 | case, tell the caller to find the prologue the hard way. */ | |
673 | return 0; | |
c906108c SS |
674 | } |
675 | ||
d2427a71 RH |
676 | /* Read an instruction from memory at PC, looking through breakpoints. */ |
677 | ||
678 | unsigned int | |
e17a4113 | 679 | alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 680 | { |
e17a4113 | 681 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e8d2d628 | 682 | gdb_byte buf[ALPHA_INSN_SIZE]; |
d09f2c3f | 683 | int res; |
c5aa993b | 684 | |
d09f2c3f PA |
685 | res = target_read_memory (pc, buf, sizeof (buf)); |
686 | if (res != 0) | |
687 | memory_error (TARGET_XFER_E_IO, pc); | |
e17a4113 | 688 | return extract_unsigned_integer (buf, sizeof (buf), byte_order); |
d2427a71 | 689 | } |
c5aa993b | 690 | |
d2427a71 RH |
691 | /* To skip prologues, I use this predicate. Returns either PC itself |
692 | if the code at PC does not look like a function prologue; otherwise | |
693 | returns an address that (if we're lucky) follows the prologue. If | |
694 | LENIENT, then we must skip everything which is involved in setting | |
695 | up the frame (it's OK to skip more, just so long as we don't skip | |
696 | anything which might clobber the registers which are being saved. */ | |
c906108c | 697 | |
d2427a71 | 698 | static CORE_ADDR |
6093d2eb | 699 | alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 RH |
700 | { |
701 | unsigned long inst; | |
702 | int offset; | |
703 | CORE_ADDR post_prologue_pc; | |
e8d2d628 | 704 | gdb_byte buf[ALPHA_INSN_SIZE]; |
c906108c | 705 | |
d2427a71 RH |
706 | /* Silently return the unaltered pc upon memory errors. |
707 | This could happen on OSF/1 if decode_line_1 tries to skip the | |
708 | prologue for quickstarted shared library functions when the | |
709 | shared library is not yet mapped in. | |
710 | Reading target memory is slow over serial lines, so we perform | |
711 | this check only if the target has shared libraries (which all | |
712 | Alpha targets do). */ | |
e8d2d628 | 713 | if (target_read_memory (pc, buf, sizeof (buf))) |
d2427a71 | 714 | return pc; |
c906108c | 715 | |
d2427a71 RH |
716 | /* See if we can determine the end of the prologue via the symbol table. |
717 | If so, then return either PC, or the PC after the prologue, whichever | |
718 | is greater. */ | |
c906108c | 719 | |
d2427a71 RH |
720 | post_prologue_pc = alpha_after_prologue (pc); |
721 | if (post_prologue_pc != 0) | |
325fac50 | 722 | return std::max (pc, post_prologue_pc); |
c906108c | 723 | |
d2427a71 RH |
724 | /* Can't determine prologue from the symbol table, need to examine |
725 | instructions. */ | |
dc1b0db2 | 726 | |
0963b4bd | 727 | /* Skip the typical prologue instructions. These are the stack adjustment |
d2427a71 RH |
728 | instruction and the instructions that save registers on the stack |
729 | or in the gcc frame. */ | |
e8d2d628 | 730 | for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE) |
d2427a71 | 731 | { |
e17a4113 | 732 | inst = alpha_read_insn (gdbarch, pc + offset); |
c906108c | 733 | |
d2427a71 RH |
734 | if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */ |
735 | continue; | |
736 | if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */ | |
737 | continue; | |
738 | if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ | |
739 | continue; | |
740 | if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */ | |
741 | continue; | |
c906108c | 742 | |
d2427a71 RH |
743 | if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */ |
744 | || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */ | |
745 | && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */ | |
746 | continue; | |
c906108c | 747 | |
d2427a71 RH |
748 | if (inst == 0x47de040f) /* bis sp,sp,fp */ |
749 | continue; | |
750 | if (inst == 0x47fe040f) /* bis zero,sp,fp */ | |
751 | continue; | |
c906108c | 752 | |
d2427a71 | 753 | break; |
c906108c | 754 | } |
d2427a71 RH |
755 | return pc + offset; |
756 | } | |
c906108c | 757 | |
46ad3598 UW |
758 | \f |
759 | static const int ldl_l_opcode = 0x2a; | |
760 | static const int ldq_l_opcode = 0x2b; | |
761 | static const int stl_c_opcode = 0x2e; | |
762 | static const int stq_c_opcode = 0x2f; | |
763 | ||
764 | /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L | |
765 | instruction and ending with a STL_C/STQ_C instruction. If such a sequence | |
766 | is found, attempt to step through it. A breakpoint is placed at the end of | |
767 | the sequence. */ | |
768 | ||
a0ff9e1a | 769 | static std::vector<CORE_ADDR> |
f5ea389a | 770 | alpha_deal_with_atomic_sequence (struct regcache *regcache) |
46ad3598 | 771 | { |
ac7936df | 772 | struct gdbarch *gdbarch = regcache->arch (); |
7ab2d087 | 773 | CORE_ADDR pc = regcache_read_pc (regcache); |
46ad3598 UW |
774 | CORE_ADDR breaks[2] = {-1, -1}; |
775 | CORE_ADDR loc = pc; | |
776 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ | |
777 | unsigned int insn = alpha_read_insn (gdbarch, loc); | |
778 | int insn_count; | |
779 | int index; | |
780 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
781 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
782 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
783 | ||
784 | /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ | |
785 | if (INSN_OPCODE (insn) != ldl_l_opcode | |
786 | && INSN_OPCODE (insn) != ldq_l_opcode) | |
a0ff9e1a | 787 | return {}; |
46ad3598 UW |
788 | |
789 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
790 | instructions. */ | |
791 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
792 | { | |
793 | loc += ALPHA_INSN_SIZE; | |
794 | insn = alpha_read_insn (gdbarch, loc); | |
795 | ||
796 | /* Assume that there is at most one branch in the atomic | |
797 | sequence. If a branch is found, put a breakpoint in | |
798 | its destination address. */ | |
799 | if (INSN_OPCODE (insn) >= br_opcode) | |
800 | { | |
801 | int immediate = (insn & 0x001fffff) << 2; | |
802 | ||
803 | immediate = (immediate ^ 0x400000) - 0x400000; | |
804 | ||
805 | if (bc_insn_count >= 1) | |
a0ff9e1a SM |
806 | return {}; /* More than one branch found, fallback |
807 | to the standard single-step code. */ | |
46ad3598 UW |
808 | |
809 | breaks[1] = loc + ALPHA_INSN_SIZE + immediate; | |
810 | ||
811 | bc_insn_count++; | |
812 | last_breakpoint++; | |
813 | } | |
814 | ||
815 | if (INSN_OPCODE (insn) == stl_c_opcode | |
816 | || INSN_OPCODE (insn) == stq_c_opcode) | |
817 | break; | |
818 | } | |
819 | ||
820 | /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ | |
821 | if (INSN_OPCODE (insn) != stl_c_opcode | |
822 | && INSN_OPCODE (insn) != stq_c_opcode) | |
a0ff9e1a | 823 | return {}; |
46ad3598 UW |
824 | |
825 | closing_insn = loc; | |
826 | loc += ALPHA_INSN_SIZE; | |
827 | ||
828 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
829 | breaks[0] = loc; | |
830 | ||
831 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
832 | placed (branch instruction's destination) anywhere in sequence. */ | |
833 | if (last_breakpoint | |
834 | && (breaks[1] == breaks[0] | |
835 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
836 | last_breakpoint = 0; | |
837 | ||
a0ff9e1a SM |
838 | std::vector<CORE_ADDR> next_pcs; |
839 | ||
46ad3598 | 840 | for (index = 0; index <= last_breakpoint; index++) |
a0ff9e1a | 841 | next_pcs.push_back (breaks[index]); |
46ad3598 | 842 | |
93f9a11f | 843 | return next_pcs; |
46ad3598 UW |
844 | } |
845 | ||
d2427a71 RH |
846 | \f |
847 | /* Figure out where the longjmp will land. | |
848 | We expect the first arg to be a pointer to the jmp_buf structure from | |
849 | which we extract the PC (JB_PC) that we will land at. The PC is copied | |
850 | into the "pc". This routine returns true on success. */ | |
c906108c SS |
851 | |
852 | static int | |
60ade65d | 853 | alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 854 | { |
e17a4113 UW |
855 | struct gdbarch *gdbarch = get_frame_arch (frame); |
856 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
857 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d2427a71 | 858 | CORE_ADDR jb_addr; |
2a1ce6ec | 859 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
c906108c | 860 | |
60ade65d | 861 | jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM); |
c906108c | 862 | |
d2427a71 RH |
863 | if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size), |
864 | raw_buffer, tdep->jb_elt_size)) | |
c906108c | 865 | return 0; |
d2427a71 | 866 | |
e17a4113 | 867 | *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order); |
d2427a71 | 868 | return 1; |
c906108c SS |
869 | } |
870 | ||
d2427a71 RH |
871 | \f |
872 | /* Frame unwinder for signal trampolines. We use alpha tdep bits that | |
873 | describe the location and shape of the sigcontext structure. After | |
874 | that, all registers are in memory, so it's easy. */ | |
875 | /* ??? Shouldn't we be able to do this generically, rather than with | |
876 | OSABI data specific to Alpha? */ | |
877 | ||
878 | struct alpha_sigtramp_unwind_cache | |
c906108c | 879 | { |
d2427a71 RH |
880 | CORE_ADDR sigcontext_addr; |
881 | }; | |
c906108c | 882 | |
d2427a71 | 883 | static struct alpha_sigtramp_unwind_cache * |
6834c9bb | 884 | alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
d2427a71 RH |
885 | void **this_prologue_cache) |
886 | { | |
887 | struct alpha_sigtramp_unwind_cache *info; | |
888 | struct gdbarch_tdep *tdep; | |
c906108c | 889 | |
d2427a71 | 890 | if (*this_prologue_cache) |
9a3c8263 | 891 | return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache; |
c906108c | 892 | |
d2427a71 RH |
893 | info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); |
894 | *this_prologue_cache = info; | |
c906108c | 895 | |
6834c9bb JB |
896 | tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
897 | info->sigcontext_addr = tdep->sigcontext_addr (this_frame); | |
c906108c | 898 | |
d2427a71 | 899 | return info; |
c906108c SS |
900 | } |
901 | ||
138e7be5 MK |
902 | /* Return the address of REGNUM in a sigtramp frame. Since this is |
903 | all arithmetic, it doesn't seem worthwhile to cache it. */ | |
c5aa993b | 904 | |
d2427a71 | 905 | static CORE_ADDR |
be8626e0 MD |
906 | alpha_sigtramp_register_address (struct gdbarch *gdbarch, |
907 | CORE_ADDR sigcontext_addr, int regnum) | |
d2427a71 | 908 | { |
be8626e0 | 909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
138e7be5 MK |
910 | |
911 | if (regnum >= 0 && regnum < 32) | |
912 | return sigcontext_addr + tdep->sc_regs_offset + regnum * 8; | |
913 | else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32) | |
914 | return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8; | |
915 | else if (regnum == ALPHA_PC_REGNUM) | |
916 | return sigcontext_addr + tdep->sc_pc_offset; | |
c5aa993b | 917 | |
d2427a71 | 918 | return 0; |
c906108c SS |
919 | } |
920 | ||
d2427a71 RH |
921 | /* Given a GDB frame, determine the address of the calling function's |
922 | frame. This will be used to create a new GDB frame struct. */ | |
140f9984 | 923 | |
dc129d82 | 924 | static void |
6834c9bb | 925 | alpha_sigtramp_frame_this_id (struct frame_info *this_frame, |
d2427a71 RH |
926 | void **this_prologue_cache, |
927 | struct frame_id *this_id) | |
c906108c | 928 | { |
6834c9bb | 929 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
be8626e0 | 930 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d2427a71 | 931 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 932 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 RH |
933 | CORE_ADDR stack_addr, code_addr; |
934 | ||
935 | /* If the OSABI couldn't locate the sigcontext, give up. */ | |
936 | if (info->sigcontext_addr == 0) | |
937 | return; | |
938 | ||
939 | /* If we have dynamic signal trampolines, find their start. | |
940 | If we do not, then we must assume there is a symbol record | |
941 | that can provide the start address. */ | |
d2427a71 | 942 | if (tdep->dynamic_sigtramp_offset) |
c906108c | 943 | { |
d2427a71 | 944 | int offset; |
6834c9bb | 945 | code_addr = get_frame_pc (this_frame); |
e17a4113 | 946 | offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr); |
d2427a71 RH |
947 | if (offset >= 0) |
948 | code_addr -= offset; | |
c906108c | 949 | else |
d2427a71 | 950 | code_addr = 0; |
c906108c | 951 | } |
d2427a71 | 952 | else |
6834c9bb | 953 | code_addr = get_frame_func (this_frame); |
c906108c | 954 | |
d2427a71 | 955 | /* The stack address is trivially read from the sigcontext. */ |
be8626e0 | 956 | stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr, |
d2427a71 | 957 | ALPHA_SP_REGNUM); |
6834c9bb | 958 | stack_addr = get_frame_memory_unsigned (this_frame, stack_addr, |
b21fd293 | 959 | ALPHA_REGISTER_SIZE); |
c906108c | 960 | |
d2427a71 | 961 | *this_id = frame_id_build (stack_addr, code_addr); |
c906108c SS |
962 | } |
963 | ||
d2427a71 | 964 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
c906108c | 965 | |
6834c9bb JB |
966 | static struct value * |
967 | alpha_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
968 | void **this_prologue_cache, int regnum) | |
c906108c | 969 | { |
d2427a71 | 970 | struct alpha_sigtramp_unwind_cache *info |
6834c9bb | 971 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
d2427a71 | 972 | CORE_ADDR addr; |
c906108c | 973 | |
d2427a71 | 974 | if (info->sigcontext_addr != 0) |
c906108c | 975 | { |
d2427a71 | 976 | /* All integer and fp registers are stored in memory. */ |
6834c9bb | 977 | addr = alpha_sigtramp_register_address (get_frame_arch (this_frame), |
be8626e0 | 978 | info->sigcontext_addr, regnum); |
d2427a71 | 979 | if (addr != 0) |
6834c9bb | 980 | return frame_unwind_got_memory (this_frame, regnum, addr); |
c906108c SS |
981 | } |
982 | ||
d2427a71 RH |
983 | /* This extra register may actually be in the sigcontext, but our |
984 | current description of it in alpha_sigtramp_frame_unwind_cache | |
985 | doesn't include it. Too bad. Fall back on whatever's in the | |
986 | outer frame. */ | |
6834c9bb | 987 | return frame_unwind_got_register (this_frame, regnum, regnum); |
d2427a71 | 988 | } |
c906108c | 989 | |
6834c9bb JB |
990 | static int |
991 | alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
992 | struct frame_info *this_frame, | |
993 | void **this_prologue_cache) | |
d2427a71 | 994 | { |
6834c9bb JB |
995 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
996 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2c02bd72 | 997 | const char *name; |
c906108c | 998 | |
f2524b93 AC |
999 | /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead |
1000 | look at tramp-frame.h and other simplier per-architecture | |
1001 | sigtramp unwinders. */ | |
1002 | ||
1003 | /* We shouldn't even bother to try if the OSABI didn't register a | |
1004 | sigcontext_addr handler or pc_in_sigtramp hander. */ | |
ec7cc0e8 | 1005 | if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL) |
6834c9bb | 1006 | return 0; |
ec7cc0e8 | 1007 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL) |
6834c9bb | 1008 | return 0; |
c906108c | 1009 | |
d2427a71 RH |
1010 | /* Otherwise we should be in a signal frame. */ |
1011 | find_pc_partial_function (pc, &name, NULL, NULL); | |
e17a4113 | 1012 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name)) |
6834c9bb | 1013 | return 1; |
c906108c | 1014 | |
6834c9bb | 1015 | return 0; |
c906108c | 1016 | } |
6834c9bb JB |
1017 | |
1018 | static const struct frame_unwind alpha_sigtramp_frame_unwind = { | |
1019 | SIGTRAMP_FRAME, | |
8fbca658 | 1020 | default_frame_unwind_stop_reason, |
6834c9bb JB |
1021 | alpha_sigtramp_frame_this_id, |
1022 | alpha_sigtramp_frame_prev_register, | |
1023 | NULL, | |
1024 | alpha_sigtramp_frame_sniffer | |
1025 | }; | |
1026 | ||
d2427a71 | 1027 | \f |
c906108c | 1028 | |
d2427a71 RH |
1029 | /* Heuristic_proc_start may hunt through the text section for a long |
1030 | time across a 2400 baud serial line. Allows the user to limit this | |
1031 | search. */ | |
44096aee | 1032 | static int heuristic_fence_post = 0; |
c906108c | 1033 | |
d2427a71 RH |
1034 | /* Attempt to locate the start of the function containing PC. We assume that |
1035 | the previous function ends with an about_to_return insn. Not foolproof by | |
1036 | any means, since gcc is happy to put the epilogue in the middle of a | |
1037 | function. But we're guessing anyway... */ | |
c906108c | 1038 | |
d2427a71 | 1039 | static CORE_ADDR |
be8626e0 | 1040 | alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
d2427a71 | 1041 | { |
be8626e0 | 1042 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d2427a71 RH |
1043 | CORE_ADDR last_non_nop = pc; |
1044 | CORE_ADDR fence = pc - heuristic_fence_post; | |
1045 | CORE_ADDR orig_pc = pc; | |
fbe586ae | 1046 | CORE_ADDR func; |
d6b48e9c | 1047 | struct inferior *inf; |
9e0b60a8 | 1048 | |
d2427a71 RH |
1049 | if (pc == 0) |
1050 | return 0; | |
9e0b60a8 | 1051 | |
fbe586ae RH |
1052 | /* First see if we can find the start of the function from minimal |
1053 | symbol information. This can succeed with a binary that doesn't | |
1054 | have debug info, but hasn't been stripped. */ | |
1055 | func = get_pc_function_start (pc); | |
1056 | if (func) | |
1057 | return func; | |
1058 | ||
44096aee | 1059 | if (heuristic_fence_post == -1 |
d2427a71 RH |
1060 | || fence < tdep->vm_min_address) |
1061 | fence = tdep->vm_min_address; | |
c906108c | 1062 | |
d2427a71 RH |
1063 | /* Search back for previous return; also stop at a 0, which might be |
1064 | seen for instance before the start of a code section. Don't include | |
1065 | nops, since this usually indicates padding between functions. */ | |
e8d2d628 | 1066 | for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE) |
c906108c | 1067 | { |
e17a4113 | 1068 | unsigned int insn = alpha_read_insn (gdbarch, pc); |
d2427a71 | 1069 | switch (insn) |
c906108c | 1070 | { |
d2427a71 RH |
1071 | case 0: /* invalid insn */ |
1072 | case 0x6bfa8001: /* ret $31,($26),1 */ | |
1073 | return last_non_nop; | |
1074 | ||
1075 | case 0x2ffe0000: /* unop: ldq_u $31,0($30) */ | |
1076 | case 0x47ff041f: /* nop: bis $31,$31,$31 */ | |
1077 | break; | |
1078 | ||
1079 | default: | |
1080 | last_non_nop = pc; | |
1081 | break; | |
c906108c | 1082 | } |
d2427a71 | 1083 | } |
c906108c | 1084 | |
d6b48e9c PA |
1085 | inf = current_inferior (); |
1086 | ||
d2427a71 RH |
1087 | /* It's not clear to me why we reach this point when stopping quietly, |
1088 | but with this test, at least we don't print out warnings for every | |
1089 | child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 1090 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
d2427a71 RH |
1091 | { |
1092 | static int blurb_printed = 0; | |
c906108c | 1093 | |
d2427a71 | 1094 | if (fence == tdep->vm_min_address) |
323e0a4a | 1095 | warning (_("Hit beginning of text section without finding \ |
5af949e3 | 1096 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1097 | else |
323e0a4a | 1098 | warning (_("Hit heuristic-fence-post without finding \ |
5af949e3 | 1099 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
c906108c | 1100 | |
d2427a71 RH |
1101 | if (!blurb_printed) |
1102 | { | |
323e0a4a | 1103 | printf_filtered (_("\ |
d2427a71 RH |
1104 | This warning occurs if you are debugging a function without any symbols\n\ |
1105 | (for example, in a stripped executable). In that case, you may wish to\n\ | |
1106 | increase the size of the search with the `set heuristic-fence-post' command.\n\ | |
1107 | \n\ | |
1108 | Otherwise, you told GDB there was a function where there isn't one, or\n\ | |
323e0a4a | 1109 | (more likely) you have encountered a bug in GDB.\n")); |
d2427a71 RH |
1110 | blurb_printed = 1; |
1111 | } | |
1112 | } | |
c906108c | 1113 | |
d2427a71 RH |
1114 | return 0; |
1115 | } | |
c906108c | 1116 | |
07ea644b MD |
1117 | /* Fallback alpha frame unwinder. Uses instruction scanning and knows |
1118 | something about the traditional layout of alpha stack frames. */ | |
1119 | ||
1120 | struct alpha_heuristic_unwind_cache | |
1121 | { | |
1122 | CORE_ADDR vfp; | |
1123 | CORE_ADDR start_pc; | |
1124 | struct trad_frame_saved_reg *saved_regs; | |
1125 | int return_reg; | |
1126 | }; | |
1127 | ||
3a48e6ff JG |
1128 | /* If a probing loop sequence starts at PC, simulate it and compute |
1129 | FRAME_SIZE and PC after its execution. Otherwise, return with PC and | |
1130 | FRAME_SIZE unchanged. */ | |
1131 | ||
1132 | static void | |
1133 | alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc, | |
1134 | int *frame_size) | |
1135 | { | |
1136 | CORE_ADDR cur_pc = *pc; | |
1137 | int cur_frame_size = *frame_size; | |
1138 | int nb_of_iterations, reg_index, reg_probe; | |
1139 | unsigned int insn; | |
1140 | ||
1141 | /* The following pattern is recognized as a probing loop: | |
1142 | ||
1143 | lda REG_INDEX,NB_OF_ITERATIONS | |
1144 | lda REG_PROBE,<immediate>(sp) | |
1145 | ||
1146 | LOOP_START: | |
1147 | stq zero,<immediate>(REG_PROBE) | |
1148 | subq REG_INDEX,0x1,REG_INDEX | |
1149 | lda REG_PROBE,<immediate>(REG_PROBE) | |
1150 | bne REG_INDEX, LOOP_START | |
1151 | ||
1152 | lda sp,<immediate>(REG_PROBE) | |
1153 | ||
1154 | If anything different is found, the function returns without | |
1155 | changing PC and FRAME_SIZE. Otherwise, PC will point immediately | |
0963b4bd | 1156 | after this sequence, and FRAME_SIZE will be updated. */ |
3a48e6ff JG |
1157 | |
1158 | /* lda REG_INDEX,NB_OF_ITERATIONS */ | |
1159 | ||
1160 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1161 | if (INSN_OPCODE (insn) != lda_opcode) | |
1162 | return; | |
1163 | reg_index = MEM_RA (insn); | |
1164 | nb_of_iterations = MEM_DISP (insn); | |
1165 | ||
1166 | /* lda REG_PROBE,<immediate>(sp) */ | |
1167 | ||
1168 | cur_pc += ALPHA_INSN_SIZE; | |
1169 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1170 | if (INSN_OPCODE (insn) != lda_opcode | |
1171 | || MEM_RB (insn) != ALPHA_SP_REGNUM) | |
1172 | return; | |
1173 | reg_probe = MEM_RA (insn); | |
1174 | cur_frame_size -= MEM_DISP (insn); | |
1175 | ||
1176 | /* stq zero,<immediate>(REG_PROBE) */ | |
1177 | ||
1178 | cur_pc += ALPHA_INSN_SIZE; | |
1179 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1180 | if (INSN_OPCODE (insn) != stq_opcode | |
1181 | || MEM_RA (insn) != 0x1f | |
1182 | || MEM_RB (insn) != reg_probe) | |
1183 | return; | |
1184 | ||
1185 | /* subq REG_INDEX,0x1,REG_INDEX */ | |
1186 | ||
1187 | cur_pc += ALPHA_INSN_SIZE; | |
1188 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1189 | if (INSN_OPCODE (insn) != subq_opcode | |
1190 | || !OPR_HAS_IMMEDIATE (insn) | |
1191 | || OPR_FUNCTION (insn) != subq_function | |
1192 | || OPR_LIT(insn) != 1 | |
1193 | || OPR_RA (insn) != reg_index | |
1194 | || OPR_RC (insn) != reg_index) | |
1195 | return; | |
1196 | ||
1197 | /* lda REG_PROBE,<immediate>(REG_PROBE) */ | |
1198 | ||
1199 | cur_pc += ALPHA_INSN_SIZE; | |
1200 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1201 | if (INSN_OPCODE (insn) != lda_opcode | |
1202 | || MEM_RA (insn) != reg_probe | |
1203 | || MEM_RB (insn) != reg_probe) | |
1204 | return; | |
1205 | cur_frame_size -= MEM_DISP (insn) * nb_of_iterations; | |
1206 | ||
1207 | /* bne REG_INDEX, LOOP_START */ | |
1208 | ||
1209 | cur_pc += ALPHA_INSN_SIZE; | |
1210 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1211 | if (INSN_OPCODE (insn) != bne_opcode | |
1212 | || MEM_RA (insn) != reg_index) | |
1213 | return; | |
1214 | ||
1215 | /* lda sp,<immediate>(REG_PROBE) */ | |
1216 | ||
1217 | cur_pc += ALPHA_INSN_SIZE; | |
1218 | insn = alpha_read_insn (gdbarch, cur_pc); | |
1219 | if (INSN_OPCODE (insn) != lda_opcode | |
1220 | || MEM_RA (insn) != ALPHA_SP_REGNUM | |
1221 | || MEM_RB (insn) != reg_probe) | |
1222 | return; | |
1223 | cur_frame_size -= MEM_DISP (insn); | |
1224 | ||
1225 | *pc = cur_pc; | |
1226 | *frame_size = cur_frame_size; | |
1227 | } | |
1228 | ||
fbe586ae | 1229 | static struct alpha_heuristic_unwind_cache * |
6834c9bb | 1230 | alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame, |
d2427a71 RH |
1231 | void **this_prologue_cache, |
1232 | CORE_ADDR start_pc) | |
1233 | { | |
6834c9bb | 1234 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
d2427a71 RH |
1235 | struct alpha_heuristic_unwind_cache *info; |
1236 | ULONGEST val; | |
1237 | CORE_ADDR limit_pc, cur_pc; | |
1238 | int frame_reg, frame_size, return_reg, reg; | |
c906108c | 1239 | |
d2427a71 | 1240 | if (*this_prologue_cache) |
9a3c8263 | 1241 | return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache; |
c906108c | 1242 | |
d2427a71 RH |
1243 | info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); |
1244 | *this_prologue_cache = info; | |
6834c9bb | 1245 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 1246 | |
6834c9bb | 1247 | limit_pc = get_frame_pc (this_frame); |
d2427a71 | 1248 | if (start_pc == 0) |
be8626e0 | 1249 | start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc); |
d2427a71 | 1250 | info->start_pc = start_pc; |
c906108c | 1251 | |
d2427a71 RH |
1252 | frame_reg = ALPHA_SP_REGNUM; |
1253 | frame_size = 0; | |
1254 | return_reg = -1; | |
c906108c | 1255 | |
d2427a71 RH |
1256 | /* If we've identified a likely place to start, do code scanning. */ |
1257 | if (start_pc != 0) | |
c5aa993b | 1258 | { |
d2427a71 RH |
1259 | /* Limit the forward search to 50 instructions. */ |
1260 | if (start_pc + 200 < limit_pc) | |
1261 | limit_pc = start_pc + 200; | |
c5aa993b | 1262 | |
e8d2d628 | 1263 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE) |
d2427a71 | 1264 | { |
e17a4113 | 1265 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1266 | |
d2427a71 RH |
1267 | if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ |
1268 | { | |
1269 | if (word & 0x8000) | |
1270 | { | |
1271 | /* Consider only the first stack allocation instruction | |
0963b4bd | 1272 | to contain the static size of the frame. */ |
d2427a71 RH |
1273 | if (frame_size == 0) |
1274 | frame_size = (-word) & 0xffff; | |
1275 | } | |
1276 | else | |
1277 | { | |
1278 | /* Exit loop if a positive stack adjustment is found, which | |
1279 | usually means that the stack cleanup code in the function | |
1280 | epilogue is reached. */ | |
1281 | break; | |
1282 | } | |
1283 | } | |
1284 | else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ | |
1285 | { | |
1286 | reg = (word & 0x03e00000) >> 21; | |
1287 | ||
d15bfd3a AC |
1288 | /* Ignore this instruction if we have already encountered |
1289 | an instruction saving the same register earlier in the | |
1290 | function code. The current instruction does not tell | |
1291 | us where the original value upon function entry is saved. | |
1292 | All it says is that the function we are scanning reused | |
1293 | that register for some computation of its own, and is now | |
1294 | saving its result. */ | |
07ea644b | 1295 | if (trad_frame_addr_p(info->saved_regs, reg)) |
d15bfd3a AC |
1296 | continue; |
1297 | ||
d2427a71 RH |
1298 | if (reg == 31) |
1299 | continue; | |
1300 | ||
1301 | /* Do not compute the address where the register was saved yet, | |
1302 | because we don't know yet if the offset will need to be | |
1303 | relative to $sp or $fp (we can not compute the address | |
1304 | relative to $sp if $sp is updated during the execution of | |
1305 | the current subroutine, for instance when doing some alloca). | |
1306 | So just store the offset for the moment, and compute the | |
1307 | address later when we know whether this frame has a frame | |
1308 | pointer or not. */ | |
1309 | /* Hack: temporarily add one, so that the offset is non-zero | |
1310 | and we can tell which registers have save offsets below. */ | |
07ea644b | 1311 | info->saved_regs[reg].addr = (word & 0xffff) + 1; |
d2427a71 RH |
1312 | |
1313 | /* Starting with OSF/1-3.2C, the system libraries are shipped | |
1314 | without local symbols, but they still contain procedure | |
1315 | descriptors without a symbol reference. GDB is currently | |
1316 | unable to find these procedure descriptors and uses | |
1317 | heuristic_proc_desc instead. | |
1318 | As some low level compiler support routines (__div*, __add*) | |
1319 | use a non-standard return address register, we have to | |
1320 | add some heuristics to determine the return address register, | |
1321 | or stepping over these routines will fail. | |
1322 | Usually the return address register is the first register | |
1323 | saved on the stack, but assembler optimization might | |
1324 | rearrange the register saves. | |
1325 | So we recognize only a few registers (t7, t9, ra) within | |
1326 | the procedure prologue as valid return address registers. | |
1327 | If we encounter a return instruction, we extract the | |
7a9dd1b2 | 1328 | return address register from it. |
d2427a71 RH |
1329 | |
1330 | FIXME: Rewriting GDB to access the procedure descriptors, | |
0963b4bd MS |
1331 | e.g. via the minimal symbol table, might obviate this |
1332 | hack. */ | |
d2427a71 RH |
1333 | if (return_reg == -1 |
1334 | && cur_pc < (start_pc + 80) | |
1335 | && (reg == ALPHA_T7_REGNUM | |
1336 | || reg == ALPHA_T9_REGNUM | |
1337 | || reg == ALPHA_RA_REGNUM)) | |
1338 | return_reg = reg; | |
1339 | } | |
1340 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1341 | return_reg = (word >> 16) & 0x1f; | |
1342 | else if (word == 0x47de040f) /* bis sp,sp,fp */ | |
1343 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
1344 | else if (word == 0x47fe040f) /* bis zero,sp,fp */ | |
1345 | frame_reg = ALPHA_GCC_FP_REGNUM; | |
3a48e6ff JG |
1346 | |
1347 | alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size); | |
d2427a71 | 1348 | } |
c5aa993b | 1349 | |
d2427a71 RH |
1350 | /* If we haven't found a valid return address register yet, keep |
1351 | searching in the procedure prologue. */ | |
1352 | if (return_reg == -1) | |
1353 | { | |
1354 | while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80)) | |
1355 | { | |
e17a4113 | 1356 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
c5aa993b | 1357 | |
d2427a71 RH |
1358 | if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ |
1359 | { | |
1360 | reg = (word & 0x03e00000) >> 21; | |
1361 | if (reg == ALPHA_T7_REGNUM | |
1362 | || reg == ALPHA_T9_REGNUM | |
1363 | || reg == ALPHA_RA_REGNUM) | |
1364 | { | |
1365 | return_reg = reg; | |
1366 | break; | |
1367 | } | |
1368 | } | |
1369 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ | |
1370 | { | |
1371 | return_reg = (word >> 16) & 0x1f; | |
1372 | break; | |
1373 | } | |
85b32d22 | 1374 | |
e8d2d628 | 1375 | cur_pc += ALPHA_INSN_SIZE; |
d2427a71 RH |
1376 | } |
1377 | } | |
c906108c | 1378 | } |
c906108c | 1379 | |
d2427a71 RH |
1380 | /* Failing that, do default to the customary RA. */ |
1381 | if (return_reg == -1) | |
1382 | return_reg = ALPHA_RA_REGNUM; | |
1383 | info->return_reg = return_reg; | |
f8453e34 | 1384 | |
6834c9bb | 1385 | val = get_frame_register_unsigned (this_frame, frame_reg); |
d2427a71 | 1386 | info->vfp = val + frame_size; |
c906108c | 1387 | |
d2427a71 RH |
1388 | /* Convert offsets to absolute addresses. See above about adding |
1389 | one to the offsets to make all detected offsets non-zero. */ | |
1390 | for (reg = 0; reg < ALPHA_NUM_REGS; ++reg) | |
07ea644b MD |
1391 | if (trad_frame_addr_p(info->saved_regs, reg)) |
1392 | info->saved_regs[reg].addr += val - 1; | |
d2427a71 | 1393 | |
bfd66dd9 JB |
1394 | /* The stack pointer of the previous frame is computed by popping |
1395 | the current stack frame. */ | |
1396 | if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM)) | |
1397 | trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp); | |
1398 | ||
d2427a71 | 1399 | return info; |
c906108c | 1400 | } |
c906108c | 1401 | |
d2427a71 RH |
1402 | /* Given a GDB frame, determine the address of the calling function's |
1403 | frame. This will be used to create a new GDB frame struct. */ | |
1404 | ||
fbe586ae | 1405 | static void |
6834c9bb JB |
1406 | alpha_heuristic_frame_this_id (struct frame_info *this_frame, |
1407 | void **this_prologue_cache, | |
1408 | struct frame_id *this_id) | |
c906108c | 1409 | { |
d2427a71 | 1410 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1411 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1412 | |
d2427a71 | 1413 | *this_id = frame_id_build (info->vfp, info->start_pc); |
c906108c SS |
1414 | } |
1415 | ||
d2427a71 RH |
1416 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
1417 | ||
6834c9bb JB |
1418 | static struct value * |
1419 | alpha_heuristic_frame_prev_register (struct frame_info *this_frame, | |
1420 | void **this_prologue_cache, int regnum) | |
c906108c | 1421 | { |
d2427a71 | 1422 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1423 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
d2427a71 RH |
1424 | |
1425 | /* The PC of the previous frame is stored in the link register of | |
1426 | the current frame. Frob regnum so that we pull the value from | |
1427 | the correct place. */ | |
1428 | if (regnum == ALPHA_PC_REGNUM) | |
1429 | regnum = info->return_reg; | |
1430 | ||
6834c9bb | 1431 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
95b80706 JT |
1432 | } |
1433 | ||
d2427a71 RH |
1434 | static const struct frame_unwind alpha_heuristic_frame_unwind = { |
1435 | NORMAL_FRAME, | |
8fbca658 | 1436 | default_frame_unwind_stop_reason, |
d2427a71 | 1437 | alpha_heuristic_frame_this_id, |
6834c9bb JB |
1438 | alpha_heuristic_frame_prev_register, |
1439 | NULL, | |
1440 | default_frame_sniffer | |
d2427a71 | 1441 | }; |
c906108c | 1442 | |
fbe586ae | 1443 | static CORE_ADDR |
6834c9bb | 1444 | alpha_heuristic_frame_base_address (struct frame_info *this_frame, |
d2427a71 | 1445 | void **this_prologue_cache) |
c906108c | 1446 | { |
d2427a71 | 1447 | struct alpha_heuristic_unwind_cache *info |
6834c9bb | 1448 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
c906108c | 1449 | |
d2427a71 | 1450 | return info->vfp; |
c906108c SS |
1451 | } |
1452 | ||
d2427a71 RH |
1453 | static const struct frame_base alpha_heuristic_frame_base = { |
1454 | &alpha_heuristic_frame_unwind, | |
1455 | alpha_heuristic_frame_base_address, | |
1456 | alpha_heuristic_frame_base_address, | |
1457 | alpha_heuristic_frame_base_address | |
1458 | }; | |
1459 | ||
c906108c | 1460 | /* Just like reinit_frame_cache, but with the right arguments to be |
d2427a71 | 1461 | callable as an sfunc. Used by the "set heuristic-fence-post" command. */ |
c906108c SS |
1462 | |
1463 | static void | |
fba45db2 | 1464 | reinit_frame_cache_sfunc (char *args, int from_tty, struct cmd_list_element *c) |
c906108c SS |
1465 | { |
1466 | reinit_frame_cache (); | |
1467 | } | |
1468 | ||
d2427a71 | 1469 | \f |
d2427a71 RH |
1470 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
1471 | dummy frame. The frame ID's base needs to match the TOS value | |
1472 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1473 | breakpoint. */ | |
d734c450 | 1474 | |
d2427a71 | 1475 | static struct frame_id |
6834c9bb | 1476 | alpha_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
0d056799 | 1477 | { |
d2427a71 | 1478 | ULONGEST base; |
6834c9bb JB |
1479 | base = get_frame_register_unsigned (this_frame, ALPHA_SP_REGNUM); |
1480 | return frame_id_build (base, get_frame_pc (this_frame)); | |
0d056799 JT |
1481 | } |
1482 | ||
dc129d82 | 1483 | static CORE_ADDR |
d2427a71 | 1484 | alpha_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
accc6d1f | 1485 | { |
d2427a71 | 1486 | ULONGEST pc; |
11411de3 | 1487 | pc = frame_unwind_register_unsigned (next_frame, ALPHA_PC_REGNUM); |
d2427a71 | 1488 | return pc; |
accc6d1f JT |
1489 | } |
1490 | ||
98a8e1e5 RH |
1491 | \f |
1492 | /* Helper routines for alpha*-nat.c files to move register sets to and | |
1493 | from core files. The UNIQUE pointer is allowed to be NULL, as most | |
1494 | targets don't supply this value in their core files. */ | |
1495 | ||
1496 | void | |
390c1522 UW |
1497 | alpha_supply_int_regs (struct regcache *regcache, int regno, |
1498 | const void *r0_r30, const void *pc, const void *unique) | |
98a8e1e5 | 1499 | { |
9a3c8263 | 1500 | const gdb_byte *regs = (const gdb_byte *) r0_r30; |
98a8e1e5 RH |
1501 | int i; |
1502 | ||
1503 | for (i = 0; i < 31; ++i) | |
1504 | if (regno == i || regno == -1) | |
390c1522 | 1505 | regcache_raw_supply (regcache, i, regs + i * 8); |
98a8e1e5 RH |
1506 | |
1507 | if (regno == ALPHA_ZERO_REGNUM || regno == -1) | |
4a1be8d2 PA |
1508 | { |
1509 | const gdb_byte zero[8] = { 0 }; | |
1510 | ||
1511 | regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero); | |
1512 | } | |
98a8e1e5 RH |
1513 | |
1514 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
390c1522 | 1515 | regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1516 | |
1517 | if (regno == ALPHA_UNIQUE_REGNUM || regno == -1) | |
390c1522 | 1518 | regcache_raw_supply (regcache, ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1519 | } |
1520 | ||
1521 | void | |
390c1522 UW |
1522 | alpha_fill_int_regs (const struct regcache *regcache, |
1523 | int regno, void *r0_r30, void *pc, void *unique) | |
98a8e1e5 | 1524 | { |
9a3c8263 | 1525 | gdb_byte *regs = (gdb_byte *) r0_r30; |
98a8e1e5 RH |
1526 | int i; |
1527 | ||
1528 | for (i = 0; i < 31; ++i) | |
1529 | if (regno == i || regno == -1) | |
390c1522 | 1530 | regcache_raw_collect (regcache, i, regs + i * 8); |
98a8e1e5 RH |
1531 | |
1532 | if (regno == ALPHA_PC_REGNUM || regno == -1) | |
390c1522 | 1533 | regcache_raw_collect (regcache, ALPHA_PC_REGNUM, pc); |
98a8e1e5 RH |
1534 | |
1535 | if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1)) | |
390c1522 | 1536 | regcache_raw_collect (regcache, ALPHA_UNIQUE_REGNUM, unique); |
98a8e1e5 RH |
1537 | } |
1538 | ||
1539 | void | |
390c1522 UW |
1540 | alpha_supply_fp_regs (struct regcache *regcache, int regno, |
1541 | const void *f0_f30, const void *fpcr) | |
98a8e1e5 | 1542 | { |
9a3c8263 | 1543 | const gdb_byte *regs = (const gdb_byte *) f0_f30; |
98a8e1e5 RH |
1544 | int i; |
1545 | ||
1546 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1547 | if (regno == i || regno == -1) | |
390c1522 | 1548 | regcache_raw_supply (regcache, i, |
2a1ce6ec | 1549 | regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1550 | |
1551 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
390c1522 | 1552 | regcache_raw_supply (regcache, ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1553 | } |
1554 | ||
1555 | void | |
390c1522 UW |
1556 | alpha_fill_fp_regs (const struct regcache *regcache, |
1557 | int regno, void *f0_f30, void *fpcr) | |
98a8e1e5 | 1558 | { |
9a3c8263 | 1559 | gdb_byte *regs = (gdb_byte *) f0_f30; |
98a8e1e5 RH |
1560 | int i; |
1561 | ||
1562 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) | |
1563 | if (regno == i || regno == -1) | |
390c1522 | 1564 | regcache_raw_collect (regcache, i, |
2a1ce6ec | 1565 | regs + (i - ALPHA_FP0_REGNUM) * 8); |
98a8e1e5 RH |
1566 | |
1567 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) | |
390c1522 | 1568 | regcache_raw_collect (regcache, ALPHA_FPCR_REGNUM, fpcr); |
98a8e1e5 RH |
1569 | } |
1570 | ||
d2427a71 | 1571 | \f |
0de94d4b JB |
1572 | |
1573 | /* Return nonzero if the G_floating register value in REG is equal to | |
1574 | zero for FP control instructions. */ | |
1575 | ||
1576 | static int | |
1577 | fp_register_zero_p (LONGEST reg) | |
1578 | { | |
1579 | /* Check that all bits except the sign bit are zero. */ | |
1580 | const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1; | |
1581 | ||
1582 | return ((reg & zero_mask) == 0); | |
1583 | } | |
1584 | ||
1585 | /* Return the value of the sign bit for the G_floating register | |
1586 | value held in REG. */ | |
1587 | ||
1588 | static int | |
1589 | fp_register_sign_bit (LONGEST reg) | |
1590 | { | |
1591 | const LONGEST sign_mask = (LONGEST) 1 << 63; | |
1592 | ||
1593 | return ((reg & sign_mask) != 0); | |
1594 | } | |
1595 | ||
ec32e4be JT |
1596 | /* alpha_software_single_step() is called just before we want to resume |
1597 | the inferior, if we want to single-step it but there is no hardware | |
1598 | or kernel single-step support (NetBSD on Alpha, for example). We find | |
e0cd558a | 1599 | the target of the coming instruction and breakpoint it. */ |
ec32e4be JT |
1600 | |
1601 | static CORE_ADDR | |
7ab2d087 | 1602 | alpha_next_pc (struct regcache *regcache, CORE_ADDR pc) |
ec32e4be | 1603 | { |
ac7936df | 1604 | struct gdbarch *gdbarch = regcache->arch (); |
ec32e4be JT |
1605 | unsigned int insn; |
1606 | unsigned int op; | |
551e4f2e | 1607 | int regno; |
ec32e4be JT |
1608 | int offset; |
1609 | LONGEST rav; | |
1610 | ||
e17a4113 | 1611 | insn = alpha_read_insn (gdbarch, pc); |
ec32e4be | 1612 | |
0963b4bd | 1613 | /* Opcode is top 6 bits. */ |
ec32e4be JT |
1614 | op = (insn >> 26) & 0x3f; |
1615 | ||
1616 | if (op == 0x1a) | |
1617 | { | |
1618 | /* Jump format: target PC is: | |
1619 | RB & ~3 */ | |
7ab2d087 | 1620 | return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3); |
ec32e4be JT |
1621 | } |
1622 | ||
1623 | if ((op & 0x30) == 0x30) | |
1624 | { | |
1625 | /* Branch format: target PC is: | |
1626 | (new PC) + (4 * sext(displacement)) */ | |
f8bf5763 PM |
1627 | if (op == 0x30 /* BR */ |
1628 | || op == 0x34) /* BSR */ | |
ec32e4be JT |
1629 | { |
1630 | branch_taken: | |
1631 | offset = (insn & 0x001fffff); | |
1632 | if (offset & 0x00100000) | |
1633 | offset |= 0xffe00000; | |
e8d2d628 MK |
1634 | offset *= ALPHA_INSN_SIZE; |
1635 | return (pc + ALPHA_INSN_SIZE + offset); | |
ec32e4be JT |
1636 | } |
1637 | ||
1638 | /* Need to determine if branch is taken; read RA. */ | |
551e4f2e JB |
1639 | regno = (insn >> 21) & 0x1f; |
1640 | switch (op) | |
1641 | { | |
1642 | case 0x31: /* FBEQ */ | |
1643 | case 0x36: /* FBGE */ | |
1644 | case 0x37: /* FBGT */ | |
1645 | case 0x33: /* FBLE */ | |
1646 | case 0x32: /* FBLT */ | |
1647 | case 0x35: /* FBNE */ | |
e17a4113 | 1648 | regno += gdbarch_fp0_regnum (gdbarch); |
551e4f2e JB |
1649 | } |
1650 | ||
7ab2d087 | 1651 | rav = regcache_raw_get_signed (regcache, regno); |
0de94d4b | 1652 | |
ec32e4be JT |
1653 | switch (op) |
1654 | { | |
1655 | case 0x38: /* BLBC */ | |
1656 | if ((rav & 1) == 0) | |
1657 | goto branch_taken; | |
1658 | break; | |
1659 | case 0x3c: /* BLBS */ | |
1660 | if (rav & 1) | |
1661 | goto branch_taken; | |
1662 | break; | |
1663 | case 0x39: /* BEQ */ | |
1664 | if (rav == 0) | |
1665 | goto branch_taken; | |
1666 | break; | |
1667 | case 0x3d: /* BNE */ | |
1668 | if (rav != 0) | |
1669 | goto branch_taken; | |
1670 | break; | |
1671 | case 0x3a: /* BLT */ | |
1672 | if (rav < 0) | |
1673 | goto branch_taken; | |
1674 | break; | |
1675 | case 0x3b: /* BLE */ | |
1676 | if (rav <= 0) | |
1677 | goto branch_taken; | |
1678 | break; | |
1679 | case 0x3f: /* BGT */ | |
1680 | if (rav > 0) | |
1681 | goto branch_taken; | |
1682 | break; | |
1683 | case 0x3e: /* BGE */ | |
1684 | if (rav >= 0) | |
1685 | goto branch_taken; | |
1686 | break; | |
d2427a71 | 1687 | |
0de94d4b JB |
1688 | /* Floating point branches. */ |
1689 | ||
1690 | case 0x31: /* FBEQ */ | |
1691 | if (fp_register_zero_p (rav)) | |
1692 | goto branch_taken; | |
1693 | break; | |
1694 | case 0x36: /* FBGE */ | |
1695 | if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav)) | |
1696 | goto branch_taken; | |
1697 | break; | |
1698 | case 0x37: /* FBGT */ | |
1699 | if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav)) | |
1700 | goto branch_taken; | |
1701 | break; | |
1702 | case 0x33: /* FBLE */ | |
1703 | if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav)) | |
1704 | goto branch_taken; | |
1705 | break; | |
1706 | case 0x32: /* FBLT */ | |
1707 | if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav)) | |
1708 | goto branch_taken; | |
1709 | break; | |
1710 | case 0x35: /* FBNE */ | |
1711 | if (! fp_register_zero_p (rav)) | |
1712 | goto branch_taken; | |
1713 | break; | |
ec32e4be JT |
1714 | } |
1715 | } | |
1716 | ||
1717 | /* Not a branch or branch not taken; target PC is: | |
1718 | pc + 4 */ | |
e8d2d628 | 1719 | return (pc + ALPHA_INSN_SIZE); |
ec32e4be JT |
1720 | } |
1721 | ||
a0ff9e1a | 1722 | std::vector<CORE_ADDR> |
f5ea389a | 1723 | alpha_software_single_step (struct regcache *regcache) |
ec32e4be | 1724 | { |
ac7936df | 1725 | struct gdbarch *gdbarch = regcache->arch (); |
93f9a11f | 1726 | CORE_ADDR pc; |
ec32e4be | 1727 | |
a0ff9e1a | 1728 | pc = alpha_next_pc (regcache, regcache_read_pc (regcache)); |
ec32e4be | 1729 | |
a0ff9e1a | 1730 | return {pc}; |
c906108c SS |
1731 | } |
1732 | ||
dc129d82 | 1733 | \f |
dc129d82 JT |
1734 | /* Initialize the current architecture based on INFO. If possible, re-use an |
1735 | architecture from ARCHES, which is a list of architectures already created | |
1736 | during this debugging session. | |
1737 | ||
1738 | Called e.g. at program startup, when reading a core file, and when reading | |
1739 | a binary file. */ | |
1740 | ||
1741 | static struct gdbarch * | |
1742 | alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1743 | { | |
1744 | struct gdbarch_tdep *tdep; | |
1745 | struct gdbarch *gdbarch; | |
dc129d82 | 1746 | |
dc129d82 | 1747 | /* Find a candidate among extant architectures. */ |
4be87837 DJ |
1748 | arches = gdbarch_list_lookup_by_info (arches, &info); |
1749 | if (arches != NULL) | |
1750 | return arches->gdbarch; | |
dc129d82 | 1751 | |
cdd238da | 1752 | tdep = XCNEW (struct gdbarch_tdep); |
dc129d82 JT |
1753 | gdbarch = gdbarch_alloc (&info, tdep); |
1754 | ||
d2427a71 RH |
1755 | /* Lowest text address. This is used by heuristic_proc_start() |
1756 | to decide when to stop looking. */ | |
594706e6 | 1757 | tdep->vm_min_address = (CORE_ADDR) 0x120000000LL; |
d9b023cc | 1758 | |
36a6271d | 1759 | tdep->dynamic_sigtramp_offset = NULL; |
5868c862 | 1760 | tdep->sigcontext_addr = NULL; |
138e7be5 MK |
1761 | tdep->sc_pc_offset = 2 * 8; |
1762 | tdep->sc_regs_offset = 4 * 8; | |
1763 | tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8; | |
36a6271d | 1764 | |
0963b4bd | 1765 | tdep->jb_pc = -1; /* longjmp support not enabled by default. */ |
accc6d1f | 1766 | |
9823e921 RH |
1767 | tdep->return_in_memory = alpha_return_in_memory_always; |
1768 | ||
dc129d82 JT |
1769 | /* Type sizes */ |
1770 | set_gdbarch_short_bit (gdbarch, 16); | |
1771 | set_gdbarch_int_bit (gdbarch, 32); | |
1772 | set_gdbarch_long_bit (gdbarch, 64); | |
1773 | set_gdbarch_long_long_bit (gdbarch, 64); | |
53375380 PA |
1774 | set_gdbarch_wchar_bit (gdbarch, 64); |
1775 | set_gdbarch_wchar_signed (gdbarch, 0); | |
dc129d82 JT |
1776 | set_gdbarch_float_bit (gdbarch, 32); |
1777 | set_gdbarch_double_bit (gdbarch, 64); | |
1778 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1779 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1780 | ||
1781 | /* Register info */ | |
1782 | set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS); | |
1783 | set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM); | |
dc129d82 JT |
1784 | set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); |
1785 | set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); | |
1786 | ||
1787 | set_gdbarch_register_name (gdbarch, alpha_register_name); | |
c483c494 | 1788 | set_gdbarch_register_type (gdbarch, alpha_register_type); |
dc129d82 JT |
1789 | |
1790 | set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); | |
1791 | set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); | |
1792 | ||
c483c494 RH |
1793 | set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p); |
1794 | set_gdbarch_register_to_value (gdbarch, alpha_register_to_value); | |
1795 | set_gdbarch_value_to_register (gdbarch, alpha_value_to_register); | |
dc129d82 | 1796 | |
615967cb RH |
1797 | set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p); |
1798 | ||
d2427a71 | 1799 | /* Prologue heuristics. */ |
dc129d82 JT |
1800 | set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); |
1801 | ||
d2427a71 | 1802 | /* Call info. */ |
dc129d82 | 1803 | |
9823e921 | 1804 | set_gdbarch_return_value (gdbarch, alpha_return_value); |
dc129d82 JT |
1805 | |
1806 | /* Settings for calling functions in the inferior. */ | |
c88e30c0 | 1807 | set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call); |
d2427a71 RH |
1808 | |
1809 | /* Methods for saving / extracting a dummy frame's ID. */ | |
6834c9bb | 1810 | set_gdbarch_dummy_id (gdbarch, alpha_dummy_id); |
d2427a71 RH |
1811 | |
1812 | /* Return the unwound PC value. */ | |
1813 | set_gdbarch_unwind_pc (gdbarch, alpha_unwind_pc); | |
dc129d82 JT |
1814 | |
1815 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
36a6271d | 1816 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
dc129d82 | 1817 | |
04180708 YQ |
1818 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1819 | alpha_breakpoint::kind_from_pc); | |
1820 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1821 | alpha_breakpoint::bp_from_kind); | |
e8d2d628 | 1822 | set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); |
9d519230 | 1823 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
95b80706 | 1824 | |
46ad3598 UW |
1825 | /* Handles single stepping of atomic sequences. */ |
1826 | set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence); | |
1827 | ||
44dffaac | 1828 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 1829 | gdbarch_init_osabi (info, gdbarch); |
44dffaac | 1830 | |
accc6d1f JT |
1831 | /* Now that we have tuned the configuration, set a few final things |
1832 | based on what the OS ABI has told us. */ | |
1833 | ||
1834 | if (tdep->jb_pc >= 0) | |
1835 | set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target); | |
1836 | ||
6834c9bb JB |
1837 | frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind); |
1838 | frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind); | |
dc129d82 | 1839 | |
d2427a71 | 1840 | frame_base_set_default (gdbarch, &alpha_heuristic_frame_base); |
accc6d1f | 1841 | |
d2427a71 | 1842 | return gdbarch; |
dc129d82 JT |
1843 | } |
1844 | ||
baa490c4 RH |
1845 | void |
1846 | alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
1847 | { | |
6834c9bb | 1848 | dwarf2_append_unwinders (gdbarch); |
336d1bba | 1849 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
baa490c4 RH |
1850 | } |
1851 | ||
c906108c | 1852 | void |
fba45db2 | 1853 | _initialize_alpha_tdep (void) |
c906108c | 1854 | { |
c906108c | 1855 | |
d2427a71 | 1856 | gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); |
c906108c SS |
1857 | |
1858 | /* Let the user set the fence post for heuristic_proc_start. */ | |
1859 | ||
1860 | /* We really would like to have both "0" and "unlimited" work, but | |
1861 | command.c doesn't deal with that. So make it a var_zinteger | |
1862 | because the user can always use "999999" or some such for unlimited. */ | |
edefbb7c AC |
1863 | /* We need to throw away the frame cache when we set this, since it |
1864 | might change our ability to get backtraces. */ | |
1865 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, | |
7915a72c AC |
1866 | &heuristic_fence_post, _("\ |
1867 | Set the distance searched for the start of a function."), _("\ | |
1868 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
1869 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
1870 | program for the start of a function. This command sets the distance of the\n\ | |
323e0a4a | 1871 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 1872 | reinit_frame_cache_sfunc, |
0963b4bd MS |
1873 | NULL, /* FIXME: i18n: The distance searched for |
1874 | the start of a function is \"%d\". */ | |
edefbb7c | 1875 | &setlist, &showlist); |
c906108c | 1876 | } |