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GDB: Fix the overflow in addr/line_is_displayed()
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
CommitLineData
e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
b811d2c2 3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
4de283e4
TT		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
4de283e4 28#include "frame.h"
c4f35dd8
MK		 29#include "frame-base.h"
30#include "frame-unwind.h"
d55e5aa6
TT		 31#include "inferior.h"
32#include "infrun.h"
4de283e4
TT		 33#include "gdbcmd.h"
34#include "gdbcore.h"
c4f35dd8 35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
4de283e4
TT		 39#include "disasm.h"
40#include "amd64-tdep.h"
41#include "i387-tdep.h"
268a13a5 42#include "gdbsupport/x86-xstate.h"
4de283e4 43#include <algorithm>
22916b07 44#include "target-descriptions.h"
4de283e4
TT		 45#include "arch/amd64.h"
46#include "producer.h"
47#include "ax.h"
48#include "ax-gdb.h"
268a13a5 49#include "gdbsupport/byte-vector.h"
4de283e4 50#include "osabi.h"
1d509aa6 51#include "x86-tdep.h"
6710bf39 52
e53bef9f
MK		 53/* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
90f90721 55 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
59
402ecd56 60/* Register information. */
c4f35dd8 61
6707b003 62static const char *amd64_register_names[] =
de220d0f 63{
6707b003 64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 65
66 /* %r8 is indeed register number 8. */
6707b003
UW		 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 69
af233647 70 /* %st0 is register number 24. */
6707b003
UW		 71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 73
af233647 74 /* %xmm0 is register number 40. */
6707b003
UW		 75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
77 "mxcsr",
0e04a514
ML		 78};
79
a055a187
L		 80static const char *amd64_ymm_names[] =
81{
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
86};
87
01f9f808
MS		 88static const char *amd64_ymm_avx512_names[] =
89{
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
94};
95
a055a187
L		 96static const char *amd64_ymmh_names[] =
97{
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
102};
de220d0f 103
01f9f808
MS		 104static const char *amd64_ymmh_avx512_names[] =
105{
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
110};
111
e43e105e
WT		 112static const char *amd64_mpx_names[] =
113{
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
115};
116
01f9f808
MS		 117static const char *amd64_k_names[] =
118{
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
121};
122
123static const char *amd64_zmmh_names[] =
124{
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
133};
134
135static const char *amd64_zmm_names[] =
136{
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
145};
146
147static const char *amd64_xmm_avx512_names[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
152};
153
51547df6
MS		 154static const char *amd64_pkeys_names[] = {
155 "pkru"
156};
157
c4f35dd8
MK		 158/* DWARF Register Number Mapping as defined in the System V psABI,
159 section 3.6. */
53e95fcf 160
e53bef9f 161static int amd64_dwarf_regmap[] =
0e04a514 162{
c4f35dd8 163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 167
168 /* Frame Pointer Register RBP. */
90f90721 169 AMD64_RBP_REGNUM,
c4f35dd8
MK		 170
171 /* Stack Pointer Register RSP. */
90f90721 172 AMD64_RSP_REGNUM,
c4f35dd8
MK		 173
174 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 175 AMD64_R8_REGNUM, /* %r8 */
176 AMD64_R9_REGNUM, /* %r9 */
177 AMD64_R10_REGNUM, /* %r10 */
178 AMD64_R11_REGNUM, /* %r11 */
179 AMD64_R12_REGNUM, /* %r12 */
180 AMD64_R13_REGNUM, /* %r13 */
181 AMD64_R14_REGNUM, /* %r14 */
182 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 183
59207364 184 /* Return Address RA. Mapped to RIP. */
90f90721 185 AMD64_RIP_REGNUM,
c4f35dd8
MK		 186
187 /* SSE Registers 0 - 7. */
90f90721
MK		 188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 192
193 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 198
199 /* Floating Point Registers 0-7. */
90f90721
MK		 200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 204
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
210
c6f4c129
JB		 211 /* Control and Status Flags Register. */
212 AMD64_EFLAGS_REGNUM,
213
214 /* Selector Registers. */
215 AMD64_ES_REGNUM,
216 AMD64_CS_REGNUM,
217 AMD64_SS_REGNUM,
218 AMD64_DS_REGNUM,
219 AMD64_FS_REGNUM,
220 AMD64_GS_REGNUM,
221 -1,
222 -1,
223
224 /* Segment Base Address Registers. */
225 -1,
226 -1,
227 -1,
228 -1,
229
230 /* Special Selector Registers. */
231 -1,
232 -1,
233
234 /* Floating Point Control Registers. */
235 AMD64_MXCSR_REGNUM,
236 AMD64_FCTRL_REGNUM,
237 AMD64_FSTAT_REGNUM
c4f35dd8 238};
0e04a514 239
e53bef9f
MK		 240static const int amd64_dwarf_regmap_len =
241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 242
c4f35dd8
MK		 243/* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
26abbdc4 245
c4f35dd8 246static int
d3f73121 247amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 248{
a055a187
L		 249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 251 int regnum = -1;
53e95fcf 252
16aff9a6 253 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 254 regnum = amd64_dwarf_regmap[reg];
53e95fcf 255
0fde2c53 256 if (ymm0_regnum >= 0
a055a187
L		 257 && i386_xmm_regnum_p (gdbarch, regnum))
258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 259
260 return regnum;
53e95fcf 261}
d532c08f 262
35669430
DE		 263/* Map architectural register numbers to gdb register numbers. */
264
265static const int amd64_arch_regmap[16] =
266{
267 AMD64_RAX_REGNUM, /* %rax */
268 AMD64_RCX_REGNUM, /* %rcx */
269 AMD64_RDX_REGNUM, /* %rdx */
270 AMD64_RBX_REGNUM, /* %rbx */
271 AMD64_RSP_REGNUM, /* %rsp */
272 AMD64_RBP_REGNUM, /* %rbp */
273 AMD64_RSI_REGNUM, /* %rsi */
274 AMD64_RDI_REGNUM, /* %rdi */
275 AMD64_R8_REGNUM, /* %r8 */
276 AMD64_R9_REGNUM, /* %r9 */
277 AMD64_R10_REGNUM, /* %r10 */
278 AMD64_R11_REGNUM, /* %r11 */
279 AMD64_R12_REGNUM, /* %r12 */
280 AMD64_R13_REGNUM, /* %r13 */
281 AMD64_R14_REGNUM, /* %r14 */
282 AMD64_R15_REGNUM /* %r15 */
283};
284
285static const int amd64_arch_regmap_len =
286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
287
288/* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
290
291static int
292amd64_arch_reg_to_regnum (int reg)
293{
294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
295
296 return amd64_arch_regmap[reg];
297}
298
1ba53b71
L		 299/* Register names for byte pseudo-registers. */
300
301static const char *amd64_byte_names[] =
302{
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
1ba53b71
L		 306};
307
fe01d668
L		 308/* Number of lower byte registers. */
309#define AMD64_NUM_LOWER_BYTE_REGS 16
310
1ba53b71
L		 311/* Register names for word pseudo-registers. */
312
313static const char *amd64_word_names[] =
314{
9cad29ac 315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
317};
318
319/* Register names for dword pseudo-registers. */
320
321static const char *amd64_dword_names[] =
322{
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
325 "eip"
1ba53b71
L		 326};
327
328/* Return the name of register REGNUM. */
329
330static const char *
331amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
332{
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (i386_byte_regnum_p (gdbarch, regnum))
335 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 336 else if (i386_zmm_regnum_p (gdbarch, regnum))
337 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 338 else if (i386_ymm_regnum_p (gdbarch, regnum))
339 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 342 else if (i386_word_regnum_p (gdbarch, regnum))
343 return amd64_word_names[regnum - tdep->ax_regnum];
344 else if (i386_dword_regnum_p (gdbarch, regnum))
345 return amd64_dword_names[regnum - tdep->eax_regnum];
346 else
347 return i386_pseudo_register_name (gdbarch, regnum);
348}
349
3543a589
TT		 350static struct value *
351amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
849d0ba8 352 readable_regcache *regcache,
3543a589 353 int regnum)
1ba53b71 354{
1ba53b71 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3543a589 356
925047fe 357 value *result_value = allocate_value (register_type (gdbarch, regnum));
3543a589
TT		 358 VALUE_LVAL (result_value) = lval_register;
359 VALUE_REGNUM (result_value) = regnum;
925047fe 360 gdb_byte *buf = value_contents_raw (result_value);
1ba53b71
L		 361
362 if (i386_byte_regnum_p (gdbarch, regnum))
363 {
364 int gpnum = regnum - tdep->al_regnum;
365
366 /* Extract (always little endian). */
fe01d668
L		 367 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
368 {
925047fe
SM		 369 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
370 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
371
fe01d668 372 /* Special handling for AH, BH, CH, DH. */
925047fe 373 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 374 if (status == REG_VALID)
375 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 376 else
377 mark_value_bytes_unavailable (result_value, 0,
378 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 379 }
380 else
381 {
925047fe
SM		 382 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
383 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 384 if (status == REG_VALID)
385 memcpy (buf, raw_buf, 1);
3543a589
TT		 386 else
387 mark_value_bytes_unavailable (result_value, 0,
388 TYPE_LENGTH (value_type (result_value)));
fe01d668 389 }
1ba53b71
L		 390 }
391 else if (i386_dword_regnum_p (gdbarch, regnum))
392 {
393 int gpnum = regnum - tdep->eax_regnum;
925047fe 394 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
1ba53b71 395 /* Extract (always little endian). */
925047fe 396 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 397 if (status == REG_VALID)
398 memcpy (buf, raw_buf, 4);
3543a589
TT		 399 else
400 mark_value_bytes_unavailable (result_value, 0,
401 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 402 }
403 else
3543a589
TT		 404 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
405 result_value);
406
407 return result_value;
1ba53b71
L		 408}
409
410static void
411amd64_pseudo_register_write (struct gdbarch *gdbarch,
412 struct regcache *regcache,
413 int regnum, const gdb_byte *buf)
414{
1ba53b71
L		 415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416
417 if (i386_byte_regnum_p (gdbarch, regnum))
418 {
419 int gpnum = regnum - tdep->al_regnum;
420
fe01d668
L		 421 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
422 {
925047fe
SM		 423 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
424 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
425
fe01d668 426 /* Read ... AH, BH, CH, DH. */
925047fe 427 regcache->raw_read (gpnum, raw_buf);
fe01d668
L		 428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf + 1, buf, 1);
430 /* ... Write. */
925047fe 431 regcache->raw_write (gpnum, raw_buf);
fe01d668
L		 432 }
433 else
434 {
925047fe
SM		 435 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
436
fe01d668 437 /* Read ... */
0b883586 438 regcache->raw_read (gpnum, raw_buf);
fe01d668
L		 439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf, buf, 1);
441 /* ... Write. */
10eaee5f 442 regcache->raw_write (gpnum, raw_buf);
fe01d668 443 }
1ba53b71
L		 444 }
445 else if (i386_dword_regnum_p (gdbarch, regnum))
446 {
447 int gpnum = regnum - tdep->eax_regnum;
925047fe 448 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
1ba53b71
L		 449
450 /* Read ... */
0b883586 451 regcache->raw_read (gpnum, raw_buf);
1ba53b71
L		 452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf, buf, 4);
454 /* ... Write. */
10eaee5f 455 regcache->raw_write (gpnum, raw_buf);
1ba53b71
L		 456 }
457 else
458 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
459}
460
62e5fd57
MK		 461/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
462
463static int
464amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
465 struct agent_expr *ax, int regnum)
466{
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468
469 if (i386_byte_regnum_p (gdbarch, regnum))
470 {
471 int gpnum = regnum - tdep->al_regnum;
472
473 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
474 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
475 else
476 ax_reg_mask (ax, gpnum);
477 return 0;
478 }
479 else if (i386_dword_regnum_p (gdbarch, regnum))
480 {
481 int gpnum = regnum - tdep->eax_regnum;
482
483 ax_reg_mask (ax, gpnum);
484 return 0;
485 }
486 else
487 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
488}
489
53e95fcf
JS		 490\f
491
bf4d6c1c
JB		 492/* Register classes as defined in the psABI. */
493
494enum amd64_reg_class
495{
496 AMD64_INTEGER,
497 AMD64_SSE,
498 AMD64_SSEUP,
499 AMD64_X87,
500 AMD64_X87UP,
501 AMD64_COMPLEX_X87,
502 AMD64_NO_CLASS,
503 AMD64_MEMORY
504};
505
efb1c01c
MK		 506/* Return the union class of CLASS1 and CLASS2. See the psABI for
507 details. */
508
509static enum amd64_reg_class
510amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
511{
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1 == class2)
514 return class1;
515
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1 == AMD64_NO_CLASS)
519 return class2;
520 if (class2 == AMD64_NO_CLASS)
521 return class1;
522
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
525 return AMD64_MEMORY;
526
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
529 return AMD64_INTEGER;
530
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
534 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
535 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
536 return AMD64_MEMORY;
537
538 /* Rule (f): Otherwise class SSE is used. */
539 return AMD64_SSE;
540}
541
fe978cb0 542static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 543
4aa866af 544/* Return true if TYPE is a structure or union with unaligned fields. */
79b1ab3d 545
4aa866af
LS		 546static bool
547amd64_has_unaligned_fields (struct type *type)
79b1ab3d 548{
4aa866af
LS		 549 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
550 || TYPE_CODE (type) == TYPE_CODE_UNION)
551 {
552 for (int i = 0; i < TYPE_NFIELDS (type); i++)
553 {
554 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
555 int bitpos = TYPE_FIELD_BITPOS (type, i);
556 int align = type_align(subtype);
557
a59240a4
TT		 558 /* Ignore static fields, empty fields (for example nested
559 empty structures), and bitfields (these are handled by
560 the caller). */
4aa866af
LS		 561 if (field_is_static (&TYPE_FIELD (type, i))
562 || (TYPE_FIELD_BITSIZE (type, i) == 0
a59240a4
TT		 563 && TYPE_LENGTH (subtype) == 0)
564 || TYPE_FIELD_PACKED (type, i))
4aa866af
LS		 565 continue;
566
567 if (bitpos % 8 != 0)
568 return true;
569
570 int bytepos = bitpos / 8;
571 if (bytepos % align != 0)
572 return true;
573
a59240a4 574 if (amd64_has_unaligned_fields (subtype))
4aa866af
LS		 575 return true;
576 }
577 }
79b1ab3d 578
4aa866af 579 return false;
79b1ab3d
MK		 580}
581
d10eccaa
TV		 582/* Classify field I of TYPE starting at BITOFFSET according to the rules for
583 structures and union types, and store the result in THECLASS. */
584
585static void
586amd64_classify_aggregate_field (struct type *type, int i,
587 enum amd64_reg_class theclass[2],
588 unsigned int bitoffset)
589{
590 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
591 int bitpos = bitoffset + TYPE_FIELD_BITPOS (type, i);
592 int pos = bitpos / 64;
593 enum amd64_reg_class subclass[2];
594 int bitsize = TYPE_FIELD_BITSIZE (type, i);
595 int endpos;
596
597 if (bitsize == 0)
598 bitsize = TYPE_LENGTH (subtype) * 8;
599 endpos = (bitpos + bitsize - 1) / 64;
600
601 /* Ignore static fields, or empty fields, for example nested
602 empty structures.*/
603 if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0)
604 return;
605
606 if (TYPE_CODE (subtype) == TYPE_CODE_STRUCT
607 || TYPE_CODE (subtype) == TYPE_CODE_UNION)
608 {
609 /* Each field of an object is classified recursively. */
610 int j;
611 for (j = 0; j < TYPE_NFIELDS (subtype); j++)
612 amd64_classify_aggregate_field (subtype, j, theclass, bitpos);
613 return;
614 }
615
616 gdb_assert (pos == 0 || pos == 1);
617
618 amd64_classify (subtype, subclass);
619 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
620 if (bitsize <= 64 && pos == 0 && endpos == 1)
621 /* This is a bit of an odd case: We have a field that would
622 normally fit in one of the two eightbytes, except that
623 it is placed in a way that this field straddles them.
624 This has been seen with a structure containing an array.
625
626 The ABI is a bit unclear in this case, but we assume that
627 this field's class (stored in subclass[0]) must also be merged
628 into class[1]. In other words, our field has a piece stored
629 in the second eight-byte, and thus its class applies to
630 the second eight-byte as well.
631
632 In the case where the field length exceeds 8 bytes,
633 it should not be necessary to merge the field class
634 into class[1]. As LEN > 8, subclass[1] is necessarily
635 different from AMD64_NO_CLASS. If subclass[1] is equal
636 to subclass[0], then the normal class[1]/subclass[1]
637 merging will take care of everything. For subclass[1]
638 to be different from subclass[0], I can only see the case
639 where we have a SSE/SSEUP or X87/X87UP pair, which both
640 use up all 16 bytes of the aggregate, and are already
641 handled just fine (because each portion sits on its own
642 8-byte). */
643 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
644 if (pos == 0)
645 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
646}
647
efb1c01c
MK		 648/* Classify TYPE according to the rules for aggregate (structures and
649 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 650
651static void
fe978cb0 652amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 653{
4aa866af 654 /* 1. If the size of an object is larger than two eightbytes, or it has
efb1c01c 655 unaligned fields, it has class memory. */
4aa866af 656 if (TYPE_LENGTH (type) > 16 || amd64_has_unaligned_fields (type))
53e95fcf 657 {
fe978cb0 658 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 659 return;
53e95fcf 660 }
efb1c01c
MK		 661
662 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 663 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 664
665 /* 3. Each field of an object is classified recursively so that
666 always two fields are considered. The resulting class is
667 calculated according to the classes of the fields in the
668 eightbyte: */
669
670 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 671 {
efb1c01c
MK		 672 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
673
674 /* All fields in an array have the same type. */
fe978cb0
PA		 675 amd64_classify (subtype, theclass);
676 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
677 theclass[1] = theclass[0];
8ffd9b1b 678 }
53e95fcf
JS		 679 else
680 {
efb1c01c 681 int i;
53e95fcf 682
efb1c01c
MK		 683 /* Structure or union. */
684 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
685 || TYPE_CODE (type) == TYPE_CODE_UNION);
686
687 for (i = 0; i < TYPE_NFIELDS (type); i++)
d10eccaa 688 amd64_classify_aggregate_field (type, i, theclass, 0);
53e95fcf 689 }
efb1c01c
MK		 690
691 /* 4. Then a post merger cleanup is done: */
692
693 /* Rule (a): If one of the classes is MEMORY, the whole argument is
694 passed in memory. */
fe978cb0
PA		 695 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
696 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 697
177b42fe 698 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 699 SSE. */
fe978cb0
PA		 700 if (theclass[0] == AMD64_SSEUP)
701 theclass[0] = AMD64_SSE;
702 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
703 theclass[1] = AMD64_SSE;
efb1c01c
MK		 704}
705
706/* Classify TYPE, and store the result in CLASS. */
707
bf4d6c1c 708static void
fe978cb0 709amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 710{
711 enum type_code code = TYPE_CODE (type);
712 int len = TYPE_LENGTH (type);
713
fe978cb0 714 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 715
716 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 717 long, long long, and pointers are in the INTEGER class. Similarly,
718 range types, used by languages such as Ada, are also in the INTEGER
719 class. */
efb1c01c 720 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 721 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 722 || code == TYPE_CODE_CHAR
aa006118 723 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
efb1c01c 724 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 725 theclass[0] = AMD64_INTEGER;
efb1c01c 726
5daa78cc
TJB		 727 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
728 are in class SSE. */
729 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
730 && (len == 4 || len == 8))
efb1c01c 731 /* FIXME: __m64 . */
fe978cb0 732 theclass[0] = AMD64_SSE;
efb1c01c 733
5daa78cc
TJB		 734 /* Arguments of types __float128, _Decimal128 and __m128 are split into
735 two halves. The least significant ones belong to class SSE, the most
efb1c01c 736 significant one to class SSEUP. */
5daa78cc
TJB		 737 else if (code == TYPE_CODE_DECFLOAT && len == 16)
738 /* FIXME: __float128, __m128. */
fe978cb0 739 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 740
741 /* The 64-bit mantissa of arguments of type long double belongs to
742 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
743 class X87UP. */
744 else if (code == TYPE_CODE_FLT && len == 16)
745 /* Class X87 and X87UP. */
fe978cb0 746 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 747
7f7930dd
MK		 748 /* Arguments of complex T where T is one of the types float or
749 double get treated as if they are implemented as:
750
751 struct complexT {
752 T real;
753 T imag;
5f52445b
YQ		 754 };
755
756 */
7f7930dd 757 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 758 theclass[0] = AMD64_SSE;
7f7930dd 759 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 760 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 761
762 /* A variable of type complex long double is classified as type
763 COMPLEX_X87. */
764 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 765 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 766
efb1c01c
MK		 767 /* Aggregates. */
768 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
769 || code == TYPE_CODE_UNION)
fe978cb0 770 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 771}
772
773static enum return_value_convention
6a3a010b 774amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 775 struct type *type, struct regcache *regcache,
42835c2b 776 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 777{
fe978cb0 778 enum amd64_reg_class theclass[2];
efb1c01c 779 int len = TYPE_LENGTH (type);
90f90721
MK		 780 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
781 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 782 int integer_reg = 0;
783 int sse_reg = 0;
784 int i;
785
786 gdb_assert (!(readbuf && writebuf));
787
788 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 789 amd64_classify (type, theclass);
efb1c01c
MK		 790
791 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 792 for the return value and passes the address of this storage in
0963b4bd 793 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 794 this address becomes a hidden first argument.
795
796 On return %rax will contain the address that has been passed in
797 by the caller in %rdi. */
fe978cb0 798 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 799 {
800 /* As indicated by the comment above, the ABI guarantees that we
801 can always find the return value just after the function has
802 returned. */
803
804 if (readbuf)
805 {
806 ULONGEST addr;
807
808 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
809 read_memory (addr, readbuf, TYPE_LENGTH (type));
810 }
811
812 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
813 }
efb1c01c 814
7f7930dd
MK		 815 /* 8. If the class is COMPLEX_X87, the real part of the value is
816 returned in %st0 and the imaginary part in %st1. */
fe978cb0 817 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 818 {
819 if (readbuf)
820 {
0b883586
SM		 821 regcache->raw_read (AMD64_ST0_REGNUM, readbuf);
822 regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16);
7f7930dd
MK		 823 }
824
825 if (writebuf)
826 {
827 i387_return_value (gdbarch, regcache);
10eaee5f
SM		 828 regcache->raw_write (AMD64_ST0_REGNUM, writebuf);
829 regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16);
7f7930dd
MK		 830
831 /* Fix up the tag word such that both %st(0) and %st(1) are
832 marked as valid. */
833 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
834 }
835
836 return RETURN_VALUE_REGISTER_CONVENTION;
837 }
838
fe978cb0 839 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 840 gdb_assert (len <= 16);
efb1c01c
MK		 841
842 for (i = 0; len > 0; i++, len -= 8)
843 {
844 int regnum = -1;
845 int offset = 0;
846
fe978cb0 847 switch (theclass[i])
efb1c01c
MK		 848 {
849 case AMD64_INTEGER:
850 /* 3. If the class is INTEGER, the next available register
851 of the sequence %rax, %rdx is used. */
852 regnum = integer_regnum[integer_reg++];
853 break;
854
855 case AMD64_SSE:
856 /* 4. If the class is SSE, the next available SSE register
857 of the sequence %xmm0, %xmm1 is used. */
858 regnum = sse_regnum[sse_reg++];
859 break;
860
861 case AMD64_SSEUP:
862 /* 5. If the class is SSEUP, the eightbyte is passed in the
863 upper half of the last used SSE register. */
864 gdb_assert (sse_reg > 0);
865 regnum = sse_regnum[sse_reg - 1];
866 offset = 8;
867 break;
868
869 case AMD64_X87:
870 /* 6. If the class is X87, the value is returned on the X87
871 stack in %st0 as 80-bit x87 number. */
90f90721 872 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 873 if (writebuf)
874 i387_return_value (gdbarch, regcache);
875 break;
876
877 case AMD64_X87UP:
878 /* 7. If the class is X87UP, the value is returned together
879 with the previous X87 value in %st0. */
fe978cb0 880 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 881 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 882 offset = 8;
883 len = 2;
884 break;
885
886 case AMD64_NO_CLASS:
887 continue;
888
889 default:
890 gdb_assert (!"Unexpected register class.");
891 }
892
893 gdb_assert (regnum != -1);
894
895 if (readbuf)
502fe83e
SM		 896 regcache->raw_read_part (regnum, offset, std::min (len, 8),
897 readbuf + i * 8);
efb1c01c 898 if (writebuf)
4f0420fd
SM		 899 regcache->raw_write_part (regnum, offset, std::min (len, 8),
900 writebuf + i * 8);
efb1c01c
MK		 901 }
902
903 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 904}
905\f
906
720aa428 907static CORE_ADDR
cf84fa6b
AH		 908amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args,
909 CORE_ADDR sp, function_call_return_method return_method)
720aa428 910{
bf4d6c1c
JB		 911 static int integer_regnum[] =
912 {
913 AMD64_RDI_REGNUM, /* %rdi */
914 AMD64_RSI_REGNUM, /* %rsi */
915 AMD64_RDX_REGNUM, /* %rdx */
916 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 917 AMD64_R8_REGNUM, /* %r8 */
918 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 919 };
720aa428
MK		 920 static int sse_regnum[] =
921 {
922 /* %xmm0 ... %xmm7 */
90f90721
MK		 923 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
924 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
925 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
926 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 927 };
224c3ddb 928 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 929 int num_stack_args = 0;
930 int num_elements = 0;
931 int element = 0;
932 int integer_reg = 0;
933 int sse_reg = 0;
934 int i;
935
6470d250 936 /* Reserve a register for the "hidden" argument. */
cf84fa6b 937if (return_method == return_method_struct)
6470d250
MK		 938 integer_reg++;
939
720aa428
MK		 940 for (i = 0; i < nargs; i++)
941 {
4991999e 942 struct type *type = value_type (args[i]);
720aa428 943 int len = TYPE_LENGTH (type);
fe978cb0 944 enum amd64_reg_class theclass[2];
720aa428
MK		 945 int needed_integer_regs = 0;
946 int needed_sse_regs = 0;
947 int j;
948
949 /* Classify argument. */
fe978cb0 950 amd64_classify (type, theclass);
720aa428
MK		 951
952 /* Calculate the number of integer and SSE registers needed for
953 this argument. */
954 for (j = 0; j < 2; j++)
955 {
fe978cb0 956 if (theclass[j] == AMD64_INTEGER)
720aa428 957 needed_integer_regs++;
fe978cb0 958 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 959 needed_sse_regs++;
960 }
961
962 /* Check whether enough registers are available, and if the
963 argument should be passed in registers at all. */
bf4d6c1c 964 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 965 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
966 || (needed_integer_regs == 0 && needed_sse_regs == 0))
967 {
968 /* The argument will be passed on the stack. */
969 num_elements += ((len + 7) / 8);
849e9755 970 stack_args[num_stack_args++] = args[i];
720aa428
MK		 971 }
972 else
973 {
974 /* The argument will be passed in registers. */
d8de1ef7
MK		 975 const gdb_byte *valbuf = value_contents (args[i]);
976 gdb_byte buf[8];
720aa428
MK		 977
978 gdb_assert (len <= 16);
979
980 for (j = 0; len > 0; j++, len -= 8)
981 {
982 int regnum = -1;
983 int offset = 0;
984
fe978cb0 985 switch (theclass[j])
720aa428
MK		 986 {
987 case AMD64_INTEGER:
bf4d6c1c 988 regnum = integer_regnum[integer_reg++];
720aa428
MK		 989 break;
990
991 case AMD64_SSE:
992 regnum = sse_regnum[sse_reg++];
993 break;
994
995 case AMD64_SSEUP:
996 gdb_assert (sse_reg > 0);
997 regnum = sse_regnum[sse_reg - 1];
998 offset = 8;
999 break;
1000
745ff14e
TV		 1001 case AMD64_NO_CLASS:
1002 continue;
1003
720aa428
MK		 1004 default:
1005 gdb_assert (!"Unexpected register class.");
1006 }
1007
1008 gdb_assert (regnum != -1);
1009 memset (buf, 0, sizeof buf);
325fac50 1010 memcpy (buf, valbuf + j * 8, std::min (len, 8));
4f0420fd 1011 regcache->raw_write_part (regnum, offset, 8, buf);
720aa428
MK		 1012 }
1013 }
1014 }
1015
1016 /* Allocate space for the arguments on the stack. */
1017 sp -= num_elements * 8;
1018
1019 /* The psABI says that "The end of the input argument area shall be
1020 aligned on a 16 byte boundary." */
1021 sp &= ~0xf;
1022
1023 /* Write out the arguments to the stack. */
1024 for (i = 0; i < num_stack_args; i++)
1025 {
4991999e 1026 struct type *type = value_type (stack_args[i]);
d8de1ef7 1027 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 1028 int len = TYPE_LENGTH (type);
1029
1030 write_memory (sp + element * 8, valbuf, len);
1031 element += ((len + 7) / 8);
720aa428
MK		 1032 }
1033
1034 /* The psABI says that "For calls that may call functions that use
1035 varargs or stdargs (prototype-less calls or calls to functions
1036 containing ellipsis (...) in the declaration) %al is used as
1037 hidden argument to specify the number of SSE registers used. */
90f90721 1038 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 1039 return sp;
1040}
1041
c4f35dd8 1042static CORE_ADDR
7d9b040b 1043amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 1044 struct regcache *regcache, CORE_ADDR bp_addr,
1045 int nargs, struct value **args, CORE_ADDR sp,
cf84fa6b
AH		 1046 function_call_return_method return_method,
1047 CORE_ADDR struct_addr)
53e95fcf 1048{
e17a4113 1049 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 1050 gdb_byte buf[8];
c4f35dd8 1051
4a612d6f
WT		 1052 /* BND registers can be in arbitrary values at the moment of the
1053 inferior call. This can cause boundary violations that are not
1054 due to a real bug or even desired by the user. The best to be done
1055 is set the BND registers to allow access to the whole memory, INIT
1056 state, before pushing the inferior call. */
1057 i387_reset_bnd_regs (gdbarch, regcache);
1058
c4f35dd8 1059 /* Pass arguments. */
cf84fa6b 1060 sp = amd64_push_arguments (regcache, nargs, args, sp, return_method);
c4f35dd8
MK		 1061
1062 /* Pass "hidden" argument". */
cf84fa6b 1063 if (return_method == return_method_struct)
c4f35dd8 1064 {
e17a4113 1065 store_unsigned_integer (buf, 8, byte_order, struct_addr);
b66f5587 1066 regcache->cooked_write (AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1067 }
1068
1069 /* Store return address. */
1070 sp -= 8;
e17a4113 1071 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1072 write_memory (sp, buf, 8);
1073
1074 /* Finally, update the stack pointer... */
e17a4113 1075 store_unsigned_integer (buf, 8, byte_order, sp);
b66f5587 1076 regcache->cooked_write (AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1077
1078 /* ...and fake a frame pointer. */
b66f5587 1079 regcache->cooked_write (AMD64_RBP_REGNUM, buf);
c4f35dd8 1080
3e210248 1081 return sp + 16;
53e95fcf 1082}
c4f35dd8 1083\f
35669430
DE		 1084/* Displaced instruction handling. */
1085
1086/* A partially decoded instruction.
1087 This contains enough details for displaced stepping purposes. */
1088
1089struct amd64_insn
1090{
1091 /* The number of opcode bytes. */
1092 int opcode_len;
50a1fdd5
PA		 1093 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1094 not present. */
1095 int enc_prefix_offset;
35669430
DE		 1096 /* The offset to the first opcode byte. */
1097 int opcode_offset;
1098 /* The offset to the modrm byte or -1 if not present. */
1099 int modrm_offset;
1100
1101 /* The raw instruction. */
1102 gdb_byte *raw_insn;
1103};
1104
cfba9872 1105struct amd64_displaced_step_closure : public displaced_step_closure
35669430 1106{
cfba9872
SM		 1107 amd64_displaced_step_closure (int insn_buf_len)
1108 : insn_buf (insn_buf_len, 0)
1109 {}
1110
35669430 1111 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
cfba9872 1112 int tmp_used = 0;
35669430
DE		 1113 int tmp_regno;
1114 ULONGEST tmp_save;
1115
1116 /* Details of the instruction. */
1117 struct amd64_insn insn_details;
1118
cfba9872
SM		 1119 /* The possibly modified insn. */
1120 gdb::byte_vector insn_buf;
35669430
DE		 1121};
1122
1123/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1124 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1125 at which point delete these in favor of libopcodes' versions). */
1126
1127static const unsigned char onebyte_has_modrm[256] = {
1128 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1129 /* ------------------------------- */
1130 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1131 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1132 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1133 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1134 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1135 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1136 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1137 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1138 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1139 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1140 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1141 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1142 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1143 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1144 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1145 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1146 /* ------------------------------- */
1147 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1148};
1149
1150static const unsigned char twobyte_has_modrm[256] = {
1151 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1152 /* ------------------------------- */
1153 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1154 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1155 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1156 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1157 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1158 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1159 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1160 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1161 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1162 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1163 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1164 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1165 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1166 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1167 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1168 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1169 /* ------------------------------- */
1170 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1171};
1172
1173static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1174
1175static int
1176rex_prefix_p (gdb_byte pfx)
1177{
1178 return REX_PREFIX_P (pfx);
1179}
1180
50a1fdd5
PA		 1181/* True if PFX is the start of the 2-byte VEX prefix. */
1182
1183static bool
1184vex2_prefix_p (gdb_byte pfx)
1185{
1186 return pfx == 0xc5;
1187}
1188
1189/* True if PFX is the start of the 3-byte VEX prefix. */
1190
1191static bool
1192vex3_prefix_p (gdb_byte pfx)
1193{
1194 return pfx == 0xc4;
1195}
1196
35669430
DE		 1197/* Skip the legacy instruction prefixes in INSN.
1198 We assume INSN is properly sentineled so we don't have to worry
1199 about falling off the end of the buffer. */
1200
1201static gdb_byte *
1903f0e6 1202amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1203{
1204 while (1)
1205 {
1206 switch (*insn)
1207 {
1208 case DATA_PREFIX_OPCODE:
1209 case ADDR_PREFIX_OPCODE:
1210 case CS_PREFIX_OPCODE:
1211 case DS_PREFIX_OPCODE:
1212 case ES_PREFIX_OPCODE:
1213 case FS_PREFIX_OPCODE:
1214 case GS_PREFIX_OPCODE:
1215 case SS_PREFIX_OPCODE:
1216 case LOCK_PREFIX_OPCODE:
1217 case REPE_PREFIX_OPCODE:
1218 case REPNE_PREFIX_OPCODE:
1219 ++insn;
1220 continue;
1221 default:
1222 break;
1223 }
1224 break;
1225 }
1226
1227 return insn;
1228}
1229
35669430
DE		 1230/* Return an integer register (other than RSP) that is unused as an input
1231 operand in INSN.
1232 In order to not require adding a rex prefix if the insn doesn't already
1233 have one, the result is restricted to RAX ... RDI, sans RSP.
1234 The register numbering of the result follows architecture ordering,
1235 e.g. RDI = 7. */
1236
1237static int
1238amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1239{
1240 /* 1 bit for each reg */
1241 int used_regs_mask = 0;
1242
1243 /* There can be at most 3 int regs used as inputs in an insn, and we have
1244 7 to choose from (RAX ... RDI, sans RSP).
1245 This allows us to take a conservative approach and keep things simple.
1246 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1247 that implicitly specify RAX. */
1248
1249 /* Avoid RAX. */
1250 used_regs_mask |= 1 << EAX_REG_NUM;
1251 /* Similarily avoid RDX, implicit operand in divides. */
1252 used_regs_mask |= 1 << EDX_REG_NUM;
1253 /* Avoid RSP. */
1254 used_regs_mask |= 1 << ESP_REG_NUM;
1255
1256 /* If the opcode is one byte long and there's no ModRM byte,
1257 assume the opcode specifies a register. */
1258 if (details->opcode_len == 1 && details->modrm_offset == -1)
1259 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1260
1261 /* Mark used regs in the modrm/sib bytes. */
1262 if (details->modrm_offset != -1)
1263 {
1264 int modrm = details->raw_insn[details->modrm_offset];
1265 int mod = MODRM_MOD_FIELD (modrm);
1266 int reg = MODRM_REG_FIELD (modrm);
1267 int rm = MODRM_RM_FIELD (modrm);
1268 int have_sib = mod != 3 && rm == 4;
1269
1270 /* Assume the reg field of the modrm byte specifies a register. */
1271 used_regs_mask |= 1 << reg;
1272
1273 if (have_sib)
1274 {
1275 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1276 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1277 used_regs_mask |= 1 << base;
d48ebb5b 1278 used_regs_mask |= 1 << idx;
35669430
DE		 1279 }
1280 else
1281 {
1282 used_regs_mask |= 1 << rm;
1283 }
1284 }
1285
1286 gdb_assert (used_regs_mask < 256);
1287 gdb_assert (used_regs_mask != 255);
1288
1289 /* Finally, find a free reg. */
1290 {
1291 int i;
1292
1293 for (i = 0; i < 8; ++i)
1294 {
1295 if (! (used_regs_mask & (1 << i)))
1296 return i;
1297 }
1298
1299 /* We shouldn't get here. */
1300 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1301 }
1302}
1303
1304/* Extract the details of INSN that we need. */
1305
1306static void
1307amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1308{
1309 gdb_byte *start = insn;
1310 int need_modrm;
1311
1312 details->raw_insn = insn;
1313
1314 details->opcode_len = -1;
50a1fdd5 1315 details->enc_prefix_offset = -1;
35669430
DE		 1316 details->opcode_offset = -1;
1317 details->modrm_offset = -1;
1318
1319 /* Skip legacy instruction prefixes. */
1903f0e6 1320 insn = amd64_skip_prefixes (insn);
35669430 1321
50a1fdd5 1322 /* Skip REX/VEX instruction encoding prefixes. */
35669430
DE		 1323 if (rex_prefix_p (*insn))
1324 {
50a1fdd5 1325 details->enc_prefix_offset = insn - start;
35669430
DE		 1326 ++insn;
1327 }
50a1fdd5
PA		 1328 else if (vex2_prefix_p (*insn))
1329 {
1330 /* Don't record the offset in this case because this prefix has
1331 no REX.B equivalent. */
1332 insn += 2;
1333 }
1334 else if (vex3_prefix_p (*insn))
1335 {
1336 details->enc_prefix_offset = insn - start;
1337 insn += 3;
1338 }
35669430
DE		 1339
1340 details->opcode_offset = insn - start;
1341
1342 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1343 {
1344 /* Two or three-byte opcode. */
1345 ++insn;
1346 need_modrm = twobyte_has_modrm[*insn];
1347
1348 /* Check for three-byte opcode. */
1903f0e6 1349 switch (*insn)
35669430 1350 {
1903f0e6
DE		 1351 case 0x24:
1352 case 0x25:
1353 case 0x38:
1354 case 0x3a:
1355 case 0x7a:
1356 case 0x7b:
35669430
DE		 1357 ++insn;
1358 details->opcode_len = 3;
1903f0e6
DE		 1359 break;
1360 default:
1361 details->opcode_len = 2;
1362 break;
35669430 1363 }
35669430
DE		 1364 }
1365 else
1366 {
1367 /* One-byte opcode. */
1368 need_modrm = onebyte_has_modrm[*insn];
1369 details->opcode_len = 1;
1370 }
1371
1372 if (need_modrm)
1373 {
1374 ++insn;
1375 details->modrm_offset = insn - start;
1376 }
1377}
1378
1379/* Update %rip-relative addressing in INSN.
1380
1381 %rip-relative addressing only uses a 32-bit displacement.
1382 32 bits is not enough to be guaranteed to cover the distance between where
1383 the real instruction is and where its copy is.
1384 Convert the insn to use base+disp addressing.
1385 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1386
35669430 1387static void
cfba9872 1388fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
35669430
DE		 1389 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1390{
1391 const struct amd64_insn *insn_details = &dsc->insn_details;
1392 int modrm_offset = insn_details->modrm_offset;
1393 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1394 CORE_ADDR rip_base;
35669430
DE		 1395 int insn_length;
1396 int arch_tmp_regno, tmp_regno;
1397 ULONGEST orig_value;
1398
1399 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1400 ++insn;
1401
1402 /* Compute the rip-relative address. */
cfba9872
SM		 1403 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1404 dsc->insn_buf.size (), from);
35669430
DE		 1405 rip_base = from + insn_length;
1406
1407 /* We need a register to hold the address.
1408 Pick one not used in the insn.
1409 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1410 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1411 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1412
50a1fdd5
PA		 1413 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1414 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1415
1416 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1417 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1418 is not r8-r15. */
1419 if (insn_details->enc_prefix_offset != -1)
1420 {
1421 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1422 if (rex_prefix_p (pfx[0]))
1423 pfx[0] &= ~REX_B;
1424 else if (vex3_prefix_p (pfx[0]))
1425 pfx[1] |= VEX3_NOT_B;
1426 else
1427 gdb_assert_not_reached ("unhandled prefix");
1428 }
35669430
DE		 1429
1430 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1431 dsc->tmp_regno = tmp_regno;
1432 dsc->tmp_save = orig_value;
1433 dsc->tmp_used = 1;
1434
1435 /* Convert the ModRM field to be base+disp. */
1436 dsc->insn_buf[modrm_offset] &= ~0xc7;
1437 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1438
1439 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1440
1441 if (debug_displaced)
1442 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1443 "displaced: using temp reg %d, old value %s, new value %s\n",
1444 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1445 paddress (gdbarch, rip_base));
35669430
DE		 1446}
1447
1448static void
1449fixup_displaced_copy (struct gdbarch *gdbarch,
cfba9872 1450 amd64_displaced_step_closure *dsc,
35669430
DE		 1451 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1452{
1453 const struct amd64_insn *details = &dsc->insn_details;
1454
1455 if (details->modrm_offset != -1)
1456 {
1457 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1458
1459 if ((modrm & 0xc7) == 0x05)
1460 {
1461 /* The insn uses rip-relative addressing.
1462 Deal with it. */
1463 fixup_riprel (gdbarch, dsc, from, to, regs);
1464 }
1465 }
1466}
1467
1468struct displaced_step_closure *
1469amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1470 CORE_ADDR from, CORE_ADDR to,
1471 struct regcache *regs)
1472{
1473 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1474 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1475 continually watch for running off the end of the buffer. */
1476 int fixup_sentinel_space = len;
cfba9872
SM		 1477 amd64_displaced_step_closure *dsc
1478 = new amd64_displaced_step_closure (len + fixup_sentinel_space);
35669430
DE		 1479 gdb_byte *buf = &dsc->insn_buf[0];
1480 struct amd64_insn *details = &dsc->insn_details;
1481
35669430
DE		 1482 read_memory (from, buf, len);
1483
1484 /* Set up the sentinel space so we don't have to worry about running
1485 off the end of the buffer. An excessive number of leading prefixes
1486 could otherwise cause this. */
1487 memset (buf + len, 0, fixup_sentinel_space);
1488
1489 amd64_get_insn_details (buf, details);
1490
1491 /* GDB may get control back after the insn after the syscall.
1492 Presumably this is a kernel bug.
1493 If this is a syscall, make sure there's a nop afterwards. */
1494 {
1495 int syscall_length;
1496
1497 if (amd64_syscall_p (details, &syscall_length))
1498 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1499 }
1500
1501 /* Modify the insn to cope with the address where it will be executed from.
1502 In particular, handle any rip-relative addressing. */
1503 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1504
1505 write_memory (to, buf, len);
1506
1507 if (debug_displaced)
1508 {
5af949e3
UW		 1509 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1510 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1511 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1512 }
1513
1514 return dsc;
1515}
1516
1517static int
1518amd64_absolute_jmp_p (const struct amd64_insn *details)
1519{
1520 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1521
1522 if (insn[0] == 0xff)
1523 {
1524 /* jump near, absolute indirect (/4) */
1525 if ((insn[1] & 0x38) == 0x20)
1526 return 1;
1527
1528 /* jump far, absolute indirect (/5) */
1529 if ((insn[1] & 0x38) == 0x28)
1530 return 1;
1531 }
1532
1533 return 0;
1534}
1535
c2170eef
MM		 1536/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1537
1538static int
1539amd64_jmp_p (const struct amd64_insn *details)
1540{
1541 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1542
1543 /* jump short, relative. */
1544 if (insn[0] == 0xeb)
1545 return 1;
1546
1547 /* jump near, relative. */
1548 if (insn[0] == 0xe9)
1549 return 1;
1550
1551 return amd64_absolute_jmp_p (details);
1552}
1553
35669430
DE		 1554static int
1555amd64_absolute_call_p (const struct amd64_insn *details)
1556{
1557 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1558
1559 if (insn[0] == 0xff)
1560 {
1561 /* Call near, absolute indirect (/2) */
1562 if ((insn[1] & 0x38) == 0x10)
1563 return 1;
1564
1565 /* Call far, absolute indirect (/3) */
1566 if ((insn[1] & 0x38) == 0x18)
1567 return 1;
1568 }
1569
1570 return 0;
1571}
1572
1573static int
1574amd64_ret_p (const struct amd64_insn *details)
1575{
1576 /* NOTE: gcc can emit "repz ; ret". */
1577 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1578
1579 switch (insn[0])
1580 {
1581 case 0xc2: /* ret near, pop N bytes */
1582 case 0xc3: /* ret near */
1583 case 0xca: /* ret far, pop N bytes */
1584 case 0xcb: /* ret far */
1585 case 0xcf: /* iret */
1586 return 1;
1587
1588 default:
1589 return 0;
1590 }
1591}
1592
1593static int
1594amd64_call_p (const struct amd64_insn *details)
1595{
1596 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1597
1598 if (amd64_absolute_call_p (details))
1599 return 1;
1600
1601 /* call near, relative */
1602 if (insn[0] == 0xe8)
1603 return 1;
1604
1605 return 0;
1606}
1607
35669430
DE		 1608/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1609 length in bytes. Otherwise, return zero. */
1610
1611static int
1612amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1613{
1614 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1615
1616 if (insn[0] == 0x0f && insn[1] == 0x05)
1617 {
1618 *lengthp = 2;
1619 return 1;
1620 }
1621
1622 return 0;
1623}
1624
c2170eef
MM		 1625/* Classify the instruction at ADDR using PRED.
1626 Throw an error if the memory can't be read. */
1627
1628static int
1629amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1630 int (*pred) (const struct amd64_insn *))
1631{
1632 struct amd64_insn details;
1633 gdb_byte *buf;
1634 int len, classification;
1635
1636 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1637 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1638
1639 read_code (addr, buf, len);
1640 amd64_get_insn_details (buf, &details);
1641
1642 classification = pred (&details);
1643
1644 return classification;
1645}
1646
1647/* The gdbarch insn_is_call method. */
1648
1649static int
1650amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1651{
1652 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1653}
1654
1655/* The gdbarch insn_is_ret method. */
1656
1657static int
1658amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1659{
1660 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1661}
1662
1663/* The gdbarch insn_is_jump method. */
1664
1665static int
1666amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1667{
1668 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1669}
1670
35669430
DE		 1671/* Fix up the state of registers and memory after having single-stepped
1672 a displaced instruction. */
1673
1674void
1675amd64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 1676 struct displaced_step_closure *dsc_,
35669430
DE		 1677 CORE_ADDR from, CORE_ADDR to,
1678 struct regcache *regs)
1679{
cfba9872 1680 amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
e17a4113 1681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1682 /* The offset we applied to the instruction's address. */
1683 ULONGEST insn_offset = to - from;
cfba9872 1684 gdb_byte *insn = dsc->insn_buf.data ();
35669430
DE		 1685 const struct amd64_insn *insn_details = &dsc->insn_details;
1686
1687 if (debug_displaced)
1688 fprintf_unfiltered (gdb_stdlog,
5af949e3 1689 "displaced: fixup (%s, %s), "
35669430 1690 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1691 paddress (gdbarch, from), paddress (gdbarch, to),
1692 insn[0], insn[1]);
35669430
DE		 1693
1694 /* If we used a tmp reg, restore it. */
1695
1696 if (dsc->tmp_used)
1697 {
1698 if (debug_displaced)
5af949e3
UW		 1699 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1700 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1701 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1702 }
1703
1704 /* The list of issues to contend with here is taken from
1705 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1706 Yay for Free Software! */
1707
1708 /* Relocate the %rip back to the program's instruction stream,
1709 if necessary. */
1710
1711 /* Except in the case of absolute or indirect jump or call
1712 instructions, or a return instruction, the new rip is relative to
1713 the displaced instruction; make it relative to the original insn.
1714 Well, signal handler returns don't need relocation either, but we use the
1715 value of %rip to recognize those; see below. */
1716 if (! amd64_absolute_jmp_p (insn_details)
1717 && ! amd64_absolute_call_p (insn_details)
1718 && ! amd64_ret_p (insn_details))
1719 {
1720 ULONGEST orig_rip;
1721 int insn_len;
1722
1723 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1724
1725 /* A signal trampoline system call changes the %rip, resuming
1726 execution of the main program after the signal handler has
1727 returned. That makes them like 'return' instructions; we
1728 shouldn't relocate %rip.
1729
1730 But most system calls don't, and we do need to relocate %rip.
1731
1732 Our heuristic for distinguishing these cases: if stepping
1733 over the system call instruction left control directly after
1734 the instruction, the we relocate --- control almost certainly
1735 doesn't belong in the displaced copy. Otherwise, we assume
1736 the instruction has put control where it belongs, and leave
1737 it unrelocated. Goodness help us if there are PC-relative
1738 system calls. */
1739 if (amd64_syscall_p (insn_details, &insn_len)
1740 && orig_rip != to + insn_len
1741 /* GDB can get control back after the insn after the syscall.
1742 Presumably this is a kernel bug.
1743 Fixup ensures its a nop, we add one to the length for it. */
1744 && orig_rip != to + insn_len + 1)
1745 {
1746 if (debug_displaced)
1747 fprintf_unfiltered (gdb_stdlog,
1748 "displaced: syscall changed %%rip; "
1749 "not relocating\n");
1750 }
1751 else
1752 {
1753 ULONGEST rip = orig_rip - insn_offset;
1754
1903f0e6
DE		 1755 /* If we just stepped over a breakpoint insn, we don't backup
1756 the pc on purpose; this is to match behaviour without
1757 stepping. */
35669430
DE		 1758
1759 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1760
1761 if (debug_displaced)
1762 fprintf_unfiltered (gdb_stdlog,
1763 "displaced: "
5af949e3
UW		 1764 "relocated %%rip from %s to %s\n",
1765 paddress (gdbarch, orig_rip),
1766 paddress (gdbarch, rip));
35669430
DE		 1767 }
1768 }
1769
1770 /* If the instruction was PUSHFL, then the TF bit will be set in the
1771 pushed value, and should be cleared. We'll leave this for later,
1772 since GDB already messes up the TF flag when stepping over a
1773 pushfl. */
1774
1775 /* If the instruction was a call, the return address now atop the
1776 stack is the address following the copied instruction. We need
1777 to make it the address following the original instruction. */
1778 if (amd64_call_p (insn_details))
1779 {
1780 ULONGEST rsp;
1781 ULONGEST retaddr;
1782 const ULONGEST retaddr_len = 8;
1783
1784 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1785 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1786 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1787 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1788
1789 if (debug_displaced)
1790 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1791 "displaced: relocated return addr at %s "
1792 "to %s\n",
1793 paddress (gdbarch, rsp),
1794 paddress (gdbarch, retaddr));
35669430
DE		 1795 }
1796}
dde08ee1
PA		 1797
1798/* If the instruction INSN uses RIP-relative addressing, return the
1799 offset into the raw INSN where the displacement to be adjusted is
1800 found. Returns 0 if the instruction doesn't use RIP-relative
1801 addressing. */
1802
1803static int
1804rip_relative_offset (struct amd64_insn *insn)
1805{
1806 if (insn->modrm_offset != -1)
1807 {
1808 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1809
1810 if ((modrm & 0xc7) == 0x05)
1811 {
1812 /* The displacement is found right after the ModRM byte. */
1813 return insn->modrm_offset + 1;
1814 }
1815 }
1816
1817 return 0;
1818}
1819
1820static void
1821append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1822{
1823 target_write_memory (*to, buf, len);
1824 *to += len;
1825}
1826
60965737 1827static void
dde08ee1
PA		 1828amd64_relocate_instruction (struct gdbarch *gdbarch,
1829 CORE_ADDR *to, CORE_ADDR oldloc)
1830{
1831 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1832 int len = gdbarch_max_insn_length (gdbarch);
1833 /* Extra space for sentinels. */
1834 int fixup_sentinel_space = len;
224c3ddb 1835 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1836 struct amd64_insn insn_details;
1837 int offset = 0;
1838 LONGEST rel32, newrel;
1839 gdb_byte *insn;
1840 int insn_length;
1841
1842 read_memory (oldloc, buf, len);
1843
1844 /* Set up the sentinel space so we don't have to worry about running
1845 off the end of the buffer. An excessive number of leading prefixes
1846 could otherwise cause this. */
1847 memset (buf + len, 0, fixup_sentinel_space);
1848
1849 insn = buf;
1850 amd64_get_insn_details (insn, &insn_details);
1851
1852 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1853
1854 /* Skip legacy instruction prefixes. */
1855 insn = amd64_skip_prefixes (insn);
1856
1857 /* Adjust calls with 32-bit relative addresses as push/jump, with
1858 the address pushed being the location where the original call in
1859 the user program would return to. */
1860 if (insn[0] == 0xe8)
1861 {
f077e978
PA		 1862 gdb_byte push_buf[32];
1863 CORE_ADDR ret_addr;
1864 int i = 0;
dde08ee1
PA		 1865
1866 /* Where "ret" in the original code will return to. */
1867 ret_addr = oldloc + insn_length;
f077e978
PA		 1868
1869 /* If pushing an address higher than or equal to 0x80000000,
1870 avoid 'pushq', as that sign extends its 32-bit operand, which
1871 would be incorrect. */
1872 if (ret_addr <= 0x7fffffff)
1873 {
1874 push_buf[0] = 0x68; /* pushq $... */
1875 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1876 i = 5;
1877 }
1878 else
1879 {
1880 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1881 push_buf[i++] = 0x83;
1882 push_buf[i++] = 0xec;
1883 push_buf[i++] = 0x08;
1884
1885 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1886 push_buf[i++] = 0x04;
1887 push_buf[i++] = 0x24;
1888 store_unsigned_integer (&push_buf[i], 4, byte_order,
1889 ret_addr & 0xffffffff);
1890 i += 4;
1891
1892 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1893 push_buf[i++] = 0x44;
1894 push_buf[i++] = 0x24;
1895 push_buf[i++] = 0x04;
1896 store_unsigned_integer (&push_buf[i], 4, byte_order,
1897 ret_addr >> 32);
1898 i += 4;
1899 }
1900 gdb_assert (i <= sizeof (push_buf));
dde08ee1 1901 /* Push the push. */
f077e978 1902 append_insns (to, i, push_buf);
dde08ee1
PA		 1903
1904 /* Convert the relative call to a relative jump. */
1905 insn[0] = 0xe9;
1906
1907 /* Adjust the destination offset. */
1908 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1909 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1910 store_signed_integer (insn + 1, 4, byte_order, newrel);
1911
1912 if (debug_displaced)
1913 fprintf_unfiltered (gdb_stdlog,
1914 "Adjusted insn rel32=%s at %s to"
1915 " rel32=%s at %s\n",
1916 hex_string (rel32), paddress (gdbarch, oldloc),
1917 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1918
1919 /* Write the adjusted jump into its displaced location. */
1920 append_insns (to, 5, insn);
1921 return;
1922 }
1923
1924 offset = rip_relative_offset (&insn_details);
1925 if (!offset)
1926 {
1927 /* Adjust jumps with 32-bit relative addresses. Calls are
1928 already handled above. */
1929 if (insn[0] == 0xe9)
1930 offset = 1;
1931 /* Adjust conditional jumps. */
1932 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1933 offset = 2;
1934 }
1935
1936 if (offset)
1937 {
1938 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1939 newrel = (oldloc - *to) + rel32;
f4a1794a 1940 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1941 if (debug_displaced)
1942 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1943 "Adjusted insn rel32=%s at %s to"
1944 " rel32=%s at %s\n",
dde08ee1
PA		 1945 hex_string (rel32), paddress (gdbarch, oldloc),
1946 hex_string (newrel), paddress (gdbarch, *to));
1947 }
1948
1949 /* Write the adjusted instruction into its displaced location. */
1950 append_insns (to, insn_length, buf);
1951}
1952
35669430 1953\f
c4f35dd8 1954/* The maximum number of saved registers. This should include %rip. */
90f90721 1955#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1956
e53bef9f 1957struct amd64_frame_cache
c4f35dd8
MK		 1958{
1959 /* Base address. */
1960 CORE_ADDR base;
8fbca658 1961 int base_p;
c4f35dd8
MK		 1962 CORE_ADDR sp_offset;
1963 CORE_ADDR pc;
1964
1965 /* Saved registers. */
e53bef9f 1966 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1967 CORE_ADDR saved_sp;
e0c62198 1968 int saved_sp_reg;
c4f35dd8
MK		 1969
1970 /* Do we have a frame? */
1971 int frameless_p;
1972};
8dda9770 1973
d2449ee8 1974/* Initialize a frame cache. */
c4f35dd8 1975
d2449ee8
DJ		 1976static void
1977amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1978{
c4f35dd8
MK		 1979 int i;
1980
c4f35dd8
MK		 1981 /* Base address. */
1982 cache->base = 0;
8fbca658 1983 cache->base_p = 0;
c4f35dd8
MK		 1984 cache->sp_offset = -8;
1985 cache->pc = 0;
1986
1987 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1988 offset (that's where %rbp is supposed to be stored).
1989 The values start out as being offsets, and are later converted to
1990 addresses (at which point -1 is interpreted as an address, still meaning
1991 "invalid"). */
e53bef9f 1992 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1993 cache->saved_regs[i] = -1;
1994 cache->saved_sp = 0;
e0c62198 1995 cache->saved_sp_reg = -1;
c4f35dd8
MK		 1996
1997 /* Frameless until proven otherwise. */
1998 cache->frameless_p = 1;
d2449ee8 1999}
c4f35dd8 2000
d2449ee8
DJ		 2001/* Allocate and initialize a frame cache. */
2002
2003static struct amd64_frame_cache *
2004amd64_alloc_frame_cache (void)
2005{
2006 struct amd64_frame_cache *cache;
2007
2008 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
2009 amd64_init_frame_cache (cache);
c4f35dd8 2010 return cache;
8dda9770 2011}
53e95fcf 2012
e0c62198
L		 2013/* GCC 4.4 and later, can put code in the prologue to realign the
2014 stack pointer. Check whether PC points to such code, and update
2015 CACHE accordingly. Return the first instruction after the code
2016 sequence or CURRENT_PC, whichever is smaller. If we don't
2017 recognize the code, return PC. */
2018
2019static CORE_ADDR
2020amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2021 struct amd64_frame_cache *cache)
2022{
2023 /* There are 2 code sequences to re-align stack before the frame
2024 gets set up:
2025
2026 1. Use a caller-saved saved register:
2027
2028 leaq 8(%rsp), %reg
2029 andq $-XXX, %rsp
2030 pushq -8(%reg)
2031
2032 2. Use a callee-saved saved register:
2033
2034 pushq %reg
2035 leaq 16(%rsp), %reg
2036 andq $-XXX, %rsp
2037 pushq -8(%reg)
2038
2039 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2040
2041 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2042 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2043 */
2044
2045 gdb_byte buf[18];
2046 int reg, r;
2047 int offset, offset_and;
e0c62198 2048
bae8a07a 2049 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 2050 return pc;
2051
2052 /* Check caller-saved saved register. The first instruction has
2053 to be "leaq 8(%rsp), %reg". */
2054 if ((buf[0] & 0xfb) == 0x48
2055 && buf[1] == 0x8d
2056 && buf[3] == 0x24
2057 && buf[4] == 0x8)
2058 {
2059 /* MOD must be binary 10 and R/M must be binary 100. */
2060 if ((buf[2] & 0xc7) != 0x44)
2061 return pc;
2062
2063 /* REG has register number. */
2064 reg = (buf[2] >> 3) & 7;
2065
2066 /* Check the REX.R bit. */
2067 if (buf[0] == 0x4c)
2068 reg += 8;
2069
2070 offset = 5;
2071 }
2072 else
2073 {
2074 /* Check callee-saved saved register. The first instruction
2075 has to be "pushq %reg". */
2076 reg = 0;
2077 if ((buf[0] & 0xf8) == 0x50)
2078 offset = 0;
2079 else if ((buf[0] & 0xf6) == 0x40
2080 && (buf[1] & 0xf8) == 0x50)
2081 {
2082 /* Check the REX.B bit. */
2083 if ((buf[0] & 1) != 0)
2084 reg = 8;
2085
2086 offset = 1;
2087 }
2088 else
2089 return pc;
2090
2091 /* Get register. */
2092 reg += buf[offset] & 0x7;
2093
2094 offset++;
2095
2096 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2097 if ((buf[offset] & 0xfb) != 0x48
2098 || buf[offset + 1] != 0x8d
2099 || buf[offset + 3] != 0x24
2100 || buf[offset + 4] != 0x10)
2101 return pc;
2102
2103 /* MOD must be binary 10 and R/M must be binary 100. */
2104 if ((buf[offset + 2] & 0xc7) != 0x44)
2105 return pc;
2106
2107 /* REG has register number. */
2108 r = (buf[offset + 2] >> 3) & 7;
2109
2110 /* Check the REX.R bit. */
2111 if (buf[offset] == 0x4c)
2112 r += 8;
2113
2114 /* Registers in pushq and leaq have to be the same. */
2115 if (reg != r)
2116 return pc;
2117
2118 offset += 5;
2119 }
2120
2121 /* Rigister can't be %rsp nor %rbp. */
2122 if (reg == 4 || reg == 5)
2123 return pc;
2124
2125 /* The next instruction has to be "andq $-XXX, %rsp". */
2126 if (buf[offset] != 0x48
2127 || buf[offset + 2] != 0xe4
2128 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2129 return pc;
2130
2131 offset_and = offset;
2132 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2133
2134 /* The next instruction has to be "pushq -8(%reg)". */
2135 r = 0;
2136 if (buf[offset] == 0xff)
2137 offset++;
2138 else if ((buf[offset] & 0xf6) == 0x40
2139 && buf[offset + 1] == 0xff)
2140 {
2141 /* Check the REX.B bit. */
2142 if ((buf[offset] & 0x1) != 0)
2143 r = 8;
2144 offset += 2;
2145 }
2146 else
2147 return pc;
2148
2149 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2150 01. */
2151 if (buf[offset + 1] != 0xf8
2152 || (buf[offset] & 0xf8) != 0x70)
2153 return pc;
2154
2155 /* R/M has register. */
2156 r += buf[offset] & 7;
2157
2158 /* Registers in leaq and pushq have to be the same. */
2159 if (reg != r)
2160 return pc;
2161
2162 if (current_pc > pc + offset_and)
35669430 2163 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198 2164
325fac50 2165 return std::min (pc + offset + 2, current_pc);
e0c62198
L		 2166}
2167
ac142d96
L		 2168/* Similar to amd64_analyze_stack_align for x32. */
2169
2170static CORE_ADDR
2171amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2172 struct amd64_frame_cache *cache)
2173{
2174 /* There are 2 code sequences to re-align stack before the frame
2175 gets set up:
2176
2177 1. Use a caller-saved saved register:
2178
2179 leaq 8(%rsp), %reg
2180 andq $-XXX, %rsp
2181 pushq -8(%reg)
2182
2183 or
2184
2185 [addr32] leal 8(%rsp), %reg
2186 andl $-XXX, %esp
2187 [addr32] pushq -8(%reg)
2188
2189 2. Use a callee-saved saved register:
2190
2191 pushq %reg
2192 leaq 16(%rsp), %reg
2193 andq $-XXX, %rsp
2194 pushq -8(%reg)
2195
2196 or
2197
2198 pushq %reg
2199 [addr32] leal 16(%rsp), %reg
2200 andl $-XXX, %esp
2201 [addr32] pushq -8(%reg)
2202
2203 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2204
2205 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2206 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2207
2208 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2209
2210 0x83 0xe4 0xf0 andl $-16, %esp
2211 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2212 */
2213
2214 gdb_byte buf[19];
2215 int reg, r;
2216 int offset, offset_and;
2217
2218 if (target_read_memory (pc, buf, sizeof buf))
2219 return pc;
2220
2221 /* Skip optional addr32 prefix. */
2222 offset = buf[0] == 0x67 ? 1 : 0;
2223
2224 /* Check caller-saved saved register. The first instruction has
2225 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2226 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2227 && buf[offset + 1] == 0x8d
2228 && buf[offset + 3] == 0x24
2229 && buf[offset + 4] == 0x8)
2230 {
2231 /* MOD must be binary 10 and R/M must be binary 100. */
2232 if ((buf[offset + 2] & 0xc7) != 0x44)
2233 return pc;
2234
2235 /* REG has register number. */
2236 reg = (buf[offset + 2] >> 3) & 7;
2237
2238 /* Check the REX.R bit. */
2239 if ((buf[offset] & 0x4) != 0)
2240 reg += 8;
2241
2242 offset += 5;
2243 }
2244 else
2245 {
2246 /* Check callee-saved saved register. The first instruction
2247 has to be "pushq %reg". */
2248 reg = 0;
2249 if ((buf[offset] & 0xf6) == 0x40
2250 && (buf[offset + 1] & 0xf8) == 0x50)
2251 {
2252 /* Check the REX.B bit. */
2253 if ((buf[offset] & 1) != 0)
2254 reg = 8;
2255
2256 offset += 1;
2257 }
2258 else if ((buf[offset] & 0xf8) != 0x50)
2259 return pc;
2260
2261 /* Get register. */
2262 reg += buf[offset] & 0x7;
2263
2264 offset++;
2265
2266 /* Skip optional addr32 prefix. */
2267 if (buf[offset] == 0x67)
2268 offset++;
2269
2270 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2271 "leal 16(%rsp), %reg". */
2272 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2273 || buf[offset + 1] != 0x8d
2274 || buf[offset + 3] != 0x24
2275 || buf[offset + 4] != 0x10)
2276 return pc;
2277
2278 /* MOD must be binary 10 and R/M must be binary 100. */
2279 if ((buf[offset + 2] & 0xc7) != 0x44)
2280 return pc;
2281
2282 /* REG has register number. */
2283 r = (buf[offset + 2] >> 3) & 7;
2284
2285 /* Check the REX.R bit. */
2286 if ((buf[offset] & 0x4) != 0)
2287 r += 8;
2288
2289 /* Registers in pushq and leaq have to be the same. */
2290 if (reg != r)
2291 return pc;
2292
2293 offset += 5;
2294 }
2295
2296 /* Rigister can't be %rsp nor %rbp. */
2297 if (reg == 4 || reg == 5)
2298 return pc;
2299
2300 /* The next instruction may be "andq $-XXX, %rsp" or
2301 "andl $-XXX, %esp". */
2302 if (buf[offset] != 0x48)
2303 offset--;
2304
2305 if (buf[offset + 2] != 0xe4
2306 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2307 return pc;
2308
2309 offset_and = offset;
2310 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2311
2312 /* Skip optional addr32 prefix. */
2313 if (buf[offset] == 0x67)
2314 offset++;
2315
2316 /* The next instruction has to be "pushq -8(%reg)". */
2317 r = 0;
2318 if (buf[offset] == 0xff)
2319 offset++;
2320 else if ((buf[offset] & 0xf6) == 0x40
2321 && buf[offset + 1] == 0xff)
2322 {
2323 /* Check the REX.B bit. */
2324 if ((buf[offset] & 0x1) != 0)
2325 r = 8;
2326 offset += 2;
2327 }
2328 else
2329 return pc;
2330
2331 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2332 01. */
2333 if (buf[offset + 1] != 0xf8
2334 || (buf[offset] & 0xf8) != 0x70)
2335 return pc;
2336
2337 /* R/M has register. */
2338 r += buf[offset] & 7;
2339
2340 /* Registers in leaq and pushq have to be the same. */
2341 if (reg != r)
2342 return pc;
2343
2344 if (current_pc > pc + offset_and)
2345 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2346
325fac50 2347 return std::min (pc + offset + 2, current_pc);
ac142d96
L		 2348}
2349
c4f35dd8
MK		 2350/* Do a limited analysis of the prologue at PC and update CACHE
2351 accordingly. Bail out early if CURRENT_PC is reached. Return the
2352 address where the analysis stopped.
2353
2354 We will handle only functions beginning with:
2355
2356 pushq %rbp 0x55
50f1ae7b 2357 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2358
649e6d92
MK		 2359 or (for the X32 ABI):
2360
2361 pushq %rbp 0x55
2362 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2363
2364 Any function that doesn't start with one of these sequences will be
2365 assumed to have no prologue and thus no valid frame pointer in
2366 %rbp. */
c4f35dd8
MK		 2367
2368static CORE_ADDR
e17a4113
UW		 2369amd64_analyze_prologue (struct gdbarch *gdbarch,
2370 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2371 struct amd64_frame_cache *cache)
53e95fcf 2372{
e17a4113 2373 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2374 /* There are two variations of movq %rsp, %rbp. */
2375 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2376 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2377 /* Ditto for movl %esp, %ebp. */
2378 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2379 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2380
d8de1ef7
MK		 2381 gdb_byte buf[3];
2382 gdb_byte op;
c4f35dd8
MK		 2383
2384 if (current_pc <= pc)
2385 return current_pc;
2386
ac142d96
L		 2387 if (gdbarch_ptr_bit (gdbarch) == 32)
2388 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2389 else
2390 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2391
bae8a07a 2392 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2393
2394 if (op == 0x55) /* pushq %rbp */
2395 {
2396 /* Take into account that we've executed the `pushq %rbp' that
2397 starts this instruction sequence. */
90f90721 2398 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2399 cache->sp_offset += 8;
2400
2401 /* If that's all, return now. */
2402 if (current_pc <= pc + 1)
2403 return current_pc;
2404
bae8a07a 2405 read_code (pc + 1, buf, 3);
c4f35dd8 2406
649e6d92
MK		 2407 /* Check for `movq %rsp, %rbp'. */
2408 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2409 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2410 {
2411 /* OK, we actually have a frame. */
2412 cache->frameless_p = 0;
2413 return pc + 4;
2414 }
2415
2416 /* For X32, also check for `movq %esp, %ebp'. */
2417 if (gdbarch_ptr_bit (gdbarch) == 32)
2418 {
2419 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2420 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2421 {
2422 /* OK, we actually have a frame. */
2423 cache->frameless_p = 0;
2424 return pc + 3;
2425 }
2426 }
2427
2428 return pc + 1;
c4f35dd8
MK		 2429 }
2430
2431 return pc;
53e95fcf
JS		 2432}
2433
df15bd07
JK		 2434/* Work around false termination of prologue - GCC PR debug/48827.
2435
2436 START_PC is the first instruction of a function, PC is its minimal already
2437 determined advanced address. Function returns PC if it has nothing to do.
2438
2439 84 c0 test %al,%al
2440 74 23 je after
2441 <-- here is 0 lines advance - the false prologue end marker.
2442 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2443 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2444 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2445 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2446 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2447 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2448 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2449 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2450 after: */
c4f35dd8
MK		 2451
2452static CORE_ADDR
df15bd07 2453amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2454{
08711b9a
JK		 2455 struct symtab_and_line start_pc_sal, next_sal;
2456 gdb_byte buf[4 + 8 * 7];
2457 int offset, xmmreg;
c4f35dd8 2458
08711b9a
JK		 2459 if (pc == start_pc)
2460 return pc;
2461
2462 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2463 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2464 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2465 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2466 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2467 return pc;
2468
2469 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2470 if (next_sal.line != start_pc_sal.line)
2471 return pc;
2472
2473 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2474 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2475 return pc;
2476
2477 /* test %al,%al */
2478 if (buf[0] != 0x84 || buf[1] != 0xc0)
2479 return pc;
2480 /* je AFTER */
2481 if (buf[2] != 0x74)
2482 return pc;
2483
2484 offset = 4;
2485 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2486 {
bede5f5f 2487 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2488 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2489 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2490 return pc;
2491
bede5f5f
JK		 2492 /* 0b01?????? */
2493 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2494 {
2495 /* 8-bit displacement. */
2496 offset += 4;
2497 }
bede5f5f
JK		 2498 /* 0b10?????? */
2499 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2500 {
2501 /* 32-bit displacement. */
2502 offset += 7;
2503 }
2504 else
2505 return pc;
2506 }
2507
2508 /* je AFTER */
2509 if (offset - 4 != buf[3])
2510 return pc;
2511
2512 return next_sal.end;
53e95fcf 2513}
df15bd07
JK		 2514
2515/* Return PC of first real instruction. */
2516
2517static CORE_ADDR
2518amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2519{
2520 struct amd64_frame_cache cache;
2521 CORE_ADDR pc;
56bf0743
KB		 2522 CORE_ADDR func_addr;
2523
2524 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2525 {
2526 CORE_ADDR post_prologue_pc
2527 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2528 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2529
2530 /* Clang always emits a line note before the prologue and another
2531 one after. We trust clang to emit usable line notes. */
2532 if (post_prologue_pc
43f3e411
DE		 2533 && (cust != NULL
2534 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2535 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
325fac50 2536 return std::max (start_pc, post_prologue_pc);
56bf0743 2537 }
df15bd07
JK		 2538
2539 amd64_init_frame_cache (&cache);
2540 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2541 &cache);
2542 if (cache.frameless_p)
2543 return start_pc;
2544
2545 return amd64_skip_xmm_prologue (pc, start_pc);
2546}
c4f35dd8 2547\f
53e95fcf 2548
c4f35dd8
MK		 2549/* Normal frames. */
2550
8fbca658
PA		 2551static void
2552amd64_frame_cache_1 (struct frame_info *this_frame,
2553 struct amd64_frame_cache *cache)
6d686a84 2554{
e17a4113
UW		 2555 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2556 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2557 gdb_byte buf[8];
6d686a84 2558 int i;
6d686a84 2559
10458914 2560 cache->pc = get_frame_func (this_frame);
c4f35dd8 2561 if (cache->pc != 0)
e17a4113
UW		 2562 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2563 cache);
c4f35dd8
MK		 2564
2565 if (cache->frameless_p)
2566 {
4a28816e
MK		 2567 /* We didn't find a valid frame. If we're at the start of a
2568 function, or somewhere half-way its prologue, the function's
2569 frame probably hasn't been fully setup yet. Try to
2570 reconstruct the base address for the stack frame by looking
2571 at the stack pointer. For truly "frameless" functions this
2572 might work too. */
c4f35dd8 2573
e0c62198
L		 2574 if (cache->saved_sp_reg != -1)
2575 {
8fbca658
PA		 2576 /* Stack pointer has been saved. */
2577 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2578 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2579
e0c62198
L		 2580 /* We're halfway aligning the stack. */
2581 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2582 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2583
2584 /* This will be added back below. */
2585 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2586 }
2587 else
2588 {
2589 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2590 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2591 + cache->sp_offset;
e0c62198 2592 }
c4f35dd8 2593 }
35883a3f
MK		 2594 else
2595 {
10458914 2596 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2597 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2598 }
c4f35dd8
MK		 2599
2600 /* Now that we have the base address for the stack frame we can
2601 calculate the value of %rsp in the calling frame. */
2602 cache->saved_sp = cache->base + 16;
2603
35883a3f
MK		 2604 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2605 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2606 address. If we're halfway aligning the stack, %rip is handled
2607 differently (see above). */
2608 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2609 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2610
c4f35dd8
MK		 2611 /* Adjust all the saved registers such that they contain addresses
2612 instead of offsets. */
e53bef9f 2613 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2614 if (cache->saved_regs[i] != -1)
2615 cache->saved_regs[i] += cache->base;
2616
8fbca658
PA		 2617 cache->base_p = 1;
2618}
2619
2620static struct amd64_frame_cache *
2621amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2622{
8fbca658
PA		 2623 struct amd64_frame_cache *cache;
2624
2625 if (*this_cache)
9a3c8263 2626 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2627
2628 cache = amd64_alloc_frame_cache ();
2629 *this_cache = cache;
2630
a70b8144 2631 try
8fbca658
PA		 2632 {
2633 amd64_frame_cache_1 (this_frame, cache);
2634 }
230d2906 2635 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2636 {
2637 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2638 throw;
7556d4a4 2639 }
8fbca658 2640
c4f35dd8 2641 return cache;
6d686a84
ML		 2642}
2643
8fbca658
PA		 2644static enum unwind_stop_reason
2645amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2646 void **this_cache)
2647{
2648 struct amd64_frame_cache *cache =
2649 amd64_frame_cache (this_frame, this_cache);
2650
2651 if (!cache->base_p)
2652 return UNWIND_UNAVAILABLE;
2653
2654 /* This marks the outermost frame. */
2655 if (cache->base == 0)
2656 return UNWIND_OUTERMOST;
2657
2658 return UNWIND_NO_REASON;
2659}
2660
c4f35dd8 2661static void
10458914 2662amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2663 struct frame_id *this_id)
c4f35dd8 2664{
e53bef9f 2665 struct amd64_frame_cache *cache =
10458914 2666 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2667
8fbca658 2668 if (!cache->base_p)
5ce0145d
PA		 2669 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2670 else if (cache->base == 0)
2671 {
2672 /* This marks the outermost frame. */
2673 return;
2674 }
2675 else
2676 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2677}
e76e1718 2678
10458914
DJ		 2679static struct value *
2680amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2681 int regnum)
53e95fcf 2682{
10458914 2683 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2684 struct amd64_frame_cache *cache =
10458914 2685 amd64_frame_cache (this_frame, this_cache);
e76e1718 2686
c4f35dd8 2687 gdb_assert (regnum >= 0);
b1ab997b 2688
2ae02b47 2689 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2690 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2691
e53bef9f 2692 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2693 return frame_unwind_got_memory (this_frame, regnum,
2694 cache->saved_regs[regnum]);
e76e1718 2695
10458914 2696 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2697}
e76e1718 2698
e53bef9f 2699static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2700{
2701 NORMAL_FRAME,
8fbca658 2702 amd64_frame_unwind_stop_reason,
e53bef9f 2703 amd64_frame_this_id,
10458914
DJ		 2704 amd64_frame_prev_register,
2705 NULL,
2706 default_frame_sniffer
c4f35dd8 2707};
c4f35dd8 2708\f
6710bf39
SS		 2709/* Generate a bytecode expression to get the value of the saved PC. */
2710
2711static void
2712amd64_gen_return_address (struct gdbarch *gdbarch,
2713 struct agent_expr *ax, struct axs_value *value,
2714 CORE_ADDR scope)
2715{
2716 /* The following sequence assumes the traditional use of the base
2717 register. */
2718 ax_reg (ax, AMD64_RBP_REGNUM);
2719 ax_const_l (ax, 8);
2720 ax_simple (ax, aop_add);
2721 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2722 value->kind = axs_lvalue_memory;
2723}
2724\f
e76e1718 2725
c4f35dd8
MK		 2726/* Signal trampolines. */
2727
2728/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2729 64-bit variants. This would require using identical frame caches
2730 on both platforms. */
2731
e53bef9f 2732static struct amd64_frame_cache *
10458914 2733amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2734{
e17a4113
UW		 2735 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2736 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2737 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2738 struct amd64_frame_cache *cache;
c4f35dd8 2739 CORE_ADDR addr;
d8de1ef7 2740 gdb_byte buf[8];
2b5e0749 2741 int i;
c4f35dd8
MK		 2742
2743 if (*this_cache)
9a3c8263 2744 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2745
e53bef9f 2746 cache = amd64_alloc_frame_cache ();
c4f35dd8 2747
a70b8144 2748 try
8fbca658
PA		 2749 {
2750 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2751 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2752
2753 addr = tdep->sigcontext_addr (this_frame);
2754 gdb_assert (tdep->sc_reg_offset);
2755 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2756 for (i = 0; i < tdep->sc_num_regs; i++)
2757 if (tdep->sc_reg_offset[i] != -1)
2758 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2759
8fbca658
PA		 2760 cache->base_p = 1;
2761 }
230d2906 2762 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2763 {
2764 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2765 throw;
7556d4a4 2766 }
c4f35dd8
MK		 2767
2768 *this_cache = cache;
2769 return cache;
53e95fcf
JS		 2770}
2771
8fbca658
PA		 2772static enum unwind_stop_reason
2773amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2774 void **this_cache)
2775{
2776 struct amd64_frame_cache *cache =
2777 amd64_sigtramp_frame_cache (this_frame, this_cache);
2778
2779 if (!cache->base_p)
2780 return UNWIND_UNAVAILABLE;
2781
2782 return UNWIND_NO_REASON;
2783}
2784
c4f35dd8 2785static void
10458914 2786amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2787 void **this_cache, struct frame_id *this_id)
c4f35dd8 2788{
e53bef9f 2789 struct amd64_frame_cache *cache =
10458914 2790 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2791
8fbca658 2792 if (!cache->base_p)
5ce0145d
PA		 2793 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2794 else if (cache->base == 0)
2795 {
2796 /* This marks the outermost frame. */
2797 return;
2798 }
2799 else
2800 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2801}
2802
10458914
DJ		 2803static struct value *
2804amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2805 void **this_cache, int regnum)
c4f35dd8
MK		 2806{
2807 /* Make sure we've initialized the cache. */
10458914 2808 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2809
10458914 2810 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2811}
2812
10458914
DJ		 2813static int
2814amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2815 struct frame_info *this_frame,
2816 void **this_cache)
c4f35dd8 2817{
10458914 2818 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2819
2820 /* We shouldn't even bother if we don't have a sigcontext_addr
2821 handler. */
2822 if (tdep->sigcontext_addr == NULL)
10458914 2823 return 0;
911bc6ee
MK		 2824
2825 if (tdep->sigtramp_p != NULL)
2826 {
10458914
DJ		 2827 if (tdep->sigtramp_p (this_frame))
2828 return 1;
911bc6ee 2829 }
c4f35dd8 2830
911bc6ee 2831 if (tdep->sigtramp_start != 0)
1c3545ae 2832 {
10458914 2833 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2834
911bc6ee
MK		 2835 gdb_assert (tdep->sigtramp_end != 0);
2836 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2837 return 1;
1c3545ae 2838 }
c4f35dd8 2839
10458914 2840 return 0;
c4f35dd8 2841}
10458914
DJ		 2842
2843static const struct frame_unwind amd64_sigtramp_frame_unwind =
2844{
2845 SIGTRAMP_FRAME,
8fbca658 2846 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2847 amd64_sigtramp_frame_this_id,
2848 amd64_sigtramp_frame_prev_register,
2849 NULL,
2850 amd64_sigtramp_frame_sniffer
2851};
c4f35dd8
MK		 2852\f
2853
2854static CORE_ADDR
10458914 2855amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2856{
e53bef9f 2857 struct amd64_frame_cache *cache =
10458914 2858 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2859
2860 return cache->base;
2861}
2862
e53bef9f 2863static const struct frame_base amd64_frame_base =
c4f35dd8 2864{
e53bef9f
MK		 2865 &amd64_frame_unwind,
2866 amd64_frame_base_address,
2867 amd64_frame_base_address,
2868 amd64_frame_base_address
c4f35dd8
MK		 2869};
2870
872761f4
MS		 2871/* Normal frames, but in a function epilogue. */
2872
c9cf6e20
MG		 2873/* Implement the stack_frame_destroyed_p gdbarch method.
2874
2875 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2876 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2877 the function's stack frame. */
2878
2879static int
c9cf6e20 2880amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2881{
2882 gdb_byte insn;
43f3e411 2883 struct compunit_symtab *cust;
e0d00bc7 2884
43f3e411
DE		 2885 cust = find_pc_compunit_symtab (pc);
2886 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2887 return 0;
872761f4
MS		 2888
2889 if (target_read_memory (pc, &insn, 1))
2890 return 0; /* Can't read memory at pc. */
2891
2892 if (insn != 0xc3) /* 'ret' instruction. */
2893 return 0;
2894
2895 return 1;
2896}
2897
2898static int
2899amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2900 struct frame_info *this_frame,
2901 void **this_prologue_cache)
2902{
2903 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2904 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2905 get_frame_pc (this_frame));
872761f4
MS		 2906 else
2907 return 0;
2908}
2909
2910static struct amd64_frame_cache *
2911amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2912{
2913 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2914 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2915 struct amd64_frame_cache *cache;
6c10c06b 2916 gdb_byte buf[8];
872761f4
MS		 2917
2918 if (*this_cache)
9a3c8263 2919 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2920
2921 cache = amd64_alloc_frame_cache ();
2922 *this_cache = cache;
2923
a70b8144 2924 try
8fbca658
PA		 2925 {
2926 /* Cache base will be %esp plus cache->sp_offset (-8). */
2927 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2928 cache->base = extract_unsigned_integer (buf, 8,
2929 byte_order) + cache->sp_offset;
2930
2931 /* Cache pc will be the frame func. */
2932 cache->pc = get_frame_pc (this_frame);
872761f4 2933
8fbca658
PA		 2934 /* The saved %esp will be at cache->base plus 16. */
2935 cache->saved_sp = cache->base + 16;
872761f4 2936
8fbca658
PA		 2937 /* The saved %eip will be at cache->base plus 8. */
2938 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2939
8fbca658
PA		 2940 cache->base_p = 1;
2941 }
230d2906 2942 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2943 {
2944 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2945 throw;
7556d4a4 2946 }
872761f4
MS		 2947
2948 return cache;
2949}
2950
8fbca658
PA		 2951static enum unwind_stop_reason
2952amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2953 void **this_cache)
2954{
2955 struct amd64_frame_cache *cache
2956 = amd64_epilogue_frame_cache (this_frame, this_cache);
2957
2958 if (!cache->base_p)
2959 return UNWIND_UNAVAILABLE;
2960
2961 return UNWIND_NO_REASON;
2962}
2963
872761f4
MS		 2964static void
2965amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2966 void **this_cache,
2967 struct frame_id *this_id)
2968{
2969 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2970 this_cache);
2971
8fbca658 2972 if (!cache->base_p)
5ce0145d
PA		 2973 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2974 else
2975 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2976}
2977
2978static const struct frame_unwind amd64_epilogue_frame_unwind =
2979{
2980 NORMAL_FRAME,
8fbca658 2981 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2982 amd64_epilogue_frame_this_id,
2983 amd64_frame_prev_register,
2984 NULL,
2985 amd64_epilogue_frame_sniffer
2986};
2987
166f4c7b 2988static struct frame_id
10458914 2989amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2990{
c4f35dd8
MK		 2991 CORE_ADDR fp;
2992
10458914 2993 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2994
10458914 2995 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 2996}
2997
8b148df9
AC		 2998/* 16 byte align the SP per frame requirements. */
2999
3000static CORE_ADDR
e53bef9f 3001amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 3002{
3003 return sp & -(CORE_ADDR)16;
3004}
473f17b0
MK		 3005\f
3006
593adc23
MK		 3007/* Supply register REGNUM from the buffer specified by FPREGS and LEN
3008 in the floating-point register set REGSET to register cache
3009 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 3010
3011static void
e53bef9f
MK		 3012amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3013 int regnum, const void *fpregs, size_t len)
473f17b0 3014{
ac7936df 3015 struct gdbarch *gdbarch = regcache->arch ();
09424cff 3016 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 3017
1528345d 3018 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 3019 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 3020}
8b148df9 3021
593adc23
MK		 3022/* Collect register REGNUM from the register cache REGCACHE and store
3023 it in the buffer specified by FPREGS and LEN as described by the
3024 floating-point register set REGSET. If REGNUM is -1, do this for
3025 all registers in REGSET. */
3026
3027static void
3028amd64_collect_fpregset (const struct regset *regset,
3029 const struct regcache *regcache,
3030 int regnum, void *fpregs, size_t len)
3031{
ac7936df 3032 struct gdbarch *gdbarch = regcache->arch ();
09424cff 3033 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 3034
1528345d 3035 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 3036 amd64_collect_fxsave (regcache, regnum, fpregs);
3037}
3038
8f0435f7 3039const struct regset amd64_fpregset =
ecc37a5a
AA		 3040 {
3041 NULL, amd64_supply_fpregset, amd64_collect_fpregset
3042 };
c6b33596
MK		 3043\f
3044
436675d3
PA		 3045/* Figure out where the longjmp will land. Slurp the jmp_buf out of
3046 %rdi. We expect its value to be a pointer to the jmp_buf structure
3047 from which we extract the address that we will land at. This
3048 address is copied into PC. This routine returns non-zero on
3049 success. */
3050
3051static int
3052amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3053{
3054 gdb_byte buf[8];
3055 CORE_ADDR jb_addr;
3056 struct gdbarch *gdbarch = get_frame_arch (frame);
3057 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 3058 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3059
3060 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3061 longjmp will land. */
3062 if (jb_pc_offset == -1)
3063 return 0;
3064
3065 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 3066 jb_addr= extract_typed_address
3067 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 3068 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3069 return 0;
3070
0dfff4cb 3071 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3072
3073 return 1;
3074}
3075
cf648174
HZ		 3076static const int amd64_record_regmap[] =
3077{
3078 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3079 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3080 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3081 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3082 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3083 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3084};
3085
1d509aa6
MM		 3086/* Implement the "in_indirect_branch_thunk" gdbarch function. */
3087
3088static bool
3089amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc)
3090{
3091 return x86_in_indirect_branch_thunk (pc, amd64_register_names,
3092 AMD64_RAX_REGNUM,
3093 AMD64_RIP_REGNUM);
3094}
3095
2213a65d 3096void
c55a47e7 3097amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3098 const target_desc *default_tdesc)
53e95fcf 3099{
0c1a73d6 3100 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 3101 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 3102 static const char *const stap_integer_prefixes[] = { "$", NULL };
3103 static const char *const stap_register_prefixes[] = { "%", NULL };
3104 static const char *const stap_register_indirection_prefixes[] = { "(",
3105 NULL };
3106 static const char *const stap_register_indirection_suffixes[] = { ")",
3107 NULL };
53e95fcf 3108
473f17b0
MK		 3109 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3110 floating-point registers. */
3111 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 3112 tdep->fpregset = &amd64_fpregset;
473f17b0 3113
90884b2b 3114 if (! tdesc_has_registers (tdesc))
c55a47e7 3115 tdesc = default_tdesc;
90884b2b
L		 3116 tdep->tdesc = tdesc;
3117
3118 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3119 tdep->register_names = amd64_register_names;
3120
01f9f808
MS		 3121 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3122 {
3123 tdep->zmmh_register_names = amd64_zmmh_names;
3124 tdep->k_register_names = amd64_k_names;
3125 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3126 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3127
3128 tdep->num_zmm_regs = 32;
3129 tdep->num_xmm_avx512_regs = 16;
3130 tdep->num_ymm_avx512_regs = 16;
3131
3132 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3133 tdep->k0_regnum = AMD64_K0_REGNUM;
3134 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3135 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3136 }
3137
a055a187
L		 3138 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3139 {
3140 tdep->ymmh_register_names = amd64_ymmh_names;
3141 tdep->num_ymm_regs = 16;
3142 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3143 }
3144
e43e105e
WT		 3145 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3146 {
3147 tdep->mpx_register_names = amd64_mpx_names;
3148 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3149 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3150 }
3151
2735833d
WT		 3152 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3153 {
1163a4b7 3154 tdep->fsbase_regnum = AMD64_FSBASE_REGNUM;
2735833d
WT		 3155 }
3156
51547df6
MS		 3157 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3158 {
3159 tdep->pkeys_register_names = amd64_pkeys_names;
3160 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3161 tdep->num_pkeys_regs = 1;
3162 }
3163
fe01d668 3164 tdep->num_byte_regs = 20;
1ba53b71
L		 3165 tdep->num_word_regs = 16;
3166 tdep->num_dword_regs = 16;
3167 /* Avoid wiring in the MMX registers for now. */
3168 tdep->num_mmx_regs = 0;
3169
3543a589
TT		 3170 set_gdbarch_pseudo_register_read_value (gdbarch,
3171 amd64_pseudo_register_read_value);
1ba53b71
L		 3172 set_gdbarch_pseudo_register_write (gdbarch,
3173 amd64_pseudo_register_write);
62e5fd57
MK		 3174 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3175 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3176
3177 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3178
5716833c 3179 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3180 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3181 tdep->num_xmm_regs = 16;
53e95fcf 3182
0c1a73d6 3183 /* This is what all the fuss is about. */
53e95fcf
JS		 3184 set_gdbarch_long_bit (gdbarch, 64);
3185 set_gdbarch_long_long_bit (gdbarch, 64);
3186 set_gdbarch_ptr_bit (gdbarch, 64);
3187
e53bef9f
MK		 3188 /* In contrast to the i386, on AMD64 a `long double' actually takes
3189 up 128 bits, even though it's still based on the i387 extended
3190 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3191 set_gdbarch_long_double_bit (gdbarch, 128);
3192
e53bef9f 3193 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3194
3195 /* Register numbers of various important registers. */
90f90721
MK		 3196 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3197 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3198 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3199 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3200
e53bef9f
MK		 3201 /* The "default" register numbering scheme for AMD64 is referred to
3202 as the "DWARF Register Number Mapping" in the System V psABI.
3203 The preferred debugging format for all known AMD64 targets is
3204 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3205 DWARF-1), but we provide the same mapping just in case. This
3206 mapping is also used for stabs, which GCC does support. */
3207 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3208 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3209
c4f35dd8 3210 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3211 be in use on any of the supported AMD64 targets. */
53e95fcf 3212
c4f35dd8 3213 /* Call dummy code. */
e53bef9f
MK		 3214 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3215 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3216 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3217
83acabca 3218 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3219 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3220 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3221
efb1c01c 3222 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3223
e53bef9f 3224 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3225
cf648174
HZ		 3226 tdep->record_regmap = amd64_record_regmap;
3227
10458914 3228 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3229
872761f4
MS		 3230 /* Hook the function epilogue frame unwinder. This unwinder is
3231 appended to the list first, so that it supercedes the other
3232 unwinders in function epilogues. */
3233 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3234
3235 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3236 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3237 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3238 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3239
436675d3 3240 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3241
3242 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3243
3244 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3245
3246 /* SystemTap variables and functions. */
05c0465e
SDJ		 3247 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3248 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3249 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3250 stap_register_indirection_prefixes);
3251 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3252 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3253 set_gdbarch_stap_is_single_operand (gdbarch,
3254 i386_stap_is_single_operand);
3255 set_gdbarch_stap_parse_special_token (gdbarch,
3256 i386_stap_parse_special_token);
c2170eef
MM		 3257 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3258 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3259 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
1d509aa6
MM		 3260
3261 set_gdbarch_in_indirect_branch_thunk (gdbarch,
3262 amd64_in_indirect_branch_thunk);
c4f35dd8 3263}
c912f608
SM		 3264
3265/* Initialize ARCH for x86-64, no osabi. */
3266
3267static void
3268amd64_none_init_abi (gdbarch_info info, gdbarch *arch)
3269{
de52b960
PA		 3270 amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK,
3271 true));
c912f608 3272}
fff4548b
MK		 3273
3274static struct type *
3275amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3276{
3277 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3278
3279 switch (regnum - tdep->eax_regnum)
3280 {
3281 case AMD64_RBP_REGNUM: /* %ebp */
3282 case AMD64_RSP_REGNUM: /* %esp */
3283 return builtin_type (gdbarch)->builtin_data_ptr;
3284 case AMD64_RIP_REGNUM: /* %eip */
3285 return builtin_type (gdbarch)->builtin_func_ptr;
3286 }
3287
3288 return i386_pseudo_register_type (gdbarch, regnum);
3289}
3290
3291void
c55a47e7 3292amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3293 const target_desc *default_tdesc)
fff4548b
MK		 3294{
3295 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
fff4548b 3296
c55a47e7 3297 amd64_init_abi (info, gdbarch, default_tdesc);
fff4548b
MK		 3298
3299 tdep->num_dword_regs = 17;
3300 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3301
3302 set_gdbarch_long_bit (gdbarch, 32);
3303 set_gdbarch_ptr_bit (gdbarch, 32);
3304}
90884b2b 3305
c912f608
SM		 3306/* Initialize ARCH for x64-32, no osabi. */
3307
3308static void
3309amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch)
3310{
3311 amd64_x32_init_abi (info, arch,
de52b960 3312 amd64_target_description (X86_XSTATE_SSE_MASK, true));
c912f608
SM		 3313}
3314
97de3545
JB		 3315/* Return the target description for a specified XSAVE feature mask. */
3316
3317const struct target_desc *
de52b960 3318amd64_target_description (uint64_t xcr0, bool segments)
97de3545 3319{
22916b07 3320 static target_desc *amd64_tdescs \
de52b960 3321 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
22916b07
YQ		 3322 target_desc **tdesc;
3323
3324 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3325 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3326 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
de52b960
PA		 3327 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0]
3328 [segments ? 1 : 0];
22916b07
YQ		 3329
3330 if (*tdesc == NULL)
de52b960
PA		 3331 *tdesc = amd64_create_target_description (xcr0, false, false,
3332 segments);
22916b07
YQ		 3333
3334 return *tdesc;
97de3545
JB		 3335}
3336
90884b2b
L		 3337void
3338_initialize_amd64_tdep (void)
3339{
c912f608
SM		 3340 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE,
3341 amd64_none_init_abi);
3342 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE,
3343 amd64_x32_none_init_abi);
90884b2b 3344}
c4f35dd8
MK		 3345\f
3346
41d041d6
MK		 3347/* The 64-bit FXSAVE format differs from the 32-bit format in the
3348 sense that the instruction pointer and data pointer are simply
3349 64-bit offsets into the code segment and the data segment instead
3350 of a selector offset pair. The functions below store the upper 32
3351 bits of these pointers (instead of just the 16-bits of the segment
3352 selector). */
3353
3354/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3355 floating-point or SSE register value from *FXSAVE. If REGNUM is
3356 -1, do this for all registers. This function masks off any of the
3357 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3358
3359void
90f90721 3360amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3361 const void *fxsave)
c4f35dd8 3362{
ac7936df 3363 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49
MD		 3364 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3365
41d041d6 3366 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3367
233dfcf0
L		 3368 if (fxsave
3369 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3370 {
9a3c8263 3371 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3372
20a6ec49 3373 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3374 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3375 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3376 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3377 }
0c1a73d6
MK		 3378}
3379
a055a187
L		 3380/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3381
3382void
3383amd64_supply_xsave (struct regcache *regcache, int regnum,
3384 const void *xsave)
3385{
ac7936df 3386 struct gdbarch *gdbarch = regcache->arch ();
a055a187
L		 3387 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3388
3389 i387_supply_xsave (regcache, regnum, xsave);
3390
233dfcf0
L		 3391 if (xsave
3392 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3393 {
9a3c8263 3394 const gdb_byte *regs = (const gdb_byte *) xsave;
8ee22052 3395 ULONGEST clear_bv;
a055a187 3396
8ee22052
AB		 3397 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
3398
3399 /* If the FISEG and FOSEG registers have not been initialised yet
3400 (their CLEAR_BV bit is set) then their default values of zero will
3401 have already been setup by I387_SUPPLY_XSAVE. */
3402 if (!(clear_bv & X86_XSTATE_X87))
3403 {
3404 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3405 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
8ee22052 3406 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3407 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
8ee22052 3408 }
a055a187
L		 3409 }
3410}
3411
3c017e40
MK		 3412/* Fill register REGNUM (if it is a floating-point or SSE register) in
3413 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3414 all registers. This function doesn't touch any of the reserved
3415 bits in *FXSAVE. */
3416
3417void
3418amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3419 void *fxsave)
3420{
ac7936df 3421 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49 3422 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3423 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3424
3425 i387_collect_fxsave (regcache, regnum, fxsave);
3426
233dfcf0 3427 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3428 {
20a6ec49 3429 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3430 regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3431 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3432 regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3433 }
3c017e40 3434}
a055a187 3435
7a9dd1b2 3436/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3437
3438void
3439amd64_collect_xsave (const struct regcache *regcache, int regnum,
3440 void *xsave, int gcore)
3441{
ac7936df 3442 struct gdbarch *gdbarch = regcache->arch ();
a055a187 3443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3444 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3445
3446 i387_collect_xsave (regcache, regnum, xsave, gcore);
3447
233dfcf0 3448 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3449 {
3450 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3451 regcache->raw_collect (I387_FISEG_REGNUM (tdep),
a055a187
L		 3452 regs + 12);
3453 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3454 regcache->raw_collect (I387_FOSEG_REGNUM (tdep),
a055a187
L		 3455 regs + 20);
3456 }
3457}
GDB Binutils - Deliverables
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