Commit | Line | Data |
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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
5ae96ec1 MK |
4 | |
5 | Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
6 | |
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
12 | (at your option) any later version. |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
21 | |
22 | #include "defs.h" | |
35669430 DE |
23 | #include "opcode/i386.h" |
24 | #include "dis-asm.h" | |
c4f35dd8 MK |
25 | #include "arch-utils.h" |
26 | #include "block.h" | |
27 | #include "dummy-frame.h" | |
28 | #include "frame.h" | |
29 | #include "frame-base.h" | |
30 | #include "frame-unwind.h" | |
53e95fcf | 31 | #include "inferior.h" |
53e95fcf | 32 | #include "gdbcmd.h" |
c4f35dd8 MK |
33 | #include "gdbcore.h" |
34 | #include "objfiles.h" | |
53e95fcf | 35 | #include "regcache.h" |
2c261fae | 36 | #include "regset.h" |
53e95fcf | 37 | #include "symfile.h" |
eda5a4d7 | 38 | #include "disasm.h" |
82dbc5f7 | 39 | #include "gdb_assert.h" |
8fbca658 | 40 | #include "exceptions.h" |
9c1488cb | 41 | #include "amd64-tdep.h" |
c4f35dd8 | 42 | #include "i387-tdep.h" |
53e95fcf | 43 | |
90884b2b | 44 | #include "features/i386/amd64.c" |
a055a187 | 45 | #include "features/i386/amd64-avx.c" |
e43e105e | 46 | #include "features/i386/amd64-mpx.c" |
ac1438b5 L |
47 | #include "features/i386/x32.c" |
48 | #include "features/i386/x32-avx.c" | |
90884b2b | 49 | |
6710bf39 SS |
50 | #include "ax.h" |
51 | #include "ax-gdb.h" | |
52 | ||
e53bef9f MK |
53 | /* Note that the AMD64 architecture was previously known as x86-64. |
54 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 55 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
56 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
57 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
58 | x86_64_-prefix since it's so much easier to type. */ | |
59 | ||
402ecd56 | 60 | /* Register information. */ |
c4f35dd8 | 61 | |
6707b003 | 62 | static const char *amd64_register_names[] = |
de220d0f | 63 | { |
6707b003 | 64 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
c4f35dd8 MK |
65 | |
66 | /* %r8 is indeed register number 8. */ | |
6707b003 UW |
67 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
68 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", | |
c4f35dd8 | 69 | |
af233647 | 70 | /* %st0 is register number 24. */ |
6707b003 UW |
71 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
72 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", | |
c4f35dd8 | 73 | |
af233647 | 74 | /* %xmm0 is register number 40. */ |
6707b003 UW |
75 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
76 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", | |
77 | "mxcsr", | |
0e04a514 ML |
78 | }; |
79 | ||
a055a187 L |
80 | static const char *amd64_ymm_names[] = |
81 | { | |
82 | "ymm0", "ymm1", "ymm2", "ymm3", | |
83 | "ymm4", "ymm5", "ymm6", "ymm7", | |
84 | "ymm8", "ymm9", "ymm10", "ymm11", | |
85 | "ymm12", "ymm13", "ymm14", "ymm15" | |
86 | }; | |
87 | ||
88 | static const char *amd64_ymmh_names[] = | |
89 | { | |
90 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
91 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
92 | "ymm8h", "ymm9h", "ymm10h", "ymm11h", | |
93 | "ymm12h", "ymm13h", "ymm14h", "ymm15h" | |
94 | }; | |
de220d0f | 95 | |
e43e105e WT |
96 | static const char *amd64_mpx_names[] = |
97 | { | |
98 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
99 | }; | |
100 | ||
c4f35dd8 MK |
101 | /* DWARF Register Number Mapping as defined in the System V psABI, |
102 | section 3.6. */ | |
53e95fcf | 103 | |
e53bef9f | 104 | static int amd64_dwarf_regmap[] = |
0e04a514 | 105 | { |
c4f35dd8 | 106 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
107 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
108 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
109 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
110 | |
111 | /* Frame Pointer Register RBP. */ | |
90f90721 | 112 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
113 | |
114 | /* Stack Pointer Register RSP. */ | |
90f90721 | 115 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
116 | |
117 | /* Extended Integer Registers 8 - 15. */ | |
5b856f36 PM |
118 | AMD64_R8_REGNUM, /* %r8 */ |
119 | AMD64_R9_REGNUM, /* %r9 */ | |
120 | AMD64_R10_REGNUM, /* %r10 */ | |
121 | AMD64_R11_REGNUM, /* %r11 */ | |
122 | AMD64_R12_REGNUM, /* %r12 */ | |
123 | AMD64_R13_REGNUM, /* %r13 */ | |
124 | AMD64_R14_REGNUM, /* %r14 */ | |
125 | AMD64_R15_REGNUM, /* %r15 */ | |
c4f35dd8 | 126 | |
59207364 | 127 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 128 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
129 | |
130 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
131 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
132 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
133 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
134 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
135 | |
136 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
137 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
138 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
139 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
140 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
141 | |
142 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
143 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
144 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
145 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 JB |
146 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
147 | ||
148 | /* Control and Status Flags Register. */ | |
149 | AMD64_EFLAGS_REGNUM, | |
150 | ||
151 | /* Selector Registers. */ | |
152 | AMD64_ES_REGNUM, | |
153 | AMD64_CS_REGNUM, | |
154 | AMD64_SS_REGNUM, | |
155 | AMD64_DS_REGNUM, | |
156 | AMD64_FS_REGNUM, | |
157 | AMD64_GS_REGNUM, | |
158 | -1, | |
159 | -1, | |
160 | ||
161 | /* Segment Base Address Registers. */ | |
162 | -1, | |
163 | -1, | |
164 | -1, | |
165 | -1, | |
166 | ||
167 | /* Special Selector Registers. */ | |
168 | -1, | |
169 | -1, | |
170 | ||
171 | /* Floating Point Control Registers. */ | |
172 | AMD64_MXCSR_REGNUM, | |
173 | AMD64_FCTRL_REGNUM, | |
174 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 175 | }; |
0e04a514 | 176 | |
e53bef9f MK |
177 | static const int amd64_dwarf_regmap_len = |
178 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 179 | |
c4f35dd8 MK |
180 | /* Convert DWARF register number REG to the appropriate register |
181 | number used by GDB. */ | |
26abbdc4 | 182 | |
c4f35dd8 | 183 | static int |
d3f73121 | 184 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
53e95fcf | 185 | { |
a055a187 L |
186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
187 | int ymm0_regnum = tdep->ymm0_regnum; | |
c4f35dd8 | 188 | int regnum = -1; |
53e95fcf | 189 | |
16aff9a6 | 190 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 191 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 192 | |
c4f35dd8 | 193 | if (regnum == -1) |
8a3fe4f8 | 194 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a055a187 L |
195 | else if (ymm0_regnum >= 0 |
196 | && i386_xmm_regnum_p (gdbarch, regnum)) | |
197 | regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); | |
c4f35dd8 MK |
198 | |
199 | return regnum; | |
53e95fcf | 200 | } |
d532c08f | 201 | |
35669430 DE |
202 | /* Map architectural register numbers to gdb register numbers. */ |
203 | ||
204 | static const int amd64_arch_regmap[16] = | |
205 | { | |
206 | AMD64_RAX_REGNUM, /* %rax */ | |
207 | AMD64_RCX_REGNUM, /* %rcx */ | |
208 | AMD64_RDX_REGNUM, /* %rdx */ | |
209 | AMD64_RBX_REGNUM, /* %rbx */ | |
210 | AMD64_RSP_REGNUM, /* %rsp */ | |
211 | AMD64_RBP_REGNUM, /* %rbp */ | |
212 | AMD64_RSI_REGNUM, /* %rsi */ | |
213 | AMD64_RDI_REGNUM, /* %rdi */ | |
214 | AMD64_R8_REGNUM, /* %r8 */ | |
215 | AMD64_R9_REGNUM, /* %r9 */ | |
216 | AMD64_R10_REGNUM, /* %r10 */ | |
217 | AMD64_R11_REGNUM, /* %r11 */ | |
218 | AMD64_R12_REGNUM, /* %r12 */ | |
219 | AMD64_R13_REGNUM, /* %r13 */ | |
220 | AMD64_R14_REGNUM, /* %r14 */ | |
221 | AMD64_R15_REGNUM /* %r15 */ | |
222 | }; | |
223 | ||
224 | static const int amd64_arch_regmap_len = | |
225 | (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); | |
226 | ||
227 | /* Convert architectural register number REG to the appropriate register | |
228 | number used by GDB. */ | |
229 | ||
230 | static int | |
231 | amd64_arch_reg_to_regnum (int reg) | |
232 | { | |
233 | gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); | |
234 | ||
235 | return amd64_arch_regmap[reg]; | |
236 | } | |
237 | ||
1ba53b71 L |
238 | /* Register names for byte pseudo-registers. */ |
239 | ||
240 | static const char *amd64_byte_names[] = | |
241 | { | |
242 | "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", | |
fe01d668 L |
243 | "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", |
244 | "ah", "bh", "ch", "dh" | |
1ba53b71 L |
245 | }; |
246 | ||
fe01d668 L |
247 | /* Number of lower byte registers. */ |
248 | #define AMD64_NUM_LOWER_BYTE_REGS 16 | |
249 | ||
1ba53b71 L |
250 | /* Register names for word pseudo-registers. */ |
251 | ||
252 | static const char *amd64_word_names[] = | |
253 | { | |
9cad29ac | 254 | "ax", "bx", "cx", "dx", "si", "di", "bp", "", |
1ba53b71 L |
255 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
256 | }; | |
257 | ||
258 | /* Register names for dword pseudo-registers. */ | |
259 | ||
260 | static const char *amd64_dword_names[] = | |
261 | { | |
262 | "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", | |
fff4548b MK |
263 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", |
264 | "eip" | |
1ba53b71 L |
265 | }; |
266 | ||
267 | /* Return the name of register REGNUM. */ | |
268 | ||
269 | static const char * | |
270 | amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
271 | { | |
272 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
273 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
274 | return amd64_byte_names[regnum - tdep->al_regnum]; | |
a055a187 L |
275 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
276 | return amd64_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
277 | else if (i386_word_regnum_p (gdbarch, regnum)) |
278 | return amd64_word_names[regnum - tdep->ax_regnum]; | |
279 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
280 | return amd64_dword_names[regnum - tdep->eax_regnum]; | |
281 | else | |
282 | return i386_pseudo_register_name (gdbarch, regnum); | |
283 | } | |
284 | ||
3543a589 TT |
285 | static struct value * |
286 | amd64_pseudo_register_read_value (struct gdbarch *gdbarch, | |
287 | struct regcache *regcache, | |
288 | int regnum) | |
1ba53b71 L |
289 | { |
290 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; | |
291 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
05d1431c | 292 | enum register_status status; |
3543a589 TT |
293 | struct value *result_value; |
294 | gdb_byte *buf; | |
295 | ||
296 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
297 | VALUE_LVAL (result_value) = lval_register; | |
298 | VALUE_REGNUM (result_value) = regnum; | |
299 | buf = value_contents_raw (result_value); | |
1ba53b71 L |
300 | |
301 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
302 | { | |
303 | int gpnum = regnum - tdep->al_regnum; | |
304 | ||
305 | /* Extract (always little endian). */ | |
fe01d668 L |
306 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
307 | { | |
308 | /* Special handling for AH, BH, CH, DH. */ | |
05d1431c PA |
309 | status = regcache_raw_read (regcache, |
310 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, | |
311 | raw_buf); | |
312 | if (status == REG_VALID) | |
313 | memcpy (buf, raw_buf + 1, 1); | |
3543a589 TT |
314 | else |
315 | mark_value_bytes_unavailable (result_value, 0, | |
316 | TYPE_LENGTH (value_type (result_value))); | |
fe01d668 L |
317 | } |
318 | else | |
319 | { | |
05d1431c PA |
320 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
321 | if (status == REG_VALID) | |
322 | memcpy (buf, raw_buf, 1); | |
3543a589 TT |
323 | else |
324 | mark_value_bytes_unavailable (result_value, 0, | |
325 | TYPE_LENGTH (value_type (result_value))); | |
fe01d668 | 326 | } |
1ba53b71 L |
327 | } |
328 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
329 | { | |
330 | int gpnum = regnum - tdep->eax_regnum; | |
331 | /* Extract (always little endian). */ | |
05d1431c PA |
332 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
333 | if (status == REG_VALID) | |
334 | memcpy (buf, raw_buf, 4); | |
3543a589 TT |
335 | else |
336 | mark_value_bytes_unavailable (result_value, 0, | |
337 | TYPE_LENGTH (value_type (result_value))); | |
1ba53b71 L |
338 | } |
339 | else | |
3543a589 TT |
340 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, |
341 | result_value); | |
342 | ||
343 | return result_value; | |
1ba53b71 L |
344 | } |
345 | ||
346 | static void | |
347 | amd64_pseudo_register_write (struct gdbarch *gdbarch, | |
348 | struct regcache *regcache, | |
349 | int regnum, const gdb_byte *buf) | |
350 | { | |
351 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; | |
352 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
353 | ||
354 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
355 | { | |
356 | int gpnum = regnum - tdep->al_regnum; | |
357 | ||
fe01d668 L |
358 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
359 | { | |
360 | /* Read ... AH, BH, CH, DH. */ | |
361 | regcache_raw_read (regcache, | |
362 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); | |
363 | /* ... Modify ... (always little endian). */ | |
364 | memcpy (raw_buf + 1, buf, 1); | |
365 | /* ... Write. */ | |
366 | regcache_raw_write (regcache, | |
367 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); | |
368 | } | |
369 | else | |
370 | { | |
371 | /* Read ... */ | |
372 | regcache_raw_read (regcache, gpnum, raw_buf); | |
373 | /* ... Modify ... (always little endian). */ | |
374 | memcpy (raw_buf, buf, 1); | |
375 | /* ... Write. */ | |
376 | regcache_raw_write (regcache, gpnum, raw_buf); | |
377 | } | |
1ba53b71 L |
378 | } |
379 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
380 | { | |
381 | int gpnum = regnum - tdep->eax_regnum; | |
382 | ||
383 | /* Read ... */ | |
384 | regcache_raw_read (regcache, gpnum, raw_buf); | |
385 | /* ... Modify ... (always little endian). */ | |
386 | memcpy (raw_buf, buf, 4); | |
387 | /* ... Write. */ | |
388 | regcache_raw_write (regcache, gpnum, raw_buf); | |
389 | } | |
390 | else | |
391 | i386_pseudo_register_write (gdbarch, regcache, regnum, buf); | |
392 | } | |
393 | ||
53e95fcf JS |
394 | \f |
395 | ||
bf4d6c1c JB |
396 | /* Register classes as defined in the psABI. */ |
397 | ||
398 | enum amd64_reg_class | |
399 | { | |
400 | AMD64_INTEGER, | |
401 | AMD64_SSE, | |
402 | AMD64_SSEUP, | |
403 | AMD64_X87, | |
404 | AMD64_X87UP, | |
405 | AMD64_COMPLEX_X87, | |
406 | AMD64_NO_CLASS, | |
407 | AMD64_MEMORY | |
408 | }; | |
409 | ||
efb1c01c MK |
410 | /* Return the union class of CLASS1 and CLASS2. See the psABI for |
411 | details. */ | |
412 | ||
413 | static enum amd64_reg_class | |
414 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
415 | { | |
416 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
417 | if (class1 == class2) | |
418 | return class1; | |
419 | ||
420 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
421 | is the other class. */ | |
422 | if (class1 == AMD64_NO_CLASS) | |
423 | return class2; | |
424 | if (class2 == AMD64_NO_CLASS) | |
425 | return class1; | |
426 | ||
427 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
428 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
429 | return AMD64_MEMORY; | |
430 | ||
431 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
432 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
433 | return AMD64_INTEGER; | |
434 | ||
435 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
436 | MEMORY is used as class. */ | |
437 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
438 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
439 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
440 | return AMD64_MEMORY; | |
441 | ||
442 | /* Rule (f): Otherwise class SSE is used. */ | |
443 | return AMD64_SSE; | |
444 | } | |
445 | ||
bf4d6c1c JB |
446 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); |
447 | ||
79b1ab3d MK |
448 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
449 | ||
450 | static int | |
451 | amd64_non_pod_p (struct type *type) | |
452 | { | |
453 | /* ??? A class with a base class certainly isn't POD, but does this | |
454 | catch all non-POD structure types? */ | |
455 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
456 | return 1; | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
efb1c01c MK |
461 | /* Classify TYPE according to the rules for aggregate (structures and |
462 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
463 | |
464 | static void | |
efb1c01c | 465 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
53e95fcf | 466 | { |
efb1c01c MK |
467 | /* 1. If the size of an object is larger than two eightbytes, or in |
468 | C++, is a non-POD structure or union type, or contains | |
469 | unaligned fields, it has class memory. */ | |
744a8059 | 470 | if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) |
53e95fcf | 471 | { |
efb1c01c MK |
472 | class[0] = class[1] = AMD64_MEMORY; |
473 | return; | |
53e95fcf | 474 | } |
efb1c01c MK |
475 | |
476 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
477 | class[0] = class[1] = AMD64_NO_CLASS; | |
478 | ||
479 | /* 3. Each field of an object is classified recursively so that | |
480 | always two fields are considered. The resulting class is | |
481 | calculated according to the classes of the fields in the | |
482 | eightbyte: */ | |
483 | ||
484 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 485 | { |
efb1c01c MK |
486 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
487 | ||
488 | /* All fields in an array have the same type. */ | |
489 | amd64_classify (subtype, class); | |
744a8059 | 490 | if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS) |
efb1c01c | 491 | class[1] = class[0]; |
8ffd9b1b | 492 | } |
53e95fcf JS |
493 | else |
494 | { | |
efb1c01c | 495 | int i; |
53e95fcf | 496 | |
efb1c01c MK |
497 | /* Structure or union. */ |
498 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
499 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
500 | ||
501 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 502 | { |
efb1c01c MK |
503 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
504 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
505 | enum amd64_reg_class subclass[2]; | |
e4e2711a JB |
506 | int bitsize = TYPE_FIELD_BITSIZE (type, i); |
507 | int endpos; | |
508 | ||
509 | if (bitsize == 0) | |
510 | bitsize = TYPE_LENGTH (subtype) * 8; | |
511 | endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; | |
efb1c01c | 512 | |
562c50c2 | 513 | /* Ignore static fields. */ |
d6a843b5 | 514 | if (field_is_static (&TYPE_FIELD (type, i))) |
562c50c2 MK |
515 | continue; |
516 | ||
efb1c01c MK |
517 | gdb_assert (pos == 0 || pos == 1); |
518 | ||
519 | amd64_classify (subtype, subclass); | |
520 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); | |
e4e2711a JB |
521 | if (bitsize <= 64 && pos == 0 && endpos == 1) |
522 | /* This is a bit of an odd case: We have a field that would | |
523 | normally fit in one of the two eightbytes, except that | |
524 | it is placed in a way that this field straddles them. | |
525 | This has been seen with a structure containing an array. | |
526 | ||
527 | The ABI is a bit unclear in this case, but we assume that | |
528 | this field's class (stored in subclass[0]) must also be merged | |
529 | into class[1]. In other words, our field has a piece stored | |
530 | in the second eight-byte, and thus its class applies to | |
531 | the second eight-byte as well. | |
532 | ||
533 | In the case where the field length exceeds 8 bytes, | |
534 | it should not be necessary to merge the field class | |
535 | into class[1]. As LEN > 8, subclass[1] is necessarily | |
536 | different from AMD64_NO_CLASS. If subclass[1] is equal | |
537 | to subclass[0], then the normal class[1]/subclass[1] | |
538 | merging will take care of everything. For subclass[1] | |
539 | to be different from subclass[0], I can only see the case | |
540 | where we have a SSE/SSEUP or X87/X87UP pair, which both | |
541 | use up all 16 bytes of the aggregate, and are already | |
542 | handled just fine (because each portion sits on its own | |
543 | 8-byte). */ | |
544 | class[1] = amd64_merge_classes (class[1], subclass[0]); | |
efb1c01c MK |
545 | if (pos == 0) |
546 | class[1] = amd64_merge_classes (class[1], subclass[1]); | |
53e95fcf | 547 | } |
53e95fcf | 548 | } |
efb1c01c MK |
549 | |
550 | /* 4. Then a post merger cleanup is done: */ | |
551 | ||
552 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
553 | passed in memory. */ | |
554 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) | |
555 | class[0] = class[1] = AMD64_MEMORY; | |
556 | ||
177b42fe | 557 | /* Rule (b): If SSEUP is not preceded by SSE, it is converted to |
efb1c01c MK |
558 | SSE. */ |
559 | if (class[0] == AMD64_SSEUP) | |
560 | class[0] = AMD64_SSE; | |
561 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) | |
562 | class[1] = AMD64_SSE; | |
563 | } | |
564 | ||
565 | /* Classify TYPE, and store the result in CLASS. */ | |
566 | ||
bf4d6c1c | 567 | static void |
efb1c01c MK |
568 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) |
569 | { | |
570 | enum type_code code = TYPE_CODE (type); | |
571 | int len = TYPE_LENGTH (type); | |
572 | ||
573 | class[0] = class[1] = AMD64_NO_CLASS; | |
574 | ||
575 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
576 | long, long long, and pointers are in the INTEGER class. Similarly, |
577 | range types, used by languages such as Ada, are also in the INTEGER | |
578 | class. */ | |
efb1c01c | 579 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
b929c77f | 580 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
9db13498 | 581 | || code == TYPE_CODE_CHAR |
efb1c01c MK |
582 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
583 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
584 | class[0] = AMD64_INTEGER; | |
585 | ||
5daa78cc TJB |
586 | /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 |
587 | are in class SSE. */ | |
588 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) | |
589 | && (len == 4 || len == 8)) | |
efb1c01c MK |
590 | /* FIXME: __m64 . */ |
591 | class[0] = AMD64_SSE; | |
592 | ||
5daa78cc TJB |
593 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
594 | two halves. The least significant ones belong to class SSE, the most | |
efb1c01c | 595 | significant one to class SSEUP. */ |
5daa78cc TJB |
596 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
597 | /* FIXME: __float128, __m128. */ | |
598 | class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; | |
efb1c01c MK |
599 | |
600 | /* The 64-bit mantissa of arguments of type long double belongs to | |
601 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
602 | class X87UP. */ | |
603 | else if (code == TYPE_CODE_FLT && len == 16) | |
604 | /* Class X87 and X87UP. */ | |
605 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; | |
606 | ||
7f7930dd MK |
607 | /* Arguments of complex T where T is one of the types float or |
608 | double get treated as if they are implemented as: | |
609 | ||
610 | struct complexT { | |
611 | T real; | |
612 | T imag; | |
613 | }; */ | |
614 | else if (code == TYPE_CODE_COMPLEX && len == 8) | |
615 | class[0] = AMD64_SSE; | |
616 | else if (code == TYPE_CODE_COMPLEX && len == 16) | |
617 | class[0] = class[1] = AMD64_SSE; | |
618 | ||
619 | /* A variable of type complex long double is classified as type | |
620 | COMPLEX_X87. */ | |
621 | else if (code == TYPE_CODE_COMPLEX && len == 32) | |
622 | class[0] = AMD64_COMPLEX_X87; | |
623 | ||
efb1c01c MK |
624 | /* Aggregates. */ |
625 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
626 | || code == TYPE_CODE_UNION) | |
627 | amd64_classify_aggregate (type, class); | |
628 | } | |
629 | ||
630 | static enum return_value_convention | |
6a3a010b | 631 | amd64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 632 | struct type *type, struct regcache *regcache, |
42835c2b | 633 | gdb_byte *readbuf, const gdb_byte *writebuf) |
efb1c01c MK |
634 | { |
635 | enum amd64_reg_class class[2]; | |
636 | int len = TYPE_LENGTH (type); | |
90f90721 MK |
637 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
638 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
639 | int integer_reg = 0; |
640 | int sse_reg = 0; | |
641 | int i; | |
642 | ||
643 | gdb_assert (!(readbuf && writebuf)); | |
644 | ||
645 | /* 1. Classify the return type with the classification algorithm. */ | |
bf4d6c1c | 646 | amd64_classify (type, class); |
efb1c01c MK |
647 | |
648 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d | 649 | for the return value and passes the address of this storage in |
0963b4bd | 650 | %rdi as if it were the first argument to the function. In effect, |
6fa57a7d MK |
651 | this address becomes a hidden first argument. |
652 | ||
653 | On return %rax will contain the address that has been passed in | |
654 | by the caller in %rdi. */ | |
efb1c01c | 655 | if (class[0] == AMD64_MEMORY) |
6fa57a7d MK |
656 | { |
657 | /* As indicated by the comment above, the ABI guarantees that we | |
658 | can always find the return value just after the function has | |
659 | returned. */ | |
660 | ||
661 | if (readbuf) | |
662 | { | |
663 | ULONGEST addr; | |
664 | ||
665 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
666 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
667 | } | |
668 | ||
669 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
670 | } | |
efb1c01c | 671 | |
7f7930dd MK |
672 | /* 8. If the class is COMPLEX_X87, the real part of the value is |
673 | returned in %st0 and the imaginary part in %st1. */ | |
674 | if (class[0] == AMD64_COMPLEX_X87) | |
675 | { | |
676 | if (readbuf) | |
677 | { | |
678 | regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); | |
679 | regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); | |
680 | } | |
681 | ||
682 | if (writebuf) | |
683 | { | |
684 | i387_return_value (gdbarch, regcache); | |
685 | regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); | |
686 | regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); | |
687 | ||
688 | /* Fix up the tag word such that both %st(0) and %st(1) are | |
689 | marked as valid. */ | |
690 | regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); | |
691 | } | |
692 | ||
693 | return RETURN_VALUE_REGISTER_CONVENTION; | |
694 | } | |
695 | ||
efb1c01c | 696 | gdb_assert (class[1] != AMD64_MEMORY); |
bad43aa5 | 697 | gdb_assert (len <= 16); |
efb1c01c MK |
698 | |
699 | for (i = 0; len > 0; i++, len -= 8) | |
700 | { | |
701 | int regnum = -1; | |
702 | int offset = 0; | |
703 | ||
704 | switch (class[i]) | |
705 | { | |
706 | case AMD64_INTEGER: | |
707 | /* 3. If the class is INTEGER, the next available register | |
708 | of the sequence %rax, %rdx is used. */ | |
709 | regnum = integer_regnum[integer_reg++]; | |
710 | break; | |
711 | ||
712 | case AMD64_SSE: | |
713 | /* 4. If the class is SSE, the next available SSE register | |
714 | of the sequence %xmm0, %xmm1 is used. */ | |
715 | regnum = sse_regnum[sse_reg++]; | |
716 | break; | |
717 | ||
718 | case AMD64_SSEUP: | |
719 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
720 | upper half of the last used SSE register. */ | |
721 | gdb_assert (sse_reg > 0); | |
722 | regnum = sse_regnum[sse_reg - 1]; | |
723 | offset = 8; | |
724 | break; | |
725 | ||
726 | case AMD64_X87: | |
727 | /* 6. If the class is X87, the value is returned on the X87 | |
728 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 729 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
730 | if (writebuf) |
731 | i387_return_value (gdbarch, regcache); | |
732 | break; | |
733 | ||
734 | case AMD64_X87UP: | |
735 | /* 7. If the class is X87UP, the value is returned together | |
736 | with the previous X87 value in %st0. */ | |
737 | gdb_assert (i > 0 && class[0] == AMD64_X87); | |
90f90721 | 738 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
739 | offset = 8; |
740 | len = 2; | |
741 | break; | |
742 | ||
743 | case AMD64_NO_CLASS: | |
744 | continue; | |
745 | ||
746 | default: | |
747 | gdb_assert (!"Unexpected register class."); | |
748 | } | |
749 | ||
750 | gdb_assert (regnum != -1); | |
751 | ||
752 | if (readbuf) | |
753 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 754 | readbuf + i * 8); |
efb1c01c MK |
755 | if (writebuf) |
756 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 757 | writebuf + i * 8); |
efb1c01c MK |
758 | } |
759 | ||
760 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
761 | } |
762 | \f | |
763 | ||
720aa428 MK |
764 | static CORE_ADDR |
765 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 766 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 | 767 | { |
bf4d6c1c JB |
768 | static int integer_regnum[] = |
769 | { | |
770 | AMD64_RDI_REGNUM, /* %rdi */ | |
771 | AMD64_RSI_REGNUM, /* %rsi */ | |
772 | AMD64_RDX_REGNUM, /* %rdx */ | |
773 | AMD64_RCX_REGNUM, /* %rcx */ | |
5b856f36 PM |
774 | AMD64_R8_REGNUM, /* %r8 */ |
775 | AMD64_R9_REGNUM /* %r9 */ | |
bf4d6c1c | 776 | }; |
720aa428 MK |
777 | static int sse_regnum[] = |
778 | { | |
779 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
780 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
781 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
782 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
783 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 MK |
784 | }; |
785 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); | |
786 | int num_stack_args = 0; | |
787 | int num_elements = 0; | |
788 | int element = 0; | |
789 | int integer_reg = 0; | |
790 | int sse_reg = 0; | |
791 | int i; | |
792 | ||
6470d250 MK |
793 | /* Reserve a register for the "hidden" argument. */ |
794 | if (struct_return) | |
795 | integer_reg++; | |
796 | ||
720aa428 MK |
797 | for (i = 0; i < nargs; i++) |
798 | { | |
4991999e | 799 | struct type *type = value_type (args[i]); |
720aa428 MK |
800 | int len = TYPE_LENGTH (type); |
801 | enum amd64_reg_class class[2]; | |
802 | int needed_integer_regs = 0; | |
803 | int needed_sse_regs = 0; | |
804 | int j; | |
805 | ||
806 | /* Classify argument. */ | |
bf4d6c1c | 807 | amd64_classify (type, class); |
720aa428 MK |
808 | |
809 | /* Calculate the number of integer and SSE registers needed for | |
810 | this argument. */ | |
811 | for (j = 0; j < 2; j++) | |
812 | { | |
813 | if (class[j] == AMD64_INTEGER) | |
814 | needed_integer_regs++; | |
815 | else if (class[j] == AMD64_SSE) | |
816 | needed_sse_regs++; | |
817 | } | |
818 | ||
819 | /* Check whether enough registers are available, and if the | |
820 | argument should be passed in registers at all. */ | |
bf4d6c1c | 821 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) |
720aa428 MK |
822 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) |
823 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
824 | { | |
825 | /* The argument will be passed on the stack. */ | |
826 | num_elements += ((len + 7) / 8); | |
849e9755 | 827 | stack_args[num_stack_args++] = args[i]; |
720aa428 MK |
828 | } |
829 | else | |
830 | { | |
831 | /* The argument will be passed in registers. */ | |
d8de1ef7 MK |
832 | const gdb_byte *valbuf = value_contents (args[i]); |
833 | gdb_byte buf[8]; | |
720aa428 MK |
834 | |
835 | gdb_assert (len <= 16); | |
836 | ||
837 | for (j = 0; len > 0; j++, len -= 8) | |
838 | { | |
839 | int regnum = -1; | |
840 | int offset = 0; | |
841 | ||
842 | switch (class[j]) | |
843 | { | |
844 | case AMD64_INTEGER: | |
bf4d6c1c | 845 | regnum = integer_regnum[integer_reg++]; |
720aa428 MK |
846 | break; |
847 | ||
848 | case AMD64_SSE: | |
849 | regnum = sse_regnum[sse_reg++]; | |
850 | break; | |
851 | ||
852 | case AMD64_SSEUP: | |
853 | gdb_assert (sse_reg > 0); | |
854 | regnum = sse_regnum[sse_reg - 1]; | |
855 | offset = 8; | |
856 | break; | |
857 | ||
858 | default: | |
859 | gdb_assert (!"Unexpected register class."); | |
860 | } | |
861 | ||
862 | gdb_assert (regnum != -1); | |
863 | memset (buf, 0, sizeof buf); | |
864 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
865 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
866 | } | |
867 | } | |
868 | } | |
869 | ||
870 | /* Allocate space for the arguments on the stack. */ | |
871 | sp -= num_elements * 8; | |
872 | ||
873 | /* The psABI says that "The end of the input argument area shall be | |
874 | aligned on a 16 byte boundary." */ | |
875 | sp &= ~0xf; | |
876 | ||
877 | /* Write out the arguments to the stack. */ | |
878 | for (i = 0; i < num_stack_args; i++) | |
879 | { | |
4991999e | 880 | struct type *type = value_type (stack_args[i]); |
d8de1ef7 | 881 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
849e9755 JB |
882 | int len = TYPE_LENGTH (type); |
883 | ||
884 | write_memory (sp + element * 8, valbuf, len); | |
885 | element += ((len + 7) / 8); | |
720aa428 MK |
886 | } |
887 | ||
888 | /* The psABI says that "For calls that may call functions that use | |
889 | varargs or stdargs (prototype-less calls or calls to functions | |
890 | containing ellipsis (...) in the declaration) %al is used as | |
891 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 892 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
893 | return sp; |
894 | } | |
895 | ||
c4f35dd8 | 896 | static CORE_ADDR |
7d9b040b | 897 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
898 | struct regcache *regcache, CORE_ADDR bp_addr, |
899 | int nargs, struct value **args, CORE_ADDR sp, | |
900 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 901 | { |
e17a4113 | 902 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d8de1ef7 | 903 | gdb_byte buf[8]; |
c4f35dd8 MK |
904 | |
905 | /* Pass arguments. */ | |
6470d250 | 906 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
907 | |
908 | /* Pass "hidden" argument". */ | |
909 | if (struct_return) | |
910 | { | |
e17a4113 | 911 | store_unsigned_integer (buf, 8, byte_order, struct_addr); |
bf4d6c1c | 912 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
913 | } |
914 | ||
915 | /* Store return address. */ | |
916 | sp -= 8; | |
e17a4113 | 917 | store_unsigned_integer (buf, 8, byte_order, bp_addr); |
c4f35dd8 MK |
918 | write_memory (sp, buf, 8); |
919 | ||
920 | /* Finally, update the stack pointer... */ | |
e17a4113 | 921 | store_unsigned_integer (buf, 8, byte_order, sp); |
90f90721 | 922 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
923 | |
924 | /* ...and fake a frame pointer. */ | |
90f90721 | 925 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 926 | |
3e210248 | 927 | return sp + 16; |
53e95fcf | 928 | } |
c4f35dd8 | 929 | \f |
35669430 DE |
930 | /* Displaced instruction handling. */ |
931 | ||
932 | /* A partially decoded instruction. | |
933 | This contains enough details for displaced stepping purposes. */ | |
934 | ||
935 | struct amd64_insn | |
936 | { | |
937 | /* The number of opcode bytes. */ | |
938 | int opcode_len; | |
939 | /* The offset of the rex prefix or -1 if not present. */ | |
940 | int rex_offset; | |
941 | /* The offset to the first opcode byte. */ | |
942 | int opcode_offset; | |
943 | /* The offset to the modrm byte or -1 if not present. */ | |
944 | int modrm_offset; | |
945 | ||
946 | /* The raw instruction. */ | |
947 | gdb_byte *raw_insn; | |
948 | }; | |
949 | ||
950 | struct displaced_step_closure | |
951 | { | |
952 | /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ | |
953 | int tmp_used; | |
954 | int tmp_regno; | |
955 | ULONGEST tmp_save; | |
956 | ||
957 | /* Details of the instruction. */ | |
958 | struct amd64_insn insn_details; | |
959 | ||
960 | /* Amount of space allocated to insn_buf. */ | |
961 | int max_len; | |
962 | ||
963 | /* The possibly modified insn. | |
964 | This is a variable-length field. */ | |
965 | gdb_byte insn_buf[1]; | |
966 | }; | |
967 | ||
968 | /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with | |
969 | ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, | |
970 | at which point delete these in favor of libopcodes' versions). */ | |
971 | ||
972 | static const unsigned char onebyte_has_modrm[256] = { | |
973 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
974 | /* ------------------------------- */ | |
975 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
976 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
977 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
978 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
979 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
980 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
981 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
982 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
983 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
984 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
985 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
986 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
987 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
988 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
989 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
990 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
991 | /* ------------------------------- */ | |
992 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
993 | }; | |
994 | ||
995 | static const unsigned char twobyte_has_modrm[256] = { | |
996 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
997 | /* ------------------------------- */ | |
998 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ | |
999 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ | |
1000 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ | |
1001 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ | |
1002 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ | |
1003 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ | |
1004 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
1005 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ | |
1006 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ | |
1007 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
1008 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ | |
1009 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ | |
1010 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ | |
1011 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ | |
1012 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ | |
1013 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ | |
1014 | /* ------------------------------- */ | |
1015 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1016 | }; | |
1017 | ||
1018 | static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); | |
1019 | ||
1020 | static int | |
1021 | rex_prefix_p (gdb_byte pfx) | |
1022 | { | |
1023 | return REX_PREFIX_P (pfx); | |
1024 | } | |
1025 | ||
1026 | /* Skip the legacy instruction prefixes in INSN. | |
1027 | We assume INSN is properly sentineled so we don't have to worry | |
1028 | about falling off the end of the buffer. */ | |
1029 | ||
1030 | static gdb_byte * | |
1903f0e6 | 1031 | amd64_skip_prefixes (gdb_byte *insn) |
35669430 DE |
1032 | { |
1033 | while (1) | |
1034 | { | |
1035 | switch (*insn) | |
1036 | { | |
1037 | case DATA_PREFIX_OPCODE: | |
1038 | case ADDR_PREFIX_OPCODE: | |
1039 | case CS_PREFIX_OPCODE: | |
1040 | case DS_PREFIX_OPCODE: | |
1041 | case ES_PREFIX_OPCODE: | |
1042 | case FS_PREFIX_OPCODE: | |
1043 | case GS_PREFIX_OPCODE: | |
1044 | case SS_PREFIX_OPCODE: | |
1045 | case LOCK_PREFIX_OPCODE: | |
1046 | case REPE_PREFIX_OPCODE: | |
1047 | case REPNE_PREFIX_OPCODE: | |
1048 | ++insn; | |
1049 | continue; | |
1050 | default: | |
1051 | break; | |
1052 | } | |
1053 | break; | |
1054 | } | |
1055 | ||
1056 | return insn; | |
1057 | } | |
1058 | ||
35669430 DE |
1059 | /* Return an integer register (other than RSP) that is unused as an input |
1060 | operand in INSN. | |
1061 | In order to not require adding a rex prefix if the insn doesn't already | |
1062 | have one, the result is restricted to RAX ... RDI, sans RSP. | |
1063 | The register numbering of the result follows architecture ordering, | |
1064 | e.g. RDI = 7. */ | |
1065 | ||
1066 | static int | |
1067 | amd64_get_unused_input_int_reg (const struct amd64_insn *details) | |
1068 | { | |
1069 | /* 1 bit for each reg */ | |
1070 | int used_regs_mask = 0; | |
1071 | ||
1072 | /* There can be at most 3 int regs used as inputs in an insn, and we have | |
1073 | 7 to choose from (RAX ... RDI, sans RSP). | |
1074 | This allows us to take a conservative approach and keep things simple. | |
1075 | E.g. By avoiding RAX, we don't have to specifically watch for opcodes | |
1076 | that implicitly specify RAX. */ | |
1077 | ||
1078 | /* Avoid RAX. */ | |
1079 | used_regs_mask |= 1 << EAX_REG_NUM; | |
1080 | /* Similarily avoid RDX, implicit operand in divides. */ | |
1081 | used_regs_mask |= 1 << EDX_REG_NUM; | |
1082 | /* Avoid RSP. */ | |
1083 | used_regs_mask |= 1 << ESP_REG_NUM; | |
1084 | ||
1085 | /* If the opcode is one byte long and there's no ModRM byte, | |
1086 | assume the opcode specifies a register. */ | |
1087 | if (details->opcode_len == 1 && details->modrm_offset == -1) | |
1088 | used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); | |
1089 | ||
1090 | /* Mark used regs in the modrm/sib bytes. */ | |
1091 | if (details->modrm_offset != -1) | |
1092 | { | |
1093 | int modrm = details->raw_insn[details->modrm_offset]; | |
1094 | int mod = MODRM_MOD_FIELD (modrm); | |
1095 | int reg = MODRM_REG_FIELD (modrm); | |
1096 | int rm = MODRM_RM_FIELD (modrm); | |
1097 | int have_sib = mod != 3 && rm == 4; | |
1098 | ||
1099 | /* Assume the reg field of the modrm byte specifies a register. */ | |
1100 | used_regs_mask |= 1 << reg; | |
1101 | ||
1102 | if (have_sib) | |
1103 | { | |
1104 | int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); | |
d48ebb5b | 1105 | int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); |
35669430 | 1106 | used_regs_mask |= 1 << base; |
d48ebb5b | 1107 | used_regs_mask |= 1 << idx; |
35669430 DE |
1108 | } |
1109 | else | |
1110 | { | |
1111 | used_regs_mask |= 1 << rm; | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | gdb_assert (used_regs_mask < 256); | |
1116 | gdb_assert (used_regs_mask != 255); | |
1117 | ||
1118 | /* Finally, find a free reg. */ | |
1119 | { | |
1120 | int i; | |
1121 | ||
1122 | for (i = 0; i < 8; ++i) | |
1123 | { | |
1124 | if (! (used_regs_mask & (1 << i))) | |
1125 | return i; | |
1126 | } | |
1127 | ||
1128 | /* We shouldn't get here. */ | |
1129 | internal_error (__FILE__, __LINE__, _("unable to find free reg")); | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | /* Extract the details of INSN that we need. */ | |
1134 | ||
1135 | static void | |
1136 | amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) | |
1137 | { | |
1138 | gdb_byte *start = insn; | |
1139 | int need_modrm; | |
1140 | ||
1141 | details->raw_insn = insn; | |
1142 | ||
1143 | details->opcode_len = -1; | |
1144 | details->rex_offset = -1; | |
1145 | details->opcode_offset = -1; | |
1146 | details->modrm_offset = -1; | |
1147 | ||
1148 | /* Skip legacy instruction prefixes. */ | |
1903f0e6 | 1149 | insn = amd64_skip_prefixes (insn); |
35669430 DE |
1150 | |
1151 | /* Skip REX instruction prefix. */ | |
1152 | if (rex_prefix_p (*insn)) | |
1153 | { | |
1154 | details->rex_offset = insn - start; | |
1155 | ++insn; | |
1156 | } | |
1157 | ||
1158 | details->opcode_offset = insn - start; | |
1159 | ||
1160 | if (*insn == TWO_BYTE_OPCODE_ESCAPE) | |
1161 | { | |
1162 | /* Two or three-byte opcode. */ | |
1163 | ++insn; | |
1164 | need_modrm = twobyte_has_modrm[*insn]; | |
1165 | ||
1166 | /* Check for three-byte opcode. */ | |
1903f0e6 | 1167 | switch (*insn) |
35669430 | 1168 | { |
1903f0e6 DE |
1169 | case 0x24: |
1170 | case 0x25: | |
1171 | case 0x38: | |
1172 | case 0x3a: | |
1173 | case 0x7a: | |
1174 | case 0x7b: | |
35669430 DE |
1175 | ++insn; |
1176 | details->opcode_len = 3; | |
1903f0e6 DE |
1177 | break; |
1178 | default: | |
1179 | details->opcode_len = 2; | |
1180 | break; | |
35669430 | 1181 | } |
35669430 DE |
1182 | } |
1183 | else | |
1184 | { | |
1185 | /* One-byte opcode. */ | |
1186 | need_modrm = onebyte_has_modrm[*insn]; | |
1187 | details->opcode_len = 1; | |
1188 | } | |
1189 | ||
1190 | if (need_modrm) | |
1191 | { | |
1192 | ++insn; | |
1193 | details->modrm_offset = insn - start; | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | /* Update %rip-relative addressing in INSN. | |
1198 | ||
1199 | %rip-relative addressing only uses a 32-bit displacement. | |
1200 | 32 bits is not enough to be guaranteed to cover the distance between where | |
1201 | the real instruction is and where its copy is. | |
1202 | Convert the insn to use base+disp addressing. | |
1203 | We set base = pc + insn_length so we can leave disp unchanged. */ | |
c4f35dd8 | 1204 | |
35669430 DE |
1205 | static void |
1206 | fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, | |
1207 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) | |
1208 | { | |
e17a4113 | 1209 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
35669430 DE |
1210 | const struct amd64_insn *insn_details = &dsc->insn_details; |
1211 | int modrm_offset = insn_details->modrm_offset; | |
1212 | gdb_byte *insn = insn_details->raw_insn + modrm_offset; | |
1213 | CORE_ADDR rip_base; | |
1214 | int32_t disp; | |
1215 | int insn_length; | |
1216 | int arch_tmp_regno, tmp_regno; | |
1217 | ULONGEST orig_value; | |
1218 | ||
1219 | /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ | |
1220 | ++insn; | |
1221 | ||
1222 | /* Compute the rip-relative address. */ | |
e17a4113 | 1223 | disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); |
eda5a4d7 PA |
1224 | insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, |
1225 | dsc->max_len, from); | |
35669430 DE |
1226 | rip_base = from + insn_length; |
1227 | ||
1228 | /* We need a register to hold the address. | |
1229 | Pick one not used in the insn. | |
1230 | NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ | |
1231 | arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); | |
1232 | tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); | |
1233 | ||
1234 | /* REX.B should be unset as we were using rip-relative addressing, | |
1235 | but ensure it's unset anyway, tmp_regno is not r8-r15. */ | |
1236 | if (insn_details->rex_offset != -1) | |
1237 | dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; | |
1238 | ||
1239 | regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); | |
1240 | dsc->tmp_regno = tmp_regno; | |
1241 | dsc->tmp_save = orig_value; | |
1242 | dsc->tmp_used = 1; | |
1243 | ||
1244 | /* Convert the ModRM field to be base+disp. */ | |
1245 | dsc->insn_buf[modrm_offset] &= ~0xc7; | |
1246 | dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; | |
1247 | ||
1248 | regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); | |
1249 | ||
1250 | if (debug_displaced) | |
1251 | fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" | |
5af949e3 UW |
1252 | "displaced: using temp reg %d, old value %s, new value %s\n", |
1253 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), | |
1254 | paddress (gdbarch, rip_base)); | |
35669430 DE |
1255 | } |
1256 | ||
1257 | static void | |
1258 | fixup_displaced_copy (struct gdbarch *gdbarch, | |
1259 | struct displaced_step_closure *dsc, | |
1260 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) | |
1261 | { | |
1262 | const struct amd64_insn *details = &dsc->insn_details; | |
1263 | ||
1264 | if (details->modrm_offset != -1) | |
1265 | { | |
1266 | gdb_byte modrm = details->raw_insn[details->modrm_offset]; | |
1267 | ||
1268 | if ((modrm & 0xc7) == 0x05) | |
1269 | { | |
1270 | /* The insn uses rip-relative addressing. | |
1271 | Deal with it. */ | |
1272 | fixup_riprel (gdbarch, dsc, from, to, regs); | |
1273 | } | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | struct displaced_step_closure * | |
1278 | amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
1279 | CORE_ADDR from, CORE_ADDR to, | |
1280 | struct regcache *regs) | |
1281 | { | |
1282 | int len = gdbarch_max_insn_length (gdbarch); | |
741e63d7 | 1283 | /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to |
35669430 DE |
1284 | continually watch for running off the end of the buffer. */ |
1285 | int fixup_sentinel_space = len; | |
1286 | struct displaced_step_closure *dsc = | |
1287 | xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); | |
1288 | gdb_byte *buf = &dsc->insn_buf[0]; | |
1289 | struct amd64_insn *details = &dsc->insn_details; | |
1290 | ||
1291 | dsc->tmp_used = 0; | |
1292 | dsc->max_len = len + fixup_sentinel_space; | |
1293 | ||
1294 | read_memory (from, buf, len); | |
1295 | ||
1296 | /* Set up the sentinel space so we don't have to worry about running | |
1297 | off the end of the buffer. An excessive number of leading prefixes | |
1298 | could otherwise cause this. */ | |
1299 | memset (buf + len, 0, fixup_sentinel_space); | |
1300 | ||
1301 | amd64_get_insn_details (buf, details); | |
1302 | ||
1303 | /* GDB may get control back after the insn after the syscall. | |
1304 | Presumably this is a kernel bug. | |
1305 | If this is a syscall, make sure there's a nop afterwards. */ | |
1306 | { | |
1307 | int syscall_length; | |
1308 | ||
1309 | if (amd64_syscall_p (details, &syscall_length)) | |
1310 | buf[details->opcode_offset + syscall_length] = NOP_OPCODE; | |
1311 | } | |
1312 | ||
1313 | /* Modify the insn to cope with the address where it will be executed from. | |
1314 | In particular, handle any rip-relative addressing. */ | |
1315 | fixup_displaced_copy (gdbarch, dsc, from, to, regs); | |
1316 | ||
1317 | write_memory (to, buf, len); | |
1318 | ||
1319 | if (debug_displaced) | |
1320 | { | |
5af949e3 UW |
1321 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", |
1322 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
35669430 DE |
1323 | displaced_step_dump_bytes (gdb_stdlog, buf, len); |
1324 | } | |
1325 | ||
1326 | return dsc; | |
1327 | } | |
1328 | ||
1329 | static int | |
1330 | amd64_absolute_jmp_p (const struct amd64_insn *details) | |
1331 | { | |
1332 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1333 | ||
1334 | if (insn[0] == 0xff) | |
1335 | { | |
1336 | /* jump near, absolute indirect (/4) */ | |
1337 | if ((insn[1] & 0x38) == 0x20) | |
1338 | return 1; | |
1339 | ||
1340 | /* jump far, absolute indirect (/5) */ | |
1341 | if ((insn[1] & 0x38) == 0x28) | |
1342 | return 1; | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | static int | |
1349 | amd64_absolute_call_p (const struct amd64_insn *details) | |
1350 | { | |
1351 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1352 | ||
1353 | if (insn[0] == 0xff) | |
1354 | { | |
1355 | /* Call near, absolute indirect (/2) */ | |
1356 | if ((insn[1] & 0x38) == 0x10) | |
1357 | return 1; | |
1358 | ||
1359 | /* Call far, absolute indirect (/3) */ | |
1360 | if ((insn[1] & 0x38) == 0x18) | |
1361 | return 1; | |
1362 | } | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | static int | |
1368 | amd64_ret_p (const struct amd64_insn *details) | |
1369 | { | |
1370 | /* NOTE: gcc can emit "repz ; ret". */ | |
1371 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1372 | ||
1373 | switch (insn[0]) | |
1374 | { | |
1375 | case 0xc2: /* ret near, pop N bytes */ | |
1376 | case 0xc3: /* ret near */ | |
1377 | case 0xca: /* ret far, pop N bytes */ | |
1378 | case 0xcb: /* ret far */ | |
1379 | case 0xcf: /* iret */ | |
1380 | return 1; | |
1381 | ||
1382 | default: | |
1383 | return 0; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | static int | |
1388 | amd64_call_p (const struct amd64_insn *details) | |
1389 | { | |
1390 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1391 | ||
1392 | if (amd64_absolute_call_p (details)) | |
1393 | return 1; | |
1394 | ||
1395 | /* call near, relative */ | |
1396 | if (insn[0] == 0xe8) | |
1397 | return 1; | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
35669430 DE |
1402 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
1403 | length in bytes. Otherwise, return zero. */ | |
1404 | ||
1405 | static int | |
1406 | amd64_syscall_p (const struct amd64_insn *details, int *lengthp) | |
1407 | { | |
1408 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1409 | ||
1410 | if (insn[0] == 0x0f && insn[1] == 0x05) | |
1411 | { | |
1412 | *lengthp = 2; | |
1413 | return 1; | |
1414 | } | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | /* Fix up the state of registers and memory after having single-stepped | |
1420 | a displaced instruction. */ | |
1421 | ||
1422 | void | |
1423 | amd64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1424 | struct displaced_step_closure *dsc, | |
1425 | CORE_ADDR from, CORE_ADDR to, | |
1426 | struct regcache *regs) | |
1427 | { | |
e17a4113 | 1428 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
35669430 DE |
1429 | /* The offset we applied to the instruction's address. */ |
1430 | ULONGEST insn_offset = to - from; | |
1431 | gdb_byte *insn = dsc->insn_buf; | |
1432 | const struct amd64_insn *insn_details = &dsc->insn_details; | |
1433 | ||
1434 | if (debug_displaced) | |
1435 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 1436 | "displaced: fixup (%s, %s), " |
35669430 | 1437 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
1438 | paddress (gdbarch, from), paddress (gdbarch, to), |
1439 | insn[0], insn[1]); | |
35669430 DE |
1440 | |
1441 | /* If we used a tmp reg, restore it. */ | |
1442 | ||
1443 | if (dsc->tmp_used) | |
1444 | { | |
1445 | if (debug_displaced) | |
5af949e3 UW |
1446 | fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", |
1447 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); | |
35669430 DE |
1448 | regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); |
1449 | } | |
1450 | ||
1451 | /* The list of issues to contend with here is taken from | |
1452 | resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. | |
1453 | Yay for Free Software! */ | |
1454 | ||
1455 | /* Relocate the %rip back to the program's instruction stream, | |
1456 | if necessary. */ | |
1457 | ||
1458 | /* Except in the case of absolute or indirect jump or call | |
1459 | instructions, or a return instruction, the new rip is relative to | |
1460 | the displaced instruction; make it relative to the original insn. | |
1461 | Well, signal handler returns don't need relocation either, but we use the | |
1462 | value of %rip to recognize those; see below. */ | |
1463 | if (! amd64_absolute_jmp_p (insn_details) | |
1464 | && ! amd64_absolute_call_p (insn_details) | |
1465 | && ! amd64_ret_p (insn_details)) | |
1466 | { | |
1467 | ULONGEST orig_rip; | |
1468 | int insn_len; | |
1469 | ||
1470 | regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); | |
1471 | ||
1472 | /* A signal trampoline system call changes the %rip, resuming | |
1473 | execution of the main program after the signal handler has | |
1474 | returned. That makes them like 'return' instructions; we | |
1475 | shouldn't relocate %rip. | |
1476 | ||
1477 | But most system calls don't, and we do need to relocate %rip. | |
1478 | ||
1479 | Our heuristic for distinguishing these cases: if stepping | |
1480 | over the system call instruction left control directly after | |
1481 | the instruction, the we relocate --- control almost certainly | |
1482 | doesn't belong in the displaced copy. Otherwise, we assume | |
1483 | the instruction has put control where it belongs, and leave | |
1484 | it unrelocated. Goodness help us if there are PC-relative | |
1485 | system calls. */ | |
1486 | if (amd64_syscall_p (insn_details, &insn_len) | |
1487 | && orig_rip != to + insn_len | |
1488 | /* GDB can get control back after the insn after the syscall. | |
1489 | Presumably this is a kernel bug. | |
1490 | Fixup ensures its a nop, we add one to the length for it. */ | |
1491 | && orig_rip != to + insn_len + 1) | |
1492 | { | |
1493 | if (debug_displaced) | |
1494 | fprintf_unfiltered (gdb_stdlog, | |
1495 | "displaced: syscall changed %%rip; " | |
1496 | "not relocating\n"); | |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | ULONGEST rip = orig_rip - insn_offset; | |
1501 | ||
1903f0e6 DE |
1502 | /* If we just stepped over a breakpoint insn, we don't backup |
1503 | the pc on purpose; this is to match behaviour without | |
1504 | stepping. */ | |
35669430 DE |
1505 | |
1506 | regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); | |
1507 | ||
1508 | if (debug_displaced) | |
1509 | fprintf_unfiltered (gdb_stdlog, | |
1510 | "displaced: " | |
5af949e3 UW |
1511 | "relocated %%rip from %s to %s\n", |
1512 | paddress (gdbarch, orig_rip), | |
1513 | paddress (gdbarch, rip)); | |
35669430 DE |
1514 | } |
1515 | } | |
1516 | ||
1517 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
1518 | pushed value, and should be cleared. We'll leave this for later, | |
1519 | since GDB already messes up the TF flag when stepping over a | |
1520 | pushfl. */ | |
1521 | ||
1522 | /* If the instruction was a call, the return address now atop the | |
1523 | stack is the address following the copied instruction. We need | |
1524 | to make it the address following the original instruction. */ | |
1525 | if (amd64_call_p (insn_details)) | |
1526 | { | |
1527 | ULONGEST rsp; | |
1528 | ULONGEST retaddr; | |
1529 | const ULONGEST retaddr_len = 8; | |
1530 | ||
1531 | regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); | |
e17a4113 | 1532 | retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); |
35669430 | 1533 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 1534 | write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); |
35669430 DE |
1535 | |
1536 | if (debug_displaced) | |
1537 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
1538 | "displaced: relocated return addr at %s " |
1539 | "to %s\n", | |
1540 | paddress (gdbarch, rsp), | |
1541 | paddress (gdbarch, retaddr)); | |
35669430 DE |
1542 | } |
1543 | } | |
dde08ee1 PA |
1544 | |
1545 | /* If the instruction INSN uses RIP-relative addressing, return the | |
1546 | offset into the raw INSN where the displacement to be adjusted is | |
1547 | found. Returns 0 if the instruction doesn't use RIP-relative | |
1548 | addressing. */ | |
1549 | ||
1550 | static int | |
1551 | rip_relative_offset (struct amd64_insn *insn) | |
1552 | { | |
1553 | if (insn->modrm_offset != -1) | |
1554 | { | |
1555 | gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; | |
1556 | ||
1557 | if ((modrm & 0xc7) == 0x05) | |
1558 | { | |
1559 | /* The displacement is found right after the ModRM byte. */ | |
1560 | return insn->modrm_offset + 1; | |
1561 | } | |
1562 | } | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | static void | |
1568 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
1569 | { | |
1570 | target_write_memory (*to, buf, len); | |
1571 | *to += len; | |
1572 | } | |
1573 | ||
60965737 | 1574 | static void |
dde08ee1 PA |
1575 | amd64_relocate_instruction (struct gdbarch *gdbarch, |
1576 | CORE_ADDR *to, CORE_ADDR oldloc) | |
1577 | { | |
1578 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1579 | int len = gdbarch_max_insn_length (gdbarch); | |
1580 | /* Extra space for sentinels. */ | |
1581 | int fixup_sentinel_space = len; | |
1582 | gdb_byte *buf = xmalloc (len + fixup_sentinel_space); | |
1583 | struct amd64_insn insn_details; | |
1584 | int offset = 0; | |
1585 | LONGEST rel32, newrel; | |
1586 | gdb_byte *insn; | |
1587 | int insn_length; | |
1588 | ||
1589 | read_memory (oldloc, buf, len); | |
1590 | ||
1591 | /* Set up the sentinel space so we don't have to worry about running | |
1592 | off the end of the buffer. An excessive number of leading prefixes | |
1593 | could otherwise cause this. */ | |
1594 | memset (buf + len, 0, fixup_sentinel_space); | |
1595 | ||
1596 | insn = buf; | |
1597 | amd64_get_insn_details (insn, &insn_details); | |
1598 | ||
1599 | insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); | |
1600 | ||
1601 | /* Skip legacy instruction prefixes. */ | |
1602 | insn = amd64_skip_prefixes (insn); | |
1603 | ||
1604 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
1605 | the address pushed being the location where the original call in | |
1606 | the user program would return to. */ | |
1607 | if (insn[0] == 0xe8) | |
1608 | { | |
1609 | gdb_byte push_buf[16]; | |
1610 | unsigned int ret_addr; | |
1611 | ||
1612 | /* Where "ret" in the original code will return to. */ | |
1613 | ret_addr = oldloc + insn_length; | |
0963b4bd | 1614 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 1615 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
1616 | /* Push the push. */ |
1617 | append_insns (to, 5, push_buf); | |
1618 | ||
1619 | /* Convert the relative call to a relative jump. */ | |
1620 | insn[0] = 0xe9; | |
1621 | ||
1622 | /* Adjust the destination offset. */ | |
1623 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1624 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1625 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1626 | ||
1627 | if (debug_displaced) | |
1628 | fprintf_unfiltered (gdb_stdlog, | |
1629 | "Adjusted insn rel32=%s at %s to" | |
1630 | " rel32=%s at %s\n", | |
1631 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1632 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1633 | |
1634 | /* Write the adjusted jump into its displaced location. */ | |
1635 | append_insns (to, 5, insn); | |
1636 | return; | |
1637 | } | |
1638 | ||
1639 | offset = rip_relative_offset (&insn_details); | |
1640 | if (!offset) | |
1641 | { | |
1642 | /* Adjust jumps with 32-bit relative addresses. Calls are | |
1643 | already handled above. */ | |
1644 | if (insn[0] == 0xe9) | |
1645 | offset = 1; | |
1646 | /* Adjust conditional jumps. */ | |
1647 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1648 | offset = 2; | |
1649 | } | |
1650 | ||
1651 | if (offset) | |
1652 | { | |
1653 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1654 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1655 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1656 | if (debug_displaced) |
1657 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1658 | "Adjusted insn rel32=%s at %s to" |
1659 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1660 | hex_string (rel32), paddress (gdbarch, oldloc), |
1661 | hex_string (newrel), paddress (gdbarch, *to)); | |
1662 | } | |
1663 | ||
1664 | /* Write the adjusted instruction into its displaced location. */ | |
1665 | append_insns (to, insn_length, buf); | |
1666 | } | |
1667 | ||
35669430 | 1668 | \f |
c4f35dd8 | 1669 | /* The maximum number of saved registers. This should include %rip. */ |
90f90721 | 1670 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 1671 | |
e53bef9f | 1672 | struct amd64_frame_cache |
c4f35dd8 MK |
1673 | { |
1674 | /* Base address. */ | |
1675 | CORE_ADDR base; | |
8fbca658 | 1676 | int base_p; |
c4f35dd8 MK |
1677 | CORE_ADDR sp_offset; |
1678 | CORE_ADDR pc; | |
1679 | ||
1680 | /* Saved registers. */ | |
e53bef9f | 1681 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 | 1682 | CORE_ADDR saved_sp; |
e0c62198 | 1683 | int saved_sp_reg; |
c4f35dd8 MK |
1684 | |
1685 | /* Do we have a frame? */ | |
1686 | int frameless_p; | |
1687 | }; | |
8dda9770 | 1688 | |
d2449ee8 | 1689 | /* Initialize a frame cache. */ |
c4f35dd8 | 1690 | |
d2449ee8 DJ |
1691 | static void |
1692 | amd64_init_frame_cache (struct amd64_frame_cache *cache) | |
8dda9770 | 1693 | { |
c4f35dd8 MK |
1694 | int i; |
1695 | ||
c4f35dd8 MK |
1696 | /* Base address. */ |
1697 | cache->base = 0; | |
8fbca658 | 1698 | cache->base_p = 0; |
c4f35dd8 MK |
1699 | cache->sp_offset = -8; |
1700 | cache->pc = 0; | |
1701 | ||
1702 | /* Saved registers. We initialize these to -1 since zero is a valid | |
bba66b87 DE |
1703 | offset (that's where %rbp is supposed to be stored). |
1704 | The values start out as being offsets, and are later converted to | |
1705 | addresses (at which point -1 is interpreted as an address, still meaning | |
1706 | "invalid"). */ | |
e53bef9f | 1707 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
1708 | cache->saved_regs[i] = -1; |
1709 | cache->saved_sp = 0; | |
e0c62198 | 1710 | cache->saved_sp_reg = -1; |
c4f35dd8 MK |
1711 | |
1712 | /* Frameless until proven otherwise. */ | |
1713 | cache->frameless_p = 1; | |
d2449ee8 | 1714 | } |
c4f35dd8 | 1715 | |
d2449ee8 DJ |
1716 | /* Allocate and initialize a frame cache. */ |
1717 | ||
1718 | static struct amd64_frame_cache * | |
1719 | amd64_alloc_frame_cache (void) | |
1720 | { | |
1721 | struct amd64_frame_cache *cache; | |
1722 | ||
1723 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); | |
1724 | amd64_init_frame_cache (cache); | |
c4f35dd8 | 1725 | return cache; |
8dda9770 | 1726 | } |
53e95fcf | 1727 | |
e0c62198 L |
1728 | /* GCC 4.4 and later, can put code in the prologue to realign the |
1729 | stack pointer. Check whether PC points to such code, and update | |
1730 | CACHE accordingly. Return the first instruction after the code | |
1731 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1732 | recognize the code, return PC. */ | |
1733 | ||
1734 | static CORE_ADDR | |
1735 | amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1736 | struct amd64_frame_cache *cache) | |
1737 | { | |
1738 | /* There are 2 code sequences to re-align stack before the frame | |
1739 | gets set up: | |
1740 | ||
1741 | 1. Use a caller-saved saved register: | |
1742 | ||
1743 | leaq 8(%rsp), %reg | |
1744 | andq $-XXX, %rsp | |
1745 | pushq -8(%reg) | |
1746 | ||
1747 | 2. Use a callee-saved saved register: | |
1748 | ||
1749 | pushq %reg | |
1750 | leaq 16(%rsp), %reg | |
1751 | andq $-XXX, %rsp | |
1752 | pushq -8(%reg) | |
1753 | ||
1754 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
1755 | ||
1756 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp | |
1757 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
1758 | */ | |
1759 | ||
1760 | gdb_byte buf[18]; | |
1761 | int reg, r; | |
1762 | int offset, offset_and; | |
e0c62198 | 1763 | |
bae8a07a | 1764 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1765 | return pc; |
1766 | ||
1767 | /* Check caller-saved saved register. The first instruction has | |
1768 | to be "leaq 8(%rsp), %reg". */ | |
1769 | if ((buf[0] & 0xfb) == 0x48 | |
1770 | && buf[1] == 0x8d | |
1771 | && buf[3] == 0x24 | |
1772 | && buf[4] == 0x8) | |
1773 | { | |
1774 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1775 | if ((buf[2] & 0xc7) != 0x44) | |
1776 | return pc; | |
1777 | ||
1778 | /* REG has register number. */ | |
1779 | reg = (buf[2] >> 3) & 7; | |
1780 | ||
1781 | /* Check the REX.R bit. */ | |
1782 | if (buf[0] == 0x4c) | |
1783 | reg += 8; | |
1784 | ||
1785 | offset = 5; | |
1786 | } | |
1787 | else | |
1788 | { | |
1789 | /* Check callee-saved saved register. The first instruction | |
1790 | has to be "pushq %reg". */ | |
1791 | reg = 0; | |
1792 | if ((buf[0] & 0xf8) == 0x50) | |
1793 | offset = 0; | |
1794 | else if ((buf[0] & 0xf6) == 0x40 | |
1795 | && (buf[1] & 0xf8) == 0x50) | |
1796 | { | |
1797 | /* Check the REX.B bit. */ | |
1798 | if ((buf[0] & 1) != 0) | |
1799 | reg = 8; | |
1800 | ||
1801 | offset = 1; | |
1802 | } | |
1803 | else | |
1804 | return pc; | |
1805 | ||
1806 | /* Get register. */ | |
1807 | reg += buf[offset] & 0x7; | |
1808 | ||
1809 | offset++; | |
1810 | ||
1811 | /* The next instruction has to be "leaq 16(%rsp), %reg". */ | |
1812 | if ((buf[offset] & 0xfb) != 0x48 | |
1813 | || buf[offset + 1] != 0x8d | |
1814 | || buf[offset + 3] != 0x24 | |
1815 | || buf[offset + 4] != 0x10) | |
1816 | return pc; | |
1817 | ||
1818 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1819 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
1820 | return pc; | |
1821 | ||
1822 | /* REG has register number. */ | |
1823 | r = (buf[offset + 2] >> 3) & 7; | |
1824 | ||
1825 | /* Check the REX.R bit. */ | |
1826 | if (buf[offset] == 0x4c) | |
1827 | r += 8; | |
1828 | ||
1829 | /* Registers in pushq and leaq have to be the same. */ | |
1830 | if (reg != r) | |
1831 | return pc; | |
1832 | ||
1833 | offset += 5; | |
1834 | } | |
1835 | ||
1836 | /* Rigister can't be %rsp nor %rbp. */ | |
1837 | if (reg == 4 || reg == 5) | |
1838 | return pc; | |
1839 | ||
1840 | /* The next instruction has to be "andq $-XXX, %rsp". */ | |
1841 | if (buf[offset] != 0x48 | |
1842 | || buf[offset + 2] != 0xe4 | |
1843 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
1844 | return pc; | |
1845 | ||
1846 | offset_and = offset; | |
1847 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
1848 | ||
1849 | /* The next instruction has to be "pushq -8(%reg)". */ | |
1850 | r = 0; | |
1851 | if (buf[offset] == 0xff) | |
1852 | offset++; | |
1853 | else if ((buf[offset] & 0xf6) == 0x40 | |
1854 | && buf[offset + 1] == 0xff) | |
1855 | { | |
1856 | /* Check the REX.B bit. */ | |
1857 | if ((buf[offset] & 0x1) != 0) | |
1858 | r = 8; | |
1859 | offset += 2; | |
1860 | } | |
1861 | else | |
1862 | return pc; | |
1863 | ||
1864 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
1865 | 01. */ | |
1866 | if (buf[offset + 1] != 0xf8 | |
1867 | || (buf[offset] & 0xf8) != 0x70) | |
1868 | return pc; | |
1869 | ||
1870 | /* R/M has register. */ | |
1871 | r += buf[offset] & 7; | |
1872 | ||
1873 | /* Registers in leaq and pushq have to be the same. */ | |
1874 | if (reg != r) | |
1875 | return pc; | |
1876 | ||
1877 | if (current_pc > pc + offset_and) | |
35669430 | 1878 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); |
e0c62198 L |
1879 | |
1880 | return min (pc + offset + 2, current_pc); | |
1881 | } | |
1882 | ||
ac142d96 L |
1883 | /* Similar to amd64_analyze_stack_align for x32. */ |
1884 | ||
1885 | static CORE_ADDR | |
1886 | amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1887 | struct amd64_frame_cache *cache) | |
1888 | { | |
1889 | /* There are 2 code sequences to re-align stack before the frame | |
1890 | gets set up: | |
1891 | ||
1892 | 1. Use a caller-saved saved register: | |
1893 | ||
1894 | leaq 8(%rsp), %reg | |
1895 | andq $-XXX, %rsp | |
1896 | pushq -8(%reg) | |
1897 | ||
1898 | or | |
1899 | ||
1900 | [addr32] leal 8(%rsp), %reg | |
1901 | andl $-XXX, %esp | |
1902 | [addr32] pushq -8(%reg) | |
1903 | ||
1904 | 2. Use a callee-saved saved register: | |
1905 | ||
1906 | pushq %reg | |
1907 | leaq 16(%rsp), %reg | |
1908 | andq $-XXX, %rsp | |
1909 | pushq -8(%reg) | |
1910 | ||
1911 | or | |
1912 | ||
1913 | pushq %reg | |
1914 | [addr32] leal 16(%rsp), %reg | |
1915 | andl $-XXX, %esp | |
1916 | [addr32] pushq -8(%reg) | |
1917 | ||
1918 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
1919 | ||
1920 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp | |
1921 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
1922 | ||
1923 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1924 | ||
1925 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1926 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1927 | */ | |
1928 | ||
1929 | gdb_byte buf[19]; | |
1930 | int reg, r; | |
1931 | int offset, offset_and; | |
1932 | ||
1933 | if (target_read_memory (pc, buf, sizeof buf)) | |
1934 | return pc; | |
1935 | ||
1936 | /* Skip optional addr32 prefix. */ | |
1937 | offset = buf[0] == 0x67 ? 1 : 0; | |
1938 | ||
1939 | /* Check caller-saved saved register. The first instruction has | |
1940 | to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ | |
1941 | if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) | |
1942 | && buf[offset + 1] == 0x8d | |
1943 | && buf[offset + 3] == 0x24 | |
1944 | && buf[offset + 4] == 0x8) | |
1945 | { | |
1946 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1947 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
1948 | return pc; | |
1949 | ||
1950 | /* REG has register number. */ | |
1951 | reg = (buf[offset + 2] >> 3) & 7; | |
1952 | ||
1953 | /* Check the REX.R bit. */ | |
1954 | if ((buf[offset] & 0x4) != 0) | |
1955 | reg += 8; | |
1956 | ||
1957 | offset += 5; | |
1958 | } | |
1959 | else | |
1960 | { | |
1961 | /* Check callee-saved saved register. The first instruction | |
1962 | has to be "pushq %reg". */ | |
1963 | reg = 0; | |
1964 | if ((buf[offset] & 0xf6) == 0x40 | |
1965 | && (buf[offset + 1] & 0xf8) == 0x50) | |
1966 | { | |
1967 | /* Check the REX.B bit. */ | |
1968 | if ((buf[offset] & 1) != 0) | |
1969 | reg = 8; | |
1970 | ||
1971 | offset += 1; | |
1972 | } | |
1973 | else if ((buf[offset] & 0xf8) != 0x50) | |
1974 | return pc; | |
1975 | ||
1976 | /* Get register. */ | |
1977 | reg += buf[offset] & 0x7; | |
1978 | ||
1979 | offset++; | |
1980 | ||
1981 | /* Skip optional addr32 prefix. */ | |
1982 | if (buf[offset] == 0x67) | |
1983 | offset++; | |
1984 | ||
1985 | /* The next instruction has to be "leaq 16(%rsp), %reg" or | |
1986 | "leal 16(%rsp), %reg". */ | |
1987 | if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) | |
1988 | || buf[offset + 1] != 0x8d | |
1989 | || buf[offset + 3] != 0x24 | |
1990 | || buf[offset + 4] != 0x10) | |
1991 | return pc; | |
1992 | ||
1993 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1994 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
1995 | return pc; | |
1996 | ||
1997 | /* REG has register number. */ | |
1998 | r = (buf[offset + 2] >> 3) & 7; | |
1999 | ||
2000 | /* Check the REX.R bit. */ | |
2001 | if ((buf[offset] & 0x4) != 0) | |
2002 | r += 8; | |
2003 | ||
2004 | /* Registers in pushq and leaq have to be the same. */ | |
2005 | if (reg != r) | |
2006 | return pc; | |
2007 | ||
2008 | offset += 5; | |
2009 | } | |
2010 | ||
2011 | /* Rigister can't be %rsp nor %rbp. */ | |
2012 | if (reg == 4 || reg == 5) | |
2013 | return pc; | |
2014 | ||
2015 | /* The next instruction may be "andq $-XXX, %rsp" or | |
2016 | "andl $-XXX, %esp". */ | |
2017 | if (buf[offset] != 0x48) | |
2018 | offset--; | |
2019 | ||
2020 | if (buf[offset + 2] != 0xe4 | |
2021 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
2022 | return pc; | |
2023 | ||
2024 | offset_and = offset; | |
2025 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
2026 | ||
2027 | /* Skip optional addr32 prefix. */ | |
2028 | if (buf[offset] == 0x67) | |
2029 | offset++; | |
2030 | ||
2031 | /* The next instruction has to be "pushq -8(%reg)". */ | |
2032 | r = 0; | |
2033 | if (buf[offset] == 0xff) | |
2034 | offset++; | |
2035 | else if ((buf[offset] & 0xf6) == 0x40 | |
2036 | && buf[offset + 1] == 0xff) | |
2037 | { | |
2038 | /* Check the REX.B bit. */ | |
2039 | if ((buf[offset] & 0x1) != 0) | |
2040 | r = 8; | |
2041 | offset += 2; | |
2042 | } | |
2043 | else | |
2044 | return pc; | |
2045 | ||
2046 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
2047 | 01. */ | |
2048 | if (buf[offset + 1] != 0xf8 | |
2049 | || (buf[offset] & 0xf8) != 0x70) | |
2050 | return pc; | |
2051 | ||
2052 | /* R/M has register. */ | |
2053 | r += buf[offset] & 7; | |
2054 | ||
2055 | /* Registers in leaq and pushq have to be the same. */ | |
2056 | if (reg != r) | |
2057 | return pc; | |
2058 | ||
2059 | if (current_pc > pc + offset_and) | |
2060 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); | |
2061 | ||
2062 | return min (pc + offset + 2, current_pc); | |
2063 | } | |
2064 | ||
c4f35dd8 MK |
2065 | /* Do a limited analysis of the prologue at PC and update CACHE |
2066 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
2067 | address where the analysis stopped. | |
2068 | ||
2069 | We will handle only functions beginning with: | |
2070 | ||
2071 | pushq %rbp 0x55 | |
50f1ae7b | 2072 | movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) |
c4f35dd8 | 2073 | |
649e6d92 MK |
2074 | or (for the X32 ABI): |
2075 | ||
2076 | pushq %rbp 0x55 | |
2077 | movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) | |
2078 | ||
2079 | Any function that doesn't start with one of these sequences will be | |
2080 | assumed to have no prologue and thus no valid frame pointer in | |
2081 | %rbp. */ | |
c4f35dd8 MK |
2082 | |
2083 | static CORE_ADDR | |
e17a4113 UW |
2084 | amd64_analyze_prologue (struct gdbarch *gdbarch, |
2085 | CORE_ADDR pc, CORE_ADDR current_pc, | |
e53bef9f | 2086 | struct amd64_frame_cache *cache) |
53e95fcf | 2087 | { |
e17a4113 | 2088 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
50f1ae7b DE |
2089 | /* There are two variations of movq %rsp, %rbp. */ |
2090 | static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; | |
2091 | static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; | |
649e6d92 MK |
2092 | /* Ditto for movl %esp, %ebp. */ |
2093 | static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; | |
2094 | static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; | |
2095 | ||
d8de1ef7 MK |
2096 | gdb_byte buf[3]; |
2097 | gdb_byte op; | |
c4f35dd8 MK |
2098 | |
2099 | if (current_pc <= pc) | |
2100 | return current_pc; | |
2101 | ||
ac142d96 L |
2102 | if (gdbarch_ptr_bit (gdbarch) == 32) |
2103 | pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); | |
2104 | else | |
2105 | pc = amd64_analyze_stack_align (pc, current_pc, cache); | |
e0c62198 | 2106 | |
bae8a07a | 2107 | op = read_code_unsigned_integer (pc, 1, byte_order); |
c4f35dd8 MK |
2108 | |
2109 | if (op == 0x55) /* pushq %rbp */ | |
2110 | { | |
2111 | /* Take into account that we've executed the `pushq %rbp' that | |
2112 | starts this instruction sequence. */ | |
90f90721 | 2113 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
2114 | cache->sp_offset += 8; |
2115 | ||
2116 | /* If that's all, return now. */ | |
2117 | if (current_pc <= pc + 1) | |
2118 | return current_pc; | |
2119 | ||
bae8a07a | 2120 | read_code (pc + 1, buf, 3); |
c4f35dd8 | 2121 | |
649e6d92 MK |
2122 | /* Check for `movq %rsp, %rbp'. */ |
2123 | if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 | |
2124 | || memcmp (buf, mov_rsp_rbp_2, 3) == 0) | |
2125 | { | |
2126 | /* OK, we actually have a frame. */ | |
2127 | cache->frameless_p = 0; | |
2128 | return pc + 4; | |
2129 | } | |
2130 | ||
2131 | /* For X32, also check for `movq %esp, %ebp'. */ | |
2132 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
2133 | { | |
2134 | if (memcmp (buf, mov_esp_ebp_1, 2) == 0 | |
2135 | || memcmp (buf, mov_esp_ebp_2, 2) == 0) | |
2136 | { | |
2137 | /* OK, we actually have a frame. */ | |
2138 | cache->frameless_p = 0; | |
2139 | return pc + 3; | |
2140 | } | |
2141 | } | |
2142 | ||
2143 | return pc + 1; | |
c4f35dd8 MK |
2144 | } |
2145 | ||
2146 | return pc; | |
53e95fcf JS |
2147 | } |
2148 | ||
df15bd07 JK |
2149 | /* Work around false termination of prologue - GCC PR debug/48827. |
2150 | ||
2151 | START_PC is the first instruction of a function, PC is its minimal already | |
2152 | determined advanced address. Function returns PC if it has nothing to do. | |
2153 | ||
2154 | 84 c0 test %al,%al | |
2155 | 74 23 je after | |
2156 | <-- here is 0 lines advance - the false prologue end marker. | |
2157 | 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) | |
2158 | 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) | |
2159 | 0f 29 55 90 movaps %xmm2,-0x70(%rbp) | |
2160 | 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) | |
2161 | 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) | |
2162 | 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) | |
2163 | 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) | |
2164 | 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) | |
2165 | after: */ | |
c4f35dd8 MK |
2166 | |
2167 | static CORE_ADDR | |
df15bd07 | 2168 | amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) |
53e95fcf | 2169 | { |
08711b9a JK |
2170 | struct symtab_and_line start_pc_sal, next_sal; |
2171 | gdb_byte buf[4 + 8 * 7]; | |
2172 | int offset, xmmreg; | |
c4f35dd8 | 2173 | |
08711b9a JK |
2174 | if (pc == start_pc) |
2175 | return pc; | |
2176 | ||
2177 | start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); | |
2178 | if (start_pc_sal.symtab == NULL | |
df15bd07 | 2179 | || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6 |
08711b9a JK |
2180 | || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) |
2181 | return pc; | |
2182 | ||
2183 | next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); | |
2184 | if (next_sal.line != start_pc_sal.line) | |
2185 | return pc; | |
2186 | ||
2187 | /* START_PC can be from overlayed memory, ignored here. */ | |
bae8a07a | 2188 | if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) |
08711b9a JK |
2189 | return pc; |
2190 | ||
2191 | /* test %al,%al */ | |
2192 | if (buf[0] != 0x84 || buf[1] != 0xc0) | |
2193 | return pc; | |
2194 | /* je AFTER */ | |
2195 | if (buf[2] != 0x74) | |
2196 | return pc; | |
2197 | ||
2198 | offset = 4; | |
2199 | for (xmmreg = 0; xmmreg < 8; xmmreg++) | |
2200 | { | |
bede5f5f | 2201 | /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ |
08711b9a | 2202 | if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 |
bede5f5f | 2203 | || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) |
08711b9a JK |
2204 | return pc; |
2205 | ||
bede5f5f JK |
2206 | /* 0b01?????? */ |
2207 | if ((buf[offset + 2] & 0xc0) == 0x40) | |
08711b9a JK |
2208 | { |
2209 | /* 8-bit displacement. */ | |
2210 | offset += 4; | |
2211 | } | |
bede5f5f JK |
2212 | /* 0b10?????? */ |
2213 | else if ((buf[offset + 2] & 0xc0) == 0x80) | |
08711b9a JK |
2214 | { |
2215 | /* 32-bit displacement. */ | |
2216 | offset += 7; | |
2217 | } | |
2218 | else | |
2219 | return pc; | |
2220 | } | |
2221 | ||
2222 | /* je AFTER */ | |
2223 | if (offset - 4 != buf[3]) | |
2224 | return pc; | |
2225 | ||
2226 | return next_sal.end; | |
53e95fcf | 2227 | } |
df15bd07 JK |
2228 | |
2229 | /* Return PC of first real instruction. */ | |
2230 | ||
2231 | static CORE_ADDR | |
2232 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) | |
2233 | { | |
2234 | struct amd64_frame_cache cache; | |
2235 | CORE_ADDR pc; | |
56bf0743 KB |
2236 | CORE_ADDR func_addr; |
2237 | ||
2238 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
2239 | { | |
2240 | CORE_ADDR post_prologue_pc | |
2241 | = skip_prologue_using_sal (gdbarch, func_addr); | |
2242 | struct symtab *s = find_pc_symtab (func_addr); | |
2243 | ||
2244 | /* Clang always emits a line note before the prologue and another | |
2245 | one after. We trust clang to emit usable line notes. */ | |
2246 | if (post_prologue_pc | |
2247 | && (s != NULL | |
2248 | && s->producer != NULL | |
2249 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) | |
2250 | return max (start_pc, post_prologue_pc); | |
2251 | } | |
df15bd07 JK |
2252 | |
2253 | amd64_init_frame_cache (&cache); | |
2254 | pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, | |
2255 | &cache); | |
2256 | if (cache.frameless_p) | |
2257 | return start_pc; | |
2258 | ||
2259 | return amd64_skip_xmm_prologue (pc, start_pc); | |
2260 | } | |
c4f35dd8 | 2261 | \f |
53e95fcf | 2262 | |
c4f35dd8 MK |
2263 | /* Normal frames. */ |
2264 | ||
8fbca658 PA |
2265 | static void |
2266 | amd64_frame_cache_1 (struct frame_info *this_frame, | |
2267 | struct amd64_frame_cache *cache) | |
6d686a84 | 2268 | { |
e17a4113 UW |
2269 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2270 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d8de1ef7 | 2271 | gdb_byte buf[8]; |
6d686a84 | 2272 | int i; |
6d686a84 | 2273 | |
10458914 | 2274 | cache->pc = get_frame_func (this_frame); |
c4f35dd8 | 2275 | if (cache->pc != 0) |
e17a4113 UW |
2276 | amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2277 | cache); | |
c4f35dd8 MK |
2278 | |
2279 | if (cache->frameless_p) | |
2280 | { | |
4a28816e MK |
2281 | /* We didn't find a valid frame. If we're at the start of a |
2282 | function, or somewhere half-way its prologue, the function's | |
2283 | frame probably hasn't been fully setup yet. Try to | |
2284 | reconstruct the base address for the stack frame by looking | |
2285 | at the stack pointer. For truly "frameless" functions this | |
2286 | might work too. */ | |
c4f35dd8 | 2287 | |
e0c62198 L |
2288 | if (cache->saved_sp_reg != -1) |
2289 | { | |
8fbca658 PA |
2290 | /* Stack pointer has been saved. */ |
2291 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2292 | cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); | |
2293 | ||
e0c62198 L |
2294 | /* We're halfway aligning the stack. */ |
2295 | cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; | |
2296 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; | |
2297 | ||
2298 | /* This will be added back below. */ | |
2299 | cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; | |
2300 | } | |
2301 | else | |
2302 | { | |
2303 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
e17a4113 UW |
2304 | cache->base = extract_unsigned_integer (buf, 8, byte_order) |
2305 | + cache->sp_offset; | |
e0c62198 | 2306 | } |
c4f35dd8 | 2307 | } |
35883a3f MK |
2308 | else |
2309 | { | |
10458914 | 2310 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
e17a4113 | 2311 | cache->base = extract_unsigned_integer (buf, 8, byte_order); |
35883a3f | 2312 | } |
c4f35dd8 MK |
2313 | |
2314 | /* Now that we have the base address for the stack frame we can | |
2315 | calculate the value of %rsp in the calling frame. */ | |
2316 | cache->saved_sp = cache->base + 16; | |
2317 | ||
35883a3f MK |
2318 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
2319 | frame we find it at the same offset from the reconstructed base | |
e0c62198 L |
2320 | address. If we're halfway aligning the stack, %rip is handled |
2321 | differently (see above). */ | |
2322 | if (!cache->frameless_p || cache->saved_sp_reg == -1) | |
2323 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; | |
35883a3f | 2324 | |
c4f35dd8 MK |
2325 | /* Adjust all the saved registers such that they contain addresses |
2326 | instead of offsets. */ | |
e53bef9f | 2327 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
2328 | if (cache->saved_regs[i] != -1) |
2329 | cache->saved_regs[i] += cache->base; | |
2330 | ||
8fbca658 PA |
2331 | cache->base_p = 1; |
2332 | } | |
2333 | ||
2334 | static struct amd64_frame_cache * | |
2335 | amd64_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2336 | { | |
2337 | volatile struct gdb_exception ex; | |
2338 | struct amd64_frame_cache *cache; | |
2339 | ||
2340 | if (*this_cache) | |
2341 | return *this_cache; | |
2342 | ||
2343 | cache = amd64_alloc_frame_cache (); | |
2344 | *this_cache = cache; | |
2345 | ||
2346 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
2347 | { | |
2348 | amd64_frame_cache_1 (this_frame, cache); | |
2349 | } | |
2350 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2351 | throw_exception (ex); | |
2352 | ||
c4f35dd8 | 2353 | return cache; |
6d686a84 ML |
2354 | } |
2355 | ||
8fbca658 PA |
2356 | static enum unwind_stop_reason |
2357 | amd64_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2358 | void **this_cache) | |
2359 | { | |
2360 | struct amd64_frame_cache *cache = | |
2361 | amd64_frame_cache (this_frame, this_cache); | |
2362 | ||
2363 | if (!cache->base_p) | |
2364 | return UNWIND_UNAVAILABLE; | |
2365 | ||
2366 | /* This marks the outermost frame. */ | |
2367 | if (cache->base == 0) | |
2368 | return UNWIND_OUTERMOST; | |
2369 | ||
2370 | return UNWIND_NO_REASON; | |
2371 | } | |
2372 | ||
c4f35dd8 | 2373 | static void |
10458914 | 2374 | amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
e53bef9f | 2375 | struct frame_id *this_id) |
c4f35dd8 | 2376 | { |
e53bef9f | 2377 | struct amd64_frame_cache *cache = |
10458914 | 2378 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2379 | |
8fbca658 | 2380 | if (!cache->base_p) |
5ce0145d PA |
2381 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2382 | else if (cache->base == 0) | |
2383 | { | |
2384 | /* This marks the outermost frame. */ | |
2385 | return; | |
2386 | } | |
2387 | else | |
2388 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
c4f35dd8 | 2389 | } |
e76e1718 | 2390 | |
10458914 DJ |
2391 | static struct value * |
2392 | amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2393 | int regnum) | |
53e95fcf | 2394 | { |
10458914 | 2395 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e53bef9f | 2396 | struct amd64_frame_cache *cache = |
10458914 | 2397 | amd64_frame_cache (this_frame, this_cache); |
e76e1718 | 2398 | |
c4f35dd8 | 2399 | gdb_assert (regnum >= 0); |
b1ab997b | 2400 | |
2ae02b47 | 2401 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
10458914 | 2402 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
e76e1718 | 2403 | |
e53bef9f | 2404 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2405 | return frame_unwind_got_memory (this_frame, regnum, |
2406 | cache->saved_regs[regnum]); | |
e76e1718 | 2407 | |
10458914 | 2408 | return frame_unwind_got_register (this_frame, regnum, regnum); |
c4f35dd8 | 2409 | } |
e76e1718 | 2410 | |
e53bef9f | 2411 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
2412 | { |
2413 | NORMAL_FRAME, | |
8fbca658 | 2414 | amd64_frame_unwind_stop_reason, |
e53bef9f | 2415 | amd64_frame_this_id, |
10458914 DJ |
2416 | amd64_frame_prev_register, |
2417 | NULL, | |
2418 | default_frame_sniffer | |
c4f35dd8 | 2419 | }; |
c4f35dd8 | 2420 | \f |
6710bf39 SS |
2421 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2422 | ||
2423 | static void | |
2424 | amd64_gen_return_address (struct gdbarch *gdbarch, | |
2425 | struct agent_expr *ax, struct axs_value *value, | |
2426 | CORE_ADDR scope) | |
2427 | { | |
2428 | /* The following sequence assumes the traditional use of the base | |
2429 | register. */ | |
2430 | ax_reg (ax, AMD64_RBP_REGNUM); | |
2431 | ax_const_l (ax, 8); | |
2432 | ax_simple (ax, aop_add); | |
2433 | value->type = register_type (gdbarch, AMD64_RIP_REGNUM); | |
2434 | value->kind = axs_lvalue_memory; | |
2435 | } | |
2436 | \f | |
e76e1718 | 2437 | |
c4f35dd8 MK |
2438 | /* Signal trampolines. */ |
2439 | ||
2440 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
2441 | 64-bit variants. This would require using identical frame caches | |
2442 | on both platforms. */ | |
2443 | ||
e53bef9f | 2444 | static struct amd64_frame_cache * |
10458914 | 2445 | amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 2446 | { |
e17a4113 UW |
2447 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2448 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2449 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2450 | volatile struct gdb_exception ex; |
e53bef9f | 2451 | struct amd64_frame_cache *cache; |
c4f35dd8 | 2452 | CORE_ADDR addr; |
d8de1ef7 | 2453 | gdb_byte buf[8]; |
2b5e0749 | 2454 | int i; |
c4f35dd8 MK |
2455 | |
2456 | if (*this_cache) | |
2457 | return *this_cache; | |
2458 | ||
e53bef9f | 2459 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 2460 | |
8fbca658 PA |
2461 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
2462 | { | |
2463 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
2464 | cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; | |
2465 | ||
2466 | addr = tdep->sigcontext_addr (this_frame); | |
2467 | gdb_assert (tdep->sc_reg_offset); | |
2468 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); | |
2469 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2470 | if (tdep->sc_reg_offset[i] != -1) | |
2471 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 | 2472 | |
8fbca658 PA |
2473 | cache->base_p = 1; |
2474 | } | |
2475 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2476 | throw_exception (ex); | |
c4f35dd8 MK |
2477 | |
2478 | *this_cache = cache; | |
2479 | return cache; | |
53e95fcf JS |
2480 | } |
2481 | ||
8fbca658 PA |
2482 | static enum unwind_stop_reason |
2483 | amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2484 | void **this_cache) | |
2485 | { | |
2486 | struct amd64_frame_cache *cache = | |
2487 | amd64_sigtramp_frame_cache (this_frame, this_cache); | |
2488 | ||
2489 | if (!cache->base_p) | |
2490 | return UNWIND_UNAVAILABLE; | |
2491 | ||
2492 | return UNWIND_NO_REASON; | |
2493 | } | |
2494 | ||
c4f35dd8 | 2495 | static void |
10458914 | 2496 | amd64_sigtramp_frame_this_id (struct frame_info *this_frame, |
e53bef9f | 2497 | void **this_cache, struct frame_id *this_id) |
c4f35dd8 | 2498 | { |
e53bef9f | 2499 | struct amd64_frame_cache *cache = |
10458914 | 2500 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2501 | |
8fbca658 | 2502 | if (!cache->base_p) |
5ce0145d PA |
2503 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2504 | else if (cache->base == 0) | |
2505 | { | |
2506 | /* This marks the outermost frame. */ | |
2507 | return; | |
2508 | } | |
2509 | else | |
2510 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); | |
c4f35dd8 MK |
2511 | } |
2512 | ||
10458914 DJ |
2513 | static struct value * |
2514 | amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2515 | void **this_cache, int regnum) | |
c4f35dd8 MK |
2516 | { |
2517 | /* Make sure we've initialized the cache. */ | |
10458914 | 2518 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2519 | |
10458914 | 2520 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
c4f35dd8 MK |
2521 | } |
2522 | ||
10458914 DJ |
2523 | static int |
2524 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2525 | struct frame_info *this_frame, | |
2526 | void **this_cache) | |
c4f35dd8 | 2527 | { |
10458914 | 2528 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
911bc6ee MK |
2529 | |
2530 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
2531 | handler. */ | |
2532 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2533 | return 0; |
911bc6ee MK |
2534 | |
2535 | if (tdep->sigtramp_p != NULL) | |
2536 | { | |
10458914 DJ |
2537 | if (tdep->sigtramp_p (this_frame)) |
2538 | return 1; | |
911bc6ee | 2539 | } |
c4f35dd8 | 2540 | |
911bc6ee | 2541 | if (tdep->sigtramp_start != 0) |
1c3545ae | 2542 | { |
10458914 | 2543 | CORE_ADDR pc = get_frame_pc (this_frame); |
1c3545ae | 2544 | |
911bc6ee MK |
2545 | gdb_assert (tdep->sigtramp_end != 0); |
2546 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2547 | return 1; |
1c3545ae | 2548 | } |
c4f35dd8 | 2549 | |
10458914 | 2550 | return 0; |
c4f35dd8 | 2551 | } |
10458914 DJ |
2552 | |
2553 | static const struct frame_unwind amd64_sigtramp_frame_unwind = | |
2554 | { | |
2555 | SIGTRAMP_FRAME, | |
8fbca658 | 2556 | amd64_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2557 | amd64_sigtramp_frame_this_id, |
2558 | amd64_sigtramp_frame_prev_register, | |
2559 | NULL, | |
2560 | amd64_sigtramp_frame_sniffer | |
2561 | }; | |
c4f35dd8 MK |
2562 | \f |
2563 | ||
2564 | static CORE_ADDR | |
10458914 | 2565 | amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 2566 | { |
e53bef9f | 2567 | struct amd64_frame_cache *cache = |
10458914 | 2568 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
2569 | |
2570 | return cache->base; | |
2571 | } | |
2572 | ||
e53bef9f | 2573 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 2574 | { |
e53bef9f MK |
2575 | &amd64_frame_unwind, |
2576 | amd64_frame_base_address, | |
2577 | amd64_frame_base_address, | |
2578 | amd64_frame_base_address | |
c4f35dd8 MK |
2579 | }; |
2580 | ||
872761f4 MS |
2581 | /* Normal frames, but in a function epilogue. */ |
2582 | ||
2583 | /* The epilogue is defined here as the 'ret' instruction, which will | |
2584 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
2585 | the function's stack frame. */ | |
2586 | ||
2587 | static int | |
2588 | amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2589 | { | |
2590 | gdb_byte insn; | |
e0d00bc7 JK |
2591 | struct symtab *symtab; |
2592 | ||
2593 | symtab = find_pc_symtab (pc); | |
2594 | if (symtab && symtab->epilogue_unwind_valid) | |
2595 | return 0; | |
872761f4 MS |
2596 | |
2597 | if (target_read_memory (pc, &insn, 1)) | |
2598 | return 0; /* Can't read memory at pc. */ | |
2599 | ||
2600 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2601 | return 0; | |
2602 | ||
2603 | return 1; | |
2604 | } | |
2605 | ||
2606 | static int | |
2607 | amd64_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2608 | struct frame_info *this_frame, | |
2609 | void **this_prologue_cache) | |
2610 | { | |
2611 | if (frame_relative_level (this_frame) == 0) | |
2612 | return amd64_in_function_epilogue_p (get_frame_arch (this_frame), | |
2613 | get_frame_pc (this_frame)); | |
2614 | else | |
2615 | return 0; | |
2616 | } | |
2617 | ||
2618 | static struct amd64_frame_cache * | |
2619 | amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2620 | { | |
2621 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2622 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2623 | volatile struct gdb_exception ex; |
872761f4 | 2624 | struct amd64_frame_cache *cache; |
6c10c06b | 2625 | gdb_byte buf[8]; |
872761f4 MS |
2626 | |
2627 | if (*this_cache) | |
2628 | return *this_cache; | |
2629 | ||
2630 | cache = amd64_alloc_frame_cache (); | |
2631 | *this_cache = cache; | |
2632 | ||
8fbca658 PA |
2633 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
2634 | { | |
2635 | /* Cache base will be %esp plus cache->sp_offset (-8). */ | |
2636 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
2637 | cache->base = extract_unsigned_integer (buf, 8, | |
2638 | byte_order) + cache->sp_offset; | |
2639 | ||
2640 | /* Cache pc will be the frame func. */ | |
2641 | cache->pc = get_frame_pc (this_frame); | |
872761f4 | 2642 | |
8fbca658 PA |
2643 | /* The saved %esp will be at cache->base plus 16. */ |
2644 | cache->saved_sp = cache->base + 16; | |
872761f4 | 2645 | |
8fbca658 PA |
2646 | /* The saved %eip will be at cache->base plus 8. */ |
2647 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; | |
872761f4 | 2648 | |
8fbca658 PA |
2649 | cache->base_p = 1; |
2650 | } | |
2651 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2652 | throw_exception (ex); | |
872761f4 MS |
2653 | |
2654 | return cache; | |
2655 | } | |
2656 | ||
8fbca658 PA |
2657 | static enum unwind_stop_reason |
2658 | amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2659 | void **this_cache) | |
2660 | { | |
2661 | struct amd64_frame_cache *cache | |
2662 | = amd64_epilogue_frame_cache (this_frame, this_cache); | |
2663 | ||
2664 | if (!cache->base_p) | |
2665 | return UNWIND_UNAVAILABLE; | |
2666 | ||
2667 | return UNWIND_NO_REASON; | |
2668 | } | |
2669 | ||
872761f4 MS |
2670 | static void |
2671 | amd64_epilogue_frame_this_id (struct frame_info *this_frame, | |
2672 | void **this_cache, | |
2673 | struct frame_id *this_id) | |
2674 | { | |
2675 | struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, | |
2676 | this_cache); | |
2677 | ||
8fbca658 | 2678 | if (!cache->base_p) |
5ce0145d PA |
2679 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2680 | else | |
2681 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
872761f4 MS |
2682 | } |
2683 | ||
2684 | static const struct frame_unwind amd64_epilogue_frame_unwind = | |
2685 | { | |
2686 | NORMAL_FRAME, | |
8fbca658 | 2687 | amd64_epilogue_frame_unwind_stop_reason, |
872761f4 MS |
2688 | amd64_epilogue_frame_this_id, |
2689 | amd64_frame_prev_register, | |
2690 | NULL, | |
2691 | amd64_epilogue_frame_sniffer | |
2692 | }; | |
2693 | ||
166f4c7b | 2694 | static struct frame_id |
10458914 | 2695 | amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
166f4c7b | 2696 | { |
c4f35dd8 MK |
2697 | CORE_ADDR fp; |
2698 | ||
10458914 | 2699 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
c4f35dd8 | 2700 | |
10458914 | 2701 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
166f4c7b ML |
2702 | } |
2703 | ||
8b148df9 AC |
2704 | /* 16 byte align the SP per frame requirements. */ |
2705 | ||
2706 | static CORE_ADDR | |
e53bef9f | 2707 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
2708 | { |
2709 | return sp & -(CORE_ADDR)16; | |
2710 | } | |
473f17b0 MK |
2711 | \f |
2712 | ||
593adc23 MK |
2713 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
2714 | in the floating-point register set REGSET to register cache | |
2715 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2716 | |
2717 | static void | |
e53bef9f MK |
2718 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
2719 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 2720 | { |
9ea75c57 | 2721 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 MK |
2722 | |
2723 | gdb_assert (len == tdep->sizeof_fpregset); | |
90f90721 | 2724 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 2725 | } |
8b148df9 | 2726 | |
593adc23 MK |
2727 | /* Collect register REGNUM from the register cache REGCACHE and store |
2728 | it in the buffer specified by FPREGS and LEN as described by the | |
2729 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2730 | all registers in REGSET. */ | |
2731 | ||
2732 | static void | |
2733 | amd64_collect_fpregset (const struct regset *regset, | |
2734 | const struct regcache *regcache, | |
2735 | int regnum, void *fpregs, size_t len) | |
2736 | { | |
2737 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2738 | ||
2739 | gdb_assert (len == tdep->sizeof_fpregset); | |
2740 | amd64_collect_fxsave (regcache, regnum, fpregs); | |
2741 | } | |
2742 | ||
a055a187 L |
2743 | /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ |
2744 | ||
2745 | static void | |
2746 | amd64_supply_xstateregset (const struct regset *regset, | |
2747 | struct regcache *regcache, int regnum, | |
2748 | const void *xstateregs, size_t len) | |
2749 | { | |
a055a187 L |
2750 | amd64_supply_xsave (regcache, regnum, xstateregs); |
2751 | } | |
2752 | ||
2753 | /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */ | |
2754 | ||
2755 | static void | |
2756 | amd64_collect_xstateregset (const struct regset *regset, | |
2757 | const struct regcache *regcache, | |
2758 | int regnum, void *xstateregs, size_t len) | |
2759 | { | |
a055a187 L |
2760 | amd64_collect_xsave (regcache, regnum, xstateregs, 1); |
2761 | } | |
2762 | ||
c6b33596 MK |
2763 | /* Return the appropriate register set for the core section identified |
2764 | by SECT_NAME and SECT_SIZE. */ | |
2765 | ||
2766 | static const struct regset * | |
e53bef9f MK |
2767 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
2768 | const char *sect_name, size_t sect_size) | |
c6b33596 MK |
2769 | { |
2770 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2771 | ||
2772 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
2773 | { | |
2774 | if (tdep->fpregset == NULL) | |
593adc23 MK |
2775 | tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, |
2776 | amd64_collect_fpregset); | |
c6b33596 MK |
2777 | |
2778 | return tdep->fpregset; | |
2779 | } | |
2780 | ||
a055a187 L |
2781 | if (strcmp (sect_name, ".reg-xstate") == 0) |
2782 | { | |
2783 | if (tdep->xstateregset == NULL) | |
2784 | tdep->xstateregset = regset_alloc (gdbarch, | |
2785 | amd64_supply_xstateregset, | |
2786 | amd64_collect_xstateregset); | |
2787 | ||
2788 | return tdep->xstateregset; | |
2789 | } | |
2790 | ||
c6b33596 MK |
2791 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); |
2792 | } | |
2793 | \f | |
2794 | ||
436675d3 PA |
2795 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
2796 | %rdi. We expect its value to be a pointer to the jmp_buf structure | |
2797 | from which we extract the address that we will land at. This | |
2798 | address is copied into PC. This routine returns non-zero on | |
2799 | success. */ | |
2800 | ||
2801 | static int | |
2802 | amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2803 | { | |
2804 | gdb_byte buf[8]; | |
2805 | CORE_ADDR jb_addr; | |
2806 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2807 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
0dfff4cb | 2808 | int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
2809 | |
2810 | /* If JB_PC_OFFSET is -1, we have no way to find out where the | |
2811 | longjmp will land. */ | |
2812 | if (jb_pc_offset == -1) | |
2813 | return 0; | |
2814 | ||
2815 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); | |
0dfff4cb UW |
2816 | jb_addr= extract_typed_address |
2817 | (buf, builtin_type (gdbarch)->builtin_data_ptr); | |
436675d3 PA |
2818 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
2819 | return 0; | |
2820 | ||
0dfff4cb | 2821 | *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
2822 | |
2823 | return 1; | |
2824 | } | |
2825 | ||
cf648174 HZ |
2826 | static const int amd64_record_regmap[] = |
2827 | { | |
2828 | AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, | |
2829 | AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
2830 | AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, | |
2831 | AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, | |
2832 | AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, | |
2833 | AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM | |
2834 | }; | |
2835 | ||
2213a65d | 2836 | void |
90f90721 | 2837 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 2838 | { |
0c1a73d6 | 2839 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
90884b2b | 2840 | const struct target_desc *tdesc = info.target_desc; |
05c0465e SDJ |
2841 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
2842 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
2843 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
2844 | NULL }; | |
2845 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
2846 | NULL }; | |
53e95fcf | 2847 | |
473f17b0 MK |
2848 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
2849 | floating-point registers. */ | |
2850 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
2851 | ||
90884b2b L |
2852 | if (! tdesc_has_registers (tdesc)) |
2853 | tdesc = tdesc_amd64; | |
2854 | tdep->tdesc = tdesc; | |
2855 | ||
2856 | tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; | |
2857 | tdep->register_names = amd64_register_names; | |
2858 | ||
a055a187 L |
2859 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) |
2860 | { | |
2861 | tdep->ymmh_register_names = amd64_ymmh_names; | |
2862 | tdep->num_ymm_regs = 16; | |
2863 | tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; | |
2864 | } | |
2865 | ||
e43e105e WT |
2866 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) |
2867 | { | |
2868 | tdep->mpx_register_names = amd64_mpx_names; | |
2869 | tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; | |
2870 | tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; | |
2871 | } | |
2872 | ||
fe01d668 | 2873 | tdep->num_byte_regs = 20; |
1ba53b71 L |
2874 | tdep->num_word_regs = 16; |
2875 | tdep->num_dword_regs = 16; | |
2876 | /* Avoid wiring in the MMX registers for now. */ | |
2877 | tdep->num_mmx_regs = 0; | |
2878 | ||
3543a589 TT |
2879 | set_gdbarch_pseudo_register_read_value (gdbarch, |
2880 | amd64_pseudo_register_read_value); | |
1ba53b71 L |
2881 | set_gdbarch_pseudo_register_write (gdbarch, |
2882 | amd64_pseudo_register_write); | |
2883 | ||
2884 | set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); | |
2885 | ||
5716833c | 2886 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 2887 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 2888 | tdep->num_xmm_regs = 16; |
53e95fcf | 2889 | |
0c1a73d6 | 2890 | /* This is what all the fuss is about. */ |
53e95fcf JS |
2891 | set_gdbarch_long_bit (gdbarch, 64); |
2892 | set_gdbarch_long_long_bit (gdbarch, 64); | |
2893 | set_gdbarch_ptr_bit (gdbarch, 64); | |
2894 | ||
e53bef9f MK |
2895 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
2896 | up 128 bits, even though it's still based on the i387 extended | |
2897 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
2898 | set_gdbarch_long_double_bit (gdbarch, 128); |
2899 | ||
e53bef9f | 2900 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
b83b026c MK |
2901 | |
2902 | /* Register numbers of various important registers. */ | |
90f90721 MK |
2903 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
2904 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
2905 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
2906 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 2907 | |
e53bef9f MK |
2908 | /* The "default" register numbering scheme for AMD64 is referred to |
2909 | as the "DWARF Register Number Mapping" in the System V psABI. | |
2910 | The preferred debugging format for all known AMD64 targets is | |
2911 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
2912 | DWARF-1), but we provide the same mapping just in case. This | |
2913 | mapping is also used for stabs, which GCC does support. */ | |
2914 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
e53bef9f | 2915 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
de220d0f | 2916 | |
c4f35dd8 | 2917 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 2918 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 2919 | |
c4f35dd8 | 2920 | /* Call dummy code. */ |
e53bef9f MK |
2921 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
2922 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 2923 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 2924 | |
83acabca | 2925 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
d532c08f MK |
2926 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
2927 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
2928 | ||
efb1c01c | 2929 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 2930 | |
e53bef9f | 2931 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 2932 | |
cf648174 HZ |
2933 | tdep->record_regmap = amd64_record_regmap; |
2934 | ||
10458914 | 2935 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
53e95fcf | 2936 | |
872761f4 MS |
2937 | /* Hook the function epilogue frame unwinder. This unwinder is |
2938 | appended to the list first, so that it supercedes the other | |
2939 | unwinders in function epilogues. */ | |
2940 | frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); | |
2941 | ||
2942 | /* Hook the prologue-based frame unwinders. */ | |
10458914 DJ |
2943 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
2944 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); | |
e53bef9f | 2945 | frame_base_set_default (gdbarch, &amd64_frame_base); |
c6b33596 MK |
2946 | |
2947 | /* If we have a register mapping, enable the generic core file support. */ | |
2948 | if (tdep->gregset_reg_offset) | |
2949 | set_gdbarch_regset_from_core_section (gdbarch, | |
e53bef9f | 2950 | amd64_regset_from_core_section); |
436675d3 PA |
2951 | |
2952 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); | |
dde08ee1 PA |
2953 | |
2954 | set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); | |
6710bf39 SS |
2955 | |
2956 | set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); | |
55aa24fb SDJ |
2957 | |
2958 | /* SystemTap variables and functions. */ | |
05c0465e SDJ |
2959 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
2960 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
2961 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
2962 | stap_register_indirection_prefixes); | |
2963 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
2964 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
2965 | set_gdbarch_stap_is_single_operand (gdbarch, |
2966 | i386_stap_is_single_operand); | |
2967 | set_gdbarch_stap_parse_special_token (gdbarch, | |
2968 | i386_stap_parse_special_token); | |
c4f35dd8 | 2969 | } |
fff4548b MK |
2970 | \f |
2971 | ||
2972 | static struct type * | |
2973 | amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2974 | { | |
2975 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2976 | ||
2977 | switch (regnum - tdep->eax_regnum) | |
2978 | { | |
2979 | case AMD64_RBP_REGNUM: /* %ebp */ | |
2980 | case AMD64_RSP_REGNUM: /* %esp */ | |
2981 | return builtin_type (gdbarch)->builtin_data_ptr; | |
2982 | case AMD64_RIP_REGNUM: /* %eip */ | |
2983 | return builtin_type (gdbarch)->builtin_func_ptr; | |
2984 | } | |
2985 | ||
2986 | return i386_pseudo_register_type (gdbarch, regnum); | |
2987 | } | |
2988 | ||
2989 | void | |
2990 | amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2991 | { | |
2992 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2993 | const struct target_desc *tdesc = info.target_desc; | |
2994 | ||
2995 | amd64_init_abi (info, gdbarch); | |
2996 | ||
2997 | if (! tdesc_has_registers (tdesc)) | |
2998 | tdesc = tdesc_x32; | |
2999 | tdep->tdesc = tdesc; | |
3000 | ||
3001 | tdep->num_dword_regs = 17; | |
3002 | set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); | |
3003 | ||
3004 | set_gdbarch_long_bit (gdbarch, 32); | |
3005 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3006 | } | |
90884b2b L |
3007 | |
3008 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
3009 | void _initialize_amd64_tdep (void); | |
3010 | ||
3011 | void | |
3012 | _initialize_amd64_tdep (void) | |
3013 | { | |
3014 | initialize_tdesc_amd64 (); | |
a055a187 | 3015 | initialize_tdesc_amd64_avx (); |
e43e105e | 3016 | initialize_tdesc_amd64_mpx (); |
ac1438b5 L |
3017 | initialize_tdesc_x32 (); |
3018 | initialize_tdesc_x32_avx (); | |
90884b2b | 3019 | } |
c4f35dd8 MK |
3020 | \f |
3021 | ||
41d041d6 MK |
3022 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
3023 | sense that the instruction pointer and data pointer are simply | |
3024 | 64-bit offsets into the code segment and the data segment instead | |
3025 | of a selector offset pair. The functions below store the upper 32 | |
3026 | bits of these pointers (instead of just the 16-bits of the segment | |
3027 | selector). */ | |
3028 | ||
3029 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
3030 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
3031 | -1, do this for all registers. This function masks off any of the | |
3032 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
3033 | |
3034 | void | |
90f90721 | 3035 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
20a6ec49 | 3036 | const void *fxsave) |
c4f35dd8 | 3037 | { |
20a6ec49 MD |
3038 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3040 | ||
41d041d6 | 3041 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 3042 | |
233dfcf0 L |
3043 | if (fxsave |
3044 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
c4f35dd8 | 3045 | { |
d8de1ef7 | 3046 | const gdb_byte *regs = fxsave; |
41d041d6 | 3047 | |
20a6ec49 MD |
3048 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
3049 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
3050 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3051 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
c4f35dd8 | 3052 | } |
0c1a73d6 MK |
3053 | } |
3054 | ||
a055a187 L |
3055 | /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ |
3056 | ||
3057 | void | |
3058 | amd64_supply_xsave (struct regcache *regcache, int regnum, | |
3059 | const void *xsave) | |
3060 | { | |
3061 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
3062 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3063 | ||
3064 | i387_supply_xsave (regcache, regnum, xsave); | |
3065 | ||
233dfcf0 L |
3066 | if (xsave |
3067 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
a055a187 L |
3068 | { |
3069 | const gdb_byte *regs = xsave; | |
3070 | ||
3071 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
3072 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), | |
3073 | regs + 12); | |
3074 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3075 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), | |
3076 | regs + 20); | |
3077 | } | |
3078 | } | |
3079 | ||
3c017e40 MK |
3080 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
3081 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
3082 | all registers. This function doesn't touch any of the reserved | |
3083 | bits in *FXSAVE. */ | |
3084 | ||
3085 | void | |
3086 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
3087 | void *fxsave) | |
3088 | { | |
20a6ec49 MD |
3089 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3090 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
d8de1ef7 | 3091 | gdb_byte *regs = fxsave; |
3c017e40 MK |
3092 | |
3093 | i387_collect_fxsave (regcache, regnum, fxsave); | |
3094 | ||
233dfcf0 | 3095 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
f0ef85a5 | 3096 | { |
20a6ec49 MD |
3097 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
3098 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
3099 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3100 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
f0ef85a5 | 3101 | } |
3c017e40 | 3102 | } |
a055a187 | 3103 | |
7a9dd1b2 | 3104 | /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ |
a055a187 L |
3105 | |
3106 | void | |
3107 | amd64_collect_xsave (const struct regcache *regcache, int regnum, | |
3108 | void *xsave, int gcore) | |
3109 | { | |
3110 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
3111 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3112 | gdb_byte *regs = xsave; | |
3113 | ||
3114 | i387_collect_xsave (regcache, regnum, xsave, gcore); | |
3115 | ||
233dfcf0 | 3116 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
a055a187 L |
3117 | { |
3118 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
3119 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), | |
3120 | regs + 12); | |
3121 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3122 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), | |
3123 | regs + 20); | |
3124 | } | |
3125 | } |