Commit | Line | Data |
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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
9b254dd1 | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
5ae96ec1 MK |
4 | Free Software Foundation, Inc. |
5 | ||
6 | Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
7 | |
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
13 | (at your option) any later version. |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
22 | |
23 | #include "defs.h" | |
c4f35dd8 MK |
24 | #include "arch-utils.h" |
25 | #include "block.h" | |
26 | #include "dummy-frame.h" | |
27 | #include "frame.h" | |
28 | #include "frame-base.h" | |
29 | #include "frame-unwind.h" | |
53e95fcf | 30 | #include "inferior.h" |
53e95fcf | 31 | #include "gdbcmd.h" |
c4f35dd8 MK |
32 | #include "gdbcore.h" |
33 | #include "objfiles.h" | |
53e95fcf | 34 | #include "regcache.h" |
2c261fae | 35 | #include "regset.h" |
53e95fcf | 36 | #include "symfile.h" |
c4f35dd8 | 37 | |
82dbc5f7 | 38 | #include "gdb_assert.h" |
c4f35dd8 | 39 | |
9c1488cb | 40 | #include "amd64-tdep.h" |
c4f35dd8 | 41 | #include "i387-tdep.h" |
53e95fcf | 42 | |
e53bef9f MK |
43 | /* Note that the AMD64 architecture was previously known as x86-64. |
44 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 45 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
46 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
47 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
48 | x86_64_-prefix since it's so much easier to type. */ | |
49 | ||
402ecd56 | 50 | /* Register information. */ |
c4f35dd8 | 51 | |
6707b003 | 52 | static const char *amd64_register_names[] = |
de220d0f | 53 | { |
6707b003 | 54 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
c4f35dd8 MK |
55 | |
56 | /* %r8 is indeed register number 8. */ | |
6707b003 UW |
57 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
58 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", | |
c4f35dd8 | 59 | |
af233647 | 60 | /* %st0 is register number 24. */ |
6707b003 UW |
61 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
62 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", | |
c4f35dd8 | 63 | |
af233647 | 64 | /* %xmm0 is register number 40. */ |
6707b003 UW |
65 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
66 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", | |
67 | "mxcsr", | |
0e04a514 ML |
68 | }; |
69 | ||
c4f35dd8 | 70 | /* Total number of registers. */ |
6707b003 | 71 | #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names) |
de220d0f | 72 | |
c4f35dd8 | 73 | /* Return the name of register REGNUM. */ |
b6779aa2 | 74 | |
8695c747 | 75 | const char * |
d93859e2 | 76 | amd64_register_name (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 77 | { |
e53bef9f | 78 | if (regnum >= 0 && regnum < AMD64_NUM_REGS) |
6707b003 | 79 | return amd64_register_names[regnum]; |
53e95fcf | 80 | |
c4f35dd8 | 81 | return NULL; |
53e95fcf JS |
82 | } |
83 | ||
84 | /* Return the GDB type object for the "standard" data type of data in | |
c4f35dd8 | 85 | register REGNUM. */ |
53e95fcf | 86 | |
8695c747 | 87 | struct type * |
e53bef9f | 88 | amd64_register_type (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 89 | { |
6707b003 UW |
90 | if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM) |
91 | return builtin_type_int64; | |
92 | if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM) | |
0dfff4cb | 93 | return builtin_type (gdbarch)->builtin_data_ptr; |
6707b003 UW |
94 | if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM) |
95 | return builtin_type_int64; | |
96 | if (regnum == AMD64_RIP_REGNUM) | |
0dfff4cb | 97 | return builtin_type (gdbarch)->builtin_func_ptr; |
6707b003 UW |
98 | if (regnum == AMD64_EFLAGS_REGNUM) |
99 | return i386_eflags_type; | |
100 | if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM) | |
101 | return builtin_type_int32; | |
102 | if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7) | |
103 | return builtin_type_i387_ext; | |
104 | if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7) | |
105 | return builtin_type_int32; | |
106 | if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15) | |
794ac428 | 107 | return i386_sse_type (gdbarch); |
6707b003 UW |
108 | if (regnum == AMD64_MXCSR_REGNUM) |
109 | return i386_mxcsr_type; | |
110 | ||
111 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
53e95fcf JS |
112 | } |
113 | ||
c4f35dd8 MK |
114 | /* DWARF Register Number Mapping as defined in the System V psABI, |
115 | section 3.6. */ | |
53e95fcf | 116 | |
e53bef9f | 117 | static int amd64_dwarf_regmap[] = |
0e04a514 | 118 | { |
c4f35dd8 | 119 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
120 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
121 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
122 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
123 | |
124 | /* Frame Pointer Register RBP. */ | |
90f90721 | 125 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
126 | |
127 | /* Stack Pointer Register RSP. */ | |
90f90721 | 128 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
129 | |
130 | /* Extended Integer Registers 8 - 15. */ | |
131 | 8, 9, 10, 11, 12, 13, 14, 15, | |
132 | ||
59207364 | 133 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 134 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
135 | |
136 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
137 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
138 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
139 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
140 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
141 | |
142 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
143 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
144 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
145 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
146 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
147 | |
148 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
149 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
150 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
151 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 JB |
152 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
153 | ||
154 | /* Control and Status Flags Register. */ | |
155 | AMD64_EFLAGS_REGNUM, | |
156 | ||
157 | /* Selector Registers. */ | |
158 | AMD64_ES_REGNUM, | |
159 | AMD64_CS_REGNUM, | |
160 | AMD64_SS_REGNUM, | |
161 | AMD64_DS_REGNUM, | |
162 | AMD64_FS_REGNUM, | |
163 | AMD64_GS_REGNUM, | |
164 | -1, | |
165 | -1, | |
166 | ||
167 | /* Segment Base Address Registers. */ | |
168 | -1, | |
169 | -1, | |
170 | -1, | |
171 | -1, | |
172 | ||
173 | /* Special Selector Registers. */ | |
174 | -1, | |
175 | -1, | |
176 | ||
177 | /* Floating Point Control Registers. */ | |
178 | AMD64_MXCSR_REGNUM, | |
179 | AMD64_FCTRL_REGNUM, | |
180 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 181 | }; |
0e04a514 | 182 | |
e53bef9f MK |
183 | static const int amd64_dwarf_regmap_len = |
184 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 185 | |
c4f35dd8 MK |
186 | /* Convert DWARF register number REG to the appropriate register |
187 | number used by GDB. */ | |
26abbdc4 | 188 | |
c4f35dd8 | 189 | static int |
d3f73121 | 190 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
53e95fcf | 191 | { |
c4f35dd8 | 192 | int regnum = -1; |
53e95fcf | 193 | |
16aff9a6 | 194 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 195 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 196 | |
c4f35dd8 | 197 | if (regnum == -1) |
8a3fe4f8 | 198 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
c4f35dd8 MK |
199 | |
200 | return regnum; | |
53e95fcf | 201 | } |
d532c08f | 202 | |
53e95fcf JS |
203 | \f |
204 | ||
efb1c01c MK |
205 | /* Register classes as defined in the psABI. */ |
206 | ||
207 | enum amd64_reg_class | |
208 | { | |
209 | AMD64_INTEGER, | |
210 | AMD64_SSE, | |
211 | AMD64_SSEUP, | |
212 | AMD64_X87, | |
213 | AMD64_X87UP, | |
214 | AMD64_COMPLEX_X87, | |
215 | AMD64_NO_CLASS, | |
216 | AMD64_MEMORY | |
217 | }; | |
218 | ||
219 | /* Return the union class of CLASS1 and CLASS2. See the psABI for | |
220 | details. */ | |
221 | ||
222 | static enum amd64_reg_class | |
223 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
224 | { | |
225 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
226 | if (class1 == class2) | |
227 | return class1; | |
228 | ||
229 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
230 | is the other class. */ | |
231 | if (class1 == AMD64_NO_CLASS) | |
232 | return class2; | |
233 | if (class2 == AMD64_NO_CLASS) | |
234 | return class1; | |
235 | ||
236 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
237 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
238 | return AMD64_MEMORY; | |
239 | ||
240 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
241 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
242 | return AMD64_INTEGER; | |
243 | ||
244 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
245 | MEMORY is used as class. */ | |
246 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
247 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
248 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
249 | return AMD64_MEMORY; | |
250 | ||
251 | /* Rule (f): Otherwise class SSE is used. */ | |
252 | return AMD64_SSE; | |
253 | } | |
254 | ||
255 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); | |
256 | ||
79b1ab3d MK |
257 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
258 | ||
259 | static int | |
260 | amd64_non_pod_p (struct type *type) | |
261 | { | |
262 | /* ??? A class with a base class certainly isn't POD, but does this | |
263 | catch all non-POD structure types? */ | |
264 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
265 | return 1; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
efb1c01c MK |
270 | /* Classify TYPE according to the rules for aggregate (structures and |
271 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
272 | |
273 | static void | |
efb1c01c | 274 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
53e95fcf JS |
275 | { |
276 | int len = TYPE_LENGTH (type); | |
277 | ||
efb1c01c MK |
278 | /* 1. If the size of an object is larger than two eightbytes, or in |
279 | C++, is a non-POD structure or union type, or contains | |
280 | unaligned fields, it has class memory. */ | |
79b1ab3d | 281 | if (len > 16 || amd64_non_pod_p (type)) |
53e95fcf | 282 | { |
efb1c01c MK |
283 | class[0] = class[1] = AMD64_MEMORY; |
284 | return; | |
53e95fcf | 285 | } |
efb1c01c MK |
286 | |
287 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
288 | class[0] = class[1] = AMD64_NO_CLASS; | |
289 | ||
290 | /* 3. Each field of an object is classified recursively so that | |
291 | always two fields are considered. The resulting class is | |
292 | calculated according to the classes of the fields in the | |
293 | eightbyte: */ | |
294 | ||
295 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 296 | { |
efb1c01c MK |
297 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
298 | ||
299 | /* All fields in an array have the same type. */ | |
300 | amd64_classify (subtype, class); | |
301 | if (len > 8 && class[1] == AMD64_NO_CLASS) | |
302 | class[1] = class[0]; | |
8ffd9b1b | 303 | } |
53e95fcf JS |
304 | else |
305 | { | |
efb1c01c | 306 | int i; |
53e95fcf | 307 | |
efb1c01c MK |
308 | /* Structure or union. */ |
309 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
310 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
311 | ||
312 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 313 | { |
efb1c01c MK |
314 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
315 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
316 | enum amd64_reg_class subclass[2]; | |
317 | ||
562c50c2 | 318 | /* Ignore static fields. */ |
d6a843b5 | 319 | if (field_is_static (&TYPE_FIELD (type, i))) |
562c50c2 MK |
320 | continue; |
321 | ||
efb1c01c MK |
322 | gdb_assert (pos == 0 || pos == 1); |
323 | ||
324 | amd64_classify (subtype, subclass); | |
325 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); | |
326 | if (pos == 0) | |
327 | class[1] = amd64_merge_classes (class[1], subclass[1]); | |
53e95fcf | 328 | } |
53e95fcf | 329 | } |
efb1c01c MK |
330 | |
331 | /* 4. Then a post merger cleanup is done: */ | |
332 | ||
333 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
334 | passed in memory. */ | |
335 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) | |
336 | class[0] = class[1] = AMD64_MEMORY; | |
337 | ||
338 | /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to | |
339 | SSE. */ | |
340 | if (class[0] == AMD64_SSEUP) | |
341 | class[0] = AMD64_SSE; | |
342 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) | |
343 | class[1] = AMD64_SSE; | |
344 | } | |
345 | ||
346 | /* Classify TYPE, and store the result in CLASS. */ | |
347 | ||
348 | static void | |
349 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) | |
350 | { | |
351 | enum type_code code = TYPE_CODE (type); | |
352 | int len = TYPE_LENGTH (type); | |
353 | ||
354 | class[0] = class[1] = AMD64_NO_CLASS; | |
355 | ||
356 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
357 | long, long long, and pointers are in the INTEGER class. Similarly, |
358 | range types, used by languages such as Ada, are also in the INTEGER | |
359 | class. */ | |
efb1c01c | 360 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
b929c77f | 361 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
9db13498 | 362 | || code == TYPE_CODE_CHAR |
efb1c01c MK |
363 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
364 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
365 | class[0] = AMD64_INTEGER; | |
366 | ||
5daa78cc TJB |
367 | /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 |
368 | are in class SSE. */ | |
369 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) | |
370 | && (len == 4 || len == 8)) | |
efb1c01c MK |
371 | /* FIXME: __m64 . */ |
372 | class[0] = AMD64_SSE; | |
373 | ||
5daa78cc TJB |
374 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
375 | two halves. The least significant ones belong to class SSE, the most | |
efb1c01c | 376 | significant one to class SSEUP. */ |
5daa78cc TJB |
377 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
378 | /* FIXME: __float128, __m128. */ | |
379 | class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; | |
efb1c01c MK |
380 | |
381 | /* The 64-bit mantissa of arguments of type long double belongs to | |
382 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
383 | class X87UP. */ | |
384 | else if (code == TYPE_CODE_FLT && len == 16) | |
385 | /* Class X87 and X87UP. */ | |
386 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; | |
387 | ||
388 | /* Aggregates. */ | |
389 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
390 | || code == TYPE_CODE_UNION) | |
391 | amd64_classify_aggregate (type, class); | |
392 | } | |
393 | ||
394 | static enum return_value_convention | |
c055b101 CV |
395 | amd64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
396 | struct type *type, struct regcache *regcache, | |
42835c2b | 397 | gdb_byte *readbuf, const gdb_byte *writebuf) |
efb1c01c MK |
398 | { |
399 | enum amd64_reg_class class[2]; | |
400 | int len = TYPE_LENGTH (type); | |
90f90721 MK |
401 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
402 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
403 | int integer_reg = 0; |
404 | int sse_reg = 0; | |
405 | int i; | |
406 | ||
407 | gdb_assert (!(readbuf && writebuf)); | |
408 | ||
409 | /* 1. Classify the return type with the classification algorithm. */ | |
410 | amd64_classify (type, class); | |
411 | ||
412 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d MK |
413 | for the return value and passes the address of this storage in |
414 | %rdi as if it were the first argument to the function. In effect, | |
415 | this address becomes a hidden first argument. | |
416 | ||
417 | On return %rax will contain the address that has been passed in | |
418 | by the caller in %rdi. */ | |
efb1c01c | 419 | if (class[0] == AMD64_MEMORY) |
6fa57a7d MK |
420 | { |
421 | /* As indicated by the comment above, the ABI guarantees that we | |
422 | can always find the return value just after the function has | |
423 | returned. */ | |
424 | ||
425 | if (readbuf) | |
426 | { | |
427 | ULONGEST addr; | |
428 | ||
429 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
430 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
431 | } | |
432 | ||
433 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
434 | } | |
efb1c01c MK |
435 | |
436 | gdb_assert (class[1] != AMD64_MEMORY); | |
437 | gdb_assert (len <= 16); | |
438 | ||
439 | for (i = 0; len > 0; i++, len -= 8) | |
440 | { | |
441 | int regnum = -1; | |
442 | int offset = 0; | |
443 | ||
444 | switch (class[i]) | |
445 | { | |
446 | case AMD64_INTEGER: | |
447 | /* 3. If the class is INTEGER, the next available register | |
448 | of the sequence %rax, %rdx is used. */ | |
449 | regnum = integer_regnum[integer_reg++]; | |
450 | break; | |
451 | ||
452 | case AMD64_SSE: | |
453 | /* 4. If the class is SSE, the next available SSE register | |
454 | of the sequence %xmm0, %xmm1 is used. */ | |
455 | regnum = sse_regnum[sse_reg++]; | |
456 | break; | |
457 | ||
458 | case AMD64_SSEUP: | |
459 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
460 | upper half of the last used SSE register. */ | |
461 | gdb_assert (sse_reg > 0); | |
462 | regnum = sse_regnum[sse_reg - 1]; | |
463 | offset = 8; | |
464 | break; | |
465 | ||
466 | case AMD64_X87: | |
467 | /* 6. If the class is X87, the value is returned on the X87 | |
468 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 469 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
470 | if (writebuf) |
471 | i387_return_value (gdbarch, regcache); | |
472 | break; | |
473 | ||
474 | case AMD64_X87UP: | |
475 | /* 7. If the class is X87UP, the value is returned together | |
476 | with the previous X87 value in %st0. */ | |
477 | gdb_assert (i > 0 && class[0] == AMD64_X87); | |
90f90721 | 478 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
479 | offset = 8; |
480 | len = 2; | |
481 | break; | |
482 | ||
483 | case AMD64_NO_CLASS: | |
484 | continue; | |
485 | ||
486 | default: | |
487 | gdb_assert (!"Unexpected register class."); | |
488 | } | |
489 | ||
490 | gdb_assert (regnum != -1); | |
491 | ||
492 | if (readbuf) | |
493 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 494 | readbuf + i * 8); |
efb1c01c MK |
495 | if (writebuf) |
496 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 497 | writebuf + i * 8); |
efb1c01c MK |
498 | } |
499 | ||
500 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
501 | } |
502 | \f | |
503 | ||
720aa428 MK |
504 | static CORE_ADDR |
505 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 506 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 MK |
507 | { |
508 | static int integer_regnum[] = | |
509 | { | |
90f90721 MK |
510 | AMD64_RDI_REGNUM, /* %rdi */ |
511 | AMD64_RSI_REGNUM, /* %rsi */ | |
512 | AMD64_RDX_REGNUM, /* %rdx */ | |
513 | AMD64_RCX_REGNUM, /* %rcx */ | |
514 | 8, /* %r8 */ | |
515 | 9 /* %r9 */ | |
720aa428 MK |
516 | }; |
517 | static int sse_regnum[] = | |
518 | { | |
519 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
520 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
521 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
522 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
523 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 MK |
524 | }; |
525 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); | |
526 | int num_stack_args = 0; | |
527 | int num_elements = 0; | |
528 | int element = 0; | |
529 | int integer_reg = 0; | |
530 | int sse_reg = 0; | |
531 | int i; | |
532 | ||
6470d250 MK |
533 | /* Reserve a register for the "hidden" argument. */ |
534 | if (struct_return) | |
535 | integer_reg++; | |
536 | ||
720aa428 MK |
537 | for (i = 0; i < nargs; i++) |
538 | { | |
4991999e | 539 | struct type *type = value_type (args[i]); |
720aa428 MK |
540 | int len = TYPE_LENGTH (type); |
541 | enum amd64_reg_class class[2]; | |
542 | int needed_integer_regs = 0; | |
543 | int needed_sse_regs = 0; | |
544 | int j; | |
545 | ||
546 | /* Classify argument. */ | |
547 | amd64_classify (type, class); | |
548 | ||
549 | /* Calculate the number of integer and SSE registers needed for | |
550 | this argument. */ | |
551 | for (j = 0; j < 2; j++) | |
552 | { | |
553 | if (class[j] == AMD64_INTEGER) | |
554 | needed_integer_regs++; | |
555 | else if (class[j] == AMD64_SSE) | |
556 | needed_sse_regs++; | |
557 | } | |
558 | ||
559 | /* Check whether enough registers are available, and if the | |
560 | argument should be passed in registers at all. */ | |
561 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) | |
562 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) | |
563 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
564 | { | |
565 | /* The argument will be passed on the stack. */ | |
566 | num_elements += ((len + 7) / 8); | |
567 | stack_args[num_stack_args++] = args[i]; | |
568 | } | |
569 | else | |
570 | { | |
571 | /* The argument will be passed in registers. */ | |
d8de1ef7 MK |
572 | const gdb_byte *valbuf = value_contents (args[i]); |
573 | gdb_byte buf[8]; | |
720aa428 MK |
574 | |
575 | gdb_assert (len <= 16); | |
576 | ||
577 | for (j = 0; len > 0; j++, len -= 8) | |
578 | { | |
579 | int regnum = -1; | |
580 | int offset = 0; | |
581 | ||
582 | switch (class[j]) | |
583 | { | |
584 | case AMD64_INTEGER: | |
585 | regnum = integer_regnum[integer_reg++]; | |
586 | break; | |
587 | ||
588 | case AMD64_SSE: | |
589 | regnum = sse_regnum[sse_reg++]; | |
590 | break; | |
591 | ||
592 | case AMD64_SSEUP: | |
593 | gdb_assert (sse_reg > 0); | |
594 | regnum = sse_regnum[sse_reg - 1]; | |
595 | offset = 8; | |
596 | break; | |
597 | ||
598 | default: | |
599 | gdb_assert (!"Unexpected register class."); | |
600 | } | |
601 | ||
602 | gdb_assert (regnum != -1); | |
603 | memset (buf, 0, sizeof buf); | |
604 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
605 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
610 | /* Allocate space for the arguments on the stack. */ | |
611 | sp -= num_elements * 8; | |
612 | ||
613 | /* The psABI says that "The end of the input argument area shall be | |
614 | aligned on a 16 byte boundary." */ | |
615 | sp &= ~0xf; | |
616 | ||
617 | /* Write out the arguments to the stack. */ | |
618 | for (i = 0; i < num_stack_args; i++) | |
619 | { | |
4991999e | 620 | struct type *type = value_type (stack_args[i]); |
d8de1ef7 | 621 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
720aa428 MK |
622 | int len = TYPE_LENGTH (type); |
623 | ||
624 | write_memory (sp + element * 8, valbuf, len); | |
625 | element += ((len + 7) / 8); | |
626 | } | |
627 | ||
628 | /* The psABI says that "For calls that may call functions that use | |
629 | varargs or stdargs (prototype-less calls or calls to functions | |
630 | containing ellipsis (...) in the declaration) %al is used as | |
631 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 632 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
633 | return sp; |
634 | } | |
635 | ||
c4f35dd8 | 636 | static CORE_ADDR |
7d9b040b | 637 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
638 | struct regcache *regcache, CORE_ADDR bp_addr, |
639 | int nargs, struct value **args, CORE_ADDR sp, | |
640 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 641 | { |
d8de1ef7 | 642 | gdb_byte buf[8]; |
c4f35dd8 MK |
643 | |
644 | /* Pass arguments. */ | |
6470d250 | 645 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
646 | |
647 | /* Pass "hidden" argument". */ | |
648 | if (struct_return) | |
649 | { | |
650 | store_unsigned_integer (buf, 8, struct_addr); | |
90f90721 | 651 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
652 | } |
653 | ||
654 | /* Store return address. */ | |
655 | sp -= 8; | |
10f93086 | 656 | store_unsigned_integer (buf, 8, bp_addr); |
c4f35dd8 MK |
657 | write_memory (sp, buf, 8); |
658 | ||
659 | /* Finally, update the stack pointer... */ | |
660 | store_unsigned_integer (buf, 8, sp); | |
90f90721 | 661 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
662 | |
663 | /* ...and fake a frame pointer. */ | |
90f90721 | 664 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 665 | |
3e210248 | 666 | return sp + 16; |
53e95fcf | 667 | } |
c4f35dd8 MK |
668 | \f |
669 | ||
670 | /* The maximum number of saved registers. This should include %rip. */ | |
90f90721 | 671 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 672 | |
e53bef9f | 673 | struct amd64_frame_cache |
c4f35dd8 MK |
674 | { |
675 | /* Base address. */ | |
676 | CORE_ADDR base; | |
677 | CORE_ADDR sp_offset; | |
678 | CORE_ADDR pc; | |
679 | ||
680 | /* Saved registers. */ | |
e53bef9f | 681 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 | 682 | CORE_ADDR saved_sp; |
e0c62198 | 683 | int saved_sp_reg; |
c4f35dd8 MK |
684 | |
685 | /* Do we have a frame? */ | |
686 | int frameless_p; | |
687 | }; | |
8dda9770 | 688 | |
d2449ee8 | 689 | /* Initialize a frame cache. */ |
c4f35dd8 | 690 | |
d2449ee8 DJ |
691 | static void |
692 | amd64_init_frame_cache (struct amd64_frame_cache *cache) | |
8dda9770 | 693 | { |
c4f35dd8 MK |
694 | int i; |
695 | ||
c4f35dd8 MK |
696 | /* Base address. */ |
697 | cache->base = 0; | |
698 | cache->sp_offset = -8; | |
699 | cache->pc = 0; | |
700 | ||
701 | /* Saved registers. We initialize these to -1 since zero is a valid | |
702 | offset (that's where %rbp is supposed to be stored). */ | |
e53bef9f | 703 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
704 | cache->saved_regs[i] = -1; |
705 | cache->saved_sp = 0; | |
e0c62198 | 706 | cache->saved_sp_reg = -1; |
c4f35dd8 MK |
707 | |
708 | /* Frameless until proven otherwise. */ | |
709 | cache->frameless_p = 1; | |
d2449ee8 | 710 | } |
c4f35dd8 | 711 | |
d2449ee8 DJ |
712 | /* Allocate and initialize a frame cache. */ |
713 | ||
714 | static struct amd64_frame_cache * | |
715 | amd64_alloc_frame_cache (void) | |
716 | { | |
717 | struct amd64_frame_cache *cache; | |
718 | ||
719 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); | |
720 | amd64_init_frame_cache (cache); | |
c4f35dd8 | 721 | return cache; |
8dda9770 | 722 | } |
53e95fcf | 723 | |
e0c62198 L |
724 | /* GCC 4.4 and later, can put code in the prologue to realign the |
725 | stack pointer. Check whether PC points to such code, and update | |
726 | CACHE accordingly. Return the first instruction after the code | |
727 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
728 | recognize the code, return PC. */ | |
729 | ||
730 | static CORE_ADDR | |
731 | amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
732 | struct amd64_frame_cache *cache) | |
733 | { | |
734 | /* There are 2 code sequences to re-align stack before the frame | |
735 | gets set up: | |
736 | ||
737 | 1. Use a caller-saved saved register: | |
738 | ||
739 | leaq 8(%rsp), %reg | |
740 | andq $-XXX, %rsp | |
741 | pushq -8(%reg) | |
742 | ||
743 | 2. Use a callee-saved saved register: | |
744 | ||
745 | pushq %reg | |
746 | leaq 16(%rsp), %reg | |
747 | andq $-XXX, %rsp | |
748 | pushq -8(%reg) | |
749 | ||
750 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
751 | ||
752 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp | |
753 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
754 | */ | |
755 | ||
756 | gdb_byte buf[18]; | |
757 | int reg, r; | |
758 | int offset, offset_and; | |
759 | static int regnums[16] = { | |
760 | AMD64_RAX_REGNUM, /* %rax */ | |
761 | AMD64_RCX_REGNUM, /* %rcx */ | |
762 | AMD64_RDX_REGNUM, /* %rdx */ | |
763 | AMD64_RBX_REGNUM, /* %rbx */ | |
764 | AMD64_RSP_REGNUM, /* %rsp */ | |
765 | AMD64_RBP_REGNUM, /* %rbp */ | |
766 | AMD64_RSI_REGNUM, /* %rsi */ | |
767 | AMD64_RDI_REGNUM, /* %rdi */ | |
768 | AMD64_R8_REGNUM, /* %r8 */ | |
769 | AMD64_R9_REGNUM, /* %r9 */ | |
770 | AMD64_R10_REGNUM, /* %r10 */ | |
771 | AMD64_R11_REGNUM, /* %r11 */ | |
772 | AMD64_R12_REGNUM, /* %r12 */ | |
773 | AMD64_R13_REGNUM, /* %r13 */ | |
774 | AMD64_R14_REGNUM, /* %r14 */ | |
775 | AMD64_R15_REGNUM, /* %r15 */ | |
776 | }; | |
777 | ||
778 | if (target_read_memory (pc, buf, sizeof buf)) | |
779 | return pc; | |
780 | ||
781 | /* Check caller-saved saved register. The first instruction has | |
782 | to be "leaq 8(%rsp), %reg". */ | |
783 | if ((buf[0] & 0xfb) == 0x48 | |
784 | && buf[1] == 0x8d | |
785 | && buf[3] == 0x24 | |
786 | && buf[4] == 0x8) | |
787 | { | |
788 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
789 | if ((buf[2] & 0xc7) != 0x44) | |
790 | return pc; | |
791 | ||
792 | /* REG has register number. */ | |
793 | reg = (buf[2] >> 3) & 7; | |
794 | ||
795 | /* Check the REX.R bit. */ | |
796 | if (buf[0] == 0x4c) | |
797 | reg += 8; | |
798 | ||
799 | offset = 5; | |
800 | } | |
801 | else | |
802 | { | |
803 | /* Check callee-saved saved register. The first instruction | |
804 | has to be "pushq %reg". */ | |
805 | reg = 0; | |
806 | if ((buf[0] & 0xf8) == 0x50) | |
807 | offset = 0; | |
808 | else if ((buf[0] & 0xf6) == 0x40 | |
809 | && (buf[1] & 0xf8) == 0x50) | |
810 | { | |
811 | /* Check the REX.B bit. */ | |
812 | if ((buf[0] & 1) != 0) | |
813 | reg = 8; | |
814 | ||
815 | offset = 1; | |
816 | } | |
817 | else | |
818 | return pc; | |
819 | ||
820 | /* Get register. */ | |
821 | reg += buf[offset] & 0x7; | |
822 | ||
823 | offset++; | |
824 | ||
825 | /* The next instruction has to be "leaq 16(%rsp), %reg". */ | |
826 | if ((buf[offset] & 0xfb) != 0x48 | |
827 | || buf[offset + 1] != 0x8d | |
828 | || buf[offset + 3] != 0x24 | |
829 | || buf[offset + 4] != 0x10) | |
830 | return pc; | |
831 | ||
832 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
833 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
834 | return pc; | |
835 | ||
836 | /* REG has register number. */ | |
837 | r = (buf[offset + 2] >> 3) & 7; | |
838 | ||
839 | /* Check the REX.R bit. */ | |
840 | if (buf[offset] == 0x4c) | |
841 | r += 8; | |
842 | ||
843 | /* Registers in pushq and leaq have to be the same. */ | |
844 | if (reg != r) | |
845 | return pc; | |
846 | ||
847 | offset += 5; | |
848 | } | |
849 | ||
850 | /* Rigister can't be %rsp nor %rbp. */ | |
851 | if (reg == 4 || reg == 5) | |
852 | return pc; | |
853 | ||
854 | /* The next instruction has to be "andq $-XXX, %rsp". */ | |
855 | if (buf[offset] != 0x48 | |
856 | || buf[offset + 2] != 0xe4 | |
857 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
858 | return pc; | |
859 | ||
860 | offset_and = offset; | |
861 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
862 | ||
863 | /* The next instruction has to be "pushq -8(%reg)". */ | |
864 | r = 0; | |
865 | if (buf[offset] == 0xff) | |
866 | offset++; | |
867 | else if ((buf[offset] & 0xf6) == 0x40 | |
868 | && buf[offset + 1] == 0xff) | |
869 | { | |
870 | /* Check the REX.B bit. */ | |
871 | if ((buf[offset] & 0x1) != 0) | |
872 | r = 8; | |
873 | offset += 2; | |
874 | } | |
875 | else | |
876 | return pc; | |
877 | ||
878 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
879 | 01. */ | |
880 | if (buf[offset + 1] != 0xf8 | |
881 | || (buf[offset] & 0xf8) != 0x70) | |
882 | return pc; | |
883 | ||
884 | /* R/M has register. */ | |
885 | r += buf[offset] & 7; | |
886 | ||
887 | /* Registers in leaq and pushq have to be the same. */ | |
888 | if (reg != r) | |
889 | return pc; | |
890 | ||
891 | if (current_pc > pc + offset_and) | |
892 | cache->saved_sp_reg = regnums[reg]; | |
893 | ||
894 | return min (pc + offset + 2, current_pc); | |
895 | } | |
896 | ||
c4f35dd8 MK |
897 | /* Do a limited analysis of the prologue at PC and update CACHE |
898 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
899 | address where the analysis stopped. | |
900 | ||
901 | We will handle only functions beginning with: | |
902 | ||
903 | pushq %rbp 0x55 | |
904 | movq %rsp, %rbp 0x48 0x89 0xe5 | |
905 | ||
906 | Any function that doesn't start with this sequence will be assumed | |
907 | to have no prologue and thus no valid frame pointer in %rbp. */ | |
908 | ||
909 | static CORE_ADDR | |
e53bef9f MK |
910 | amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
911 | struct amd64_frame_cache *cache) | |
53e95fcf | 912 | { |
d8de1ef7 MK |
913 | static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ |
914 | gdb_byte buf[3]; | |
915 | gdb_byte op; | |
c4f35dd8 MK |
916 | |
917 | if (current_pc <= pc) | |
918 | return current_pc; | |
919 | ||
e0c62198 L |
920 | pc = amd64_analyze_stack_align (pc, current_pc, cache); |
921 | ||
c4f35dd8 MK |
922 | op = read_memory_unsigned_integer (pc, 1); |
923 | ||
924 | if (op == 0x55) /* pushq %rbp */ | |
925 | { | |
926 | /* Take into account that we've executed the `pushq %rbp' that | |
927 | starts this instruction sequence. */ | |
90f90721 | 928 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
929 | cache->sp_offset += 8; |
930 | ||
931 | /* If that's all, return now. */ | |
932 | if (current_pc <= pc + 1) | |
933 | return current_pc; | |
934 | ||
935 | /* Check for `movq %rsp, %rbp'. */ | |
936 | read_memory (pc + 1, buf, 3); | |
937 | if (memcmp (buf, proto, 3) != 0) | |
938 | return pc + 1; | |
939 | ||
940 | /* OK, we actually have a frame. */ | |
941 | cache->frameless_p = 0; | |
942 | return pc + 4; | |
943 | } | |
944 | ||
945 | return pc; | |
53e95fcf JS |
946 | } |
947 | ||
c4f35dd8 MK |
948 | /* Return PC of first real instruction. */ |
949 | ||
950 | static CORE_ADDR | |
6093d2eb | 951 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
53e95fcf | 952 | { |
e53bef9f | 953 | struct amd64_frame_cache cache; |
c4f35dd8 MK |
954 | CORE_ADDR pc; |
955 | ||
d2449ee8 | 956 | amd64_init_frame_cache (&cache); |
594706e6 | 957 | pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache); |
c4f35dd8 MK |
958 | if (cache.frameless_p) |
959 | return start_pc; | |
960 | ||
961 | return pc; | |
53e95fcf | 962 | } |
c4f35dd8 | 963 | \f |
53e95fcf | 964 | |
c4f35dd8 MK |
965 | /* Normal frames. */ |
966 | ||
e53bef9f | 967 | static struct amd64_frame_cache * |
10458914 | 968 | amd64_frame_cache (struct frame_info *this_frame, void **this_cache) |
6d686a84 | 969 | { |
e53bef9f | 970 | struct amd64_frame_cache *cache; |
d8de1ef7 | 971 | gdb_byte buf[8]; |
6d686a84 | 972 | int i; |
6d686a84 | 973 | |
c4f35dd8 MK |
974 | if (*this_cache) |
975 | return *this_cache; | |
6d686a84 | 976 | |
e53bef9f | 977 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 MK |
978 | *this_cache = cache; |
979 | ||
10458914 | 980 | cache->pc = get_frame_func (this_frame); |
c4f35dd8 | 981 | if (cache->pc != 0) |
10458914 | 982 | amd64_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache); |
c4f35dd8 | 983 | |
e0c62198 L |
984 | if (cache->saved_sp_reg != -1) |
985 | { | |
986 | /* Stack pointer has been saved. */ | |
987 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
988 | cache->saved_sp = extract_unsigned_integer(buf, 8); | |
989 | } | |
990 | ||
c4f35dd8 MK |
991 | if (cache->frameless_p) |
992 | { | |
4a28816e MK |
993 | /* We didn't find a valid frame. If we're at the start of a |
994 | function, or somewhere half-way its prologue, the function's | |
995 | frame probably hasn't been fully setup yet. Try to | |
996 | reconstruct the base address for the stack frame by looking | |
997 | at the stack pointer. For truly "frameless" functions this | |
998 | might work too. */ | |
c4f35dd8 | 999 | |
e0c62198 L |
1000 | if (cache->saved_sp_reg != -1) |
1001 | { | |
1002 | /* We're halfway aligning the stack. */ | |
1003 | cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; | |
1004 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; | |
1005 | ||
1006 | /* This will be added back below. */ | |
1007 | cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; | |
1008 | } | |
1009 | else | |
1010 | { | |
1011 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
1012 | cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; | |
1013 | } | |
c4f35dd8 | 1014 | } |
35883a3f MK |
1015 | else |
1016 | { | |
10458914 | 1017 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
35883a3f MK |
1018 | cache->base = extract_unsigned_integer (buf, 8); |
1019 | } | |
c4f35dd8 MK |
1020 | |
1021 | /* Now that we have the base address for the stack frame we can | |
1022 | calculate the value of %rsp in the calling frame. */ | |
1023 | cache->saved_sp = cache->base + 16; | |
1024 | ||
35883a3f MK |
1025 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
1026 | frame we find it at the same offset from the reconstructed base | |
e0c62198 L |
1027 | address. If we're halfway aligning the stack, %rip is handled |
1028 | differently (see above). */ | |
1029 | if (!cache->frameless_p || cache->saved_sp_reg == -1) | |
1030 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; | |
35883a3f | 1031 | |
c4f35dd8 MK |
1032 | /* Adjust all the saved registers such that they contain addresses |
1033 | instead of offsets. */ | |
e53bef9f | 1034 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
1035 | if (cache->saved_regs[i] != -1) |
1036 | cache->saved_regs[i] += cache->base; | |
1037 | ||
1038 | return cache; | |
6d686a84 ML |
1039 | } |
1040 | ||
c4f35dd8 | 1041 | static void |
10458914 | 1042 | amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
e53bef9f | 1043 | struct frame_id *this_id) |
c4f35dd8 | 1044 | { |
e53bef9f | 1045 | struct amd64_frame_cache *cache = |
10458914 | 1046 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
1047 | |
1048 | /* This marks the outermost frame. */ | |
1049 | if (cache->base == 0) | |
1050 | return; | |
1051 | ||
1052 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
1053 | } | |
e76e1718 | 1054 | |
10458914 DJ |
1055 | static struct value * |
1056 | amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1057 | int regnum) | |
53e95fcf | 1058 | { |
10458914 | 1059 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e53bef9f | 1060 | struct amd64_frame_cache *cache = |
10458914 | 1061 | amd64_frame_cache (this_frame, this_cache); |
e76e1718 | 1062 | |
c4f35dd8 | 1063 | gdb_assert (regnum >= 0); |
b1ab997b | 1064 | |
2ae02b47 | 1065 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
10458914 | 1066 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
e76e1718 | 1067 | |
e53bef9f | 1068 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1069 | return frame_unwind_got_memory (this_frame, regnum, |
1070 | cache->saved_regs[regnum]); | |
e76e1718 | 1071 | |
10458914 | 1072 | return frame_unwind_got_register (this_frame, regnum, regnum); |
c4f35dd8 | 1073 | } |
e76e1718 | 1074 | |
e53bef9f | 1075 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
1076 | { |
1077 | NORMAL_FRAME, | |
e53bef9f | 1078 | amd64_frame_this_id, |
10458914 DJ |
1079 | amd64_frame_prev_register, |
1080 | NULL, | |
1081 | default_frame_sniffer | |
c4f35dd8 | 1082 | }; |
c4f35dd8 | 1083 | \f |
e76e1718 | 1084 | |
c4f35dd8 MK |
1085 | /* Signal trampolines. */ |
1086 | ||
1087 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
1088 | 64-bit variants. This would require using identical frame caches | |
1089 | on both platforms. */ | |
1090 | ||
e53bef9f | 1091 | static struct amd64_frame_cache * |
10458914 | 1092 | amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 1093 | { |
e53bef9f | 1094 | struct amd64_frame_cache *cache; |
10458914 | 1095 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
c4f35dd8 | 1096 | CORE_ADDR addr; |
d8de1ef7 | 1097 | gdb_byte buf[8]; |
2b5e0749 | 1098 | int i; |
c4f35dd8 MK |
1099 | |
1100 | if (*this_cache) | |
1101 | return *this_cache; | |
1102 | ||
e53bef9f | 1103 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 1104 | |
10458914 | 1105 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
1106 | cache->base = extract_unsigned_integer (buf, 8) - 8; |
1107 | ||
10458914 | 1108 | addr = tdep->sigcontext_addr (this_frame); |
2b5e0749 | 1109 | gdb_assert (tdep->sc_reg_offset); |
e53bef9f | 1110 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); |
2b5e0749 MK |
1111 | for (i = 0; i < tdep->sc_num_regs; i++) |
1112 | if (tdep->sc_reg_offset[i] != -1) | |
1113 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 MK |
1114 | |
1115 | *this_cache = cache; | |
1116 | return cache; | |
53e95fcf JS |
1117 | } |
1118 | ||
c4f35dd8 | 1119 | static void |
10458914 | 1120 | amd64_sigtramp_frame_this_id (struct frame_info *this_frame, |
e53bef9f | 1121 | void **this_cache, struct frame_id *this_id) |
c4f35dd8 | 1122 | { |
e53bef9f | 1123 | struct amd64_frame_cache *cache = |
10458914 | 1124 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 1125 | |
10458914 | 1126 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); |
c4f35dd8 MK |
1127 | } |
1128 | ||
10458914 DJ |
1129 | static struct value * |
1130 | amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1131 | void **this_cache, int regnum) | |
c4f35dd8 MK |
1132 | { |
1133 | /* Make sure we've initialized the cache. */ | |
10458914 | 1134 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 1135 | |
10458914 | 1136 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
c4f35dd8 MK |
1137 | } |
1138 | ||
10458914 DJ |
1139 | static int |
1140 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1141 | struct frame_info *this_frame, | |
1142 | void **this_cache) | |
c4f35dd8 | 1143 | { |
10458914 | 1144 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
911bc6ee MK |
1145 | |
1146 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
1147 | handler. */ | |
1148 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1149 | return 0; |
911bc6ee MK |
1150 | |
1151 | if (tdep->sigtramp_p != NULL) | |
1152 | { | |
10458914 DJ |
1153 | if (tdep->sigtramp_p (this_frame)) |
1154 | return 1; | |
911bc6ee | 1155 | } |
c4f35dd8 | 1156 | |
911bc6ee | 1157 | if (tdep->sigtramp_start != 0) |
1c3545ae | 1158 | { |
10458914 | 1159 | CORE_ADDR pc = get_frame_pc (this_frame); |
1c3545ae | 1160 | |
911bc6ee MK |
1161 | gdb_assert (tdep->sigtramp_end != 0); |
1162 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1163 | return 1; |
1c3545ae | 1164 | } |
c4f35dd8 | 1165 | |
10458914 | 1166 | return 0; |
c4f35dd8 | 1167 | } |
10458914 DJ |
1168 | |
1169 | static const struct frame_unwind amd64_sigtramp_frame_unwind = | |
1170 | { | |
1171 | SIGTRAMP_FRAME, | |
1172 | amd64_sigtramp_frame_this_id, | |
1173 | amd64_sigtramp_frame_prev_register, | |
1174 | NULL, | |
1175 | amd64_sigtramp_frame_sniffer | |
1176 | }; | |
c4f35dd8 MK |
1177 | \f |
1178 | ||
1179 | static CORE_ADDR | |
10458914 | 1180 | amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 1181 | { |
e53bef9f | 1182 | struct amd64_frame_cache *cache = |
10458914 | 1183 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
1184 | |
1185 | return cache->base; | |
1186 | } | |
1187 | ||
e53bef9f | 1188 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 1189 | { |
e53bef9f MK |
1190 | &amd64_frame_unwind, |
1191 | amd64_frame_base_address, | |
1192 | amd64_frame_base_address, | |
1193 | amd64_frame_base_address | |
c4f35dd8 MK |
1194 | }; |
1195 | ||
166f4c7b | 1196 | static struct frame_id |
10458914 | 1197 | amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
166f4c7b | 1198 | { |
c4f35dd8 MK |
1199 | CORE_ADDR fp; |
1200 | ||
10458914 | 1201 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
c4f35dd8 | 1202 | |
10458914 | 1203 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
166f4c7b ML |
1204 | } |
1205 | ||
8b148df9 AC |
1206 | /* 16 byte align the SP per frame requirements. */ |
1207 | ||
1208 | static CORE_ADDR | |
e53bef9f | 1209 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
1210 | { |
1211 | return sp & -(CORE_ADDR)16; | |
1212 | } | |
473f17b0 MK |
1213 | \f |
1214 | ||
593adc23 MK |
1215 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
1216 | in the floating-point register set REGSET to register cache | |
1217 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
1218 | |
1219 | static void | |
e53bef9f MK |
1220 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
1221 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 1222 | { |
9ea75c57 | 1223 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 MK |
1224 | |
1225 | gdb_assert (len == tdep->sizeof_fpregset); | |
90f90721 | 1226 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 1227 | } |
8b148df9 | 1228 | |
593adc23 MK |
1229 | /* Collect register REGNUM from the register cache REGCACHE and store |
1230 | it in the buffer specified by FPREGS and LEN as described by the | |
1231 | floating-point register set REGSET. If REGNUM is -1, do this for | |
1232 | all registers in REGSET. */ | |
1233 | ||
1234 | static void | |
1235 | amd64_collect_fpregset (const struct regset *regset, | |
1236 | const struct regcache *regcache, | |
1237 | int regnum, void *fpregs, size_t len) | |
1238 | { | |
1239 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1240 | ||
1241 | gdb_assert (len == tdep->sizeof_fpregset); | |
1242 | amd64_collect_fxsave (regcache, regnum, fpregs); | |
1243 | } | |
1244 | ||
c6b33596 MK |
1245 | /* Return the appropriate register set for the core section identified |
1246 | by SECT_NAME and SECT_SIZE. */ | |
1247 | ||
1248 | static const struct regset * | |
e53bef9f MK |
1249 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
1250 | const char *sect_name, size_t sect_size) | |
c6b33596 MK |
1251 | { |
1252 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1253 | ||
1254 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
1255 | { | |
1256 | if (tdep->fpregset == NULL) | |
593adc23 MK |
1257 | tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, |
1258 | amd64_collect_fpregset); | |
c6b33596 MK |
1259 | |
1260 | return tdep->fpregset; | |
1261 | } | |
1262 | ||
1263 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); | |
1264 | } | |
1265 | \f | |
1266 | ||
436675d3 PA |
1267 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
1268 | %rdi. We expect its value to be a pointer to the jmp_buf structure | |
1269 | from which we extract the address that we will land at. This | |
1270 | address is copied into PC. This routine returns non-zero on | |
1271 | success. */ | |
1272 | ||
1273 | static int | |
1274 | amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1275 | { | |
1276 | gdb_byte buf[8]; | |
1277 | CORE_ADDR jb_addr; | |
1278 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1279 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
0dfff4cb | 1280 | int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
1281 | |
1282 | /* If JB_PC_OFFSET is -1, we have no way to find out where the | |
1283 | longjmp will land. */ | |
1284 | if (jb_pc_offset == -1) | |
1285 | return 0; | |
1286 | ||
1287 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); | |
0dfff4cb UW |
1288 | jb_addr= extract_typed_address |
1289 | (buf, builtin_type (gdbarch)->builtin_data_ptr); | |
436675d3 PA |
1290 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
1291 | return 0; | |
1292 | ||
0dfff4cb | 1293 | *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
1294 | |
1295 | return 1; | |
1296 | } | |
1297 | ||
2213a65d | 1298 | void |
90f90721 | 1299 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 1300 | { |
0c1a73d6 | 1301 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53e95fcf | 1302 | |
473f17b0 MK |
1303 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
1304 | floating-point registers. */ | |
1305 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
1306 | ||
5716833c | 1307 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 1308 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 1309 | tdep->num_xmm_regs = 16; |
53e95fcf | 1310 | |
0c1a73d6 | 1311 | /* This is what all the fuss is about. */ |
53e95fcf JS |
1312 | set_gdbarch_long_bit (gdbarch, 64); |
1313 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1314 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1315 | ||
e53bef9f MK |
1316 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
1317 | up 128 bits, even though it's still based on the i387 extended | |
1318 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
1319 | set_gdbarch_long_double_bit (gdbarch, 128); |
1320 | ||
e53bef9f MK |
1321 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
1322 | set_gdbarch_register_name (gdbarch, amd64_register_name); | |
1323 | set_gdbarch_register_type (gdbarch, amd64_register_type); | |
b83b026c MK |
1324 | |
1325 | /* Register numbers of various important registers. */ | |
90f90721 MK |
1326 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
1327 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
1328 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
1329 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 1330 | |
e53bef9f MK |
1331 | /* The "default" register numbering scheme for AMD64 is referred to |
1332 | as the "DWARF Register Number Mapping" in the System V psABI. | |
1333 | The preferred debugging format for all known AMD64 targets is | |
1334 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
1335 | DWARF-1), but we provide the same mapping just in case. This | |
1336 | mapping is also used for stabs, which GCC does support. */ | |
1337 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
e53bef9f | 1338 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
de220d0f | 1339 | |
c4f35dd8 | 1340 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 1341 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 1342 | |
c4f35dd8 | 1343 | /* Call dummy code. */ |
e53bef9f MK |
1344 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
1345 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 1346 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 1347 | |
83acabca | 1348 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
d532c08f MK |
1349 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
1350 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
1351 | ||
efb1c01c | 1352 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 1353 | |
e53bef9f | 1354 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 1355 | |
c4f35dd8 | 1356 | /* Avoid wiring in the MMX registers for now. */ |
2213a65d | 1357 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
5716833c | 1358 | tdep->mm0_regnum = -1; |
2213a65d | 1359 | |
10458914 | 1360 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
53e95fcf | 1361 | |
10458914 DJ |
1362 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
1363 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); | |
e53bef9f | 1364 | frame_base_set_default (gdbarch, &amd64_frame_base); |
c6b33596 MK |
1365 | |
1366 | /* If we have a register mapping, enable the generic core file support. */ | |
1367 | if (tdep->gregset_reg_offset) | |
1368 | set_gdbarch_regset_from_core_section (gdbarch, | |
e53bef9f | 1369 | amd64_regset_from_core_section); |
436675d3 PA |
1370 | |
1371 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); | |
c4f35dd8 MK |
1372 | } |
1373 | \f | |
1374 | ||
41d041d6 MK |
1375 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
1376 | sense that the instruction pointer and data pointer are simply | |
1377 | 64-bit offsets into the code segment and the data segment instead | |
1378 | of a selector offset pair. The functions below store the upper 32 | |
1379 | bits of these pointers (instead of just the 16-bits of the segment | |
1380 | selector). */ | |
1381 | ||
1382 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
1383 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
1384 | -1, do this for all registers. This function masks off any of the | |
1385 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
1386 | |
1387 | void | |
90f90721 | 1388 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
20a6ec49 | 1389 | const void *fxsave) |
c4f35dd8 | 1390 | { |
20a6ec49 MD |
1391 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1392 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1393 | ||
41d041d6 | 1394 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 1395 | |
20a6ec49 | 1396 | if (fxsave && gdbarch_ptr_bit (gdbarch) == 64) |
c4f35dd8 | 1397 | { |
d8de1ef7 | 1398 | const gdb_byte *regs = fxsave; |
41d041d6 | 1399 | |
20a6ec49 MD |
1400 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
1401 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
1402 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
1403 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
c4f35dd8 | 1404 | } |
0c1a73d6 MK |
1405 | } |
1406 | ||
3c017e40 MK |
1407 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
1408 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
1409 | all registers. This function doesn't touch any of the reserved | |
1410 | bits in *FXSAVE. */ | |
1411 | ||
1412 | void | |
1413 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
1414 | void *fxsave) | |
1415 | { | |
20a6ec49 MD |
1416 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1417 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
d8de1ef7 | 1418 | gdb_byte *regs = fxsave; |
3c017e40 MK |
1419 | |
1420 | i387_collect_fxsave (regcache, regnum, fxsave); | |
1421 | ||
20a6ec49 | 1422 | if (gdbarch_ptr_bit (gdbarch) == 64) |
f0ef85a5 | 1423 | { |
20a6ec49 MD |
1424 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
1425 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
1426 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
1427 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
f0ef85a5 | 1428 | } |
3c017e40 | 1429 | } |