Commit | Line | Data |
---|---|---|
e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
0fd88904 AC |
3 | Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, |
4 | Inc. Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
c4f35dd8 MK |
24 | #include "arch-utils.h" |
25 | #include "block.h" | |
26 | #include "dummy-frame.h" | |
27 | #include "frame.h" | |
28 | #include "frame-base.h" | |
29 | #include "frame-unwind.h" | |
53e95fcf | 30 | #include "inferior.h" |
53e95fcf | 31 | #include "gdbcmd.h" |
c4f35dd8 MK |
32 | #include "gdbcore.h" |
33 | #include "objfiles.h" | |
53e95fcf | 34 | #include "regcache.h" |
2c261fae | 35 | #include "regset.h" |
53e95fcf | 36 | #include "symfile.h" |
c4f35dd8 | 37 | |
82dbc5f7 | 38 | #include "gdb_assert.h" |
c4f35dd8 | 39 | |
9c1488cb | 40 | #include "amd64-tdep.h" |
c4f35dd8 | 41 | #include "i387-tdep.h" |
53e95fcf | 42 | |
e53bef9f MK |
43 | /* Note that the AMD64 architecture was previously known as x86-64. |
44 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 45 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
46 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
47 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
48 | x86_64_-prefix since it's so much easier to type. */ | |
49 | ||
402ecd56 | 50 | /* Register information. */ |
c4f35dd8 | 51 | |
e53bef9f | 52 | struct amd64_register_info |
de220d0f | 53 | { |
de220d0f ML |
54 | char *name; |
55 | struct type **type; | |
56 | }; | |
53e95fcf | 57 | |
2f4535c7 DJ |
58 | static struct type *amd64_sse_type; |
59 | ||
60 | static struct amd64_register_info const amd64_register_info[] = | |
c4f35dd8 MK |
61 | { |
62 | { "rax", &builtin_type_int64 }, | |
63 | { "rbx", &builtin_type_int64 }, | |
64 | { "rcx", &builtin_type_int64 }, | |
65 | { "rdx", &builtin_type_int64 }, | |
66 | { "rsi", &builtin_type_int64 }, | |
67 | { "rdi", &builtin_type_int64 }, | |
68 | { "rbp", &builtin_type_void_data_ptr }, | |
69 | { "rsp", &builtin_type_void_data_ptr }, | |
70 | ||
71 | /* %r8 is indeed register number 8. */ | |
72 | { "r8", &builtin_type_int64 }, | |
73 | { "r9", &builtin_type_int64 }, | |
74 | { "r10", &builtin_type_int64 }, | |
75 | { "r11", &builtin_type_int64 }, | |
76 | { "r12", &builtin_type_int64 }, | |
77 | { "r13", &builtin_type_int64 }, | |
78 | { "r14", &builtin_type_int64 }, | |
79 | { "r15", &builtin_type_int64 }, | |
80 | { "rip", &builtin_type_void_func_ptr }, | |
81 | { "eflags", &builtin_type_int32 }, | |
af233647 MK |
82 | { "cs", &builtin_type_int32 }, |
83 | { "ss", &builtin_type_int32 }, | |
c4f35dd8 MK |
84 | { "ds", &builtin_type_int32 }, |
85 | { "es", &builtin_type_int32 }, | |
86 | { "fs", &builtin_type_int32 }, | |
87 | { "gs", &builtin_type_int32 }, | |
88 | ||
af233647 | 89 | /* %st0 is register number 24. */ |
c4f35dd8 MK |
90 | { "st0", &builtin_type_i387_ext }, |
91 | { "st1", &builtin_type_i387_ext }, | |
92 | { "st2", &builtin_type_i387_ext }, | |
93 | { "st3", &builtin_type_i387_ext }, | |
94 | { "st4", &builtin_type_i387_ext }, | |
95 | { "st5", &builtin_type_i387_ext }, | |
96 | { "st6", &builtin_type_i387_ext }, | |
97 | { "st7", &builtin_type_i387_ext }, | |
98 | { "fctrl", &builtin_type_int32 }, | |
99 | { "fstat", &builtin_type_int32 }, | |
100 | { "ftag", &builtin_type_int32 }, | |
101 | { "fiseg", &builtin_type_int32 }, | |
102 | { "fioff", &builtin_type_int32 }, | |
103 | { "foseg", &builtin_type_int32 }, | |
104 | { "fooff", &builtin_type_int32 }, | |
105 | { "fop", &builtin_type_int32 }, | |
106 | ||
af233647 | 107 | /* %xmm0 is register number 40. */ |
2f4535c7 DJ |
108 | { "xmm0", &amd64_sse_type }, |
109 | { "xmm1", &amd64_sse_type }, | |
110 | { "xmm2", &amd64_sse_type }, | |
111 | { "xmm3", &amd64_sse_type }, | |
112 | { "xmm4", &amd64_sse_type }, | |
113 | { "xmm5", &amd64_sse_type }, | |
114 | { "xmm6", &amd64_sse_type }, | |
115 | { "xmm7", &amd64_sse_type }, | |
116 | { "xmm8", &amd64_sse_type }, | |
117 | { "xmm9", &amd64_sse_type }, | |
118 | { "xmm10", &amd64_sse_type }, | |
119 | { "xmm11", &amd64_sse_type }, | |
120 | { "xmm12", &amd64_sse_type }, | |
121 | { "xmm13", &amd64_sse_type }, | |
122 | { "xmm14", &amd64_sse_type }, | |
123 | { "xmm15", &amd64_sse_type }, | |
c4f35dd8 | 124 | { "mxcsr", &builtin_type_int32 } |
0e04a514 ML |
125 | }; |
126 | ||
c4f35dd8 | 127 | /* Total number of registers. */ |
e53bef9f MK |
128 | #define AMD64_NUM_REGS \ |
129 | (sizeof (amd64_register_info) / sizeof (amd64_register_info[0])) | |
de220d0f | 130 | |
c4f35dd8 | 131 | /* Return the name of register REGNUM. */ |
b6779aa2 | 132 | |
c4f35dd8 | 133 | static const char * |
e53bef9f | 134 | amd64_register_name (int regnum) |
53e95fcf | 135 | { |
e53bef9f MK |
136 | if (regnum >= 0 && regnum < AMD64_NUM_REGS) |
137 | return amd64_register_info[regnum].name; | |
53e95fcf | 138 | |
c4f35dd8 | 139 | return NULL; |
53e95fcf JS |
140 | } |
141 | ||
142 | /* Return the GDB type object for the "standard" data type of data in | |
c4f35dd8 | 143 | register REGNUM. */ |
53e95fcf | 144 | |
c4f35dd8 | 145 | static struct type * |
e53bef9f | 146 | amd64_register_type (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 147 | { |
2f4535c7 DJ |
148 | struct type *t; |
149 | ||
e53bef9f | 150 | gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS); |
4657573b | 151 | |
2f4535c7 DJ |
152 | /* ??? Unfortunately, amd64_init_abi is called too early, and so we |
153 | cannot create the amd64_sse_type early enough to avoid any check | |
154 | at this point. */ | |
155 | t = *amd64_register_info[regnum].type; | |
156 | if (t != NULL) | |
157 | return t; | |
158 | ||
159 | gdb_assert (amd64_sse_type == NULL); | |
160 | ||
161 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
162 | append_composite_type_field (t, "v4_float", builtin_type_v4_float); | |
163 | append_composite_type_field (t, "v2_double", builtin_type_v2_double); | |
164 | append_composite_type_field (t, "v16_int8", builtin_type_v16_int8); | |
165 | append_composite_type_field (t, "v8_int16", builtin_type_v8_int16); | |
166 | append_composite_type_field (t, "v4_int32", builtin_type_v4_int32); | |
167 | append_composite_type_field (t, "v2_int64", builtin_type_v2_int64); | |
168 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
169 | ||
170 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
171 | TYPE_NAME (t) = "builtin_type_vec128i"; | |
172 | ||
173 | amd64_sse_type = t; | |
174 | return t; | |
53e95fcf JS |
175 | } |
176 | ||
c4f35dd8 MK |
177 | /* DWARF Register Number Mapping as defined in the System V psABI, |
178 | section 3.6. */ | |
53e95fcf | 179 | |
e53bef9f | 180 | static int amd64_dwarf_regmap[] = |
0e04a514 | 181 | { |
c4f35dd8 | 182 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
183 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
184 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
185 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
186 | |
187 | /* Frame Pointer Register RBP. */ | |
90f90721 | 188 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
189 | |
190 | /* Stack Pointer Register RSP. */ | |
90f90721 | 191 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
192 | |
193 | /* Extended Integer Registers 8 - 15. */ | |
194 | 8, 9, 10, 11, 12, 13, 14, 15, | |
195 | ||
59207364 | 196 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 197 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
198 | |
199 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
200 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
201 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
202 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
203 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
204 | |
205 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
206 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
207 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
208 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
209 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
210 | |
211 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
212 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
213 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
214 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 JB |
215 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
216 | ||
217 | /* Control and Status Flags Register. */ | |
218 | AMD64_EFLAGS_REGNUM, | |
219 | ||
220 | /* Selector Registers. */ | |
221 | AMD64_ES_REGNUM, | |
222 | AMD64_CS_REGNUM, | |
223 | AMD64_SS_REGNUM, | |
224 | AMD64_DS_REGNUM, | |
225 | AMD64_FS_REGNUM, | |
226 | AMD64_GS_REGNUM, | |
227 | -1, | |
228 | -1, | |
229 | ||
230 | /* Segment Base Address Registers. */ | |
231 | -1, | |
232 | -1, | |
233 | -1, | |
234 | -1, | |
235 | ||
236 | /* Special Selector Registers. */ | |
237 | -1, | |
238 | -1, | |
239 | ||
240 | /* Floating Point Control Registers. */ | |
241 | AMD64_MXCSR_REGNUM, | |
242 | AMD64_FCTRL_REGNUM, | |
243 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 244 | }; |
0e04a514 | 245 | |
e53bef9f MK |
246 | static const int amd64_dwarf_regmap_len = |
247 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 248 | |
c4f35dd8 MK |
249 | /* Convert DWARF register number REG to the appropriate register |
250 | number used by GDB. */ | |
26abbdc4 | 251 | |
c4f35dd8 | 252 | static int |
e53bef9f | 253 | amd64_dwarf_reg_to_regnum (int reg) |
53e95fcf | 254 | { |
c4f35dd8 | 255 | int regnum = -1; |
53e95fcf | 256 | |
16aff9a6 | 257 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 258 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 259 | |
c4f35dd8 | 260 | if (regnum == -1) |
8a3fe4f8 | 261 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
c4f35dd8 MK |
262 | |
263 | return regnum; | |
53e95fcf | 264 | } |
d532c08f MK |
265 | |
266 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
267 | needs any special handling. */ | |
268 | ||
269 | static int | |
e53bef9f | 270 | amd64_convert_register_p (int regnum, struct type *type) |
d532c08f MK |
271 | { |
272 | return i386_fp_regnum_p (regnum); | |
273 | } | |
53e95fcf JS |
274 | \f |
275 | ||
efb1c01c MK |
276 | /* Register classes as defined in the psABI. */ |
277 | ||
278 | enum amd64_reg_class | |
279 | { | |
280 | AMD64_INTEGER, | |
281 | AMD64_SSE, | |
282 | AMD64_SSEUP, | |
283 | AMD64_X87, | |
284 | AMD64_X87UP, | |
285 | AMD64_COMPLEX_X87, | |
286 | AMD64_NO_CLASS, | |
287 | AMD64_MEMORY | |
288 | }; | |
289 | ||
290 | /* Return the union class of CLASS1 and CLASS2. See the psABI for | |
291 | details. */ | |
292 | ||
293 | static enum amd64_reg_class | |
294 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
295 | { | |
296 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
297 | if (class1 == class2) | |
298 | return class1; | |
299 | ||
300 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
301 | is the other class. */ | |
302 | if (class1 == AMD64_NO_CLASS) | |
303 | return class2; | |
304 | if (class2 == AMD64_NO_CLASS) | |
305 | return class1; | |
306 | ||
307 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
308 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
309 | return AMD64_MEMORY; | |
310 | ||
311 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
312 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
313 | return AMD64_INTEGER; | |
314 | ||
315 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
316 | MEMORY is used as class. */ | |
317 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
318 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
319 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
320 | return AMD64_MEMORY; | |
321 | ||
322 | /* Rule (f): Otherwise class SSE is used. */ | |
323 | return AMD64_SSE; | |
324 | } | |
325 | ||
326 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); | |
327 | ||
79b1ab3d MK |
328 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
329 | ||
330 | static int | |
331 | amd64_non_pod_p (struct type *type) | |
332 | { | |
333 | /* ??? A class with a base class certainly isn't POD, but does this | |
334 | catch all non-POD structure types? */ | |
335 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
336 | return 1; | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
efb1c01c MK |
341 | /* Classify TYPE according to the rules for aggregate (structures and |
342 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
343 | |
344 | static void | |
efb1c01c | 345 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
53e95fcf JS |
346 | { |
347 | int len = TYPE_LENGTH (type); | |
348 | ||
efb1c01c MK |
349 | /* 1. If the size of an object is larger than two eightbytes, or in |
350 | C++, is a non-POD structure or union type, or contains | |
351 | unaligned fields, it has class memory. */ | |
79b1ab3d | 352 | if (len > 16 || amd64_non_pod_p (type)) |
53e95fcf | 353 | { |
efb1c01c MK |
354 | class[0] = class[1] = AMD64_MEMORY; |
355 | return; | |
53e95fcf | 356 | } |
efb1c01c MK |
357 | |
358 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
359 | class[0] = class[1] = AMD64_NO_CLASS; | |
360 | ||
361 | /* 3. Each field of an object is classified recursively so that | |
362 | always two fields are considered. The resulting class is | |
363 | calculated according to the classes of the fields in the | |
364 | eightbyte: */ | |
365 | ||
366 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 367 | { |
efb1c01c MK |
368 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
369 | ||
370 | /* All fields in an array have the same type. */ | |
371 | amd64_classify (subtype, class); | |
372 | if (len > 8 && class[1] == AMD64_NO_CLASS) | |
373 | class[1] = class[0]; | |
8ffd9b1b | 374 | } |
53e95fcf JS |
375 | else |
376 | { | |
efb1c01c | 377 | int i; |
53e95fcf | 378 | |
efb1c01c MK |
379 | /* Structure or union. */ |
380 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
381 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
382 | ||
383 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 384 | { |
efb1c01c MK |
385 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
386 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
387 | enum amd64_reg_class subclass[2]; | |
388 | ||
562c50c2 MK |
389 | /* Ignore static fields. */ |
390 | if (TYPE_FIELD_STATIC (type, i)) | |
391 | continue; | |
392 | ||
efb1c01c MK |
393 | gdb_assert (pos == 0 || pos == 1); |
394 | ||
395 | amd64_classify (subtype, subclass); | |
396 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); | |
397 | if (pos == 0) | |
398 | class[1] = amd64_merge_classes (class[1], subclass[1]); | |
53e95fcf | 399 | } |
53e95fcf | 400 | } |
efb1c01c MK |
401 | |
402 | /* 4. Then a post merger cleanup is done: */ | |
403 | ||
404 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
405 | passed in memory. */ | |
406 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) | |
407 | class[0] = class[1] = AMD64_MEMORY; | |
408 | ||
409 | /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to | |
410 | SSE. */ | |
411 | if (class[0] == AMD64_SSEUP) | |
412 | class[0] = AMD64_SSE; | |
413 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) | |
414 | class[1] = AMD64_SSE; | |
415 | } | |
416 | ||
417 | /* Classify TYPE, and store the result in CLASS. */ | |
418 | ||
419 | static void | |
420 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) | |
421 | { | |
422 | enum type_code code = TYPE_CODE (type); | |
423 | int len = TYPE_LENGTH (type); | |
424 | ||
425 | class[0] = class[1] = AMD64_NO_CLASS; | |
426 | ||
427 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
428 | long, long long, and pointers are in the INTEGER class. Similarly, |
429 | range types, used by languages such as Ada, are also in the INTEGER | |
430 | class. */ | |
efb1c01c | 431 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
5a7225ed | 432 | || code == TYPE_CODE_RANGE |
efb1c01c MK |
433 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
434 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
435 | class[0] = AMD64_INTEGER; | |
436 | ||
437 | /* Arguments of types float, double and __m64 are in class SSE. */ | |
438 | else if (code == TYPE_CODE_FLT && (len == 4 || len == 8)) | |
439 | /* FIXME: __m64 . */ | |
440 | class[0] = AMD64_SSE; | |
441 | ||
442 | /* Arguments of types __float128 and __m128 are split into two | |
443 | halves. The least significant ones belong to class SSE, the most | |
444 | significant one to class SSEUP. */ | |
445 | /* FIXME: __float128, __m128. */ | |
446 | ||
447 | /* The 64-bit mantissa of arguments of type long double belongs to | |
448 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
449 | class X87UP. */ | |
450 | else if (code == TYPE_CODE_FLT && len == 16) | |
451 | /* Class X87 and X87UP. */ | |
452 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; | |
453 | ||
454 | /* Aggregates. */ | |
455 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
456 | || code == TYPE_CODE_UNION) | |
457 | amd64_classify_aggregate (type, class); | |
458 | } | |
459 | ||
460 | static enum return_value_convention | |
461 | amd64_return_value (struct gdbarch *gdbarch, struct type *type, | |
462 | struct regcache *regcache, | |
42835c2b | 463 | gdb_byte *readbuf, const gdb_byte *writebuf) |
efb1c01c MK |
464 | { |
465 | enum amd64_reg_class class[2]; | |
466 | int len = TYPE_LENGTH (type); | |
90f90721 MK |
467 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
468 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
469 | int integer_reg = 0; |
470 | int sse_reg = 0; | |
471 | int i; | |
472 | ||
473 | gdb_assert (!(readbuf && writebuf)); | |
474 | ||
475 | /* 1. Classify the return type with the classification algorithm. */ | |
476 | amd64_classify (type, class); | |
477 | ||
478 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d MK |
479 | for the return value and passes the address of this storage in |
480 | %rdi as if it were the first argument to the function. In effect, | |
481 | this address becomes a hidden first argument. | |
482 | ||
483 | On return %rax will contain the address that has been passed in | |
484 | by the caller in %rdi. */ | |
efb1c01c | 485 | if (class[0] == AMD64_MEMORY) |
6fa57a7d MK |
486 | { |
487 | /* As indicated by the comment above, the ABI guarantees that we | |
488 | can always find the return value just after the function has | |
489 | returned. */ | |
490 | ||
491 | if (readbuf) | |
492 | { | |
493 | ULONGEST addr; | |
494 | ||
495 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
496 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
497 | } | |
498 | ||
499 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
500 | } | |
efb1c01c MK |
501 | |
502 | gdb_assert (class[1] != AMD64_MEMORY); | |
503 | gdb_assert (len <= 16); | |
504 | ||
505 | for (i = 0; len > 0; i++, len -= 8) | |
506 | { | |
507 | int regnum = -1; | |
508 | int offset = 0; | |
509 | ||
510 | switch (class[i]) | |
511 | { | |
512 | case AMD64_INTEGER: | |
513 | /* 3. If the class is INTEGER, the next available register | |
514 | of the sequence %rax, %rdx is used. */ | |
515 | regnum = integer_regnum[integer_reg++]; | |
516 | break; | |
517 | ||
518 | case AMD64_SSE: | |
519 | /* 4. If the class is SSE, the next available SSE register | |
520 | of the sequence %xmm0, %xmm1 is used. */ | |
521 | regnum = sse_regnum[sse_reg++]; | |
522 | break; | |
523 | ||
524 | case AMD64_SSEUP: | |
525 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
526 | upper half of the last used SSE register. */ | |
527 | gdb_assert (sse_reg > 0); | |
528 | regnum = sse_regnum[sse_reg - 1]; | |
529 | offset = 8; | |
530 | break; | |
531 | ||
532 | case AMD64_X87: | |
533 | /* 6. If the class is X87, the value is returned on the X87 | |
534 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 535 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
536 | if (writebuf) |
537 | i387_return_value (gdbarch, regcache); | |
538 | break; | |
539 | ||
540 | case AMD64_X87UP: | |
541 | /* 7. If the class is X87UP, the value is returned together | |
542 | with the previous X87 value in %st0. */ | |
543 | gdb_assert (i > 0 && class[0] == AMD64_X87); | |
90f90721 | 544 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
545 | offset = 8; |
546 | len = 2; | |
547 | break; | |
548 | ||
549 | case AMD64_NO_CLASS: | |
550 | continue; | |
551 | ||
552 | default: | |
553 | gdb_assert (!"Unexpected register class."); | |
554 | } | |
555 | ||
556 | gdb_assert (regnum != -1); | |
557 | ||
558 | if (readbuf) | |
559 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 560 | readbuf + i * 8); |
efb1c01c MK |
561 | if (writebuf) |
562 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 563 | writebuf + i * 8); |
efb1c01c MK |
564 | } |
565 | ||
566 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
567 | } |
568 | \f | |
569 | ||
720aa428 MK |
570 | static CORE_ADDR |
571 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 572 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 MK |
573 | { |
574 | static int integer_regnum[] = | |
575 | { | |
90f90721 MK |
576 | AMD64_RDI_REGNUM, /* %rdi */ |
577 | AMD64_RSI_REGNUM, /* %rsi */ | |
578 | AMD64_RDX_REGNUM, /* %rdx */ | |
579 | AMD64_RCX_REGNUM, /* %rcx */ | |
580 | 8, /* %r8 */ | |
581 | 9 /* %r9 */ | |
720aa428 MK |
582 | }; |
583 | static int sse_regnum[] = | |
584 | { | |
585 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
586 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
587 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
588 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
589 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 MK |
590 | }; |
591 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); | |
592 | int num_stack_args = 0; | |
593 | int num_elements = 0; | |
594 | int element = 0; | |
595 | int integer_reg = 0; | |
596 | int sse_reg = 0; | |
597 | int i; | |
598 | ||
6470d250 MK |
599 | /* Reserve a register for the "hidden" argument. */ |
600 | if (struct_return) | |
601 | integer_reg++; | |
602 | ||
720aa428 MK |
603 | for (i = 0; i < nargs; i++) |
604 | { | |
4991999e | 605 | struct type *type = value_type (args[i]); |
720aa428 MK |
606 | int len = TYPE_LENGTH (type); |
607 | enum amd64_reg_class class[2]; | |
608 | int needed_integer_regs = 0; | |
609 | int needed_sse_regs = 0; | |
610 | int j; | |
611 | ||
612 | /* Classify argument. */ | |
613 | amd64_classify (type, class); | |
614 | ||
615 | /* Calculate the number of integer and SSE registers needed for | |
616 | this argument. */ | |
617 | for (j = 0; j < 2; j++) | |
618 | { | |
619 | if (class[j] == AMD64_INTEGER) | |
620 | needed_integer_regs++; | |
621 | else if (class[j] == AMD64_SSE) | |
622 | needed_sse_regs++; | |
623 | } | |
624 | ||
625 | /* Check whether enough registers are available, and if the | |
626 | argument should be passed in registers at all. */ | |
627 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) | |
628 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) | |
629 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
630 | { | |
631 | /* The argument will be passed on the stack. */ | |
632 | num_elements += ((len + 7) / 8); | |
633 | stack_args[num_stack_args++] = args[i]; | |
634 | } | |
635 | else | |
636 | { | |
637 | /* The argument will be passed in registers. */ | |
d8de1ef7 MK |
638 | const gdb_byte *valbuf = value_contents (args[i]); |
639 | gdb_byte buf[8]; | |
720aa428 MK |
640 | |
641 | gdb_assert (len <= 16); | |
642 | ||
643 | for (j = 0; len > 0; j++, len -= 8) | |
644 | { | |
645 | int regnum = -1; | |
646 | int offset = 0; | |
647 | ||
648 | switch (class[j]) | |
649 | { | |
650 | case AMD64_INTEGER: | |
651 | regnum = integer_regnum[integer_reg++]; | |
652 | break; | |
653 | ||
654 | case AMD64_SSE: | |
655 | regnum = sse_regnum[sse_reg++]; | |
656 | break; | |
657 | ||
658 | case AMD64_SSEUP: | |
659 | gdb_assert (sse_reg > 0); | |
660 | regnum = sse_regnum[sse_reg - 1]; | |
661 | offset = 8; | |
662 | break; | |
663 | ||
664 | default: | |
665 | gdb_assert (!"Unexpected register class."); | |
666 | } | |
667 | ||
668 | gdb_assert (regnum != -1); | |
669 | memset (buf, 0, sizeof buf); | |
670 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
671 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
672 | } | |
673 | } | |
674 | } | |
675 | ||
676 | /* Allocate space for the arguments on the stack. */ | |
677 | sp -= num_elements * 8; | |
678 | ||
679 | /* The psABI says that "The end of the input argument area shall be | |
680 | aligned on a 16 byte boundary." */ | |
681 | sp &= ~0xf; | |
682 | ||
683 | /* Write out the arguments to the stack. */ | |
684 | for (i = 0; i < num_stack_args; i++) | |
685 | { | |
4991999e | 686 | struct type *type = value_type (stack_args[i]); |
d8de1ef7 | 687 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
720aa428 MK |
688 | int len = TYPE_LENGTH (type); |
689 | ||
690 | write_memory (sp + element * 8, valbuf, len); | |
691 | element += ((len + 7) / 8); | |
692 | } | |
693 | ||
694 | /* The psABI says that "For calls that may call functions that use | |
695 | varargs or stdargs (prototype-less calls or calls to functions | |
696 | containing ellipsis (...) in the declaration) %al is used as | |
697 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 698 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
699 | return sp; |
700 | } | |
701 | ||
c4f35dd8 | 702 | static CORE_ADDR |
7d9b040b | 703 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
704 | struct regcache *regcache, CORE_ADDR bp_addr, |
705 | int nargs, struct value **args, CORE_ADDR sp, | |
706 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 707 | { |
d8de1ef7 | 708 | gdb_byte buf[8]; |
c4f35dd8 MK |
709 | |
710 | /* Pass arguments. */ | |
6470d250 | 711 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
712 | |
713 | /* Pass "hidden" argument". */ | |
714 | if (struct_return) | |
715 | { | |
716 | store_unsigned_integer (buf, 8, struct_addr); | |
90f90721 | 717 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
718 | } |
719 | ||
720 | /* Store return address. */ | |
721 | sp -= 8; | |
10f93086 | 722 | store_unsigned_integer (buf, 8, bp_addr); |
c4f35dd8 MK |
723 | write_memory (sp, buf, 8); |
724 | ||
725 | /* Finally, update the stack pointer... */ | |
726 | store_unsigned_integer (buf, 8, sp); | |
90f90721 | 727 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
728 | |
729 | /* ...and fake a frame pointer. */ | |
90f90721 | 730 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 731 | |
3e210248 | 732 | return sp + 16; |
53e95fcf | 733 | } |
c4f35dd8 MK |
734 | \f |
735 | ||
736 | /* The maximum number of saved registers. This should include %rip. */ | |
90f90721 | 737 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 738 | |
e53bef9f | 739 | struct amd64_frame_cache |
c4f35dd8 MK |
740 | { |
741 | /* Base address. */ | |
742 | CORE_ADDR base; | |
743 | CORE_ADDR sp_offset; | |
744 | CORE_ADDR pc; | |
745 | ||
746 | /* Saved registers. */ | |
e53bef9f | 747 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 MK |
748 | CORE_ADDR saved_sp; |
749 | ||
750 | /* Do we have a frame? */ | |
751 | int frameless_p; | |
752 | }; | |
8dda9770 | 753 | |
c4f35dd8 MK |
754 | /* Allocate and initialize a frame cache. */ |
755 | ||
e53bef9f MK |
756 | static struct amd64_frame_cache * |
757 | amd64_alloc_frame_cache (void) | |
8dda9770 | 758 | { |
e53bef9f | 759 | struct amd64_frame_cache *cache; |
c4f35dd8 MK |
760 | int i; |
761 | ||
e53bef9f | 762 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); |
8dda9770 | 763 | |
c4f35dd8 MK |
764 | /* Base address. */ |
765 | cache->base = 0; | |
766 | cache->sp_offset = -8; | |
767 | cache->pc = 0; | |
768 | ||
769 | /* Saved registers. We initialize these to -1 since zero is a valid | |
770 | offset (that's where %rbp is supposed to be stored). */ | |
e53bef9f | 771 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
772 | cache->saved_regs[i] = -1; |
773 | cache->saved_sp = 0; | |
774 | ||
775 | /* Frameless until proven otherwise. */ | |
776 | cache->frameless_p = 1; | |
777 | ||
778 | return cache; | |
8dda9770 | 779 | } |
53e95fcf | 780 | |
c4f35dd8 MK |
781 | /* Do a limited analysis of the prologue at PC and update CACHE |
782 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
783 | address where the analysis stopped. | |
784 | ||
785 | We will handle only functions beginning with: | |
786 | ||
787 | pushq %rbp 0x55 | |
788 | movq %rsp, %rbp 0x48 0x89 0xe5 | |
789 | ||
790 | Any function that doesn't start with this sequence will be assumed | |
791 | to have no prologue and thus no valid frame pointer in %rbp. */ | |
792 | ||
793 | static CORE_ADDR | |
e53bef9f MK |
794 | amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
795 | struct amd64_frame_cache *cache) | |
53e95fcf | 796 | { |
d8de1ef7 MK |
797 | static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ |
798 | gdb_byte buf[3]; | |
799 | gdb_byte op; | |
c4f35dd8 MK |
800 | |
801 | if (current_pc <= pc) | |
802 | return current_pc; | |
803 | ||
804 | op = read_memory_unsigned_integer (pc, 1); | |
805 | ||
806 | if (op == 0x55) /* pushq %rbp */ | |
807 | { | |
808 | /* Take into account that we've executed the `pushq %rbp' that | |
809 | starts this instruction sequence. */ | |
90f90721 | 810 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
811 | cache->sp_offset += 8; |
812 | ||
813 | /* If that's all, return now. */ | |
814 | if (current_pc <= pc + 1) | |
815 | return current_pc; | |
816 | ||
817 | /* Check for `movq %rsp, %rbp'. */ | |
818 | read_memory (pc + 1, buf, 3); | |
819 | if (memcmp (buf, proto, 3) != 0) | |
820 | return pc + 1; | |
821 | ||
822 | /* OK, we actually have a frame. */ | |
823 | cache->frameless_p = 0; | |
824 | return pc + 4; | |
825 | } | |
826 | ||
827 | return pc; | |
53e95fcf JS |
828 | } |
829 | ||
c4f35dd8 MK |
830 | /* Return PC of first real instruction. */ |
831 | ||
832 | static CORE_ADDR | |
e53bef9f | 833 | amd64_skip_prologue (CORE_ADDR start_pc) |
53e95fcf | 834 | { |
e53bef9f | 835 | struct amd64_frame_cache cache; |
c4f35dd8 MK |
836 | CORE_ADDR pc; |
837 | ||
594706e6 | 838 | pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache); |
c4f35dd8 MK |
839 | if (cache.frameless_p) |
840 | return start_pc; | |
841 | ||
842 | return pc; | |
53e95fcf | 843 | } |
c4f35dd8 | 844 | \f |
53e95fcf | 845 | |
c4f35dd8 MK |
846 | /* Normal frames. */ |
847 | ||
e53bef9f MK |
848 | static struct amd64_frame_cache * |
849 | amd64_frame_cache (struct frame_info *next_frame, void **this_cache) | |
6d686a84 | 850 | { |
e53bef9f | 851 | struct amd64_frame_cache *cache; |
d8de1ef7 | 852 | gdb_byte buf[8]; |
6d686a84 | 853 | int i; |
6d686a84 | 854 | |
c4f35dd8 MK |
855 | if (*this_cache) |
856 | return *this_cache; | |
6d686a84 | 857 | |
e53bef9f | 858 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 MK |
859 | *this_cache = cache; |
860 | ||
c4f35dd8 MK |
861 | cache->pc = frame_func_unwind (next_frame); |
862 | if (cache->pc != 0) | |
e53bef9f | 863 | amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); |
c4f35dd8 MK |
864 | |
865 | if (cache->frameless_p) | |
866 | { | |
4a28816e MK |
867 | /* We didn't find a valid frame. If we're at the start of a |
868 | function, or somewhere half-way its prologue, the function's | |
869 | frame probably hasn't been fully setup yet. Try to | |
870 | reconstruct the base address for the stack frame by looking | |
871 | at the stack pointer. For truly "frameless" functions this | |
872 | might work too. */ | |
c4f35dd8 | 873 | |
90f90721 | 874 | frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
875 | cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; |
876 | } | |
35883a3f MK |
877 | else |
878 | { | |
90f90721 | 879 | frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); |
35883a3f MK |
880 | cache->base = extract_unsigned_integer (buf, 8); |
881 | } | |
c4f35dd8 MK |
882 | |
883 | /* Now that we have the base address for the stack frame we can | |
884 | calculate the value of %rsp in the calling frame. */ | |
885 | cache->saved_sp = cache->base + 16; | |
886 | ||
35883a3f MK |
887 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
888 | frame we find it at the same offset from the reconstructed base | |
889 | address. */ | |
90f90721 | 890 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; |
35883a3f | 891 | |
c4f35dd8 MK |
892 | /* Adjust all the saved registers such that they contain addresses |
893 | instead of offsets. */ | |
e53bef9f | 894 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
895 | if (cache->saved_regs[i] != -1) |
896 | cache->saved_regs[i] += cache->base; | |
897 | ||
898 | return cache; | |
6d686a84 ML |
899 | } |
900 | ||
c4f35dd8 | 901 | static void |
e53bef9f MK |
902 | amd64_frame_this_id (struct frame_info *next_frame, void **this_cache, |
903 | struct frame_id *this_id) | |
c4f35dd8 | 904 | { |
e53bef9f MK |
905 | struct amd64_frame_cache *cache = |
906 | amd64_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
907 | |
908 | /* This marks the outermost frame. */ | |
909 | if (cache->base == 0) | |
910 | return; | |
911 | ||
912 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
913 | } | |
e76e1718 | 914 | |
c4f35dd8 | 915 | static void |
e53bef9f MK |
916 | amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache, |
917 | int regnum, int *optimizedp, | |
918 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
5323dd1d | 919 | int *realnump, gdb_byte *valuep) |
53e95fcf | 920 | { |
e53bef9f MK |
921 | struct amd64_frame_cache *cache = |
922 | amd64_frame_cache (next_frame, this_cache); | |
e76e1718 | 923 | |
c4f35dd8 | 924 | gdb_assert (regnum >= 0); |
b1ab997b | 925 | |
c4f35dd8 MK |
926 | if (regnum == SP_REGNUM && cache->saved_sp) |
927 | { | |
928 | *optimizedp = 0; | |
929 | *lvalp = not_lval; | |
930 | *addrp = 0; | |
931 | *realnump = -1; | |
932 | if (valuep) | |
933 | { | |
934 | /* Store the value. */ | |
935 | store_unsigned_integer (valuep, 8, cache->saved_sp); | |
936 | } | |
937 | return; | |
938 | } | |
e76e1718 | 939 | |
e53bef9f | 940 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
c4f35dd8 MK |
941 | { |
942 | *optimizedp = 0; | |
943 | *lvalp = lval_memory; | |
944 | *addrp = cache->saved_regs[regnum]; | |
945 | *realnump = -1; | |
946 | if (valuep) | |
947 | { | |
948 | /* Read the value in from memory. */ | |
949 | read_memory (*addrp, valuep, | |
950 | register_size (current_gdbarch, regnum)); | |
951 | } | |
952 | return; | |
953 | } | |
e76e1718 | 954 | |
00b25ff3 AC |
955 | *optimizedp = 0; |
956 | *lvalp = lval_register; | |
957 | *addrp = 0; | |
958 | *realnump = regnum; | |
959 | if (valuep) | |
960 | frame_unwind_register (next_frame, (*realnump), valuep); | |
c4f35dd8 | 961 | } |
e76e1718 | 962 | |
e53bef9f | 963 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
964 | { |
965 | NORMAL_FRAME, | |
e53bef9f MK |
966 | amd64_frame_this_id, |
967 | amd64_frame_prev_register | |
c4f35dd8 | 968 | }; |
e76e1718 | 969 | |
c4f35dd8 | 970 | static const struct frame_unwind * |
e53bef9f | 971 | amd64_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 | 972 | { |
e53bef9f | 973 | return &amd64_frame_unwind; |
c4f35dd8 MK |
974 | } |
975 | \f | |
e76e1718 | 976 | |
c4f35dd8 MK |
977 | /* Signal trampolines. */ |
978 | ||
979 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
980 | 64-bit variants. This would require using identical frame caches | |
981 | on both platforms. */ | |
982 | ||
e53bef9f MK |
983 | static struct amd64_frame_cache * |
984 | amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c4f35dd8 | 985 | { |
e53bef9f | 986 | struct amd64_frame_cache *cache; |
c4f35dd8 MK |
987 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
988 | CORE_ADDR addr; | |
d8de1ef7 | 989 | gdb_byte buf[8]; |
2b5e0749 | 990 | int i; |
c4f35dd8 MK |
991 | |
992 | if (*this_cache) | |
993 | return *this_cache; | |
994 | ||
e53bef9f | 995 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 996 | |
90f90721 | 997 | frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
998 | cache->base = extract_unsigned_integer (buf, 8) - 8; |
999 | ||
1000 | addr = tdep->sigcontext_addr (next_frame); | |
2b5e0749 | 1001 | gdb_assert (tdep->sc_reg_offset); |
e53bef9f | 1002 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); |
2b5e0749 MK |
1003 | for (i = 0; i < tdep->sc_num_regs; i++) |
1004 | if (tdep->sc_reg_offset[i] != -1) | |
1005 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 MK |
1006 | |
1007 | *this_cache = cache; | |
1008 | return cache; | |
53e95fcf JS |
1009 | } |
1010 | ||
c4f35dd8 | 1011 | static void |
e53bef9f MK |
1012 | amd64_sigtramp_frame_this_id (struct frame_info *next_frame, |
1013 | void **this_cache, struct frame_id *this_id) | |
c4f35dd8 | 1014 | { |
e53bef9f MK |
1015 | struct amd64_frame_cache *cache = |
1016 | amd64_sigtramp_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
1017 | |
1018 | (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); | |
1019 | } | |
1020 | ||
1021 | static void | |
e53bef9f MK |
1022 | amd64_sigtramp_frame_prev_register (struct frame_info *next_frame, |
1023 | void **this_cache, | |
1024 | int regnum, int *optimizedp, | |
1025 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
5323dd1d | 1026 | int *realnump, gdb_byte *valuep) |
c4f35dd8 MK |
1027 | { |
1028 | /* Make sure we've initialized the cache. */ | |
e53bef9f | 1029 | amd64_sigtramp_frame_cache (next_frame, this_cache); |
c4f35dd8 | 1030 | |
e53bef9f MK |
1031 | amd64_frame_prev_register (next_frame, this_cache, regnum, |
1032 | optimizedp, lvalp, addrp, realnump, valuep); | |
c4f35dd8 MK |
1033 | } |
1034 | ||
e53bef9f | 1035 | static const struct frame_unwind amd64_sigtramp_frame_unwind = |
c4f35dd8 MK |
1036 | { |
1037 | SIGTRAMP_FRAME, | |
e53bef9f MK |
1038 | amd64_sigtramp_frame_this_id, |
1039 | amd64_sigtramp_frame_prev_register | |
c4f35dd8 MK |
1040 | }; |
1041 | ||
1042 | static const struct frame_unwind * | |
e53bef9f | 1043 | amd64_sigtramp_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 | 1044 | { |
911bc6ee MK |
1045 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame)); |
1046 | ||
1047 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
1048 | handler. */ | |
1049 | if (tdep->sigcontext_addr == NULL) | |
1050 | return NULL; | |
1051 | ||
1052 | if (tdep->sigtramp_p != NULL) | |
1053 | { | |
1054 | if (tdep->sigtramp_p (next_frame)) | |
1055 | return &amd64_sigtramp_frame_unwind; | |
1056 | } | |
c4f35dd8 | 1057 | |
911bc6ee | 1058 | if (tdep->sigtramp_start != 0) |
1c3545ae | 1059 | { |
911bc6ee | 1060 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1c3545ae | 1061 | |
911bc6ee MK |
1062 | gdb_assert (tdep->sigtramp_end != 0); |
1063 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
1064 | return &amd64_sigtramp_frame_unwind; | |
1c3545ae | 1065 | } |
c4f35dd8 MK |
1066 | |
1067 | return NULL; | |
1068 | } | |
1069 | \f | |
1070 | ||
1071 | static CORE_ADDR | |
e53bef9f | 1072 | amd64_frame_base_address (struct frame_info *next_frame, void **this_cache) |
c4f35dd8 | 1073 | { |
e53bef9f MK |
1074 | struct amd64_frame_cache *cache = |
1075 | amd64_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
1076 | |
1077 | return cache->base; | |
1078 | } | |
1079 | ||
e53bef9f | 1080 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 1081 | { |
e53bef9f MK |
1082 | &amd64_frame_unwind, |
1083 | amd64_frame_base_address, | |
1084 | amd64_frame_base_address, | |
1085 | amd64_frame_base_address | |
c4f35dd8 MK |
1086 | }; |
1087 | ||
166f4c7b | 1088 | static struct frame_id |
e53bef9f | 1089 | amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
166f4c7b | 1090 | { |
d8de1ef7 | 1091 | gdb_byte buf[8]; |
c4f35dd8 MK |
1092 | CORE_ADDR fp; |
1093 | ||
90f90721 | 1094 | frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); |
c4f35dd8 MK |
1095 | fp = extract_unsigned_integer (buf, 8); |
1096 | ||
1097 | return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); | |
166f4c7b ML |
1098 | } |
1099 | ||
8b148df9 AC |
1100 | /* 16 byte align the SP per frame requirements. */ |
1101 | ||
1102 | static CORE_ADDR | |
e53bef9f | 1103 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
1104 | { |
1105 | return sp & -(CORE_ADDR)16; | |
1106 | } | |
473f17b0 MK |
1107 | \f |
1108 | ||
593adc23 MK |
1109 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
1110 | in the floating-point register set REGSET to register cache | |
1111 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
1112 | |
1113 | static void | |
e53bef9f MK |
1114 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
1115 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 1116 | { |
9ea75c57 | 1117 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 MK |
1118 | |
1119 | gdb_assert (len == tdep->sizeof_fpregset); | |
90f90721 | 1120 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 1121 | } |
8b148df9 | 1122 | |
593adc23 MK |
1123 | /* Collect register REGNUM from the register cache REGCACHE and store |
1124 | it in the buffer specified by FPREGS and LEN as described by the | |
1125 | floating-point register set REGSET. If REGNUM is -1, do this for | |
1126 | all registers in REGSET. */ | |
1127 | ||
1128 | static void | |
1129 | amd64_collect_fpregset (const struct regset *regset, | |
1130 | const struct regcache *regcache, | |
1131 | int regnum, void *fpregs, size_t len) | |
1132 | { | |
1133 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1134 | ||
1135 | gdb_assert (len == tdep->sizeof_fpregset); | |
1136 | amd64_collect_fxsave (regcache, regnum, fpregs); | |
1137 | } | |
1138 | ||
c6b33596 MK |
1139 | /* Return the appropriate register set for the core section identified |
1140 | by SECT_NAME and SECT_SIZE. */ | |
1141 | ||
1142 | static const struct regset * | |
e53bef9f MK |
1143 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
1144 | const char *sect_name, size_t sect_size) | |
c6b33596 MK |
1145 | { |
1146 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1147 | ||
1148 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
1149 | { | |
1150 | if (tdep->fpregset == NULL) | |
593adc23 MK |
1151 | tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, |
1152 | amd64_collect_fpregset); | |
c6b33596 MK |
1153 | |
1154 | return tdep->fpregset; | |
1155 | } | |
1156 | ||
1157 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); | |
1158 | } | |
1159 | \f | |
1160 | ||
2213a65d | 1161 | void |
90f90721 | 1162 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 1163 | { |
0c1a73d6 | 1164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53e95fcf | 1165 | |
473f17b0 MK |
1166 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
1167 | floating-point registers. */ | |
1168 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
1169 | ||
5716833c | 1170 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 1171 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 1172 | tdep->num_xmm_regs = 16; |
53e95fcf | 1173 | |
0c1a73d6 | 1174 | /* This is what all the fuss is about. */ |
53e95fcf JS |
1175 | set_gdbarch_long_bit (gdbarch, 64); |
1176 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1177 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1178 | ||
e53bef9f MK |
1179 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
1180 | up 128 bits, even though it's still based on the i387 extended | |
1181 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
1182 | set_gdbarch_long_double_bit (gdbarch, 128); |
1183 | ||
e53bef9f MK |
1184 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
1185 | set_gdbarch_register_name (gdbarch, amd64_register_name); | |
1186 | set_gdbarch_register_type (gdbarch, amd64_register_type); | |
b83b026c MK |
1187 | |
1188 | /* Register numbers of various important registers. */ | |
90f90721 MK |
1189 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
1190 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
1191 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
1192 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 1193 | |
e53bef9f MK |
1194 | /* The "default" register numbering scheme for AMD64 is referred to |
1195 | as the "DWARF Register Number Mapping" in the System V psABI. | |
1196 | The preferred debugging format for all known AMD64 targets is | |
1197 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
1198 | DWARF-1), but we provide the same mapping just in case. This | |
1199 | mapping is also used for stabs, which GCC does support. */ | |
1200 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
1201 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
1202 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
de220d0f | 1203 | |
c4f35dd8 | 1204 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 1205 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 1206 | |
c4f35dd8 | 1207 | /* Call dummy code. */ |
e53bef9f MK |
1208 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
1209 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 1210 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 1211 | |
e53bef9f | 1212 | set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p); |
d532c08f MK |
1213 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
1214 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
1215 | ||
efb1c01c | 1216 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 1217 | |
e53bef9f | 1218 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 1219 | |
c4f35dd8 | 1220 | /* Avoid wiring in the MMX registers for now. */ |
2213a65d | 1221 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
5716833c | 1222 | tdep->mm0_regnum = -1; |
2213a65d | 1223 | |
e53bef9f | 1224 | set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id); |
53e95fcf | 1225 | |
e53bef9f MK |
1226 | frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer); |
1227 | frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer); | |
1228 | frame_base_set_default (gdbarch, &amd64_frame_base); | |
c6b33596 MK |
1229 | |
1230 | /* If we have a register mapping, enable the generic core file support. */ | |
1231 | if (tdep->gregset_reg_offset) | |
1232 | set_gdbarch_regset_from_core_section (gdbarch, | |
e53bef9f | 1233 | amd64_regset_from_core_section); |
c4f35dd8 MK |
1234 | } |
1235 | \f | |
1236 | ||
90f90721 | 1237 | #define I387_ST0_REGNUM AMD64_ST0_REGNUM |
c4f35dd8 | 1238 | |
41d041d6 MK |
1239 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
1240 | sense that the instruction pointer and data pointer are simply | |
1241 | 64-bit offsets into the code segment and the data segment instead | |
1242 | of a selector offset pair. The functions below store the upper 32 | |
1243 | bits of these pointers (instead of just the 16-bits of the segment | |
1244 | selector). */ | |
1245 | ||
1246 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
1247 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
1248 | -1, do this for all registers. This function masks off any of the | |
1249 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
1250 | |
1251 | void | |
90f90721 | 1252 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
41d041d6 | 1253 | const void *fxsave) |
c4f35dd8 | 1254 | { |
41d041d6 | 1255 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 1256 | |
f0ef85a5 | 1257 | if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c4f35dd8 | 1258 | { |
d8de1ef7 | 1259 | const gdb_byte *regs = fxsave; |
41d041d6 | 1260 | |
0485f6ad | 1261 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) |
41d041d6 | 1262 | regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); |
0485f6ad | 1263 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) |
41d041d6 | 1264 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); |
c4f35dd8 | 1265 | } |
0c1a73d6 MK |
1266 | } |
1267 | ||
3c017e40 MK |
1268 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
1269 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
1270 | all registers. This function doesn't touch any of the reserved | |
1271 | bits in *FXSAVE. */ | |
1272 | ||
1273 | void | |
1274 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
1275 | void *fxsave) | |
1276 | { | |
d8de1ef7 | 1277 | gdb_byte *regs = fxsave; |
3c017e40 MK |
1278 | |
1279 | i387_collect_fxsave (regcache, regnum, fxsave); | |
1280 | ||
f0ef85a5 MK |
1281 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
1282 | { | |
1283 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) | |
1284 | regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12); | |
1285 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) | |
1286 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20); | |
1287 | } | |
3c017e40 | 1288 | } |