Commit | Line | Data |
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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
9b254dd1 | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
5ae96ec1 MK |
4 | Free Software Foundation, Inc. |
5 | ||
6 | Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
7 | |
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
13 | (at your option) any later version. |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
22 | |
23 | #include "defs.h" | |
c4f35dd8 MK |
24 | #include "arch-utils.h" |
25 | #include "block.h" | |
26 | #include "dummy-frame.h" | |
27 | #include "frame.h" | |
28 | #include "frame-base.h" | |
29 | #include "frame-unwind.h" | |
53e95fcf | 30 | #include "inferior.h" |
53e95fcf | 31 | #include "gdbcmd.h" |
c4f35dd8 MK |
32 | #include "gdbcore.h" |
33 | #include "objfiles.h" | |
53e95fcf | 34 | #include "regcache.h" |
2c261fae | 35 | #include "regset.h" |
53e95fcf | 36 | #include "symfile.h" |
c4f35dd8 | 37 | |
82dbc5f7 | 38 | #include "gdb_assert.h" |
c4f35dd8 | 39 | |
9c1488cb | 40 | #include "amd64-tdep.h" |
c4f35dd8 | 41 | #include "i387-tdep.h" |
53e95fcf | 42 | |
e53bef9f MK |
43 | /* Note that the AMD64 architecture was previously known as x86-64. |
44 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 45 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
46 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
47 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
48 | x86_64_-prefix since it's so much easier to type. */ | |
49 | ||
402ecd56 | 50 | /* Register information. */ |
c4f35dd8 | 51 | |
6707b003 | 52 | static const char *amd64_register_names[] = |
de220d0f | 53 | { |
6707b003 | 54 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
c4f35dd8 MK |
55 | |
56 | /* %r8 is indeed register number 8. */ | |
6707b003 UW |
57 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
58 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", | |
c4f35dd8 | 59 | |
af233647 | 60 | /* %st0 is register number 24. */ |
6707b003 UW |
61 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
62 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", | |
c4f35dd8 | 63 | |
af233647 | 64 | /* %xmm0 is register number 40. */ |
6707b003 UW |
65 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
66 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", | |
67 | "mxcsr", | |
0e04a514 ML |
68 | }; |
69 | ||
c4f35dd8 | 70 | /* Total number of registers. */ |
6707b003 | 71 | #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names) |
de220d0f | 72 | |
c4f35dd8 | 73 | /* Return the name of register REGNUM. */ |
b6779aa2 | 74 | |
8695c747 | 75 | const char * |
d93859e2 | 76 | amd64_register_name (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 77 | { |
e53bef9f | 78 | if (regnum >= 0 && regnum < AMD64_NUM_REGS) |
6707b003 | 79 | return amd64_register_names[regnum]; |
53e95fcf | 80 | |
c4f35dd8 | 81 | return NULL; |
53e95fcf JS |
82 | } |
83 | ||
84 | /* Return the GDB type object for the "standard" data type of data in | |
c4f35dd8 | 85 | register REGNUM. */ |
53e95fcf | 86 | |
8695c747 | 87 | struct type * |
e53bef9f | 88 | amd64_register_type (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 89 | { |
6707b003 UW |
90 | if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM) |
91 | return builtin_type_int64; | |
92 | if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM) | |
93 | return builtin_type_void_data_ptr; | |
94 | if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM) | |
95 | return builtin_type_int64; | |
96 | if (regnum == AMD64_RIP_REGNUM) | |
97 | return builtin_type_void_func_ptr; | |
98 | if (regnum == AMD64_EFLAGS_REGNUM) | |
99 | return i386_eflags_type; | |
100 | if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM) | |
101 | return builtin_type_int32; | |
102 | if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7) | |
103 | return builtin_type_i387_ext; | |
104 | if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7) | |
105 | return builtin_type_int32; | |
106 | if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15) | |
794ac428 | 107 | return i386_sse_type (gdbarch); |
6707b003 UW |
108 | if (regnum == AMD64_MXCSR_REGNUM) |
109 | return i386_mxcsr_type; | |
110 | ||
111 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
53e95fcf JS |
112 | } |
113 | ||
c4f35dd8 MK |
114 | /* DWARF Register Number Mapping as defined in the System V psABI, |
115 | section 3.6. */ | |
53e95fcf | 116 | |
e53bef9f | 117 | static int amd64_dwarf_regmap[] = |
0e04a514 | 118 | { |
c4f35dd8 | 119 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
120 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
121 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
122 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
123 | |
124 | /* Frame Pointer Register RBP. */ | |
90f90721 | 125 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
126 | |
127 | /* Stack Pointer Register RSP. */ | |
90f90721 | 128 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
129 | |
130 | /* Extended Integer Registers 8 - 15. */ | |
131 | 8, 9, 10, 11, 12, 13, 14, 15, | |
132 | ||
59207364 | 133 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 134 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
135 | |
136 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
137 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
138 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
139 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
140 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
141 | |
142 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
143 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
144 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
145 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
146 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
147 | |
148 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
149 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
150 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
151 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 JB |
152 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
153 | ||
154 | /* Control and Status Flags Register. */ | |
155 | AMD64_EFLAGS_REGNUM, | |
156 | ||
157 | /* Selector Registers. */ | |
158 | AMD64_ES_REGNUM, | |
159 | AMD64_CS_REGNUM, | |
160 | AMD64_SS_REGNUM, | |
161 | AMD64_DS_REGNUM, | |
162 | AMD64_FS_REGNUM, | |
163 | AMD64_GS_REGNUM, | |
164 | -1, | |
165 | -1, | |
166 | ||
167 | /* Segment Base Address Registers. */ | |
168 | -1, | |
169 | -1, | |
170 | -1, | |
171 | -1, | |
172 | ||
173 | /* Special Selector Registers. */ | |
174 | -1, | |
175 | -1, | |
176 | ||
177 | /* Floating Point Control Registers. */ | |
178 | AMD64_MXCSR_REGNUM, | |
179 | AMD64_FCTRL_REGNUM, | |
180 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 181 | }; |
0e04a514 | 182 | |
e53bef9f MK |
183 | static const int amd64_dwarf_regmap_len = |
184 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 185 | |
c4f35dd8 MK |
186 | /* Convert DWARF register number REG to the appropriate register |
187 | number used by GDB. */ | |
26abbdc4 | 188 | |
c4f35dd8 | 189 | static int |
d3f73121 | 190 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
53e95fcf | 191 | { |
c4f35dd8 | 192 | int regnum = -1; |
53e95fcf | 193 | |
16aff9a6 | 194 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 195 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 196 | |
c4f35dd8 | 197 | if (regnum == -1) |
8a3fe4f8 | 198 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
c4f35dd8 MK |
199 | |
200 | return regnum; | |
53e95fcf | 201 | } |
d532c08f | 202 | |
53e95fcf JS |
203 | \f |
204 | ||
efb1c01c MK |
205 | /* Register classes as defined in the psABI. */ |
206 | ||
207 | enum amd64_reg_class | |
208 | { | |
209 | AMD64_INTEGER, | |
210 | AMD64_SSE, | |
211 | AMD64_SSEUP, | |
212 | AMD64_X87, | |
213 | AMD64_X87UP, | |
214 | AMD64_COMPLEX_X87, | |
215 | AMD64_NO_CLASS, | |
216 | AMD64_MEMORY | |
217 | }; | |
218 | ||
219 | /* Return the union class of CLASS1 and CLASS2. See the psABI for | |
220 | details. */ | |
221 | ||
222 | static enum amd64_reg_class | |
223 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
224 | { | |
225 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
226 | if (class1 == class2) | |
227 | return class1; | |
228 | ||
229 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
230 | is the other class. */ | |
231 | if (class1 == AMD64_NO_CLASS) | |
232 | return class2; | |
233 | if (class2 == AMD64_NO_CLASS) | |
234 | return class1; | |
235 | ||
236 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
237 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
238 | return AMD64_MEMORY; | |
239 | ||
240 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
241 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
242 | return AMD64_INTEGER; | |
243 | ||
244 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
245 | MEMORY is used as class. */ | |
246 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
247 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
248 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
249 | return AMD64_MEMORY; | |
250 | ||
251 | /* Rule (f): Otherwise class SSE is used. */ | |
252 | return AMD64_SSE; | |
253 | } | |
254 | ||
255 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); | |
256 | ||
79b1ab3d MK |
257 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
258 | ||
259 | static int | |
260 | amd64_non_pod_p (struct type *type) | |
261 | { | |
262 | /* ??? A class with a base class certainly isn't POD, but does this | |
263 | catch all non-POD structure types? */ | |
264 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
265 | return 1; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
efb1c01c MK |
270 | /* Classify TYPE according to the rules for aggregate (structures and |
271 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
272 | |
273 | static void | |
efb1c01c | 274 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
53e95fcf JS |
275 | { |
276 | int len = TYPE_LENGTH (type); | |
277 | ||
efb1c01c MK |
278 | /* 1. If the size of an object is larger than two eightbytes, or in |
279 | C++, is a non-POD structure or union type, or contains | |
280 | unaligned fields, it has class memory. */ | |
79b1ab3d | 281 | if (len > 16 || amd64_non_pod_p (type)) |
53e95fcf | 282 | { |
efb1c01c MK |
283 | class[0] = class[1] = AMD64_MEMORY; |
284 | return; | |
53e95fcf | 285 | } |
efb1c01c MK |
286 | |
287 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
288 | class[0] = class[1] = AMD64_NO_CLASS; | |
289 | ||
290 | /* 3. Each field of an object is classified recursively so that | |
291 | always two fields are considered. The resulting class is | |
292 | calculated according to the classes of the fields in the | |
293 | eightbyte: */ | |
294 | ||
295 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 296 | { |
efb1c01c MK |
297 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
298 | ||
299 | /* All fields in an array have the same type. */ | |
300 | amd64_classify (subtype, class); | |
301 | if (len > 8 && class[1] == AMD64_NO_CLASS) | |
302 | class[1] = class[0]; | |
8ffd9b1b | 303 | } |
53e95fcf JS |
304 | else |
305 | { | |
efb1c01c | 306 | int i; |
53e95fcf | 307 | |
efb1c01c MK |
308 | /* Structure or union. */ |
309 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
310 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
311 | ||
312 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 313 | { |
efb1c01c MK |
314 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
315 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
316 | enum amd64_reg_class subclass[2]; | |
317 | ||
562c50c2 MK |
318 | /* Ignore static fields. */ |
319 | if (TYPE_FIELD_STATIC (type, i)) | |
320 | continue; | |
321 | ||
efb1c01c MK |
322 | gdb_assert (pos == 0 || pos == 1); |
323 | ||
324 | amd64_classify (subtype, subclass); | |
325 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); | |
326 | if (pos == 0) | |
327 | class[1] = amd64_merge_classes (class[1], subclass[1]); | |
53e95fcf | 328 | } |
53e95fcf | 329 | } |
efb1c01c MK |
330 | |
331 | /* 4. Then a post merger cleanup is done: */ | |
332 | ||
333 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
334 | passed in memory. */ | |
335 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) | |
336 | class[0] = class[1] = AMD64_MEMORY; | |
337 | ||
338 | /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to | |
339 | SSE. */ | |
340 | if (class[0] == AMD64_SSEUP) | |
341 | class[0] = AMD64_SSE; | |
342 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) | |
343 | class[1] = AMD64_SSE; | |
344 | } | |
345 | ||
346 | /* Classify TYPE, and store the result in CLASS. */ | |
347 | ||
348 | static void | |
349 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) | |
350 | { | |
351 | enum type_code code = TYPE_CODE (type); | |
352 | int len = TYPE_LENGTH (type); | |
353 | ||
354 | class[0] = class[1] = AMD64_NO_CLASS; | |
355 | ||
356 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
357 | long, long long, and pointers are in the INTEGER class. Similarly, |
358 | range types, used by languages such as Ada, are also in the INTEGER | |
359 | class. */ | |
efb1c01c | 360 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
b929c77f | 361 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
9db13498 | 362 | || code == TYPE_CODE_CHAR |
efb1c01c MK |
363 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
364 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
365 | class[0] = AMD64_INTEGER; | |
366 | ||
5daa78cc TJB |
367 | /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 |
368 | are in class SSE. */ | |
369 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) | |
370 | && (len == 4 || len == 8)) | |
efb1c01c MK |
371 | /* FIXME: __m64 . */ |
372 | class[0] = AMD64_SSE; | |
373 | ||
5daa78cc TJB |
374 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
375 | two halves. The least significant ones belong to class SSE, the most | |
efb1c01c | 376 | significant one to class SSEUP. */ |
5daa78cc TJB |
377 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
378 | /* FIXME: __float128, __m128. */ | |
379 | class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; | |
efb1c01c MK |
380 | |
381 | /* The 64-bit mantissa of arguments of type long double belongs to | |
382 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
383 | class X87UP. */ | |
384 | else if (code == TYPE_CODE_FLT && len == 16) | |
385 | /* Class X87 and X87UP. */ | |
386 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; | |
387 | ||
388 | /* Aggregates. */ | |
389 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
390 | || code == TYPE_CODE_UNION) | |
391 | amd64_classify_aggregate (type, class); | |
392 | } | |
393 | ||
394 | static enum return_value_convention | |
c055b101 CV |
395 | amd64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
396 | struct type *type, struct regcache *regcache, | |
42835c2b | 397 | gdb_byte *readbuf, const gdb_byte *writebuf) |
efb1c01c MK |
398 | { |
399 | enum amd64_reg_class class[2]; | |
400 | int len = TYPE_LENGTH (type); | |
90f90721 MK |
401 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
402 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
403 | int integer_reg = 0; |
404 | int sse_reg = 0; | |
405 | int i; | |
406 | ||
407 | gdb_assert (!(readbuf && writebuf)); | |
408 | ||
409 | /* 1. Classify the return type with the classification algorithm. */ | |
410 | amd64_classify (type, class); | |
411 | ||
412 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d MK |
413 | for the return value and passes the address of this storage in |
414 | %rdi as if it were the first argument to the function. In effect, | |
415 | this address becomes a hidden first argument. | |
416 | ||
417 | On return %rax will contain the address that has been passed in | |
418 | by the caller in %rdi. */ | |
efb1c01c | 419 | if (class[0] == AMD64_MEMORY) |
6fa57a7d MK |
420 | { |
421 | /* As indicated by the comment above, the ABI guarantees that we | |
422 | can always find the return value just after the function has | |
423 | returned. */ | |
424 | ||
425 | if (readbuf) | |
426 | { | |
427 | ULONGEST addr; | |
428 | ||
429 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
430 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
431 | } | |
432 | ||
433 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
434 | } | |
efb1c01c MK |
435 | |
436 | gdb_assert (class[1] != AMD64_MEMORY); | |
437 | gdb_assert (len <= 16); | |
438 | ||
439 | for (i = 0; len > 0; i++, len -= 8) | |
440 | { | |
441 | int regnum = -1; | |
442 | int offset = 0; | |
443 | ||
444 | switch (class[i]) | |
445 | { | |
446 | case AMD64_INTEGER: | |
447 | /* 3. If the class is INTEGER, the next available register | |
448 | of the sequence %rax, %rdx is used. */ | |
449 | regnum = integer_regnum[integer_reg++]; | |
450 | break; | |
451 | ||
452 | case AMD64_SSE: | |
453 | /* 4. If the class is SSE, the next available SSE register | |
454 | of the sequence %xmm0, %xmm1 is used. */ | |
455 | regnum = sse_regnum[sse_reg++]; | |
456 | break; | |
457 | ||
458 | case AMD64_SSEUP: | |
459 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
460 | upper half of the last used SSE register. */ | |
461 | gdb_assert (sse_reg > 0); | |
462 | regnum = sse_regnum[sse_reg - 1]; | |
463 | offset = 8; | |
464 | break; | |
465 | ||
466 | case AMD64_X87: | |
467 | /* 6. If the class is X87, the value is returned on the X87 | |
468 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 469 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
470 | if (writebuf) |
471 | i387_return_value (gdbarch, regcache); | |
472 | break; | |
473 | ||
474 | case AMD64_X87UP: | |
475 | /* 7. If the class is X87UP, the value is returned together | |
476 | with the previous X87 value in %st0. */ | |
477 | gdb_assert (i > 0 && class[0] == AMD64_X87); | |
90f90721 | 478 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
479 | offset = 8; |
480 | len = 2; | |
481 | break; | |
482 | ||
483 | case AMD64_NO_CLASS: | |
484 | continue; | |
485 | ||
486 | default: | |
487 | gdb_assert (!"Unexpected register class."); | |
488 | } | |
489 | ||
490 | gdb_assert (regnum != -1); | |
491 | ||
492 | if (readbuf) | |
493 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 494 | readbuf + i * 8); |
efb1c01c MK |
495 | if (writebuf) |
496 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 497 | writebuf + i * 8); |
efb1c01c MK |
498 | } |
499 | ||
500 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
501 | } |
502 | \f | |
503 | ||
720aa428 MK |
504 | static CORE_ADDR |
505 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 506 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 MK |
507 | { |
508 | static int integer_regnum[] = | |
509 | { | |
90f90721 MK |
510 | AMD64_RDI_REGNUM, /* %rdi */ |
511 | AMD64_RSI_REGNUM, /* %rsi */ | |
512 | AMD64_RDX_REGNUM, /* %rdx */ | |
513 | AMD64_RCX_REGNUM, /* %rcx */ | |
514 | 8, /* %r8 */ | |
515 | 9 /* %r9 */ | |
720aa428 MK |
516 | }; |
517 | static int sse_regnum[] = | |
518 | { | |
519 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
520 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
521 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
522 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
523 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 MK |
524 | }; |
525 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); | |
526 | int num_stack_args = 0; | |
527 | int num_elements = 0; | |
528 | int element = 0; | |
529 | int integer_reg = 0; | |
530 | int sse_reg = 0; | |
531 | int i; | |
532 | ||
6470d250 MK |
533 | /* Reserve a register for the "hidden" argument. */ |
534 | if (struct_return) | |
535 | integer_reg++; | |
536 | ||
720aa428 MK |
537 | for (i = 0; i < nargs; i++) |
538 | { | |
4991999e | 539 | struct type *type = value_type (args[i]); |
720aa428 MK |
540 | int len = TYPE_LENGTH (type); |
541 | enum amd64_reg_class class[2]; | |
542 | int needed_integer_regs = 0; | |
543 | int needed_sse_regs = 0; | |
544 | int j; | |
545 | ||
546 | /* Classify argument. */ | |
547 | amd64_classify (type, class); | |
548 | ||
549 | /* Calculate the number of integer and SSE registers needed for | |
550 | this argument. */ | |
551 | for (j = 0; j < 2; j++) | |
552 | { | |
553 | if (class[j] == AMD64_INTEGER) | |
554 | needed_integer_regs++; | |
555 | else if (class[j] == AMD64_SSE) | |
556 | needed_sse_regs++; | |
557 | } | |
558 | ||
559 | /* Check whether enough registers are available, and if the | |
560 | argument should be passed in registers at all. */ | |
561 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) | |
562 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) | |
563 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
564 | { | |
565 | /* The argument will be passed on the stack. */ | |
566 | num_elements += ((len + 7) / 8); | |
567 | stack_args[num_stack_args++] = args[i]; | |
568 | } | |
569 | else | |
570 | { | |
571 | /* The argument will be passed in registers. */ | |
d8de1ef7 MK |
572 | const gdb_byte *valbuf = value_contents (args[i]); |
573 | gdb_byte buf[8]; | |
720aa428 MK |
574 | |
575 | gdb_assert (len <= 16); | |
576 | ||
577 | for (j = 0; len > 0; j++, len -= 8) | |
578 | { | |
579 | int regnum = -1; | |
580 | int offset = 0; | |
581 | ||
582 | switch (class[j]) | |
583 | { | |
584 | case AMD64_INTEGER: | |
585 | regnum = integer_regnum[integer_reg++]; | |
586 | break; | |
587 | ||
588 | case AMD64_SSE: | |
589 | regnum = sse_regnum[sse_reg++]; | |
590 | break; | |
591 | ||
592 | case AMD64_SSEUP: | |
593 | gdb_assert (sse_reg > 0); | |
594 | regnum = sse_regnum[sse_reg - 1]; | |
595 | offset = 8; | |
596 | break; | |
597 | ||
598 | default: | |
599 | gdb_assert (!"Unexpected register class."); | |
600 | } | |
601 | ||
602 | gdb_assert (regnum != -1); | |
603 | memset (buf, 0, sizeof buf); | |
604 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
605 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
610 | /* Allocate space for the arguments on the stack. */ | |
611 | sp -= num_elements * 8; | |
612 | ||
613 | /* The psABI says that "The end of the input argument area shall be | |
614 | aligned on a 16 byte boundary." */ | |
615 | sp &= ~0xf; | |
616 | ||
617 | /* Write out the arguments to the stack. */ | |
618 | for (i = 0; i < num_stack_args; i++) | |
619 | { | |
4991999e | 620 | struct type *type = value_type (stack_args[i]); |
d8de1ef7 | 621 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
720aa428 MK |
622 | int len = TYPE_LENGTH (type); |
623 | ||
624 | write_memory (sp + element * 8, valbuf, len); | |
625 | element += ((len + 7) / 8); | |
626 | } | |
627 | ||
628 | /* The psABI says that "For calls that may call functions that use | |
629 | varargs or stdargs (prototype-less calls or calls to functions | |
630 | containing ellipsis (...) in the declaration) %al is used as | |
631 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 632 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
633 | return sp; |
634 | } | |
635 | ||
c4f35dd8 | 636 | static CORE_ADDR |
7d9b040b | 637 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
638 | struct regcache *regcache, CORE_ADDR bp_addr, |
639 | int nargs, struct value **args, CORE_ADDR sp, | |
640 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 641 | { |
d8de1ef7 | 642 | gdb_byte buf[8]; |
c4f35dd8 MK |
643 | |
644 | /* Pass arguments. */ | |
6470d250 | 645 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
646 | |
647 | /* Pass "hidden" argument". */ | |
648 | if (struct_return) | |
649 | { | |
650 | store_unsigned_integer (buf, 8, struct_addr); | |
90f90721 | 651 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
652 | } |
653 | ||
654 | /* Store return address. */ | |
655 | sp -= 8; | |
10f93086 | 656 | store_unsigned_integer (buf, 8, bp_addr); |
c4f35dd8 MK |
657 | write_memory (sp, buf, 8); |
658 | ||
659 | /* Finally, update the stack pointer... */ | |
660 | store_unsigned_integer (buf, 8, sp); | |
90f90721 | 661 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
662 | |
663 | /* ...and fake a frame pointer. */ | |
90f90721 | 664 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 665 | |
3e210248 | 666 | return sp + 16; |
53e95fcf | 667 | } |
c4f35dd8 MK |
668 | \f |
669 | ||
670 | /* The maximum number of saved registers. This should include %rip. */ | |
90f90721 | 671 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 672 | |
e53bef9f | 673 | struct amd64_frame_cache |
c4f35dd8 MK |
674 | { |
675 | /* Base address. */ | |
676 | CORE_ADDR base; | |
677 | CORE_ADDR sp_offset; | |
678 | CORE_ADDR pc; | |
679 | ||
680 | /* Saved registers. */ | |
e53bef9f | 681 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 MK |
682 | CORE_ADDR saved_sp; |
683 | ||
684 | /* Do we have a frame? */ | |
685 | int frameless_p; | |
686 | }; | |
8dda9770 | 687 | |
d2449ee8 | 688 | /* Initialize a frame cache. */ |
c4f35dd8 | 689 | |
d2449ee8 DJ |
690 | static void |
691 | amd64_init_frame_cache (struct amd64_frame_cache *cache) | |
8dda9770 | 692 | { |
c4f35dd8 MK |
693 | int i; |
694 | ||
c4f35dd8 MK |
695 | /* Base address. */ |
696 | cache->base = 0; | |
697 | cache->sp_offset = -8; | |
698 | cache->pc = 0; | |
699 | ||
700 | /* Saved registers. We initialize these to -1 since zero is a valid | |
701 | offset (that's where %rbp is supposed to be stored). */ | |
e53bef9f | 702 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
703 | cache->saved_regs[i] = -1; |
704 | cache->saved_sp = 0; | |
705 | ||
706 | /* Frameless until proven otherwise. */ | |
707 | cache->frameless_p = 1; | |
d2449ee8 | 708 | } |
c4f35dd8 | 709 | |
d2449ee8 DJ |
710 | /* Allocate and initialize a frame cache. */ |
711 | ||
712 | static struct amd64_frame_cache * | |
713 | amd64_alloc_frame_cache (void) | |
714 | { | |
715 | struct amd64_frame_cache *cache; | |
716 | ||
717 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); | |
718 | amd64_init_frame_cache (cache); | |
c4f35dd8 | 719 | return cache; |
8dda9770 | 720 | } |
53e95fcf | 721 | |
c4f35dd8 MK |
722 | /* Do a limited analysis of the prologue at PC and update CACHE |
723 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
724 | address where the analysis stopped. | |
725 | ||
726 | We will handle only functions beginning with: | |
727 | ||
728 | pushq %rbp 0x55 | |
729 | movq %rsp, %rbp 0x48 0x89 0xe5 | |
730 | ||
731 | Any function that doesn't start with this sequence will be assumed | |
732 | to have no prologue and thus no valid frame pointer in %rbp. */ | |
733 | ||
734 | static CORE_ADDR | |
e53bef9f MK |
735 | amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
736 | struct amd64_frame_cache *cache) | |
53e95fcf | 737 | { |
d8de1ef7 MK |
738 | static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ |
739 | gdb_byte buf[3]; | |
740 | gdb_byte op; | |
c4f35dd8 MK |
741 | |
742 | if (current_pc <= pc) | |
743 | return current_pc; | |
744 | ||
745 | op = read_memory_unsigned_integer (pc, 1); | |
746 | ||
747 | if (op == 0x55) /* pushq %rbp */ | |
748 | { | |
749 | /* Take into account that we've executed the `pushq %rbp' that | |
750 | starts this instruction sequence. */ | |
90f90721 | 751 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
752 | cache->sp_offset += 8; |
753 | ||
754 | /* If that's all, return now. */ | |
755 | if (current_pc <= pc + 1) | |
756 | return current_pc; | |
757 | ||
758 | /* Check for `movq %rsp, %rbp'. */ | |
759 | read_memory (pc + 1, buf, 3); | |
760 | if (memcmp (buf, proto, 3) != 0) | |
761 | return pc + 1; | |
762 | ||
763 | /* OK, we actually have a frame. */ | |
764 | cache->frameless_p = 0; | |
765 | return pc + 4; | |
766 | } | |
767 | ||
768 | return pc; | |
53e95fcf JS |
769 | } |
770 | ||
c4f35dd8 MK |
771 | /* Return PC of first real instruction. */ |
772 | ||
773 | static CORE_ADDR | |
6093d2eb | 774 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
53e95fcf | 775 | { |
e53bef9f | 776 | struct amd64_frame_cache cache; |
c4f35dd8 MK |
777 | CORE_ADDR pc; |
778 | ||
d2449ee8 | 779 | amd64_init_frame_cache (&cache); |
594706e6 | 780 | pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache); |
c4f35dd8 MK |
781 | if (cache.frameless_p) |
782 | return start_pc; | |
783 | ||
784 | return pc; | |
53e95fcf | 785 | } |
c4f35dd8 | 786 | \f |
53e95fcf | 787 | |
c4f35dd8 MK |
788 | /* Normal frames. */ |
789 | ||
e53bef9f | 790 | static struct amd64_frame_cache * |
10458914 | 791 | amd64_frame_cache (struct frame_info *this_frame, void **this_cache) |
6d686a84 | 792 | { |
e53bef9f | 793 | struct amd64_frame_cache *cache; |
d8de1ef7 | 794 | gdb_byte buf[8]; |
6d686a84 | 795 | int i; |
6d686a84 | 796 | |
c4f35dd8 MK |
797 | if (*this_cache) |
798 | return *this_cache; | |
6d686a84 | 799 | |
e53bef9f | 800 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 MK |
801 | *this_cache = cache; |
802 | ||
10458914 | 803 | cache->pc = get_frame_func (this_frame); |
c4f35dd8 | 804 | if (cache->pc != 0) |
10458914 | 805 | amd64_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache); |
c4f35dd8 MK |
806 | |
807 | if (cache->frameless_p) | |
808 | { | |
4a28816e MK |
809 | /* We didn't find a valid frame. If we're at the start of a |
810 | function, or somewhere half-way its prologue, the function's | |
811 | frame probably hasn't been fully setup yet. Try to | |
812 | reconstruct the base address for the stack frame by looking | |
813 | at the stack pointer. For truly "frameless" functions this | |
814 | might work too. */ | |
c4f35dd8 | 815 | |
10458914 | 816 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
817 | cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; |
818 | } | |
35883a3f MK |
819 | else |
820 | { | |
10458914 | 821 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
35883a3f MK |
822 | cache->base = extract_unsigned_integer (buf, 8); |
823 | } | |
c4f35dd8 MK |
824 | |
825 | /* Now that we have the base address for the stack frame we can | |
826 | calculate the value of %rsp in the calling frame. */ | |
827 | cache->saved_sp = cache->base + 16; | |
828 | ||
35883a3f MK |
829 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
830 | frame we find it at the same offset from the reconstructed base | |
831 | address. */ | |
90f90721 | 832 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; |
35883a3f | 833 | |
c4f35dd8 MK |
834 | /* Adjust all the saved registers such that they contain addresses |
835 | instead of offsets. */ | |
e53bef9f | 836 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
837 | if (cache->saved_regs[i] != -1) |
838 | cache->saved_regs[i] += cache->base; | |
839 | ||
840 | return cache; | |
6d686a84 ML |
841 | } |
842 | ||
c4f35dd8 | 843 | static void |
10458914 | 844 | amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
e53bef9f | 845 | struct frame_id *this_id) |
c4f35dd8 | 846 | { |
e53bef9f | 847 | struct amd64_frame_cache *cache = |
10458914 | 848 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
849 | |
850 | /* This marks the outermost frame. */ | |
851 | if (cache->base == 0) | |
852 | return; | |
853 | ||
854 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
855 | } | |
e76e1718 | 856 | |
10458914 DJ |
857 | static struct value * |
858 | amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
859 | int regnum) | |
53e95fcf | 860 | { |
10458914 | 861 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e53bef9f | 862 | struct amd64_frame_cache *cache = |
10458914 | 863 | amd64_frame_cache (this_frame, this_cache); |
e76e1718 | 864 | |
c4f35dd8 | 865 | gdb_assert (regnum >= 0); |
b1ab997b | 866 | |
2ae02b47 | 867 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
10458914 | 868 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
e76e1718 | 869 | |
e53bef9f | 870 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
871 | return frame_unwind_got_memory (this_frame, regnum, |
872 | cache->saved_regs[regnum]); | |
e76e1718 | 873 | |
10458914 | 874 | return frame_unwind_got_register (this_frame, regnum, regnum); |
c4f35dd8 | 875 | } |
e76e1718 | 876 | |
e53bef9f | 877 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
878 | { |
879 | NORMAL_FRAME, | |
e53bef9f | 880 | amd64_frame_this_id, |
10458914 DJ |
881 | amd64_frame_prev_register, |
882 | NULL, | |
883 | default_frame_sniffer | |
c4f35dd8 | 884 | }; |
c4f35dd8 | 885 | \f |
e76e1718 | 886 | |
c4f35dd8 MK |
887 | /* Signal trampolines. */ |
888 | ||
889 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
890 | 64-bit variants. This would require using identical frame caches | |
891 | on both platforms. */ | |
892 | ||
e53bef9f | 893 | static struct amd64_frame_cache * |
10458914 | 894 | amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 895 | { |
e53bef9f | 896 | struct amd64_frame_cache *cache; |
10458914 | 897 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
c4f35dd8 | 898 | CORE_ADDR addr; |
d8de1ef7 | 899 | gdb_byte buf[8]; |
2b5e0749 | 900 | int i; |
c4f35dd8 MK |
901 | |
902 | if (*this_cache) | |
903 | return *this_cache; | |
904 | ||
e53bef9f | 905 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 906 | |
10458914 | 907 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
908 | cache->base = extract_unsigned_integer (buf, 8) - 8; |
909 | ||
10458914 | 910 | addr = tdep->sigcontext_addr (this_frame); |
2b5e0749 | 911 | gdb_assert (tdep->sc_reg_offset); |
e53bef9f | 912 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); |
2b5e0749 MK |
913 | for (i = 0; i < tdep->sc_num_regs; i++) |
914 | if (tdep->sc_reg_offset[i] != -1) | |
915 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 MK |
916 | |
917 | *this_cache = cache; | |
918 | return cache; | |
53e95fcf JS |
919 | } |
920 | ||
c4f35dd8 | 921 | static void |
10458914 | 922 | amd64_sigtramp_frame_this_id (struct frame_info *this_frame, |
e53bef9f | 923 | void **this_cache, struct frame_id *this_id) |
c4f35dd8 | 924 | { |
e53bef9f | 925 | struct amd64_frame_cache *cache = |
10458914 | 926 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 927 | |
10458914 | 928 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); |
c4f35dd8 MK |
929 | } |
930 | ||
10458914 DJ |
931 | static struct value * |
932 | amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
933 | void **this_cache, int regnum) | |
c4f35dd8 MK |
934 | { |
935 | /* Make sure we've initialized the cache. */ | |
10458914 | 936 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 937 | |
10458914 | 938 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
c4f35dd8 MK |
939 | } |
940 | ||
10458914 DJ |
941 | static int |
942 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
943 | struct frame_info *this_frame, | |
944 | void **this_cache) | |
c4f35dd8 | 945 | { |
10458914 | 946 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
911bc6ee MK |
947 | |
948 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
949 | handler. */ | |
950 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 951 | return 0; |
911bc6ee MK |
952 | |
953 | if (tdep->sigtramp_p != NULL) | |
954 | { | |
10458914 DJ |
955 | if (tdep->sigtramp_p (this_frame)) |
956 | return 1; | |
911bc6ee | 957 | } |
c4f35dd8 | 958 | |
911bc6ee | 959 | if (tdep->sigtramp_start != 0) |
1c3545ae | 960 | { |
10458914 | 961 | CORE_ADDR pc = get_frame_pc (this_frame); |
1c3545ae | 962 | |
911bc6ee MK |
963 | gdb_assert (tdep->sigtramp_end != 0); |
964 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 965 | return 1; |
1c3545ae | 966 | } |
c4f35dd8 | 967 | |
10458914 | 968 | return 0; |
c4f35dd8 | 969 | } |
10458914 DJ |
970 | |
971 | static const struct frame_unwind amd64_sigtramp_frame_unwind = | |
972 | { | |
973 | SIGTRAMP_FRAME, | |
974 | amd64_sigtramp_frame_this_id, | |
975 | amd64_sigtramp_frame_prev_register, | |
976 | NULL, | |
977 | amd64_sigtramp_frame_sniffer | |
978 | }; | |
c4f35dd8 MK |
979 | \f |
980 | ||
981 | static CORE_ADDR | |
10458914 | 982 | amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 983 | { |
e53bef9f | 984 | struct amd64_frame_cache *cache = |
10458914 | 985 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
986 | |
987 | return cache->base; | |
988 | } | |
989 | ||
e53bef9f | 990 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 991 | { |
e53bef9f MK |
992 | &amd64_frame_unwind, |
993 | amd64_frame_base_address, | |
994 | amd64_frame_base_address, | |
995 | amd64_frame_base_address | |
c4f35dd8 MK |
996 | }; |
997 | ||
166f4c7b | 998 | static struct frame_id |
10458914 | 999 | amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
166f4c7b | 1000 | { |
c4f35dd8 MK |
1001 | CORE_ADDR fp; |
1002 | ||
10458914 | 1003 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
c4f35dd8 | 1004 | |
10458914 | 1005 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
166f4c7b ML |
1006 | } |
1007 | ||
8b148df9 AC |
1008 | /* 16 byte align the SP per frame requirements. */ |
1009 | ||
1010 | static CORE_ADDR | |
e53bef9f | 1011 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
1012 | { |
1013 | return sp & -(CORE_ADDR)16; | |
1014 | } | |
473f17b0 MK |
1015 | \f |
1016 | ||
593adc23 MK |
1017 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
1018 | in the floating-point register set REGSET to register cache | |
1019 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
1020 | |
1021 | static void | |
e53bef9f MK |
1022 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
1023 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 1024 | { |
9ea75c57 | 1025 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 MK |
1026 | |
1027 | gdb_assert (len == tdep->sizeof_fpregset); | |
90f90721 | 1028 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 1029 | } |
8b148df9 | 1030 | |
593adc23 MK |
1031 | /* Collect register REGNUM from the register cache REGCACHE and store |
1032 | it in the buffer specified by FPREGS and LEN as described by the | |
1033 | floating-point register set REGSET. If REGNUM is -1, do this for | |
1034 | all registers in REGSET. */ | |
1035 | ||
1036 | static void | |
1037 | amd64_collect_fpregset (const struct regset *regset, | |
1038 | const struct regcache *regcache, | |
1039 | int regnum, void *fpregs, size_t len) | |
1040 | { | |
1041 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1042 | ||
1043 | gdb_assert (len == tdep->sizeof_fpregset); | |
1044 | amd64_collect_fxsave (regcache, regnum, fpregs); | |
1045 | } | |
1046 | ||
c6b33596 MK |
1047 | /* Return the appropriate register set for the core section identified |
1048 | by SECT_NAME and SECT_SIZE. */ | |
1049 | ||
1050 | static const struct regset * | |
e53bef9f MK |
1051 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
1052 | const char *sect_name, size_t sect_size) | |
c6b33596 MK |
1053 | { |
1054 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1055 | ||
1056 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
1057 | { | |
1058 | if (tdep->fpregset == NULL) | |
593adc23 MK |
1059 | tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, |
1060 | amd64_collect_fpregset); | |
c6b33596 MK |
1061 | |
1062 | return tdep->fpregset; | |
1063 | } | |
1064 | ||
1065 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); | |
1066 | } | |
1067 | \f | |
1068 | ||
436675d3 PA |
1069 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
1070 | %rdi. We expect its value to be a pointer to the jmp_buf structure | |
1071 | from which we extract the address that we will land at. This | |
1072 | address is copied into PC. This routine returns non-zero on | |
1073 | success. */ | |
1074 | ||
1075 | static int | |
1076 | amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1077 | { | |
1078 | gdb_byte buf[8]; | |
1079 | CORE_ADDR jb_addr; | |
1080 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1081 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
1082 | int len = TYPE_LENGTH (builtin_type_void_func_ptr); | |
1083 | ||
1084 | /* If JB_PC_OFFSET is -1, we have no way to find out where the | |
1085 | longjmp will land. */ | |
1086 | if (jb_pc_offset == -1) | |
1087 | return 0; | |
1088 | ||
1089 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); | |
1090 | jb_addr = extract_typed_address (buf, builtin_type_void_data_ptr); | |
1091 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) | |
1092 | return 0; | |
1093 | ||
1094 | *pc = extract_typed_address (buf, builtin_type_void_func_ptr); | |
1095 | ||
1096 | return 1; | |
1097 | } | |
1098 | ||
2213a65d | 1099 | void |
90f90721 | 1100 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 1101 | { |
0c1a73d6 | 1102 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53e95fcf | 1103 | |
473f17b0 MK |
1104 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
1105 | floating-point registers. */ | |
1106 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
1107 | ||
5716833c | 1108 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 1109 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 1110 | tdep->num_xmm_regs = 16; |
53e95fcf | 1111 | |
0c1a73d6 | 1112 | /* This is what all the fuss is about. */ |
53e95fcf JS |
1113 | set_gdbarch_long_bit (gdbarch, 64); |
1114 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1115 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1116 | ||
e53bef9f MK |
1117 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
1118 | up 128 bits, even though it's still based on the i387 extended | |
1119 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
1120 | set_gdbarch_long_double_bit (gdbarch, 128); |
1121 | ||
e53bef9f MK |
1122 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
1123 | set_gdbarch_register_name (gdbarch, amd64_register_name); | |
1124 | set_gdbarch_register_type (gdbarch, amd64_register_type); | |
b83b026c MK |
1125 | |
1126 | /* Register numbers of various important registers. */ | |
90f90721 MK |
1127 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
1128 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
1129 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
1130 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 1131 | |
e53bef9f MK |
1132 | /* The "default" register numbering scheme for AMD64 is referred to |
1133 | as the "DWARF Register Number Mapping" in the System V psABI. | |
1134 | The preferred debugging format for all known AMD64 targets is | |
1135 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
1136 | DWARF-1), but we provide the same mapping just in case. This | |
1137 | mapping is also used for stabs, which GCC does support. */ | |
1138 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
e53bef9f | 1139 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
de220d0f | 1140 | |
c4f35dd8 | 1141 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 1142 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 1143 | |
c4f35dd8 | 1144 | /* Call dummy code. */ |
e53bef9f MK |
1145 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
1146 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 1147 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 1148 | |
83acabca | 1149 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
d532c08f MK |
1150 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
1151 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
1152 | ||
efb1c01c | 1153 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 1154 | |
e53bef9f | 1155 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 1156 | |
c4f35dd8 | 1157 | /* Avoid wiring in the MMX registers for now. */ |
2213a65d | 1158 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
5716833c | 1159 | tdep->mm0_regnum = -1; |
2213a65d | 1160 | |
10458914 | 1161 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
53e95fcf | 1162 | |
10458914 DJ |
1163 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
1164 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); | |
e53bef9f | 1165 | frame_base_set_default (gdbarch, &amd64_frame_base); |
c6b33596 MK |
1166 | |
1167 | /* If we have a register mapping, enable the generic core file support. */ | |
1168 | if (tdep->gregset_reg_offset) | |
1169 | set_gdbarch_regset_from_core_section (gdbarch, | |
e53bef9f | 1170 | amd64_regset_from_core_section); |
436675d3 PA |
1171 | |
1172 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); | |
c4f35dd8 MK |
1173 | } |
1174 | \f | |
1175 | ||
41d041d6 MK |
1176 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
1177 | sense that the instruction pointer and data pointer are simply | |
1178 | 64-bit offsets into the code segment and the data segment instead | |
1179 | of a selector offset pair. The functions below store the upper 32 | |
1180 | bits of these pointers (instead of just the 16-bits of the segment | |
1181 | selector). */ | |
1182 | ||
1183 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
1184 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
1185 | -1, do this for all registers. This function masks off any of the | |
1186 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
1187 | |
1188 | void | |
90f90721 | 1189 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
20a6ec49 | 1190 | const void *fxsave) |
c4f35dd8 | 1191 | { |
20a6ec49 MD |
1192 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1193 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1194 | ||
41d041d6 | 1195 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 1196 | |
20a6ec49 | 1197 | if (fxsave && gdbarch_ptr_bit (gdbarch) == 64) |
c4f35dd8 | 1198 | { |
d8de1ef7 | 1199 | const gdb_byte *regs = fxsave; |
41d041d6 | 1200 | |
20a6ec49 MD |
1201 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
1202 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
1203 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
1204 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
c4f35dd8 | 1205 | } |
0c1a73d6 MK |
1206 | } |
1207 | ||
3c017e40 MK |
1208 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
1209 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
1210 | all registers. This function doesn't touch any of the reserved | |
1211 | bits in *FXSAVE. */ | |
1212 | ||
1213 | void | |
1214 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
1215 | void *fxsave) | |
1216 | { | |
20a6ec49 MD |
1217 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
d8de1ef7 | 1219 | gdb_byte *regs = fxsave; |
3c017e40 MK |
1220 | |
1221 | i387_collect_fxsave (regcache, regnum, fxsave); | |
1222 | ||
20a6ec49 | 1223 | if (gdbarch_ptr_bit (gdbarch) == 64) |
f0ef85a5 | 1224 | { |
20a6ec49 MD |
1225 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
1226 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
1227 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
1228 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
f0ef85a5 | 1229 | } |
3c017e40 | 1230 | } |