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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
618f726f | 3 | Copyright (C) 2001-2016 Free Software Foundation, Inc. |
5ae96ec1 MK |
4 | |
5 | Contributed by Jiri Smid, SuSE Labs. | |
53e95fcf JS |
6 | |
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
12 | (at your option) any later version. |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf JS |
21 | |
22 | #include "defs.h" | |
35669430 DE |
23 | #include "opcode/i386.h" |
24 | #include "dis-asm.h" | |
c4f35dd8 MK |
25 | #include "arch-utils.h" |
26 | #include "block.h" | |
27 | #include "dummy-frame.h" | |
28 | #include "frame.h" | |
29 | #include "frame-base.h" | |
30 | #include "frame-unwind.h" | |
53e95fcf | 31 | #include "inferior.h" |
45741a9c | 32 | #include "infrun.h" |
53e95fcf | 33 | #include "gdbcmd.h" |
c4f35dd8 MK |
34 | #include "gdbcore.h" |
35 | #include "objfiles.h" | |
53e95fcf | 36 | #include "regcache.h" |
2c261fae | 37 | #include "regset.h" |
53e95fcf | 38 | #include "symfile.h" |
eda5a4d7 | 39 | #include "disasm.h" |
9c1488cb | 40 | #include "amd64-tdep.h" |
c4f35dd8 | 41 | #include "i387-tdep.h" |
97de3545 | 42 | #include "x86-xstate.h" |
53e95fcf | 43 | |
90884b2b | 44 | #include "features/i386/amd64.c" |
a055a187 | 45 | #include "features/i386/amd64-avx.c" |
e43e105e | 46 | #include "features/i386/amd64-mpx.c" |
01f9f808 MS |
47 | #include "features/i386/amd64-avx512.c" |
48 | ||
ac1438b5 L |
49 | #include "features/i386/x32.c" |
50 | #include "features/i386/x32-avx.c" | |
01f9f808 | 51 | #include "features/i386/x32-avx512.c" |
90884b2b | 52 | |
6710bf39 SS |
53 | #include "ax.h" |
54 | #include "ax-gdb.h" | |
55 | ||
e53bef9f MK |
56 | /* Note that the AMD64 architecture was previously known as x86-64. |
57 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 58 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
59 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
60 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
61 | x86_64_-prefix since it's so much easier to type. */ | |
62 | ||
402ecd56 | 63 | /* Register information. */ |
c4f35dd8 | 64 | |
6707b003 | 65 | static const char *amd64_register_names[] = |
de220d0f | 66 | { |
6707b003 | 67 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
c4f35dd8 MK |
68 | |
69 | /* %r8 is indeed register number 8. */ | |
6707b003 UW |
70 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
71 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", | |
c4f35dd8 | 72 | |
af233647 | 73 | /* %st0 is register number 24. */ |
6707b003 UW |
74 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
75 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", | |
c4f35dd8 | 76 | |
af233647 | 77 | /* %xmm0 is register number 40. */ |
6707b003 UW |
78 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
79 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", | |
80 | "mxcsr", | |
0e04a514 ML |
81 | }; |
82 | ||
a055a187 L |
83 | static const char *amd64_ymm_names[] = |
84 | { | |
85 | "ymm0", "ymm1", "ymm2", "ymm3", | |
86 | "ymm4", "ymm5", "ymm6", "ymm7", | |
87 | "ymm8", "ymm9", "ymm10", "ymm11", | |
88 | "ymm12", "ymm13", "ymm14", "ymm15" | |
89 | }; | |
90 | ||
01f9f808 MS |
91 | static const char *amd64_ymm_avx512_names[] = |
92 | { | |
93 | "ymm16", "ymm17", "ymm18", "ymm19", | |
94 | "ymm20", "ymm21", "ymm22", "ymm23", | |
95 | "ymm24", "ymm25", "ymm26", "ymm27", | |
96 | "ymm28", "ymm29", "ymm30", "ymm31" | |
97 | }; | |
98 | ||
a055a187 L |
99 | static const char *amd64_ymmh_names[] = |
100 | { | |
101 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
102 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
103 | "ymm8h", "ymm9h", "ymm10h", "ymm11h", | |
104 | "ymm12h", "ymm13h", "ymm14h", "ymm15h" | |
105 | }; | |
de220d0f | 106 | |
01f9f808 MS |
107 | static const char *amd64_ymmh_avx512_names[] = |
108 | { | |
109 | "ymm16h", "ymm17h", "ymm18h", "ymm19h", | |
110 | "ymm20h", "ymm21h", "ymm22h", "ymm23h", | |
111 | "ymm24h", "ymm25h", "ymm26h", "ymm27h", | |
112 | "ymm28h", "ymm29h", "ymm30h", "ymm31h" | |
113 | }; | |
114 | ||
e43e105e WT |
115 | static const char *amd64_mpx_names[] = |
116 | { | |
117 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
118 | }; | |
119 | ||
01f9f808 MS |
120 | static const char *amd64_k_names[] = |
121 | { | |
122 | "k0", "k1", "k2", "k3", | |
123 | "k4", "k5", "k6", "k7" | |
124 | }; | |
125 | ||
126 | static const char *amd64_zmmh_names[] = | |
127 | { | |
128 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
129 | "zmm4h", "zmm5h", "zmm6h", "zmm7h", | |
130 | "zmm8h", "zmm9h", "zmm10h", "zmm11h", | |
131 | "zmm12h", "zmm13h", "zmm14h", "zmm15h", | |
132 | "zmm16h", "zmm17h", "zmm18h", "zmm19h", | |
133 | "zmm20h", "zmm21h", "zmm22h", "zmm23h", | |
134 | "zmm24h", "zmm25h", "zmm26h", "zmm27h", | |
135 | "zmm28h", "zmm29h", "zmm30h", "zmm31h" | |
136 | }; | |
137 | ||
138 | static const char *amd64_zmm_names[] = | |
139 | { | |
140 | "zmm0", "zmm1", "zmm2", "zmm3", | |
141 | "zmm4", "zmm5", "zmm6", "zmm7", | |
142 | "zmm8", "zmm9", "zmm10", "zmm11", | |
143 | "zmm12", "zmm13", "zmm14", "zmm15", | |
144 | "zmm16", "zmm17", "zmm18", "zmm19", | |
145 | "zmm20", "zmm21", "zmm22", "zmm23", | |
146 | "zmm24", "zmm25", "zmm26", "zmm27", | |
147 | "zmm28", "zmm29", "zmm30", "zmm31" | |
148 | }; | |
149 | ||
150 | static const char *amd64_xmm_avx512_names[] = { | |
151 | "xmm16", "xmm17", "xmm18", "xmm19", | |
152 | "xmm20", "xmm21", "xmm22", "xmm23", | |
153 | "xmm24", "xmm25", "xmm26", "xmm27", | |
154 | "xmm28", "xmm29", "xmm30", "xmm31" | |
155 | }; | |
156 | ||
c4f35dd8 MK |
157 | /* DWARF Register Number Mapping as defined in the System V psABI, |
158 | section 3.6. */ | |
53e95fcf | 159 | |
e53bef9f | 160 | static int amd64_dwarf_regmap[] = |
0e04a514 | 161 | { |
c4f35dd8 | 162 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
163 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
164 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
165 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
166 | |
167 | /* Frame Pointer Register RBP. */ | |
90f90721 | 168 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
169 | |
170 | /* Stack Pointer Register RSP. */ | |
90f90721 | 171 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
172 | |
173 | /* Extended Integer Registers 8 - 15. */ | |
5b856f36 PM |
174 | AMD64_R8_REGNUM, /* %r8 */ |
175 | AMD64_R9_REGNUM, /* %r9 */ | |
176 | AMD64_R10_REGNUM, /* %r10 */ | |
177 | AMD64_R11_REGNUM, /* %r11 */ | |
178 | AMD64_R12_REGNUM, /* %r12 */ | |
179 | AMD64_R13_REGNUM, /* %r13 */ | |
180 | AMD64_R14_REGNUM, /* %r14 */ | |
181 | AMD64_R15_REGNUM, /* %r15 */ | |
c4f35dd8 | 182 | |
59207364 | 183 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 184 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
185 | |
186 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
187 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
188 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
189 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
190 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
191 | |
192 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
193 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
194 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
195 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
196 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
197 | |
198 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
199 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
200 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
201 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
c6f4c129 | 202 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
f7ca3fcf PM |
203 | |
204 | /* MMX Registers 0 - 7. | |
205 | We have to handle those registers specifically, as their register | |
206 | number within GDB depends on the target (or they may even not be | |
207 | available at all). */ | |
208 | -1, -1, -1, -1, -1, -1, -1, -1, | |
209 | ||
c6f4c129 JB |
210 | /* Control and Status Flags Register. */ |
211 | AMD64_EFLAGS_REGNUM, | |
212 | ||
213 | /* Selector Registers. */ | |
214 | AMD64_ES_REGNUM, | |
215 | AMD64_CS_REGNUM, | |
216 | AMD64_SS_REGNUM, | |
217 | AMD64_DS_REGNUM, | |
218 | AMD64_FS_REGNUM, | |
219 | AMD64_GS_REGNUM, | |
220 | -1, | |
221 | -1, | |
222 | ||
223 | /* Segment Base Address Registers. */ | |
224 | -1, | |
225 | -1, | |
226 | -1, | |
227 | -1, | |
228 | ||
229 | /* Special Selector Registers. */ | |
230 | -1, | |
231 | -1, | |
232 | ||
233 | /* Floating Point Control Registers. */ | |
234 | AMD64_MXCSR_REGNUM, | |
235 | AMD64_FCTRL_REGNUM, | |
236 | AMD64_FSTAT_REGNUM | |
c4f35dd8 | 237 | }; |
0e04a514 | 238 | |
e53bef9f MK |
239 | static const int amd64_dwarf_regmap_len = |
240 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 241 | |
c4f35dd8 MK |
242 | /* Convert DWARF register number REG to the appropriate register |
243 | number used by GDB. */ | |
26abbdc4 | 244 | |
c4f35dd8 | 245 | static int |
d3f73121 | 246 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
53e95fcf | 247 | { |
a055a187 L |
248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
249 | int ymm0_regnum = tdep->ymm0_regnum; | |
c4f35dd8 | 250 | int regnum = -1; |
53e95fcf | 251 | |
16aff9a6 | 252 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
e53bef9f | 253 | regnum = amd64_dwarf_regmap[reg]; |
53e95fcf | 254 | |
0fde2c53 | 255 | if (ymm0_regnum >= 0 |
a055a187 L |
256 | && i386_xmm_regnum_p (gdbarch, regnum)) |
257 | regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); | |
c4f35dd8 MK |
258 | |
259 | return regnum; | |
53e95fcf | 260 | } |
d532c08f | 261 | |
35669430 DE |
262 | /* Map architectural register numbers to gdb register numbers. */ |
263 | ||
264 | static const int amd64_arch_regmap[16] = | |
265 | { | |
266 | AMD64_RAX_REGNUM, /* %rax */ | |
267 | AMD64_RCX_REGNUM, /* %rcx */ | |
268 | AMD64_RDX_REGNUM, /* %rdx */ | |
269 | AMD64_RBX_REGNUM, /* %rbx */ | |
270 | AMD64_RSP_REGNUM, /* %rsp */ | |
271 | AMD64_RBP_REGNUM, /* %rbp */ | |
272 | AMD64_RSI_REGNUM, /* %rsi */ | |
273 | AMD64_RDI_REGNUM, /* %rdi */ | |
274 | AMD64_R8_REGNUM, /* %r8 */ | |
275 | AMD64_R9_REGNUM, /* %r9 */ | |
276 | AMD64_R10_REGNUM, /* %r10 */ | |
277 | AMD64_R11_REGNUM, /* %r11 */ | |
278 | AMD64_R12_REGNUM, /* %r12 */ | |
279 | AMD64_R13_REGNUM, /* %r13 */ | |
280 | AMD64_R14_REGNUM, /* %r14 */ | |
281 | AMD64_R15_REGNUM /* %r15 */ | |
282 | }; | |
283 | ||
284 | static const int amd64_arch_regmap_len = | |
285 | (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); | |
286 | ||
287 | /* Convert architectural register number REG to the appropriate register | |
288 | number used by GDB. */ | |
289 | ||
290 | static int | |
291 | amd64_arch_reg_to_regnum (int reg) | |
292 | { | |
293 | gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); | |
294 | ||
295 | return amd64_arch_regmap[reg]; | |
296 | } | |
297 | ||
1ba53b71 L |
298 | /* Register names for byte pseudo-registers. */ |
299 | ||
300 | static const char *amd64_byte_names[] = | |
301 | { | |
302 | "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", | |
fe01d668 L |
303 | "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", |
304 | "ah", "bh", "ch", "dh" | |
1ba53b71 L |
305 | }; |
306 | ||
fe01d668 L |
307 | /* Number of lower byte registers. */ |
308 | #define AMD64_NUM_LOWER_BYTE_REGS 16 | |
309 | ||
1ba53b71 L |
310 | /* Register names for word pseudo-registers. */ |
311 | ||
312 | static const char *amd64_word_names[] = | |
313 | { | |
9cad29ac | 314 | "ax", "bx", "cx", "dx", "si", "di", "bp", "", |
1ba53b71 L |
315 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
316 | }; | |
317 | ||
318 | /* Register names for dword pseudo-registers. */ | |
319 | ||
320 | static const char *amd64_dword_names[] = | |
321 | { | |
322 | "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", | |
fff4548b MK |
323 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", |
324 | "eip" | |
1ba53b71 L |
325 | }; |
326 | ||
327 | /* Return the name of register REGNUM. */ | |
328 | ||
329 | static const char * | |
330 | amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
331 | { | |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
333 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
334 | return amd64_byte_names[regnum - tdep->al_regnum]; | |
01f9f808 MS |
335 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
336 | return amd64_zmm_names[regnum - tdep->zmm0_regnum]; | |
a055a187 L |
337 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
338 | return amd64_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
339 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
340 | return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum]; | |
1ba53b71 L |
341 | else if (i386_word_regnum_p (gdbarch, regnum)) |
342 | return amd64_word_names[regnum - tdep->ax_regnum]; | |
343 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
344 | return amd64_dword_names[regnum - tdep->eax_regnum]; | |
345 | else | |
346 | return i386_pseudo_register_name (gdbarch, regnum); | |
347 | } | |
348 | ||
3543a589 TT |
349 | static struct value * |
350 | amd64_pseudo_register_read_value (struct gdbarch *gdbarch, | |
351 | struct regcache *regcache, | |
352 | int regnum) | |
1ba53b71 L |
353 | { |
354 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; | |
355 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
05d1431c | 356 | enum register_status status; |
3543a589 TT |
357 | struct value *result_value; |
358 | gdb_byte *buf; | |
359 | ||
360 | result_value = allocate_value (register_type (gdbarch, regnum)); | |
361 | VALUE_LVAL (result_value) = lval_register; | |
362 | VALUE_REGNUM (result_value) = regnum; | |
363 | buf = value_contents_raw (result_value); | |
1ba53b71 L |
364 | |
365 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
366 | { | |
367 | int gpnum = regnum - tdep->al_regnum; | |
368 | ||
369 | /* Extract (always little endian). */ | |
fe01d668 L |
370 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
371 | { | |
372 | /* Special handling for AH, BH, CH, DH. */ | |
05d1431c PA |
373 | status = regcache_raw_read (regcache, |
374 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, | |
375 | raw_buf); | |
376 | if (status == REG_VALID) | |
377 | memcpy (buf, raw_buf + 1, 1); | |
3543a589 TT |
378 | else |
379 | mark_value_bytes_unavailable (result_value, 0, | |
380 | TYPE_LENGTH (value_type (result_value))); | |
fe01d668 L |
381 | } |
382 | else | |
383 | { | |
05d1431c PA |
384 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
385 | if (status == REG_VALID) | |
386 | memcpy (buf, raw_buf, 1); | |
3543a589 TT |
387 | else |
388 | mark_value_bytes_unavailable (result_value, 0, | |
389 | TYPE_LENGTH (value_type (result_value))); | |
fe01d668 | 390 | } |
1ba53b71 L |
391 | } |
392 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
393 | { | |
394 | int gpnum = regnum - tdep->eax_regnum; | |
395 | /* Extract (always little endian). */ | |
05d1431c PA |
396 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
397 | if (status == REG_VALID) | |
398 | memcpy (buf, raw_buf, 4); | |
3543a589 TT |
399 | else |
400 | mark_value_bytes_unavailable (result_value, 0, | |
401 | TYPE_LENGTH (value_type (result_value))); | |
1ba53b71 L |
402 | } |
403 | else | |
3543a589 TT |
404 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, |
405 | result_value); | |
406 | ||
407 | return result_value; | |
1ba53b71 L |
408 | } |
409 | ||
410 | static void | |
411 | amd64_pseudo_register_write (struct gdbarch *gdbarch, | |
412 | struct regcache *regcache, | |
413 | int regnum, const gdb_byte *buf) | |
414 | { | |
415 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; | |
416 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
417 | ||
418 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
419 | { | |
420 | int gpnum = regnum - tdep->al_regnum; | |
421 | ||
fe01d668 L |
422 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
423 | { | |
424 | /* Read ... AH, BH, CH, DH. */ | |
425 | regcache_raw_read (regcache, | |
426 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); | |
427 | /* ... Modify ... (always little endian). */ | |
428 | memcpy (raw_buf + 1, buf, 1); | |
429 | /* ... Write. */ | |
430 | regcache_raw_write (regcache, | |
431 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); | |
432 | } | |
433 | else | |
434 | { | |
435 | /* Read ... */ | |
436 | regcache_raw_read (regcache, gpnum, raw_buf); | |
437 | /* ... Modify ... (always little endian). */ | |
438 | memcpy (raw_buf, buf, 1); | |
439 | /* ... Write. */ | |
440 | regcache_raw_write (regcache, gpnum, raw_buf); | |
441 | } | |
1ba53b71 L |
442 | } |
443 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
444 | { | |
445 | int gpnum = regnum - tdep->eax_regnum; | |
446 | ||
447 | /* Read ... */ | |
448 | regcache_raw_read (regcache, gpnum, raw_buf); | |
449 | /* ... Modify ... (always little endian). */ | |
450 | memcpy (raw_buf, buf, 4); | |
451 | /* ... Write. */ | |
452 | regcache_raw_write (regcache, gpnum, raw_buf); | |
453 | } | |
454 | else | |
455 | i386_pseudo_register_write (gdbarch, regcache, regnum, buf); | |
456 | } | |
457 | ||
53e95fcf JS |
458 | \f |
459 | ||
bf4d6c1c JB |
460 | /* Register classes as defined in the psABI. */ |
461 | ||
462 | enum amd64_reg_class | |
463 | { | |
464 | AMD64_INTEGER, | |
465 | AMD64_SSE, | |
466 | AMD64_SSEUP, | |
467 | AMD64_X87, | |
468 | AMD64_X87UP, | |
469 | AMD64_COMPLEX_X87, | |
470 | AMD64_NO_CLASS, | |
471 | AMD64_MEMORY | |
472 | }; | |
473 | ||
efb1c01c MK |
474 | /* Return the union class of CLASS1 and CLASS2. See the psABI for |
475 | details. */ | |
476 | ||
477 | static enum amd64_reg_class | |
478 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
479 | { | |
480 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
481 | if (class1 == class2) | |
482 | return class1; | |
483 | ||
484 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
485 | is the other class. */ | |
486 | if (class1 == AMD64_NO_CLASS) | |
487 | return class2; | |
488 | if (class2 == AMD64_NO_CLASS) | |
489 | return class1; | |
490 | ||
491 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
492 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
493 | return AMD64_MEMORY; | |
494 | ||
495 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
496 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
497 | return AMD64_INTEGER; | |
498 | ||
499 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
500 | MEMORY is used as class. */ | |
501 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
502 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
503 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
504 | return AMD64_MEMORY; | |
505 | ||
506 | /* Rule (f): Otherwise class SSE is used. */ | |
507 | return AMD64_SSE; | |
508 | } | |
509 | ||
fe978cb0 | 510 | static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); |
bf4d6c1c | 511 | |
79b1ab3d MK |
512 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
513 | ||
514 | static int | |
515 | amd64_non_pod_p (struct type *type) | |
516 | { | |
517 | /* ??? A class with a base class certainly isn't POD, but does this | |
518 | catch all non-POD structure types? */ | |
519 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
520 | return 1; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
efb1c01c MK |
525 | /* Classify TYPE according to the rules for aggregate (structures and |
526 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
527 | |
528 | static void | |
fe978cb0 | 529 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) |
53e95fcf | 530 | { |
efb1c01c MK |
531 | /* 1. If the size of an object is larger than two eightbytes, or in |
532 | C++, is a non-POD structure or union type, or contains | |
533 | unaligned fields, it has class memory. */ | |
744a8059 | 534 | if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) |
53e95fcf | 535 | { |
fe978cb0 | 536 | theclass[0] = theclass[1] = AMD64_MEMORY; |
efb1c01c | 537 | return; |
53e95fcf | 538 | } |
efb1c01c MK |
539 | |
540 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
fe978cb0 | 541 | theclass[0] = theclass[1] = AMD64_NO_CLASS; |
efb1c01c MK |
542 | |
543 | /* 3. Each field of an object is classified recursively so that | |
544 | always two fields are considered. The resulting class is | |
545 | calculated according to the classes of the fields in the | |
546 | eightbyte: */ | |
547 | ||
548 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 549 | { |
efb1c01c MK |
550 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
551 | ||
552 | /* All fields in an array have the same type. */ | |
fe978cb0 PA |
553 | amd64_classify (subtype, theclass); |
554 | if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS) | |
555 | theclass[1] = theclass[0]; | |
8ffd9b1b | 556 | } |
53e95fcf JS |
557 | else |
558 | { | |
efb1c01c | 559 | int i; |
53e95fcf | 560 | |
efb1c01c MK |
561 | /* Structure or union. */ |
562 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
563 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
564 | ||
565 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 566 | { |
efb1c01c MK |
567 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
568 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
569 | enum amd64_reg_class subclass[2]; | |
e4e2711a JB |
570 | int bitsize = TYPE_FIELD_BITSIZE (type, i); |
571 | int endpos; | |
572 | ||
573 | if (bitsize == 0) | |
574 | bitsize = TYPE_LENGTH (subtype) * 8; | |
575 | endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; | |
efb1c01c | 576 | |
562c50c2 | 577 | /* Ignore static fields. */ |
d6a843b5 | 578 | if (field_is_static (&TYPE_FIELD (type, i))) |
562c50c2 MK |
579 | continue; |
580 | ||
efb1c01c MK |
581 | gdb_assert (pos == 0 || pos == 1); |
582 | ||
583 | amd64_classify (subtype, subclass); | |
fe978cb0 | 584 | theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); |
e4e2711a JB |
585 | if (bitsize <= 64 && pos == 0 && endpos == 1) |
586 | /* This is a bit of an odd case: We have a field that would | |
587 | normally fit in one of the two eightbytes, except that | |
588 | it is placed in a way that this field straddles them. | |
589 | This has been seen with a structure containing an array. | |
590 | ||
591 | The ABI is a bit unclear in this case, but we assume that | |
592 | this field's class (stored in subclass[0]) must also be merged | |
593 | into class[1]. In other words, our field has a piece stored | |
594 | in the second eight-byte, and thus its class applies to | |
595 | the second eight-byte as well. | |
596 | ||
597 | In the case where the field length exceeds 8 bytes, | |
598 | it should not be necessary to merge the field class | |
599 | into class[1]. As LEN > 8, subclass[1] is necessarily | |
600 | different from AMD64_NO_CLASS. If subclass[1] is equal | |
601 | to subclass[0], then the normal class[1]/subclass[1] | |
602 | merging will take care of everything. For subclass[1] | |
603 | to be different from subclass[0], I can only see the case | |
604 | where we have a SSE/SSEUP or X87/X87UP pair, which both | |
605 | use up all 16 bytes of the aggregate, and are already | |
606 | handled just fine (because each portion sits on its own | |
607 | 8-byte). */ | |
fe978cb0 | 608 | theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); |
efb1c01c | 609 | if (pos == 0) |
fe978cb0 | 610 | theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); |
53e95fcf | 611 | } |
53e95fcf | 612 | } |
efb1c01c MK |
613 | |
614 | /* 4. Then a post merger cleanup is done: */ | |
615 | ||
616 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
617 | passed in memory. */ | |
fe978cb0 PA |
618 | if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY) |
619 | theclass[0] = theclass[1] = AMD64_MEMORY; | |
efb1c01c | 620 | |
177b42fe | 621 | /* Rule (b): If SSEUP is not preceded by SSE, it is converted to |
efb1c01c | 622 | SSE. */ |
fe978cb0 PA |
623 | if (theclass[0] == AMD64_SSEUP) |
624 | theclass[0] = AMD64_SSE; | |
625 | if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE) | |
626 | theclass[1] = AMD64_SSE; | |
efb1c01c MK |
627 | } |
628 | ||
629 | /* Classify TYPE, and store the result in CLASS. */ | |
630 | ||
bf4d6c1c | 631 | static void |
fe978cb0 | 632 | amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) |
efb1c01c MK |
633 | { |
634 | enum type_code code = TYPE_CODE (type); | |
635 | int len = TYPE_LENGTH (type); | |
636 | ||
fe978cb0 | 637 | theclass[0] = theclass[1] = AMD64_NO_CLASS; |
efb1c01c MK |
638 | |
639 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
5a7225ed JB |
640 | long, long long, and pointers are in the INTEGER class. Similarly, |
641 | range types, used by languages such as Ada, are also in the INTEGER | |
642 | class. */ | |
efb1c01c | 643 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
b929c77f | 644 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
9db13498 | 645 | || code == TYPE_CODE_CHAR |
efb1c01c MK |
646 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
647 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
fe978cb0 | 648 | theclass[0] = AMD64_INTEGER; |
efb1c01c | 649 | |
5daa78cc TJB |
650 | /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 |
651 | are in class SSE. */ | |
652 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) | |
653 | && (len == 4 || len == 8)) | |
efb1c01c | 654 | /* FIXME: __m64 . */ |
fe978cb0 | 655 | theclass[0] = AMD64_SSE; |
efb1c01c | 656 | |
5daa78cc TJB |
657 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
658 | two halves. The least significant ones belong to class SSE, the most | |
efb1c01c | 659 | significant one to class SSEUP. */ |
5daa78cc TJB |
660 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
661 | /* FIXME: __float128, __m128. */ | |
fe978cb0 | 662 | theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP; |
efb1c01c MK |
663 | |
664 | /* The 64-bit mantissa of arguments of type long double belongs to | |
665 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
666 | class X87UP. */ | |
667 | else if (code == TYPE_CODE_FLT && len == 16) | |
668 | /* Class X87 and X87UP. */ | |
fe978cb0 | 669 | theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; |
efb1c01c | 670 | |
7f7930dd MK |
671 | /* Arguments of complex T where T is one of the types float or |
672 | double get treated as if they are implemented as: | |
673 | ||
674 | struct complexT { | |
675 | T real; | |
676 | T imag; | |
5f52445b YQ |
677 | }; |
678 | ||
679 | */ | |
7f7930dd | 680 | else if (code == TYPE_CODE_COMPLEX && len == 8) |
fe978cb0 | 681 | theclass[0] = AMD64_SSE; |
7f7930dd | 682 | else if (code == TYPE_CODE_COMPLEX && len == 16) |
fe978cb0 | 683 | theclass[0] = theclass[1] = AMD64_SSE; |
7f7930dd MK |
684 | |
685 | /* A variable of type complex long double is classified as type | |
686 | COMPLEX_X87. */ | |
687 | else if (code == TYPE_CODE_COMPLEX && len == 32) | |
fe978cb0 | 688 | theclass[0] = AMD64_COMPLEX_X87; |
7f7930dd | 689 | |
efb1c01c MK |
690 | /* Aggregates. */ |
691 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
692 | || code == TYPE_CODE_UNION) | |
fe978cb0 | 693 | amd64_classify_aggregate (type, theclass); |
efb1c01c MK |
694 | } |
695 | ||
696 | static enum return_value_convention | |
6a3a010b | 697 | amd64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 698 | struct type *type, struct regcache *regcache, |
42835c2b | 699 | gdb_byte *readbuf, const gdb_byte *writebuf) |
efb1c01c | 700 | { |
fe978cb0 | 701 | enum amd64_reg_class theclass[2]; |
efb1c01c | 702 | int len = TYPE_LENGTH (type); |
90f90721 MK |
703 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
704 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
705 | int integer_reg = 0; |
706 | int sse_reg = 0; | |
707 | int i; | |
708 | ||
709 | gdb_assert (!(readbuf && writebuf)); | |
710 | ||
711 | /* 1. Classify the return type with the classification algorithm. */ | |
fe978cb0 | 712 | amd64_classify (type, theclass); |
efb1c01c MK |
713 | |
714 | /* 2. If the type has class MEMORY, then the caller provides space | |
6fa57a7d | 715 | for the return value and passes the address of this storage in |
0963b4bd | 716 | %rdi as if it were the first argument to the function. In effect, |
6fa57a7d MK |
717 | this address becomes a hidden first argument. |
718 | ||
719 | On return %rax will contain the address that has been passed in | |
720 | by the caller in %rdi. */ | |
fe978cb0 | 721 | if (theclass[0] == AMD64_MEMORY) |
6fa57a7d MK |
722 | { |
723 | /* As indicated by the comment above, the ABI guarantees that we | |
724 | can always find the return value just after the function has | |
725 | returned. */ | |
726 | ||
727 | if (readbuf) | |
728 | { | |
729 | ULONGEST addr; | |
730 | ||
731 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); | |
732 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
733 | } | |
734 | ||
735 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
736 | } | |
efb1c01c | 737 | |
7f7930dd MK |
738 | /* 8. If the class is COMPLEX_X87, the real part of the value is |
739 | returned in %st0 and the imaginary part in %st1. */ | |
fe978cb0 | 740 | if (theclass[0] == AMD64_COMPLEX_X87) |
7f7930dd MK |
741 | { |
742 | if (readbuf) | |
743 | { | |
744 | regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); | |
745 | regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); | |
746 | } | |
747 | ||
748 | if (writebuf) | |
749 | { | |
750 | i387_return_value (gdbarch, regcache); | |
751 | regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); | |
752 | regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); | |
753 | ||
754 | /* Fix up the tag word such that both %st(0) and %st(1) are | |
755 | marked as valid. */ | |
756 | regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); | |
757 | } | |
758 | ||
759 | return RETURN_VALUE_REGISTER_CONVENTION; | |
760 | } | |
761 | ||
fe978cb0 | 762 | gdb_assert (theclass[1] != AMD64_MEMORY); |
bad43aa5 | 763 | gdb_assert (len <= 16); |
efb1c01c MK |
764 | |
765 | for (i = 0; len > 0; i++, len -= 8) | |
766 | { | |
767 | int regnum = -1; | |
768 | int offset = 0; | |
769 | ||
fe978cb0 | 770 | switch (theclass[i]) |
efb1c01c MK |
771 | { |
772 | case AMD64_INTEGER: | |
773 | /* 3. If the class is INTEGER, the next available register | |
774 | of the sequence %rax, %rdx is used. */ | |
775 | regnum = integer_regnum[integer_reg++]; | |
776 | break; | |
777 | ||
778 | case AMD64_SSE: | |
779 | /* 4. If the class is SSE, the next available SSE register | |
780 | of the sequence %xmm0, %xmm1 is used. */ | |
781 | regnum = sse_regnum[sse_reg++]; | |
782 | break; | |
783 | ||
784 | case AMD64_SSEUP: | |
785 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
786 | upper half of the last used SSE register. */ | |
787 | gdb_assert (sse_reg > 0); | |
788 | regnum = sse_regnum[sse_reg - 1]; | |
789 | offset = 8; | |
790 | break; | |
791 | ||
792 | case AMD64_X87: | |
793 | /* 6. If the class is X87, the value is returned on the X87 | |
794 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 795 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
796 | if (writebuf) |
797 | i387_return_value (gdbarch, regcache); | |
798 | break; | |
799 | ||
800 | case AMD64_X87UP: | |
801 | /* 7. If the class is X87UP, the value is returned together | |
802 | with the previous X87 value in %st0. */ | |
fe978cb0 | 803 | gdb_assert (i > 0 && theclass[0] == AMD64_X87); |
90f90721 | 804 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
805 | offset = 8; |
806 | len = 2; | |
807 | break; | |
808 | ||
809 | case AMD64_NO_CLASS: | |
810 | continue; | |
811 | ||
812 | default: | |
813 | gdb_assert (!"Unexpected register class."); | |
814 | } | |
815 | ||
816 | gdb_assert (regnum != -1); | |
817 | ||
818 | if (readbuf) | |
819 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 820 | readbuf + i * 8); |
efb1c01c MK |
821 | if (writebuf) |
822 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
42835c2b | 823 | writebuf + i * 8); |
efb1c01c MK |
824 | } |
825 | ||
826 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
827 | } |
828 | \f | |
829 | ||
720aa428 MK |
830 | static CORE_ADDR |
831 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 832 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 | 833 | { |
bf4d6c1c JB |
834 | static int integer_regnum[] = |
835 | { | |
836 | AMD64_RDI_REGNUM, /* %rdi */ | |
837 | AMD64_RSI_REGNUM, /* %rsi */ | |
838 | AMD64_RDX_REGNUM, /* %rdx */ | |
839 | AMD64_RCX_REGNUM, /* %rcx */ | |
5b856f36 PM |
840 | AMD64_R8_REGNUM, /* %r8 */ |
841 | AMD64_R9_REGNUM /* %r9 */ | |
bf4d6c1c | 842 | }; |
720aa428 MK |
843 | static int sse_regnum[] = |
844 | { | |
845 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
846 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
847 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
848 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
849 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 | 850 | }; |
224c3ddb | 851 | struct value **stack_args = XALLOCAVEC (struct value *, nargs); |
720aa428 MK |
852 | int num_stack_args = 0; |
853 | int num_elements = 0; | |
854 | int element = 0; | |
855 | int integer_reg = 0; | |
856 | int sse_reg = 0; | |
857 | int i; | |
858 | ||
6470d250 MK |
859 | /* Reserve a register for the "hidden" argument. */ |
860 | if (struct_return) | |
861 | integer_reg++; | |
862 | ||
720aa428 MK |
863 | for (i = 0; i < nargs; i++) |
864 | { | |
4991999e | 865 | struct type *type = value_type (args[i]); |
720aa428 | 866 | int len = TYPE_LENGTH (type); |
fe978cb0 | 867 | enum amd64_reg_class theclass[2]; |
720aa428 MK |
868 | int needed_integer_regs = 0; |
869 | int needed_sse_regs = 0; | |
870 | int j; | |
871 | ||
872 | /* Classify argument. */ | |
fe978cb0 | 873 | amd64_classify (type, theclass); |
720aa428 MK |
874 | |
875 | /* Calculate the number of integer and SSE registers needed for | |
876 | this argument. */ | |
877 | for (j = 0; j < 2; j++) | |
878 | { | |
fe978cb0 | 879 | if (theclass[j] == AMD64_INTEGER) |
720aa428 | 880 | needed_integer_regs++; |
fe978cb0 | 881 | else if (theclass[j] == AMD64_SSE) |
720aa428 MK |
882 | needed_sse_regs++; |
883 | } | |
884 | ||
885 | /* Check whether enough registers are available, and if the | |
886 | argument should be passed in registers at all. */ | |
bf4d6c1c | 887 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) |
720aa428 MK |
888 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) |
889 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
890 | { | |
891 | /* The argument will be passed on the stack. */ | |
892 | num_elements += ((len + 7) / 8); | |
849e9755 | 893 | stack_args[num_stack_args++] = args[i]; |
720aa428 MK |
894 | } |
895 | else | |
896 | { | |
897 | /* The argument will be passed in registers. */ | |
d8de1ef7 MK |
898 | const gdb_byte *valbuf = value_contents (args[i]); |
899 | gdb_byte buf[8]; | |
720aa428 MK |
900 | |
901 | gdb_assert (len <= 16); | |
902 | ||
903 | for (j = 0; len > 0; j++, len -= 8) | |
904 | { | |
905 | int regnum = -1; | |
906 | int offset = 0; | |
907 | ||
fe978cb0 | 908 | switch (theclass[j]) |
720aa428 MK |
909 | { |
910 | case AMD64_INTEGER: | |
bf4d6c1c | 911 | regnum = integer_regnum[integer_reg++]; |
720aa428 MK |
912 | break; |
913 | ||
914 | case AMD64_SSE: | |
915 | regnum = sse_regnum[sse_reg++]; | |
916 | break; | |
917 | ||
918 | case AMD64_SSEUP: | |
919 | gdb_assert (sse_reg > 0); | |
920 | regnum = sse_regnum[sse_reg - 1]; | |
921 | offset = 8; | |
922 | break; | |
923 | ||
924 | default: | |
925 | gdb_assert (!"Unexpected register class."); | |
926 | } | |
927 | ||
928 | gdb_assert (regnum != -1); | |
929 | memset (buf, 0, sizeof buf); | |
930 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
931 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
932 | } | |
933 | } | |
934 | } | |
935 | ||
936 | /* Allocate space for the arguments on the stack. */ | |
937 | sp -= num_elements * 8; | |
938 | ||
939 | /* The psABI says that "The end of the input argument area shall be | |
940 | aligned on a 16 byte boundary." */ | |
941 | sp &= ~0xf; | |
942 | ||
943 | /* Write out the arguments to the stack. */ | |
944 | for (i = 0; i < num_stack_args; i++) | |
945 | { | |
4991999e | 946 | struct type *type = value_type (stack_args[i]); |
d8de1ef7 | 947 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
849e9755 JB |
948 | int len = TYPE_LENGTH (type); |
949 | ||
950 | write_memory (sp + element * 8, valbuf, len); | |
951 | element += ((len + 7) / 8); | |
720aa428 MK |
952 | } |
953 | ||
954 | /* The psABI says that "For calls that may call functions that use | |
955 | varargs or stdargs (prototype-less calls or calls to functions | |
956 | containing ellipsis (...) in the declaration) %al is used as | |
957 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 958 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
959 | return sp; |
960 | } | |
961 | ||
c4f35dd8 | 962 | static CORE_ADDR |
7d9b040b | 963 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
e53bef9f MK |
964 | struct regcache *regcache, CORE_ADDR bp_addr, |
965 | int nargs, struct value **args, CORE_ADDR sp, | |
966 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 967 | { |
e17a4113 | 968 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d8de1ef7 | 969 | gdb_byte buf[8]; |
c4f35dd8 MK |
970 | |
971 | /* Pass arguments. */ | |
6470d250 | 972 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
973 | |
974 | /* Pass "hidden" argument". */ | |
975 | if (struct_return) | |
976 | { | |
e17a4113 | 977 | store_unsigned_integer (buf, 8, byte_order, struct_addr); |
bf4d6c1c | 978 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
979 | } |
980 | ||
981 | /* Store return address. */ | |
982 | sp -= 8; | |
e17a4113 | 983 | store_unsigned_integer (buf, 8, byte_order, bp_addr); |
c4f35dd8 MK |
984 | write_memory (sp, buf, 8); |
985 | ||
986 | /* Finally, update the stack pointer... */ | |
e17a4113 | 987 | store_unsigned_integer (buf, 8, byte_order, sp); |
90f90721 | 988 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
989 | |
990 | /* ...and fake a frame pointer. */ | |
90f90721 | 991 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 992 | |
3e210248 | 993 | return sp + 16; |
53e95fcf | 994 | } |
c4f35dd8 | 995 | \f |
35669430 DE |
996 | /* Displaced instruction handling. */ |
997 | ||
998 | /* A partially decoded instruction. | |
999 | This contains enough details for displaced stepping purposes. */ | |
1000 | ||
1001 | struct amd64_insn | |
1002 | { | |
1003 | /* The number of opcode bytes. */ | |
1004 | int opcode_len; | |
1005 | /* The offset of the rex prefix or -1 if not present. */ | |
1006 | int rex_offset; | |
1007 | /* The offset to the first opcode byte. */ | |
1008 | int opcode_offset; | |
1009 | /* The offset to the modrm byte or -1 if not present. */ | |
1010 | int modrm_offset; | |
1011 | ||
1012 | /* The raw instruction. */ | |
1013 | gdb_byte *raw_insn; | |
1014 | }; | |
1015 | ||
1016 | struct displaced_step_closure | |
1017 | { | |
1018 | /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ | |
1019 | int tmp_used; | |
1020 | int tmp_regno; | |
1021 | ULONGEST tmp_save; | |
1022 | ||
1023 | /* Details of the instruction. */ | |
1024 | struct amd64_insn insn_details; | |
1025 | ||
1026 | /* Amount of space allocated to insn_buf. */ | |
1027 | int max_len; | |
1028 | ||
1029 | /* The possibly modified insn. | |
1030 | This is a variable-length field. */ | |
1031 | gdb_byte insn_buf[1]; | |
1032 | }; | |
1033 | ||
1034 | /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with | |
1035 | ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, | |
1036 | at which point delete these in favor of libopcodes' versions). */ | |
1037 | ||
1038 | static const unsigned char onebyte_has_modrm[256] = { | |
1039 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1040 | /* ------------------------------- */ | |
1041 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
1042 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
1043 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
1044 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
1045 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
1046 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
1047 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
1048 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
1049 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
1050 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
1051 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
1052 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
1053 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
1054 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
1055 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
1056 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
1057 | /* ------------------------------- */ | |
1058 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1059 | }; | |
1060 | ||
1061 | static const unsigned char twobyte_has_modrm[256] = { | |
1062 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1063 | /* ------------------------------- */ | |
1064 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ | |
1065 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ | |
1066 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ | |
1067 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ | |
1068 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ | |
1069 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ | |
1070 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
1071 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ | |
1072 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ | |
1073 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
1074 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ | |
1075 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ | |
1076 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ | |
1077 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ | |
1078 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ | |
1079 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ | |
1080 | /* ------------------------------- */ | |
1081 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1082 | }; | |
1083 | ||
1084 | static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); | |
1085 | ||
1086 | static int | |
1087 | rex_prefix_p (gdb_byte pfx) | |
1088 | { | |
1089 | return REX_PREFIX_P (pfx); | |
1090 | } | |
1091 | ||
1092 | /* Skip the legacy instruction prefixes in INSN. | |
1093 | We assume INSN is properly sentineled so we don't have to worry | |
1094 | about falling off the end of the buffer. */ | |
1095 | ||
1096 | static gdb_byte * | |
1903f0e6 | 1097 | amd64_skip_prefixes (gdb_byte *insn) |
35669430 DE |
1098 | { |
1099 | while (1) | |
1100 | { | |
1101 | switch (*insn) | |
1102 | { | |
1103 | case DATA_PREFIX_OPCODE: | |
1104 | case ADDR_PREFIX_OPCODE: | |
1105 | case CS_PREFIX_OPCODE: | |
1106 | case DS_PREFIX_OPCODE: | |
1107 | case ES_PREFIX_OPCODE: | |
1108 | case FS_PREFIX_OPCODE: | |
1109 | case GS_PREFIX_OPCODE: | |
1110 | case SS_PREFIX_OPCODE: | |
1111 | case LOCK_PREFIX_OPCODE: | |
1112 | case REPE_PREFIX_OPCODE: | |
1113 | case REPNE_PREFIX_OPCODE: | |
1114 | ++insn; | |
1115 | continue; | |
1116 | default: | |
1117 | break; | |
1118 | } | |
1119 | break; | |
1120 | } | |
1121 | ||
1122 | return insn; | |
1123 | } | |
1124 | ||
35669430 DE |
1125 | /* Return an integer register (other than RSP) that is unused as an input |
1126 | operand in INSN. | |
1127 | In order to not require adding a rex prefix if the insn doesn't already | |
1128 | have one, the result is restricted to RAX ... RDI, sans RSP. | |
1129 | The register numbering of the result follows architecture ordering, | |
1130 | e.g. RDI = 7. */ | |
1131 | ||
1132 | static int | |
1133 | amd64_get_unused_input_int_reg (const struct amd64_insn *details) | |
1134 | { | |
1135 | /* 1 bit for each reg */ | |
1136 | int used_regs_mask = 0; | |
1137 | ||
1138 | /* There can be at most 3 int regs used as inputs in an insn, and we have | |
1139 | 7 to choose from (RAX ... RDI, sans RSP). | |
1140 | This allows us to take a conservative approach and keep things simple. | |
1141 | E.g. By avoiding RAX, we don't have to specifically watch for opcodes | |
1142 | that implicitly specify RAX. */ | |
1143 | ||
1144 | /* Avoid RAX. */ | |
1145 | used_regs_mask |= 1 << EAX_REG_NUM; | |
1146 | /* Similarily avoid RDX, implicit operand in divides. */ | |
1147 | used_regs_mask |= 1 << EDX_REG_NUM; | |
1148 | /* Avoid RSP. */ | |
1149 | used_regs_mask |= 1 << ESP_REG_NUM; | |
1150 | ||
1151 | /* If the opcode is one byte long and there's no ModRM byte, | |
1152 | assume the opcode specifies a register. */ | |
1153 | if (details->opcode_len == 1 && details->modrm_offset == -1) | |
1154 | used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); | |
1155 | ||
1156 | /* Mark used regs in the modrm/sib bytes. */ | |
1157 | if (details->modrm_offset != -1) | |
1158 | { | |
1159 | int modrm = details->raw_insn[details->modrm_offset]; | |
1160 | int mod = MODRM_MOD_FIELD (modrm); | |
1161 | int reg = MODRM_REG_FIELD (modrm); | |
1162 | int rm = MODRM_RM_FIELD (modrm); | |
1163 | int have_sib = mod != 3 && rm == 4; | |
1164 | ||
1165 | /* Assume the reg field of the modrm byte specifies a register. */ | |
1166 | used_regs_mask |= 1 << reg; | |
1167 | ||
1168 | if (have_sib) | |
1169 | { | |
1170 | int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); | |
d48ebb5b | 1171 | int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); |
35669430 | 1172 | used_regs_mask |= 1 << base; |
d48ebb5b | 1173 | used_regs_mask |= 1 << idx; |
35669430 DE |
1174 | } |
1175 | else | |
1176 | { | |
1177 | used_regs_mask |= 1 << rm; | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | gdb_assert (used_regs_mask < 256); | |
1182 | gdb_assert (used_regs_mask != 255); | |
1183 | ||
1184 | /* Finally, find a free reg. */ | |
1185 | { | |
1186 | int i; | |
1187 | ||
1188 | for (i = 0; i < 8; ++i) | |
1189 | { | |
1190 | if (! (used_regs_mask & (1 << i))) | |
1191 | return i; | |
1192 | } | |
1193 | ||
1194 | /* We shouldn't get here. */ | |
1195 | internal_error (__FILE__, __LINE__, _("unable to find free reg")); | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | /* Extract the details of INSN that we need. */ | |
1200 | ||
1201 | static void | |
1202 | amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) | |
1203 | { | |
1204 | gdb_byte *start = insn; | |
1205 | int need_modrm; | |
1206 | ||
1207 | details->raw_insn = insn; | |
1208 | ||
1209 | details->opcode_len = -1; | |
1210 | details->rex_offset = -1; | |
1211 | details->opcode_offset = -1; | |
1212 | details->modrm_offset = -1; | |
1213 | ||
1214 | /* Skip legacy instruction prefixes. */ | |
1903f0e6 | 1215 | insn = amd64_skip_prefixes (insn); |
35669430 DE |
1216 | |
1217 | /* Skip REX instruction prefix. */ | |
1218 | if (rex_prefix_p (*insn)) | |
1219 | { | |
1220 | details->rex_offset = insn - start; | |
1221 | ++insn; | |
1222 | } | |
1223 | ||
1224 | details->opcode_offset = insn - start; | |
1225 | ||
1226 | if (*insn == TWO_BYTE_OPCODE_ESCAPE) | |
1227 | { | |
1228 | /* Two or three-byte opcode. */ | |
1229 | ++insn; | |
1230 | need_modrm = twobyte_has_modrm[*insn]; | |
1231 | ||
1232 | /* Check for three-byte opcode. */ | |
1903f0e6 | 1233 | switch (*insn) |
35669430 | 1234 | { |
1903f0e6 DE |
1235 | case 0x24: |
1236 | case 0x25: | |
1237 | case 0x38: | |
1238 | case 0x3a: | |
1239 | case 0x7a: | |
1240 | case 0x7b: | |
35669430 DE |
1241 | ++insn; |
1242 | details->opcode_len = 3; | |
1903f0e6 DE |
1243 | break; |
1244 | default: | |
1245 | details->opcode_len = 2; | |
1246 | break; | |
35669430 | 1247 | } |
35669430 DE |
1248 | } |
1249 | else | |
1250 | { | |
1251 | /* One-byte opcode. */ | |
1252 | need_modrm = onebyte_has_modrm[*insn]; | |
1253 | details->opcode_len = 1; | |
1254 | } | |
1255 | ||
1256 | if (need_modrm) | |
1257 | { | |
1258 | ++insn; | |
1259 | details->modrm_offset = insn - start; | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | /* Update %rip-relative addressing in INSN. | |
1264 | ||
1265 | %rip-relative addressing only uses a 32-bit displacement. | |
1266 | 32 bits is not enough to be guaranteed to cover the distance between where | |
1267 | the real instruction is and where its copy is. | |
1268 | Convert the insn to use base+disp addressing. | |
1269 | We set base = pc + insn_length so we can leave disp unchanged. */ | |
c4f35dd8 | 1270 | |
35669430 DE |
1271 | static void |
1272 | fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, | |
1273 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) | |
1274 | { | |
e17a4113 | 1275 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
35669430 DE |
1276 | const struct amd64_insn *insn_details = &dsc->insn_details; |
1277 | int modrm_offset = insn_details->modrm_offset; | |
1278 | gdb_byte *insn = insn_details->raw_insn + modrm_offset; | |
1279 | CORE_ADDR rip_base; | |
1280 | int32_t disp; | |
1281 | int insn_length; | |
1282 | int arch_tmp_regno, tmp_regno; | |
1283 | ULONGEST orig_value; | |
1284 | ||
1285 | /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ | |
1286 | ++insn; | |
1287 | ||
1288 | /* Compute the rip-relative address. */ | |
e17a4113 | 1289 | disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); |
eda5a4d7 PA |
1290 | insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, |
1291 | dsc->max_len, from); | |
35669430 DE |
1292 | rip_base = from + insn_length; |
1293 | ||
1294 | /* We need a register to hold the address. | |
1295 | Pick one not used in the insn. | |
1296 | NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ | |
1297 | arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); | |
1298 | tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); | |
1299 | ||
1300 | /* REX.B should be unset as we were using rip-relative addressing, | |
1301 | but ensure it's unset anyway, tmp_regno is not r8-r15. */ | |
1302 | if (insn_details->rex_offset != -1) | |
1303 | dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; | |
1304 | ||
1305 | regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); | |
1306 | dsc->tmp_regno = tmp_regno; | |
1307 | dsc->tmp_save = orig_value; | |
1308 | dsc->tmp_used = 1; | |
1309 | ||
1310 | /* Convert the ModRM field to be base+disp. */ | |
1311 | dsc->insn_buf[modrm_offset] &= ~0xc7; | |
1312 | dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; | |
1313 | ||
1314 | regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); | |
1315 | ||
1316 | if (debug_displaced) | |
1317 | fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" | |
5af949e3 UW |
1318 | "displaced: using temp reg %d, old value %s, new value %s\n", |
1319 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), | |
1320 | paddress (gdbarch, rip_base)); | |
35669430 DE |
1321 | } |
1322 | ||
1323 | static void | |
1324 | fixup_displaced_copy (struct gdbarch *gdbarch, | |
1325 | struct displaced_step_closure *dsc, | |
1326 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) | |
1327 | { | |
1328 | const struct amd64_insn *details = &dsc->insn_details; | |
1329 | ||
1330 | if (details->modrm_offset != -1) | |
1331 | { | |
1332 | gdb_byte modrm = details->raw_insn[details->modrm_offset]; | |
1333 | ||
1334 | if ((modrm & 0xc7) == 0x05) | |
1335 | { | |
1336 | /* The insn uses rip-relative addressing. | |
1337 | Deal with it. */ | |
1338 | fixup_riprel (gdbarch, dsc, from, to, regs); | |
1339 | } | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | struct displaced_step_closure * | |
1344 | amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
1345 | CORE_ADDR from, CORE_ADDR to, | |
1346 | struct regcache *regs) | |
1347 | { | |
1348 | int len = gdbarch_max_insn_length (gdbarch); | |
741e63d7 | 1349 | /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to |
35669430 DE |
1350 | continually watch for running off the end of the buffer. */ |
1351 | int fixup_sentinel_space = len; | |
224c3ddb SM |
1352 | struct displaced_step_closure *dsc |
1353 | = ((struct displaced_step_closure *) | |
1354 | xmalloc (sizeof (*dsc) + len + fixup_sentinel_space)); | |
35669430 DE |
1355 | gdb_byte *buf = &dsc->insn_buf[0]; |
1356 | struct amd64_insn *details = &dsc->insn_details; | |
1357 | ||
1358 | dsc->tmp_used = 0; | |
1359 | dsc->max_len = len + fixup_sentinel_space; | |
1360 | ||
1361 | read_memory (from, buf, len); | |
1362 | ||
1363 | /* Set up the sentinel space so we don't have to worry about running | |
1364 | off the end of the buffer. An excessive number of leading prefixes | |
1365 | could otherwise cause this. */ | |
1366 | memset (buf + len, 0, fixup_sentinel_space); | |
1367 | ||
1368 | amd64_get_insn_details (buf, details); | |
1369 | ||
1370 | /* GDB may get control back after the insn after the syscall. | |
1371 | Presumably this is a kernel bug. | |
1372 | If this is a syscall, make sure there's a nop afterwards. */ | |
1373 | { | |
1374 | int syscall_length; | |
1375 | ||
1376 | if (amd64_syscall_p (details, &syscall_length)) | |
1377 | buf[details->opcode_offset + syscall_length] = NOP_OPCODE; | |
1378 | } | |
1379 | ||
1380 | /* Modify the insn to cope with the address where it will be executed from. | |
1381 | In particular, handle any rip-relative addressing. */ | |
1382 | fixup_displaced_copy (gdbarch, dsc, from, to, regs); | |
1383 | ||
1384 | write_memory (to, buf, len); | |
1385 | ||
1386 | if (debug_displaced) | |
1387 | { | |
5af949e3 UW |
1388 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", |
1389 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
35669430 DE |
1390 | displaced_step_dump_bytes (gdb_stdlog, buf, len); |
1391 | } | |
1392 | ||
1393 | return dsc; | |
1394 | } | |
1395 | ||
1396 | static int | |
1397 | amd64_absolute_jmp_p (const struct amd64_insn *details) | |
1398 | { | |
1399 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1400 | ||
1401 | if (insn[0] == 0xff) | |
1402 | { | |
1403 | /* jump near, absolute indirect (/4) */ | |
1404 | if ((insn[1] & 0x38) == 0x20) | |
1405 | return 1; | |
1406 | ||
1407 | /* jump far, absolute indirect (/5) */ | |
1408 | if ((insn[1] & 0x38) == 0x28) | |
1409 | return 1; | |
1410 | } | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
c2170eef MM |
1415 | /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */ |
1416 | ||
1417 | static int | |
1418 | amd64_jmp_p (const struct amd64_insn *details) | |
1419 | { | |
1420 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1421 | ||
1422 | /* jump short, relative. */ | |
1423 | if (insn[0] == 0xeb) | |
1424 | return 1; | |
1425 | ||
1426 | /* jump near, relative. */ | |
1427 | if (insn[0] == 0xe9) | |
1428 | return 1; | |
1429 | ||
1430 | return amd64_absolute_jmp_p (details); | |
1431 | } | |
1432 | ||
35669430 DE |
1433 | static int |
1434 | amd64_absolute_call_p (const struct amd64_insn *details) | |
1435 | { | |
1436 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1437 | ||
1438 | if (insn[0] == 0xff) | |
1439 | { | |
1440 | /* Call near, absolute indirect (/2) */ | |
1441 | if ((insn[1] & 0x38) == 0x10) | |
1442 | return 1; | |
1443 | ||
1444 | /* Call far, absolute indirect (/3) */ | |
1445 | if ((insn[1] & 0x38) == 0x18) | |
1446 | return 1; | |
1447 | } | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | static int | |
1453 | amd64_ret_p (const struct amd64_insn *details) | |
1454 | { | |
1455 | /* NOTE: gcc can emit "repz ; ret". */ | |
1456 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1457 | ||
1458 | switch (insn[0]) | |
1459 | { | |
1460 | case 0xc2: /* ret near, pop N bytes */ | |
1461 | case 0xc3: /* ret near */ | |
1462 | case 0xca: /* ret far, pop N bytes */ | |
1463 | case 0xcb: /* ret far */ | |
1464 | case 0xcf: /* iret */ | |
1465 | return 1; | |
1466 | ||
1467 | default: | |
1468 | return 0; | |
1469 | } | |
1470 | } | |
1471 | ||
1472 | static int | |
1473 | amd64_call_p (const struct amd64_insn *details) | |
1474 | { | |
1475 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1476 | ||
1477 | if (amd64_absolute_call_p (details)) | |
1478 | return 1; | |
1479 | ||
1480 | /* call near, relative */ | |
1481 | if (insn[0] == 0xe8) | |
1482 | return 1; | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
35669430 DE |
1487 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
1488 | length in bytes. Otherwise, return zero. */ | |
1489 | ||
1490 | static int | |
1491 | amd64_syscall_p (const struct amd64_insn *details, int *lengthp) | |
1492 | { | |
1493 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; | |
1494 | ||
1495 | if (insn[0] == 0x0f && insn[1] == 0x05) | |
1496 | { | |
1497 | *lengthp = 2; | |
1498 | return 1; | |
1499 | } | |
1500 | ||
1501 | return 0; | |
1502 | } | |
1503 | ||
c2170eef MM |
1504 | /* Classify the instruction at ADDR using PRED. |
1505 | Throw an error if the memory can't be read. */ | |
1506 | ||
1507 | static int | |
1508 | amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1509 | int (*pred) (const struct amd64_insn *)) | |
1510 | { | |
1511 | struct amd64_insn details; | |
1512 | gdb_byte *buf; | |
1513 | int len, classification; | |
1514 | ||
1515 | len = gdbarch_max_insn_length (gdbarch); | |
224c3ddb | 1516 | buf = (gdb_byte *) alloca (len); |
c2170eef MM |
1517 | |
1518 | read_code (addr, buf, len); | |
1519 | amd64_get_insn_details (buf, &details); | |
1520 | ||
1521 | classification = pred (&details); | |
1522 | ||
1523 | return classification; | |
1524 | } | |
1525 | ||
1526 | /* The gdbarch insn_is_call method. */ | |
1527 | ||
1528 | static int | |
1529 | amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1530 | { | |
1531 | return amd64_classify_insn_at (gdbarch, addr, amd64_call_p); | |
1532 | } | |
1533 | ||
1534 | /* The gdbarch insn_is_ret method. */ | |
1535 | ||
1536 | static int | |
1537 | amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1538 | { | |
1539 | return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p); | |
1540 | } | |
1541 | ||
1542 | /* The gdbarch insn_is_jump method. */ | |
1543 | ||
1544 | static int | |
1545 | amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1546 | { | |
1547 | return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p); | |
1548 | } | |
1549 | ||
35669430 DE |
1550 | /* Fix up the state of registers and memory after having single-stepped |
1551 | a displaced instruction. */ | |
1552 | ||
1553 | void | |
1554 | amd64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1555 | struct displaced_step_closure *dsc, | |
1556 | CORE_ADDR from, CORE_ADDR to, | |
1557 | struct regcache *regs) | |
1558 | { | |
e17a4113 | 1559 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
35669430 DE |
1560 | /* The offset we applied to the instruction's address. */ |
1561 | ULONGEST insn_offset = to - from; | |
1562 | gdb_byte *insn = dsc->insn_buf; | |
1563 | const struct amd64_insn *insn_details = &dsc->insn_details; | |
1564 | ||
1565 | if (debug_displaced) | |
1566 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 1567 | "displaced: fixup (%s, %s), " |
35669430 | 1568 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
1569 | paddress (gdbarch, from), paddress (gdbarch, to), |
1570 | insn[0], insn[1]); | |
35669430 DE |
1571 | |
1572 | /* If we used a tmp reg, restore it. */ | |
1573 | ||
1574 | if (dsc->tmp_used) | |
1575 | { | |
1576 | if (debug_displaced) | |
5af949e3 UW |
1577 | fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", |
1578 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); | |
35669430 DE |
1579 | regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); |
1580 | } | |
1581 | ||
1582 | /* The list of issues to contend with here is taken from | |
1583 | resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. | |
1584 | Yay for Free Software! */ | |
1585 | ||
1586 | /* Relocate the %rip back to the program's instruction stream, | |
1587 | if necessary. */ | |
1588 | ||
1589 | /* Except in the case of absolute or indirect jump or call | |
1590 | instructions, or a return instruction, the new rip is relative to | |
1591 | the displaced instruction; make it relative to the original insn. | |
1592 | Well, signal handler returns don't need relocation either, but we use the | |
1593 | value of %rip to recognize those; see below. */ | |
1594 | if (! amd64_absolute_jmp_p (insn_details) | |
1595 | && ! amd64_absolute_call_p (insn_details) | |
1596 | && ! amd64_ret_p (insn_details)) | |
1597 | { | |
1598 | ULONGEST orig_rip; | |
1599 | int insn_len; | |
1600 | ||
1601 | regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); | |
1602 | ||
1603 | /* A signal trampoline system call changes the %rip, resuming | |
1604 | execution of the main program after the signal handler has | |
1605 | returned. That makes them like 'return' instructions; we | |
1606 | shouldn't relocate %rip. | |
1607 | ||
1608 | But most system calls don't, and we do need to relocate %rip. | |
1609 | ||
1610 | Our heuristic for distinguishing these cases: if stepping | |
1611 | over the system call instruction left control directly after | |
1612 | the instruction, the we relocate --- control almost certainly | |
1613 | doesn't belong in the displaced copy. Otherwise, we assume | |
1614 | the instruction has put control where it belongs, and leave | |
1615 | it unrelocated. Goodness help us if there are PC-relative | |
1616 | system calls. */ | |
1617 | if (amd64_syscall_p (insn_details, &insn_len) | |
1618 | && orig_rip != to + insn_len | |
1619 | /* GDB can get control back after the insn after the syscall. | |
1620 | Presumably this is a kernel bug. | |
1621 | Fixup ensures its a nop, we add one to the length for it. */ | |
1622 | && orig_rip != to + insn_len + 1) | |
1623 | { | |
1624 | if (debug_displaced) | |
1625 | fprintf_unfiltered (gdb_stdlog, | |
1626 | "displaced: syscall changed %%rip; " | |
1627 | "not relocating\n"); | |
1628 | } | |
1629 | else | |
1630 | { | |
1631 | ULONGEST rip = orig_rip - insn_offset; | |
1632 | ||
1903f0e6 DE |
1633 | /* If we just stepped over a breakpoint insn, we don't backup |
1634 | the pc on purpose; this is to match behaviour without | |
1635 | stepping. */ | |
35669430 DE |
1636 | |
1637 | regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); | |
1638 | ||
1639 | if (debug_displaced) | |
1640 | fprintf_unfiltered (gdb_stdlog, | |
1641 | "displaced: " | |
5af949e3 UW |
1642 | "relocated %%rip from %s to %s\n", |
1643 | paddress (gdbarch, orig_rip), | |
1644 | paddress (gdbarch, rip)); | |
35669430 DE |
1645 | } |
1646 | } | |
1647 | ||
1648 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
1649 | pushed value, and should be cleared. We'll leave this for later, | |
1650 | since GDB already messes up the TF flag when stepping over a | |
1651 | pushfl. */ | |
1652 | ||
1653 | /* If the instruction was a call, the return address now atop the | |
1654 | stack is the address following the copied instruction. We need | |
1655 | to make it the address following the original instruction. */ | |
1656 | if (amd64_call_p (insn_details)) | |
1657 | { | |
1658 | ULONGEST rsp; | |
1659 | ULONGEST retaddr; | |
1660 | const ULONGEST retaddr_len = 8; | |
1661 | ||
1662 | regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); | |
e17a4113 | 1663 | retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); |
4dafcdeb | 1664 | retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; |
e17a4113 | 1665 | write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); |
35669430 DE |
1666 | |
1667 | if (debug_displaced) | |
1668 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
1669 | "displaced: relocated return addr at %s " |
1670 | "to %s\n", | |
1671 | paddress (gdbarch, rsp), | |
1672 | paddress (gdbarch, retaddr)); | |
35669430 DE |
1673 | } |
1674 | } | |
dde08ee1 PA |
1675 | |
1676 | /* If the instruction INSN uses RIP-relative addressing, return the | |
1677 | offset into the raw INSN where the displacement to be adjusted is | |
1678 | found. Returns 0 if the instruction doesn't use RIP-relative | |
1679 | addressing. */ | |
1680 | ||
1681 | static int | |
1682 | rip_relative_offset (struct amd64_insn *insn) | |
1683 | { | |
1684 | if (insn->modrm_offset != -1) | |
1685 | { | |
1686 | gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; | |
1687 | ||
1688 | if ((modrm & 0xc7) == 0x05) | |
1689 | { | |
1690 | /* The displacement is found right after the ModRM byte. */ | |
1691 | return insn->modrm_offset + 1; | |
1692 | } | |
1693 | } | |
1694 | ||
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static void | |
1699 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
1700 | { | |
1701 | target_write_memory (*to, buf, len); | |
1702 | *to += len; | |
1703 | } | |
1704 | ||
60965737 | 1705 | static void |
dde08ee1 PA |
1706 | amd64_relocate_instruction (struct gdbarch *gdbarch, |
1707 | CORE_ADDR *to, CORE_ADDR oldloc) | |
1708 | { | |
1709 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1710 | int len = gdbarch_max_insn_length (gdbarch); | |
1711 | /* Extra space for sentinels. */ | |
1712 | int fixup_sentinel_space = len; | |
224c3ddb | 1713 | gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space); |
dde08ee1 PA |
1714 | struct amd64_insn insn_details; |
1715 | int offset = 0; | |
1716 | LONGEST rel32, newrel; | |
1717 | gdb_byte *insn; | |
1718 | int insn_length; | |
1719 | ||
1720 | read_memory (oldloc, buf, len); | |
1721 | ||
1722 | /* Set up the sentinel space so we don't have to worry about running | |
1723 | off the end of the buffer. An excessive number of leading prefixes | |
1724 | could otherwise cause this. */ | |
1725 | memset (buf + len, 0, fixup_sentinel_space); | |
1726 | ||
1727 | insn = buf; | |
1728 | amd64_get_insn_details (insn, &insn_details); | |
1729 | ||
1730 | insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); | |
1731 | ||
1732 | /* Skip legacy instruction prefixes. */ | |
1733 | insn = amd64_skip_prefixes (insn); | |
1734 | ||
1735 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
1736 | the address pushed being the location where the original call in | |
1737 | the user program would return to. */ | |
1738 | if (insn[0] == 0xe8) | |
1739 | { | |
1740 | gdb_byte push_buf[16]; | |
1741 | unsigned int ret_addr; | |
1742 | ||
1743 | /* Where "ret" in the original code will return to. */ | |
1744 | ret_addr = oldloc + insn_length; | |
0963b4bd | 1745 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 1746 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
1747 | /* Push the push. */ |
1748 | append_insns (to, 5, push_buf); | |
1749 | ||
1750 | /* Convert the relative call to a relative jump. */ | |
1751 | insn[0] = 0xe9; | |
1752 | ||
1753 | /* Adjust the destination offset. */ | |
1754 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1755 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1756 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1757 | ||
1758 | if (debug_displaced) | |
1759 | fprintf_unfiltered (gdb_stdlog, | |
1760 | "Adjusted insn rel32=%s at %s to" | |
1761 | " rel32=%s at %s\n", | |
1762 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1763 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1764 | |
1765 | /* Write the adjusted jump into its displaced location. */ | |
1766 | append_insns (to, 5, insn); | |
1767 | return; | |
1768 | } | |
1769 | ||
1770 | offset = rip_relative_offset (&insn_details); | |
1771 | if (!offset) | |
1772 | { | |
1773 | /* Adjust jumps with 32-bit relative addresses. Calls are | |
1774 | already handled above. */ | |
1775 | if (insn[0] == 0xe9) | |
1776 | offset = 1; | |
1777 | /* Adjust conditional jumps. */ | |
1778 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1779 | offset = 2; | |
1780 | } | |
1781 | ||
1782 | if (offset) | |
1783 | { | |
1784 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1785 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1786 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1787 | if (debug_displaced) |
1788 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1789 | "Adjusted insn rel32=%s at %s to" |
1790 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1791 | hex_string (rel32), paddress (gdbarch, oldloc), |
1792 | hex_string (newrel), paddress (gdbarch, *to)); | |
1793 | } | |
1794 | ||
1795 | /* Write the adjusted instruction into its displaced location. */ | |
1796 | append_insns (to, insn_length, buf); | |
1797 | } | |
1798 | ||
35669430 | 1799 | \f |
c4f35dd8 | 1800 | /* The maximum number of saved registers. This should include %rip. */ |
90f90721 | 1801 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 1802 | |
e53bef9f | 1803 | struct amd64_frame_cache |
c4f35dd8 MK |
1804 | { |
1805 | /* Base address. */ | |
1806 | CORE_ADDR base; | |
8fbca658 | 1807 | int base_p; |
c4f35dd8 MK |
1808 | CORE_ADDR sp_offset; |
1809 | CORE_ADDR pc; | |
1810 | ||
1811 | /* Saved registers. */ | |
e53bef9f | 1812 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 | 1813 | CORE_ADDR saved_sp; |
e0c62198 | 1814 | int saved_sp_reg; |
c4f35dd8 MK |
1815 | |
1816 | /* Do we have a frame? */ | |
1817 | int frameless_p; | |
1818 | }; | |
8dda9770 | 1819 | |
d2449ee8 | 1820 | /* Initialize a frame cache. */ |
c4f35dd8 | 1821 | |
d2449ee8 DJ |
1822 | static void |
1823 | amd64_init_frame_cache (struct amd64_frame_cache *cache) | |
8dda9770 | 1824 | { |
c4f35dd8 MK |
1825 | int i; |
1826 | ||
c4f35dd8 MK |
1827 | /* Base address. */ |
1828 | cache->base = 0; | |
8fbca658 | 1829 | cache->base_p = 0; |
c4f35dd8 MK |
1830 | cache->sp_offset = -8; |
1831 | cache->pc = 0; | |
1832 | ||
1833 | /* Saved registers. We initialize these to -1 since zero is a valid | |
bba66b87 DE |
1834 | offset (that's where %rbp is supposed to be stored). |
1835 | The values start out as being offsets, and are later converted to | |
1836 | addresses (at which point -1 is interpreted as an address, still meaning | |
1837 | "invalid"). */ | |
e53bef9f | 1838 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
1839 | cache->saved_regs[i] = -1; |
1840 | cache->saved_sp = 0; | |
e0c62198 | 1841 | cache->saved_sp_reg = -1; |
c4f35dd8 MK |
1842 | |
1843 | /* Frameless until proven otherwise. */ | |
1844 | cache->frameless_p = 1; | |
d2449ee8 | 1845 | } |
c4f35dd8 | 1846 | |
d2449ee8 DJ |
1847 | /* Allocate and initialize a frame cache. */ |
1848 | ||
1849 | static struct amd64_frame_cache * | |
1850 | amd64_alloc_frame_cache (void) | |
1851 | { | |
1852 | struct amd64_frame_cache *cache; | |
1853 | ||
1854 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); | |
1855 | amd64_init_frame_cache (cache); | |
c4f35dd8 | 1856 | return cache; |
8dda9770 | 1857 | } |
53e95fcf | 1858 | |
e0c62198 L |
1859 | /* GCC 4.4 and later, can put code in the prologue to realign the |
1860 | stack pointer. Check whether PC points to such code, and update | |
1861 | CACHE accordingly. Return the first instruction after the code | |
1862 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1863 | recognize the code, return PC. */ | |
1864 | ||
1865 | static CORE_ADDR | |
1866 | amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1867 | struct amd64_frame_cache *cache) | |
1868 | { | |
1869 | /* There are 2 code sequences to re-align stack before the frame | |
1870 | gets set up: | |
1871 | ||
1872 | 1. Use a caller-saved saved register: | |
1873 | ||
1874 | leaq 8(%rsp), %reg | |
1875 | andq $-XXX, %rsp | |
1876 | pushq -8(%reg) | |
1877 | ||
1878 | 2. Use a callee-saved saved register: | |
1879 | ||
1880 | pushq %reg | |
1881 | leaq 16(%rsp), %reg | |
1882 | andq $-XXX, %rsp | |
1883 | pushq -8(%reg) | |
1884 | ||
1885 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
1886 | ||
1887 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp | |
1888 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
1889 | */ | |
1890 | ||
1891 | gdb_byte buf[18]; | |
1892 | int reg, r; | |
1893 | int offset, offset_and; | |
e0c62198 | 1894 | |
bae8a07a | 1895 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1896 | return pc; |
1897 | ||
1898 | /* Check caller-saved saved register. The first instruction has | |
1899 | to be "leaq 8(%rsp), %reg". */ | |
1900 | if ((buf[0] & 0xfb) == 0x48 | |
1901 | && buf[1] == 0x8d | |
1902 | && buf[3] == 0x24 | |
1903 | && buf[4] == 0x8) | |
1904 | { | |
1905 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1906 | if ((buf[2] & 0xc7) != 0x44) | |
1907 | return pc; | |
1908 | ||
1909 | /* REG has register number. */ | |
1910 | reg = (buf[2] >> 3) & 7; | |
1911 | ||
1912 | /* Check the REX.R bit. */ | |
1913 | if (buf[0] == 0x4c) | |
1914 | reg += 8; | |
1915 | ||
1916 | offset = 5; | |
1917 | } | |
1918 | else | |
1919 | { | |
1920 | /* Check callee-saved saved register. The first instruction | |
1921 | has to be "pushq %reg". */ | |
1922 | reg = 0; | |
1923 | if ((buf[0] & 0xf8) == 0x50) | |
1924 | offset = 0; | |
1925 | else if ((buf[0] & 0xf6) == 0x40 | |
1926 | && (buf[1] & 0xf8) == 0x50) | |
1927 | { | |
1928 | /* Check the REX.B bit. */ | |
1929 | if ((buf[0] & 1) != 0) | |
1930 | reg = 8; | |
1931 | ||
1932 | offset = 1; | |
1933 | } | |
1934 | else | |
1935 | return pc; | |
1936 | ||
1937 | /* Get register. */ | |
1938 | reg += buf[offset] & 0x7; | |
1939 | ||
1940 | offset++; | |
1941 | ||
1942 | /* The next instruction has to be "leaq 16(%rsp), %reg". */ | |
1943 | if ((buf[offset] & 0xfb) != 0x48 | |
1944 | || buf[offset + 1] != 0x8d | |
1945 | || buf[offset + 3] != 0x24 | |
1946 | || buf[offset + 4] != 0x10) | |
1947 | return pc; | |
1948 | ||
1949 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1950 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
1951 | return pc; | |
1952 | ||
1953 | /* REG has register number. */ | |
1954 | r = (buf[offset + 2] >> 3) & 7; | |
1955 | ||
1956 | /* Check the REX.R bit. */ | |
1957 | if (buf[offset] == 0x4c) | |
1958 | r += 8; | |
1959 | ||
1960 | /* Registers in pushq and leaq have to be the same. */ | |
1961 | if (reg != r) | |
1962 | return pc; | |
1963 | ||
1964 | offset += 5; | |
1965 | } | |
1966 | ||
1967 | /* Rigister can't be %rsp nor %rbp. */ | |
1968 | if (reg == 4 || reg == 5) | |
1969 | return pc; | |
1970 | ||
1971 | /* The next instruction has to be "andq $-XXX, %rsp". */ | |
1972 | if (buf[offset] != 0x48 | |
1973 | || buf[offset + 2] != 0xe4 | |
1974 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
1975 | return pc; | |
1976 | ||
1977 | offset_and = offset; | |
1978 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
1979 | ||
1980 | /* The next instruction has to be "pushq -8(%reg)". */ | |
1981 | r = 0; | |
1982 | if (buf[offset] == 0xff) | |
1983 | offset++; | |
1984 | else if ((buf[offset] & 0xf6) == 0x40 | |
1985 | && buf[offset + 1] == 0xff) | |
1986 | { | |
1987 | /* Check the REX.B bit. */ | |
1988 | if ((buf[offset] & 0x1) != 0) | |
1989 | r = 8; | |
1990 | offset += 2; | |
1991 | } | |
1992 | else | |
1993 | return pc; | |
1994 | ||
1995 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
1996 | 01. */ | |
1997 | if (buf[offset + 1] != 0xf8 | |
1998 | || (buf[offset] & 0xf8) != 0x70) | |
1999 | return pc; | |
2000 | ||
2001 | /* R/M has register. */ | |
2002 | r += buf[offset] & 7; | |
2003 | ||
2004 | /* Registers in leaq and pushq have to be the same. */ | |
2005 | if (reg != r) | |
2006 | return pc; | |
2007 | ||
2008 | if (current_pc > pc + offset_and) | |
35669430 | 2009 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); |
e0c62198 L |
2010 | |
2011 | return min (pc + offset + 2, current_pc); | |
2012 | } | |
2013 | ||
ac142d96 L |
2014 | /* Similar to amd64_analyze_stack_align for x32. */ |
2015 | ||
2016 | static CORE_ADDR | |
2017 | amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
2018 | struct amd64_frame_cache *cache) | |
2019 | { | |
2020 | /* There are 2 code sequences to re-align stack before the frame | |
2021 | gets set up: | |
2022 | ||
2023 | 1. Use a caller-saved saved register: | |
2024 | ||
2025 | leaq 8(%rsp), %reg | |
2026 | andq $-XXX, %rsp | |
2027 | pushq -8(%reg) | |
2028 | ||
2029 | or | |
2030 | ||
2031 | [addr32] leal 8(%rsp), %reg | |
2032 | andl $-XXX, %esp | |
2033 | [addr32] pushq -8(%reg) | |
2034 | ||
2035 | 2. Use a callee-saved saved register: | |
2036 | ||
2037 | pushq %reg | |
2038 | leaq 16(%rsp), %reg | |
2039 | andq $-XXX, %rsp | |
2040 | pushq -8(%reg) | |
2041 | ||
2042 | or | |
2043 | ||
2044 | pushq %reg | |
2045 | [addr32] leal 16(%rsp), %reg | |
2046 | andl $-XXX, %esp | |
2047 | [addr32] pushq -8(%reg) | |
2048 | ||
2049 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: | |
2050 | ||
2051 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp | |
2052 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp | |
2053 | ||
2054 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
2055 | ||
2056 | 0x83 0xe4 0xf0 andl $-16, %esp | |
2057 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
2058 | */ | |
2059 | ||
2060 | gdb_byte buf[19]; | |
2061 | int reg, r; | |
2062 | int offset, offset_and; | |
2063 | ||
2064 | if (target_read_memory (pc, buf, sizeof buf)) | |
2065 | return pc; | |
2066 | ||
2067 | /* Skip optional addr32 prefix. */ | |
2068 | offset = buf[0] == 0x67 ? 1 : 0; | |
2069 | ||
2070 | /* Check caller-saved saved register. The first instruction has | |
2071 | to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ | |
2072 | if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) | |
2073 | && buf[offset + 1] == 0x8d | |
2074 | && buf[offset + 3] == 0x24 | |
2075 | && buf[offset + 4] == 0x8) | |
2076 | { | |
2077 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2078 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
2079 | return pc; | |
2080 | ||
2081 | /* REG has register number. */ | |
2082 | reg = (buf[offset + 2] >> 3) & 7; | |
2083 | ||
2084 | /* Check the REX.R bit. */ | |
2085 | if ((buf[offset] & 0x4) != 0) | |
2086 | reg += 8; | |
2087 | ||
2088 | offset += 5; | |
2089 | } | |
2090 | else | |
2091 | { | |
2092 | /* Check callee-saved saved register. The first instruction | |
2093 | has to be "pushq %reg". */ | |
2094 | reg = 0; | |
2095 | if ((buf[offset] & 0xf6) == 0x40 | |
2096 | && (buf[offset + 1] & 0xf8) == 0x50) | |
2097 | { | |
2098 | /* Check the REX.B bit. */ | |
2099 | if ((buf[offset] & 1) != 0) | |
2100 | reg = 8; | |
2101 | ||
2102 | offset += 1; | |
2103 | } | |
2104 | else if ((buf[offset] & 0xf8) != 0x50) | |
2105 | return pc; | |
2106 | ||
2107 | /* Get register. */ | |
2108 | reg += buf[offset] & 0x7; | |
2109 | ||
2110 | offset++; | |
2111 | ||
2112 | /* Skip optional addr32 prefix. */ | |
2113 | if (buf[offset] == 0x67) | |
2114 | offset++; | |
2115 | ||
2116 | /* The next instruction has to be "leaq 16(%rsp), %reg" or | |
2117 | "leal 16(%rsp), %reg". */ | |
2118 | if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) | |
2119 | || buf[offset + 1] != 0x8d | |
2120 | || buf[offset + 3] != 0x24 | |
2121 | || buf[offset + 4] != 0x10) | |
2122 | return pc; | |
2123 | ||
2124 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
2125 | if ((buf[offset + 2] & 0xc7) != 0x44) | |
2126 | return pc; | |
2127 | ||
2128 | /* REG has register number. */ | |
2129 | r = (buf[offset + 2] >> 3) & 7; | |
2130 | ||
2131 | /* Check the REX.R bit. */ | |
2132 | if ((buf[offset] & 0x4) != 0) | |
2133 | r += 8; | |
2134 | ||
2135 | /* Registers in pushq and leaq have to be the same. */ | |
2136 | if (reg != r) | |
2137 | return pc; | |
2138 | ||
2139 | offset += 5; | |
2140 | } | |
2141 | ||
2142 | /* Rigister can't be %rsp nor %rbp. */ | |
2143 | if (reg == 4 || reg == 5) | |
2144 | return pc; | |
2145 | ||
2146 | /* The next instruction may be "andq $-XXX, %rsp" or | |
2147 | "andl $-XXX, %esp". */ | |
2148 | if (buf[offset] != 0x48) | |
2149 | offset--; | |
2150 | ||
2151 | if (buf[offset + 2] != 0xe4 | |
2152 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) | |
2153 | return pc; | |
2154 | ||
2155 | offset_and = offset; | |
2156 | offset += buf[offset + 1] == 0x81 ? 7 : 4; | |
2157 | ||
2158 | /* Skip optional addr32 prefix. */ | |
2159 | if (buf[offset] == 0x67) | |
2160 | offset++; | |
2161 | ||
2162 | /* The next instruction has to be "pushq -8(%reg)". */ | |
2163 | r = 0; | |
2164 | if (buf[offset] == 0xff) | |
2165 | offset++; | |
2166 | else if ((buf[offset] & 0xf6) == 0x40 | |
2167 | && buf[offset + 1] == 0xff) | |
2168 | { | |
2169 | /* Check the REX.B bit. */ | |
2170 | if ((buf[offset] & 0x1) != 0) | |
2171 | r = 8; | |
2172 | offset += 2; | |
2173 | } | |
2174 | else | |
2175 | return pc; | |
2176 | ||
2177 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary | |
2178 | 01. */ | |
2179 | if (buf[offset + 1] != 0xf8 | |
2180 | || (buf[offset] & 0xf8) != 0x70) | |
2181 | return pc; | |
2182 | ||
2183 | /* R/M has register. */ | |
2184 | r += buf[offset] & 7; | |
2185 | ||
2186 | /* Registers in leaq and pushq have to be the same. */ | |
2187 | if (reg != r) | |
2188 | return pc; | |
2189 | ||
2190 | if (current_pc > pc + offset_and) | |
2191 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); | |
2192 | ||
2193 | return min (pc + offset + 2, current_pc); | |
2194 | } | |
2195 | ||
c4f35dd8 MK |
2196 | /* Do a limited analysis of the prologue at PC and update CACHE |
2197 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
2198 | address where the analysis stopped. | |
2199 | ||
2200 | We will handle only functions beginning with: | |
2201 | ||
2202 | pushq %rbp 0x55 | |
50f1ae7b | 2203 | movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) |
c4f35dd8 | 2204 | |
649e6d92 MK |
2205 | or (for the X32 ABI): |
2206 | ||
2207 | pushq %rbp 0x55 | |
2208 | movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) | |
2209 | ||
2210 | Any function that doesn't start with one of these sequences will be | |
2211 | assumed to have no prologue and thus no valid frame pointer in | |
2212 | %rbp. */ | |
c4f35dd8 MK |
2213 | |
2214 | static CORE_ADDR | |
e17a4113 UW |
2215 | amd64_analyze_prologue (struct gdbarch *gdbarch, |
2216 | CORE_ADDR pc, CORE_ADDR current_pc, | |
e53bef9f | 2217 | struct amd64_frame_cache *cache) |
53e95fcf | 2218 | { |
e17a4113 | 2219 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
50f1ae7b DE |
2220 | /* There are two variations of movq %rsp, %rbp. */ |
2221 | static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; | |
2222 | static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; | |
649e6d92 MK |
2223 | /* Ditto for movl %esp, %ebp. */ |
2224 | static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; | |
2225 | static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; | |
2226 | ||
d8de1ef7 MK |
2227 | gdb_byte buf[3]; |
2228 | gdb_byte op; | |
c4f35dd8 MK |
2229 | |
2230 | if (current_pc <= pc) | |
2231 | return current_pc; | |
2232 | ||
ac142d96 L |
2233 | if (gdbarch_ptr_bit (gdbarch) == 32) |
2234 | pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); | |
2235 | else | |
2236 | pc = amd64_analyze_stack_align (pc, current_pc, cache); | |
e0c62198 | 2237 | |
bae8a07a | 2238 | op = read_code_unsigned_integer (pc, 1, byte_order); |
c4f35dd8 MK |
2239 | |
2240 | if (op == 0x55) /* pushq %rbp */ | |
2241 | { | |
2242 | /* Take into account that we've executed the `pushq %rbp' that | |
2243 | starts this instruction sequence. */ | |
90f90721 | 2244 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
2245 | cache->sp_offset += 8; |
2246 | ||
2247 | /* If that's all, return now. */ | |
2248 | if (current_pc <= pc + 1) | |
2249 | return current_pc; | |
2250 | ||
bae8a07a | 2251 | read_code (pc + 1, buf, 3); |
c4f35dd8 | 2252 | |
649e6d92 MK |
2253 | /* Check for `movq %rsp, %rbp'. */ |
2254 | if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 | |
2255 | || memcmp (buf, mov_rsp_rbp_2, 3) == 0) | |
2256 | { | |
2257 | /* OK, we actually have a frame. */ | |
2258 | cache->frameless_p = 0; | |
2259 | return pc + 4; | |
2260 | } | |
2261 | ||
2262 | /* For X32, also check for `movq %esp, %ebp'. */ | |
2263 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
2264 | { | |
2265 | if (memcmp (buf, mov_esp_ebp_1, 2) == 0 | |
2266 | || memcmp (buf, mov_esp_ebp_2, 2) == 0) | |
2267 | { | |
2268 | /* OK, we actually have a frame. */ | |
2269 | cache->frameless_p = 0; | |
2270 | return pc + 3; | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | return pc + 1; | |
c4f35dd8 MK |
2275 | } |
2276 | ||
2277 | return pc; | |
53e95fcf JS |
2278 | } |
2279 | ||
df15bd07 JK |
2280 | /* Work around false termination of prologue - GCC PR debug/48827. |
2281 | ||
2282 | START_PC is the first instruction of a function, PC is its minimal already | |
2283 | determined advanced address. Function returns PC if it has nothing to do. | |
2284 | ||
2285 | 84 c0 test %al,%al | |
2286 | 74 23 je after | |
2287 | <-- here is 0 lines advance - the false prologue end marker. | |
2288 | 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) | |
2289 | 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) | |
2290 | 0f 29 55 90 movaps %xmm2,-0x70(%rbp) | |
2291 | 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) | |
2292 | 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) | |
2293 | 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) | |
2294 | 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) | |
2295 | 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) | |
2296 | after: */ | |
c4f35dd8 MK |
2297 | |
2298 | static CORE_ADDR | |
df15bd07 | 2299 | amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) |
53e95fcf | 2300 | { |
08711b9a JK |
2301 | struct symtab_and_line start_pc_sal, next_sal; |
2302 | gdb_byte buf[4 + 8 * 7]; | |
2303 | int offset, xmmreg; | |
c4f35dd8 | 2304 | |
08711b9a JK |
2305 | if (pc == start_pc) |
2306 | return pc; | |
2307 | ||
2308 | start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); | |
2309 | if (start_pc_sal.symtab == NULL | |
43f3e411 DE |
2310 | || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER |
2311 | (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6 | |
08711b9a JK |
2312 | || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) |
2313 | return pc; | |
2314 | ||
2315 | next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); | |
2316 | if (next_sal.line != start_pc_sal.line) | |
2317 | return pc; | |
2318 | ||
2319 | /* START_PC can be from overlayed memory, ignored here. */ | |
bae8a07a | 2320 | if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) |
08711b9a JK |
2321 | return pc; |
2322 | ||
2323 | /* test %al,%al */ | |
2324 | if (buf[0] != 0x84 || buf[1] != 0xc0) | |
2325 | return pc; | |
2326 | /* je AFTER */ | |
2327 | if (buf[2] != 0x74) | |
2328 | return pc; | |
2329 | ||
2330 | offset = 4; | |
2331 | for (xmmreg = 0; xmmreg < 8; xmmreg++) | |
2332 | { | |
bede5f5f | 2333 | /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ |
08711b9a | 2334 | if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 |
bede5f5f | 2335 | || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) |
08711b9a JK |
2336 | return pc; |
2337 | ||
bede5f5f JK |
2338 | /* 0b01?????? */ |
2339 | if ((buf[offset + 2] & 0xc0) == 0x40) | |
08711b9a JK |
2340 | { |
2341 | /* 8-bit displacement. */ | |
2342 | offset += 4; | |
2343 | } | |
bede5f5f JK |
2344 | /* 0b10?????? */ |
2345 | else if ((buf[offset + 2] & 0xc0) == 0x80) | |
08711b9a JK |
2346 | { |
2347 | /* 32-bit displacement. */ | |
2348 | offset += 7; | |
2349 | } | |
2350 | else | |
2351 | return pc; | |
2352 | } | |
2353 | ||
2354 | /* je AFTER */ | |
2355 | if (offset - 4 != buf[3]) | |
2356 | return pc; | |
2357 | ||
2358 | return next_sal.end; | |
53e95fcf | 2359 | } |
df15bd07 JK |
2360 | |
2361 | /* Return PC of first real instruction. */ | |
2362 | ||
2363 | static CORE_ADDR | |
2364 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) | |
2365 | { | |
2366 | struct amd64_frame_cache cache; | |
2367 | CORE_ADDR pc; | |
56bf0743 KB |
2368 | CORE_ADDR func_addr; |
2369 | ||
2370 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
2371 | { | |
2372 | CORE_ADDR post_prologue_pc | |
2373 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 2374 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
2375 | |
2376 | /* Clang always emits a line note before the prologue and another | |
2377 | one after. We trust clang to emit usable line notes. */ | |
2378 | if (post_prologue_pc | |
43f3e411 DE |
2379 | && (cust != NULL |
2380 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 2381 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
56bf0743 KB |
2382 | return max (start_pc, post_prologue_pc); |
2383 | } | |
df15bd07 JK |
2384 | |
2385 | amd64_init_frame_cache (&cache); | |
2386 | pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, | |
2387 | &cache); | |
2388 | if (cache.frameless_p) | |
2389 | return start_pc; | |
2390 | ||
2391 | return amd64_skip_xmm_prologue (pc, start_pc); | |
2392 | } | |
c4f35dd8 | 2393 | \f |
53e95fcf | 2394 | |
c4f35dd8 MK |
2395 | /* Normal frames. */ |
2396 | ||
8fbca658 PA |
2397 | static void |
2398 | amd64_frame_cache_1 (struct frame_info *this_frame, | |
2399 | struct amd64_frame_cache *cache) | |
6d686a84 | 2400 | { |
e17a4113 UW |
2401 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2402 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
d8de1ef7 | 2403 | gdb_byte buf[8]; |
6d686a84 | 2404 | int i; |
6d686a84 | 2405 | |
10458914 | 2406 | cache->pc = get_frame_func (this_frame); |
c4f35dd8 | 2407 | if (cache->pc != 0) |
e17a4113 UW |
2408 | amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2409 | cache); | |
c4f35dd8 MK |
2410 | |
2411 | if (cache->frameless_p) | |
2412 | { | |
4a28816e MK |
2413 | /* We didn't find a valid frame. If we're at the start of a |
2414 | function, or somewhere half-way its prologue, the function's | |
2415 | frame probably hasn't been fully setup yet. Try to | |
2416 | reconstruct the base address for the stack frame by looking | |
2417 | at the stack pointer. For truly "frameless" functions this | |
2418 | might work too. */ | |
c4f35dd8 | 2419 | |
e0c62198 L |
2420 | if (cache->saved_sp_reg != -1) |
2421 | { | |
8fbca658 PA |
2422 | /* Stack pointer has been saved. */ |
2423 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2424 | cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); | |
2425 | ||
e0c62198 L |
2426 | /* We're halfway aligning the stack. */ |
2427 | cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; | |
2428 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; | |
2429 | ||
2430 | /* This will be added back below. */ | |
2431 | cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; | |
2432 | } | |
2433 | else | |
2434 | { | |
2435 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
e17a4113 UW |
2436 | cache->base = extract_unsigned_integer (buf, 8, byte_order) |
2437 | + cache->sp_offset; | |
e0c62198 | 2438 | } |
c4f35dd8 | 2439 | } |
35883a3f MK |
2440 | else |
2441 | { | |
10458914 | 2442 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
e17a4113 | 2443 | cache->base = extract_unsigned_integer (buf, 8, byte_order); |
35883a3f | 2444 | } |
c4f35dd8 MK |
2445 | |
2446 | /* Now that we have the base address for the stack frame we can | |
2447 | calculate the value of %rsp in the calling frame. */ | |
2448 | cache->saved_sp = cache->base + 16; | |
2449 | ||
35883a3f MK |
2450 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
2451 | frame we find it at the same offset from the reconstructed base | |
e0c62198 L |
2452 | address. If we're halfway aligning the stack, %rip is handled |
2453 | differently (see above). */ | |
2454 | if (!cache->frameless_p || cache->saved_sp_reg == -1) | |
2455 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; | |
35883a3f | 2456 | |
c4f35dd8 MK |
2457 | /* Adjust all the saved registers such that they contain addresses |
2458 | instead of offsets. */ | |
e53bef9f | 2459 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
2460 | if (cache->saved_regs[i] != -1) |
2461 | cache->saved_regs[i] += cache->base; | |
2462 | ||
8fbca658 PA |
2463 | cache->base_p = 1; |
2464 | } | |
2465 | ||
2466 | static struct amd64_frame_cache * | |
2467 | amd64_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2468 | { | |
8fbca658 PA |
2469 | struct amd64_frame_cache *cache; |
2470 | ||
2471 | if (*this_cache) | |
9a3c8263 | 2472 | return (struct amd64_frame_cache *) *this_cache; |
8fbca658 PA |
2473 | |
2474 | cache = amd64_alloc_frame_cache (); | |
2475 | *this_cache = cache; | |
2476 | ||
492d29ea | 2477 | TRY |
8fbca658 PA |
2478 | { |
2479 | amd64_frame_cache_1 (this_frame, cache); | |
2480 | } | |
492d29ea | 2481 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2482 | { |
2483 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2484 | throw_exception (ex); | |
2485 | } | |
492d29ea | 2486 | END_CATCH |
8fbca658 | 2487 | |
c4f35dd8 | 2488 | return cache; |
6d686a84 ML |
2489 | } |
2490 | ||
8fbca658 PA |
2491 | static enum unwind_stop_reason |
2492 | amd64_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2493 | void **this_cache) | |
2494 | { | |
2495 | struct amd64_frame_cache *cache = | |
2496 | amd64_frame_cache (this_frame, this_cache); | |
2497 | ||
2498 | if (!cache->base_p) | |
2499 | return UNWIND_UNAVAILABLE; | |
2500 | ||
2501 | /* This marks the outermost frame. */ | |
2502 | if (cache->base == 0) | |
2503 | return UNWIND_OUTERMOST; | |
2504 | ||
2505 | return UNWIND_NO_REASON; | |
2506 | } | |
2507 | ||
c4f35dd8 | 2508 | static void |
10458914 | 2509 | amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
e53bef9f | 2510 | struct frame_id *this_id) |
c4f35dd8 | 2511 | { |
e53bef9f | 2512 | struct amd64_frame_cache *cache = |
10458914 | 2513 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2514 | |
8fbca658 | 2515 | if (!cache->base_p) |
5ce0145d PA |
2516 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2517 | else if (cache->base == 0) | |
2518 | { | |
2519 | /* This marks the outermost frame. */ | |
2520 | return; | |
2521 | } | |
2522 | else | |
2523 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
c4f35dd8 | 2524 | } |
e76e1718 | 2525 | |
10458914 DJ |
2526 | static struct value * |
2527 | amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2528 | int regnum) | |
53e95fcf | 2529 | { |
10458914 | 2530 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e53bef9f | 2531 | struct amd64_frame_cache *cache = |
10458914 | 2532 | amd64_frame_cache (this_frame, this_cache); |
e76e1718 | 2533 | |
c4f35dd8 | 2534 | gdb_assert (regnum >= 0); |
b1ab997b | 2535 | |
2ae02b47 | 2536 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
10458914 | 2537 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
e76e1718 | 2538 | |
e53bef9f | 2539 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2540 | return frame_unwind_got_memory (this_frame, regnum, |
2541 | cache->saved_regs[regnum]); | |
e76e1718 | 2542 | |
10458914 | 2543 | return frame_unwind_got_register (this_frame, regnum, regnum); |
c4f35dd8 | 2544 | } |
e76e1718 | 2545 | |
e53bef9f | 2546 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
2547 | { |
2548 | NORMAL_FRAME, | |
8fbca658 | 2549 | amd64_frame_unwind_stop_reason, |
e53bef9f | 2550 | amd64_frame_this_id, |
10458914 DJ |
2551 | amd64_frame_prev_register, |
2552 | NULL, | |
2553 | default_frame_sniffer | |
c4f35dd8 | 2554 | }; |
c4f35dd8 | 2555 | \f |
6710bf39 SS |
2556 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2557 | ||
2558 | static void | |
2559 | amd64_gen_return_address (struct gdbarch *gdbarch, | |
2560 | struct agent_expr *ax, struct axs_value *value, | |
2561 | CORE_ADDR scope) | |
2562 | { | |
2563 | /* The following sequence assumes the traditional use of the base | |
2564 | register. */ | |
2565 | ax_reg (ax, AMD64_RBP_REGNUM); | |
2566 | ax_const_l (ax, 8); | |
2567 | ax_simple (ax, aop_add); | |
2568 | value->type = register_type (gdbarch, AMD64_RIP_REGNUM); | |
2569 | value->kind = axs_lvalue_memory; | |
2570 | } | |
2571 | \f | |
e76e1718 | 2572 | |
c4f35dd8 MK |
2573 | /* Signal trampolines. */ |
2574 | ||
2575 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
2576 | 64-bit variants. This would require using identical frame caches | |
2577 | on both platforms. */ | |
2578 | ||
e53bef9f | 2579 | static struct amd64_frame_cache * |
10458914 | 2580 | amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 2581 | { |
e17a4113 UW |
2582 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2583 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2584 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
e53bef9f | 2585 | struct amd64_frame_cache *cache; |
c4f35dd8 | 2586 | CORE_ADDR addr; |
d8de1ef7 | 2587 | gdb_byte buf[8]; |
2b5e0749 | 2588 | int i; |
c4f35dd8 MK |
2589 | |
2590 | if (*this_cache) | |
9a3c8263 | 2591 | return (struct amd64_frame_cache *) *this_cache; |
c4f35dd8 | 2592 | |
e53bef9f | 2593 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 2594 | |
492d29ea | 2595 | TRY |
8fbca658 PA |
2596 | { |
2597 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
2598 | cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; | |
2599 | ||
2600 | addr = tdep->sigcontext_addr (this_frame); | |
2601 | gdb_assert (tdep->sc_reg_offset); | |
2602 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); | |
2603 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2604 | if (tdep->sc_reg_offset[i] != -1) | |
2605 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 | 2606 | |
8fbca658 PA |
2607 | cache->base_p = 1; |
2608 | } | |
492d29ea | 2609 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2610 | { |
2611 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2612 | throw_exception (ex); | |
2613 | } | |
492d29ea | 2614 | END_CATCH |
c4f35dd8 MK |
2615 | |
2616 | *this_cache = cache; | |
2617 | return cache; | |
53e95fcf JS |
2618 | } |
2619 | ||
8fbca658 PA |
2620 | static enum unwind_stop_reason |
2621 | amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2622 | void **this_cache) | |
2623 | { | |
2624 | struct amd64_frame_cache *cache = | |
2625 | amd64_sigtramp_frame_cache (this_frame, this_cache); | |
2626 | ||
2627 | if (!cache->base_p) | |
2628 | return UNWIND_UNAVAILABLE; | |
2629 | ||
2630 | return UNWIND_NO_REASON; | |
2631 | } | |
2632 | ||
c4f35dd8 | 2633 | static void |
10458914 | 2634 | amd64_sigtramp_frame_this_id (struct frame_info *this_frame, |
e53bef9f | 2635 | void **this_cache, struct frame_id *this_id) |
c4f35dd8 | 2636 | { |
e53bef9f | 2637 | struct amd64_frame_cache *cache = |
10458914 | 2638 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2639 | |
8fbca658 | 2640 | if (!cache->base_p) |
5ce0145d PA |
2641 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2642 | else if (cache->base == 0) | |
2643 | { | |
2644 | /* This marks the outermost frame. */ | |
2645 | return; | |
2646 | } | |
2647 | else | |
2648 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); | |
c4f35dd8 MK |
2649 | } |
2650 | ||
10458914 DJ |
2651 | static struct value * |
2652 | amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2653 | void **this_cache, int regnum) | |
c4f35dd8 MK |
2654 | { |
2655 | /* Make sure we've initialized the cache. */ | |
10458914 | 2656 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
c4f35dd8 | 2657 | |
10458914 | 2658 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
c4f35dd8 MK |
2659 | } |
2660 | ||
10458914 DJ |
2661 | static int |
2662 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2663 | struct frame_info *this_frame, | |
2664 | void **this_cache) | |
c4f35dd8 | 2665 | { |
10458914 | 2666 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
911bc6ee MK |
2667 | |
2668 | /* We shouldn't even bother if we don't have a sigcontext_addr | |
2669 | handler. */ | |
2670 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2671 | return 0; |
911bc6ee MK |
2672 | |
2673 | if (tdep->sigtramp_p != NULL) | |
2674 | { | |
10458914 DJ |
2675 | if (tdep->sigtramp_p (this_frame)) |
2676 | return 1; | |
911bc6ee | 2677 | } |
c4f35dd8 | 2678 | |
911bc6ee | 2679 | if (tdep->sigtramp_start != 0) |
1c3545ae | 2680 | { |
10458914 | 2681 | CORE_ADDR pc = get_frame_pc (this_frame); |
1c3545ae | 2682 | |
911bc6ee MK |
2683 | gdb_assert (tdep->sigtramp_end != 0); |
2684 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2685 | return 1; |
1c3545ae | 2686 | } |
c4f35dd8 | 2687 | |
10458914 | 2688 | return 0; |
c4f35dd8 | 2689 | } |
10458914 DJ |
2690 | |
2691 | static const struct frame_unwind amd64_sigtramp_frame_unwind = | |
2692 | { | |
2693 | SIGTRAMP_FRAME, | |
8fbca658 | 2694 | amd64_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2695 | amd64_sigtramp_frame_this_id, |
2696 | amd64_sigtramp_frame_prev_register, | |
2697 | NULL, | |
2698 | amd64_sigtramp_frame_sniffer | |
2699 | }; | |
c4f35dd8 MK |
2700 | \f |
2701 | ||
2702 | static CORE_ADDR | |
10458914 | 2703 | amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c4f35dd8 | 2704 | { |
e53bef9f | 2705 | struct amd64_frame_cache *cache = |
10458914 | 2706 | amd64_frame_cache (this_frame, this_cache); |
c4f35dd8 MK |
2707 | |
2708 | return cache->base; | |
2709 | } | |
2710 | ||
e53bef9f | 2711 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 2712 | { |
e53bef9f MK |
2713 | &amd64_frame_unwind, |
2714 | amd64_frame_base_address, | |
2715 | amd64_frame_base_address, | |
2716 | amd64_frame_base_address | |
c4f35dd8 MK |
2717 | }; |
2718 | ||
872761f4 MS |
2719 | /* Normal frames, but in a function epilogue. */ |
2720 | ||
c9cf6e20 MG |
2721 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2722 | ||
2723 | The epilogue is defined here as the 'ret' instruction, which will | |
872761f4 MS |
2724 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2725 | the function's stack frame. */ | |
2726 | ||
2727 | static int | |
c9cf6e20 | 2728 | amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
872761f4 MS |
2729 | { |
2730 | gdb_byte insn; | |
43f3e411 | 2731 | struct compunit_symtab *cust; |
e0d00bc7 | 2732 | |
43f3e411 DE |
2733 | cust = find_pc_compunit_symtab (pc); |
2734 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2735 | return 0; |
872761f4 MS |
2736 | |
2737 | if (target_read_memory (pc, &insn, 1)) | |
2738 | return 0; /* Can't read memory at pc. */ | |
2739 | ||
2740 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2741 | return 0; | |
2742 | ||
2743 | return 1; | |
2744 | } | |
2745 | ||
2746 | static int | |
2747 | amd64_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2748 | struct frame_info *this_frame, | |
2749 | void **this_prologue_cache) | |
2750 | { | |
2751 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2752 | return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2753 | get_frame_pc (this_frame)); | |
872761f4 MS |
2754 | else |
2755 | return 0; | |
2756 | } | |
2757 | ||
2758 | static struct amd64_frame_cache * | |
2759 | amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2760 | { | |
2761 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2762 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2763 | struct amd64_frame_cache *cache; | |
6c10c06b | 2764 | gdb_byte buf[8]; |
872761f4 MS |
2765 | |
2766 | if (*this_cache) | |
9a3c8263 | 2767 | return (struct amd64_frame_cache *) *this_cache; |
872761f4 MS |
2768 | |
2769 | cache = amd64_alloc_frame_cache (); | |
2770 | *this_cache = cache; | |
2771 | ||
492d29ea | 2772 | TRY |
8fbca658 PA |
2773 | { |
2774 | /* Cache base will be %esp plus cache->sp_offset (-8). */ | |
2775 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); | |
2776 | cache->base = extract_unsigned_integer (buf, 8, | |
2777 | byte_order) + cache->sp_offset; | |
2778 | ||
2779 | /* Cache pc will be the frame func. */ | |
2780 | cache->pc = get_frame_pc (this_frame); | |
872761f4 | 2781 | |
8fbca658 PA |
2782 | /* The saved %esp will be at cache->base plus 16. */ |
2783 | cache->saved_sp = cache->base + 16; | |
872761f4 | 2784 | |
8fbca658 PA |
2785 | /* The saved %eip will be at cache->base plus 8. */ |
2786 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; | |
872761f4 | 2787 | |
8fbca658 PA |
2788 | cache->base_p = 1; |
2789 | } | |
492d29ea | 2790 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2791 | { |
2792 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2793 | throw_exception (ex); | |
2794 | } | |
492d29ea | 2795 | END_CATCH |
872761f4 MS |
2796 | |
2797 | return cache; | |
2798 | } | |
2799 | ||
8fbca658 PA |
2800 | static enum unwind_stop_reason |
2801 | amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2802 | void **this_cache) | |
2803 | { | |
2804 | struct amd64_frame_cache *cache | |
2805 | = amd64_epilogue_frame_cache (this_frame, this_cache); | |
2806 | ||
2807 | if (!cache->base_p) | |
2808 | return UNWIND_UNAVAILABLE; | |
2809 | ||
2810 | return UNWIND_NO_REASON; | |
2811 | } | |
2812 | ||
872761f4 MS |
2813 | static void |
2814 | amd64_epilogue_frame_this_id (struct frame_info *this_frame, | |
2815 | void **this_cache, | |
2816 | struct frame_id *this_id) | |
2817 | { | |
2818 | struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, | |
2819 | this_cache); | |
2820 | ||
8fbca658 | 2821 | if (!cache->base_p) |
5ce0145d PA |
2822 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2823 | else | |
2824 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
872761f4 MS |
2825 | } |
2826 | ||
2827 | static const struct frame_unwind amd64_epilogue_frame_unwind = | |
2828 | { | |
2829 | NORMAL_FRAME, | |
8fbca658 | 2830 | amd64_epilogue_frame_unwind_stop_reason, |
872761f4 MS |
2831 | amd64_epilogue_frame_this_id, |
2832 | amd64_frame_prev_register, | |
2833 | NULL, | |
2834 | amd64_epilogue_frame_sniffer | |
2835 | }; | |
2836 | ||
166f4c7b | 2837 | static struct frame_id |
10458914 | 2838 | amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
166f4c7b | 2839 | { |
c4f35dd8 MK |
2840 | CORE_ADDR fp; |
2841 | ||
10458914 | 2842 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
c4f35dd8 | 2843 | |
10458914 | 2844 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
166f4c7b ML |
2845 | } |
2846 | ||
8b148df9 AC |
2847 | /* 16 byte align the SP per frame requirements. */ |
2848 | ||
2849 | static CORE_ADDR | |
e53bef9f | 2850 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
2851 | { |
2852 | return sp & -(CORE_ADDR)16; | |
2853 | } | |
473f17b0 MK |
2854 | \f |
2855 | ||
593adc23 MK |
2856 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
2857 | in the floating-point register set REGSET to register cache | |
2858 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2859 | |
2860 | static void | |
e53bef9f MK |
2861 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
2862 | int regnum, const void *fpregs, size_t len) | |
473f17b0 | 2863 | { |
09424cff AA |
2864 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2865 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 2866 | |
1528345d | 2867 | gdb_assert (len >= tdep->sizeof_fpregset); |
90f90721 | 2868 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 2869 | } |
8b148df9 | 2870 | |
593adc23 MK |
2871 | /* Collect register REGNUM from the register cache REGCACHE and store |
2872 | it in the buffer specified by FPREGS and LEN as described by the | |
2873 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2874 | all registers in REGSET. */ | |
2875 | ||
2876 | static void | |
2877 | amd64_collect_fpregset (const struct regset *regset, | |
2878 | const struct regcache *regcache, | |
2879 | int regnum, void *fpregs, size_t len) | |
2880 | { | |
09424cff AA |
2881 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2882 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
593adc23 | 2883 | |
1528345d | 2884 | gdb_assert (len >= tdep->sizeof_fpregset); |
593adc23 MK |
2885 | amd64_collect_fxsave (regcache, regnum, fpregs); |
2886 | } | |
2887 | ||
8f0435f7 | 2888 | const struct regset amd64_fpregset = |
ecc37a5a AA |
2889 | { |
2890 | NULL, amd64_supply_fpregset, amd64_collect_fpregset | |
2891 | }; | |
c6b33596 MK |
2892 | \f |
2893 | ||
436675d3 PA |
2894 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
2895 | %rdi. We expect its value to be a pointer to the jmp_buf structure | |
2896 | from which we extract the address that we will land at. This | |
2897 | address is copied into PC. This routine returns non-zero on | |
2898 | success. */ | |
2899 | ||
2900 | static int | |
2901 | amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2902 | { | |
2903 | gdb_byte buf[8]; | |
2904 | CORE_ADDR jb_addr; | |
2905 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
2906 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
0dfff4cb | 2907 | int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
2908 | |
2909 | /* If JB_PC_OFFSET is -1, we have no way to find out where the | |
2910 | longjmp will land. */ | |
2911 | if (jb_pc_offset == -1) | |
2912 | return 0; | |
2913 | ||
2914 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); | |
0dfff4cb UW |
2915 | jb_addr= extract_typed_address |
2916 | (buf, builtin_type (gdbarch)->builtin_data_ptr); | |
436675d3 PA |
2917 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
2918 | return 0; | |
2919 | ||
0dfff4cb | 2920 | *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
436675d3 PA |
2921 | |
2922 | return 1; | |
2923 | } | |
2924 | ||
cf648174 HZ |
2925 | static const int amd64_record_regmap[] = |
2926 | { | |
2927 | AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, | |
2928 | AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
2929 | AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, | |
2930 | AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, | |
2931 | AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, | |
2932 | AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM | |
2933 | }; | |
2934 | ||
2213a65d | 2935 | void |
90f90721 | 2936 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 2937 | { |
0c1a73d6 | 2938 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
90884b2b | 2939 | const struct target_desc *tdesc = info.target_desc; |
05c0465e SDJ |
2940 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
2941 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
2942 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
2943 | NULL }; | |
2944 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
2945 | NULL }; | |
53e95fcf | 2946 | |
473f17b0 MK |
2947 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
2948 | floating-point registers. */ | |
2949 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
8f0435f7 | 2950 | tdep->fpregset = &amd64_fpregset; |
473f17b0 | 2951 | |
90884b2b L |
2952 | if (! tdesc_has_registers (tdesc)) |
2953 | tdesc = tdesc_amd64; | |
2954 | tdep->tdesc = tdesc; | |
2955 | ||
2956 | tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; | |
2957 | tdep->register_names = amd64_register_names; | |
2958 | ||
01f9f808 MS |
2959 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL) |
2960 | { | |
2961 | tdep->zmmh_register_names = amd64_zmmh_names; | |
2962 | tdep->k_register_names = amd64_k_names; | |
2963 | tdep->xmm_avx512_register_names = amd64_xmm_avx512_names; | |
2964 | tdep->ymm16h_register_names = amd64_ymmh_avx512_names; | |
2965 | ||
2966 | tdep->num_zmm_regs = 32; | |
2967 | tdep->num_xmm_avx512_regs = 16; | |
2968 | tdep->num_ymm_avx512_regs = 16; | |
2969 | ||
2970 | tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM; | |
2971 | tdep->k0_regnum = AMD64_K0_REGNUM; | |
2972 | tdep->xmm16_regnum = AMD64_XMM16_REGNUM; | |
2973 | tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM; | |
2974 | } | |
2975 | ||
a055a187 L |
2976 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) |
2977 | { | |
2978 | tdep->ymmh_register_names = amd64_ymmh_names; | |
2979 | tdep->num_ymm_regs = 16; | |
2980 | tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; | |
2981 | } | |
2982 | ||
e43e105e WT |
2983 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) |
2984 | { | |
2985 | tdep->mpx_register_names = amd64_mpx_names; | |
2986 | tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; | |
2987 | tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; | |
2988 | } | |
2989 | ||
fe01d668 | 2990 | tdep->num_byte_regs = 20; |
1ba53b71 L |
2991 | tdep->num_word_regs = 16; |
2992 | tdep->num_dword_regs = 16; | |
2993 | /* Avoid wiring in the MMX registers for now. */ | |
2994 | tdep->num_mmx_regs = 0; | |
2995 | ||
3543a589 TT |
2996 | set_gdbarch_pseudo_register_read_value (gdbarch, |
2997 | amd64_pseudo_register_read_value); | |
1ba53b71 L |
2998 | set_gdbarch_pseudo_register_write (gdbarch, |
2999 | amd64_pseudo_register_write); | |
3000 | ||
3001 | set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); | |
3002 | ||
5716833c | 3003 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 3004 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 3005 | tdep->num_xmm_regs = 16; |
53e95fcf | 3006 | |
0c1a73d6 | 3007 | /* This is what all the fuss is about. */ |
53e95fcf JS |
3008 | set_gdbarch_long_bit (gdbarch, 64); |
3009 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3010 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3011 | ||
e53bef9f MK |
3012 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
3013 | up 128 bits, even though it's still based on the i387 extended | |
3014 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
3015 | set_gdbarch_long_double_bit (gdbarch, 128); |
3016 | ||
e53bef9f | 3017 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
b83b026c MK |
3018 | |
3019 | /* Register numbers of various important registers. */ | |
90f90721 MK |
3020 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
3021 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
3022 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
3023 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 3024 | |
e53bef9f MK |
3025 | /* The "default" register numbering scheme for AMD64 is referred to |
3026 | as the "DWARF Register Number Mapping" in the System V psABI. | |
3027 | The preferred debugging format for all known AMD64 targets is | |
3028 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
3029 | DWARF-1), but we provide the same mapping just in case. This | |
3030 | mapping is also used for stabs, which GCC does support. */ | |
3031 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
e53bef9f | 3032 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
de220d0f | 3033 | |
c4f35dd8 | 3034 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 3035 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 3036 | |
c4f35dd8 | 3037 | /* Call dummy code. */ |
e53bef9f MK |
3038 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
3039 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 3040 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 3041 | |
83acabca | 3042 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
d532c08f MK |
3043 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
3044 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
3045 | ||
efb1c01c | 3046 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 3047 | |
e53bef9f | 3048 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 3049 | |
cf648174 HZ |
3050 | tdep->record_regmap = amd64_record_regmap; |
3051 | ||
10458914 | 3052 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
53e95fcf | 3053 | |
872761f4 MS |
3054 | /* Hook the function epilogue frame unwinder. This unwinder is |
3055 | appended to the list first, so that it supercedes the other | |
3056 | unwinders in function epilogues. */ | |
3057 | frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); | |
3058 | ||
3059 | /* Hook the prologue-based frame unwinders. */ | |
10458914 DJ |
3060 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
3061 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); | |
e53bef9f | 3062 | frame_base_set_default (gdbarch, &amd64_frame_base); |
c6b33596 | 3063 | |
436675d3 | 3064 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); |
dde08ee1 PA |
3065 | |
3066 | set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); | |
6710bf39 SS |
3067 | |
3068 | set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); | |
55aa24fb SDJ |
3069 | |
3070 | /* SystemTap variables and functions. */ | |
05c0465e SDJ |
3071 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
3072 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
3073 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
3074 | stap_register_indirection_prefixes); | |
3075 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
3076 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
3077 | set_gdbarch_stap_is_single_operand (gdbarch, |
3078 | i386_stap_is_single_operand); | |
3079 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3080 | i386_stap_parse_special_token); | |
c2170eef MM |
3081 | set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); |
3082 | set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); | |
3083 | set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); | |
c4f35dd8 | 3084 | } |
fff4548b MK |
3085 | \f |
3086 | ||
3087 | static struct type * | |
3088 | amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
3089 | { | |
3090 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3091 | ||
3092 | switch (regnum - tdep->eax_regnum) | |
3093 | { | |
3094 | case AMD64_RBP_REGNUM: /* %ebp */ | |
3095 | case AMD64_RSP_REGNUM: /* %esp */ | |
3096 | return builtin_type (gdbarch)->builtin_data_ptr; | |
3097 | case AMD64_RIP_REGNUM: /* %eip */ | |
3098 | return builtin_type (gdbarch)->builtin_func_ptr; | |
3099 | } | |
3100 | ||
3101 | return i386_pseudo_register_type (gdbarch, regnum); | |
3102 | } | |
3103 | ||
3104 | void | |
3105 | amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3106 | { | |
3107 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3108 | const struct target_desc *tdesc = info.target_desc; | |
3109 | ||
3110 | amd64_init_abi (info, gdbarch); | |
3111 | ||
3112 | if (! tdesc_has_registers (tdesc)) | |
3113 | tdesc = tdesc_x32; | |
3114 | tdep->tdesc = tdesc; | |
3115 | ||
3116 | tdep->num_dword_regs = 17; | |
3117 | set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); | |
3118 | ||
3119 | set_gdbarch_long_bit (gdbarch, 32); | |
3120 | set_gdbarch_ptr_bit (gdbarch, 32); | |
3121 | } | |
90884b2b | 3122 | |
97de3545 JB |
3123 | /* Return the target description for a specified XSAVE feature mask. */ |
3124 | ||
3125 | const struct target_desc * | |
3126 | amd64_target_description (uint64_t xcr0) | |
3127 | { | |
3128 | switch (xcr0 & X86_XSTATE_ALL_MASK) | |
3129 | { | |
3130 | case X86_XSTATE_MPX_AVX512_MASK: | |
3131 | case X86_XSTATE_AVX512_MASK: | |
3132 | return tdesc_amd64_avx512; | |
3133 | case X86_XSTATE_MPX_MASK: | |
3134 | return tdesc_amd64_mpx; | |
3135 | case X86_XSTATE_AVX_MASK: | |
3136 | return tdesc_amd64_avx; | |
3137 | default: | |
3138 | return tdesc_amd64; | |
3139 | } | |
3140 | } | |
3141 | ||
90884b2b L |
3142 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
3143 | void _initialize_amd64_tdep (void); | |
3144 | ||
3145 | void | |
3146 | _initialize_amd64_tdep (void) | |
3147 | { | |
3148 | initialize_tdesc_amd64 (); | |
a055a187 | 3149 | initialize_tdesc_amd64_avx (); |
e43e105e | 3150 | initialize_tdesc_amd64_mpx (); |
01f9f808 MS |
3151 | initialize_tdesc_amd64_avx512 (); |
3152 | ||
ac1438b5 L |
3153 | initialize_tdesc_x32 (); |
3154 | initialize_tdesc_x32_avx (); | |
01f9f808 | 3155 | initialize_tdesc_x32_avx512 (); |
90884b2b | 3156 | } |
c4f35dd8 MK |
3157 | \f |
3158 | ||
41d041d6 MK |
3159 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
3160 | sense that the instruction pointer and data pointer are simply | |
3161 | 64-bit offsets into the code segment and the data segment instead | |
3162 | of a selector offset pair. The functions below store the upper 32 | |
3163 | bits of these pointers (instead of just the 16-bits of the segment | |
3164 | selector). */ | |
3165 | ||
3166 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
3167 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
3168 | -1, do this for all registers. This function masks off any of the | |
3169 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
3170 | |
3171 | void | |
90f90721 | 3172 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
20a6ec49 | 3173 | const void *fxsave) |
c4f35dd8 | 3174 | { |
20a6ec49 MD |
3175 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3177 | ||
41d041d6 | 3178 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 | 3179 | |
233dfcf0 L |
3180 | if (fxsave |
3181 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
c4f35dd8 | 3182 | { |
9a3c8263 | 3183 | const gdb_byte *regs = (const gdb_byte *) fxsave; |
41d041d6 | 3184 | |
20a6ec49 MD |
3185 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
3186 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
3187 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3188 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
c4f35dd8 | 3189 | } |
0c1a73d6 MK |
3190 | } |
3191 | ||
a055a187 L |
3192 | /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ |
3193 | ||
3194 | void | |
3195 | amd64_supply_xsave (struct regcache *regcache, int regnum, | |
3196 | const void *xsave) | |
3197 | { | |
3198 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
3199 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3200 | ||
3201 | i387_supply_xsave (regcache, regnum, xsave); | |
3202 | ||
233dfcf0 L |
3203 | if (xsave |
3204 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) | |
a055a187 | 3205 | { |
9a3c8263 | 3206 | const gdb_byte *regs = (const gdb_byte *) xsave; |
a055a187 L |
3207 | |
3208 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
3209 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), | |
3210 | regs + 12); | |
3211 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3212 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), | |
3213 | regs + 20); | |
3214 | } | |
3215 | } | |
3216 | ||
3c017e40 MK |
3217 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
3218 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
3219 | all registers. This function doesn't touch any of the reserved | |
3220 | bits in *FXSAVE. */ | |
3221 | ||
3222 | void | |
3223 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
3224 | void *fxsave) | |
3225 | { | |
20a6ec49 MD |
3226 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3228 | gdb_byte *regs = (gdb_byte *) fxsave; |
3c017e40 MK |
3229 | |
3230 | i387_collect_fxsave (regcache, regnum, fxsave); | |
3231 | ||
233dfcf0 | 3232 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
f0ef85a5 | 3233 | { |
20a6ec49 MD |
3234 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
3235 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); | |
3236 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3237 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); | |
f0ef85a5 | 3238 | } |
3c017e40 | 3239 | } |
a055a187 | 3240 | |
7a9dd1b2 | 3241 | /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ |
a055a187 L |
3242 | |
3243 | void | |
3244 | amd64_collect_xsave (const struct regcache *regcache, int regnum, | |
3245 | void *xsave, int gcore) | |
3246 | { | |
3247 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
3248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3249 | gdb_byte *regs = (gdb_byte *) xsave; |
a055a187 L |
3250 | |
3251 | i387_collect_xsave (regcache, regnum, xsave, gcore); | |
3252 | ||
233dfcf0 | 3253 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
a055a187 L |
3254 | { |
3255 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) | |
3256 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), | |
3257 | regs + 12); | |
3258 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) | |
3259 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), | |
3260 | regs + 20); | |
3261 | } | |
3262 | } |