Commit | Line | Data |
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e53bef9f | 1 | /* Target-dependent code for AMD64. |
ce0eebec | 2 | |
e53bef9f | 3 | Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
c4f35dd8 MK |
24 | #include "arch-utils.h" |
25 | #include "block.h" | |
26 | #include "dummy-frame.h" | |
27 | #include "frame.h" | |
28 | #include "frame-base.h" | |
29 | #include "frame-unwind.h" | |
53e95fcf | 30 | #include "inferior.h" |
53e95fcf | 31 | #include "gdbcmd.h" |
c4f35dd8 MK |
32 | #include "gdbcore.h" |
33 | #include "objfiles.h" | |
53e95fcf | 34 | #include "regcache.h" |
2c261fae | 35 | #include "regset.h" |
53e95fcf | 36 | #include "symfile.h" |
c4f35dd8 | 37 | |
82dbc5f7 | 38 | #include "gdb_assert.h" |
c4f35dd8 | 39 | |
9c1488cb | 40 | #include "amd64-tdep.h" |
c4f35dd8 | 41 | #include "i387-tdep.h" |
53e95fcf | 42 | |
e53bef9f MK |
43 | /* Note that the AMD64 architecture was previously known as x86-64. |
44 | The latter is (forever) engraved into the canonical system name as | |
90f90721 | 45 | returned by config.guess, and used as the name for the AMD64 port |
e53bef9f MK |
46 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
47 | don't like to shout. For GDB we prefer the amd64_-prefix over the | |
48 | x86_64_-prefix since it's so much easier to type. */ | |
49 | ||
402ecd56 | 50 | /* Register information. */ |
c4f35dd8 | 51 | |
e53bef9f | 52 | struct amd64_register_info |
de220d0f | 53 | { |
de220d0f ML |
54 | char *name; |
55 | struct type **type; | |
56 | }; | |
53e95fcf | 57 | |
e53bef9f | 58 | static struct amd64_register_info amd64_register_info[] = |
c4f35dd8 MK |
59 | { |
60 | { "rax", &builtin_type_int64 }, | |
61 | { "rbx", &builtin_type_int64 }, | |
62 | { "rcx", &builtin_type_int64 }, | |
63 | { "rdx", &builtin_type_int64 }, | |
64 | { "rsi", &builtin_type_int64 }, | |
65 | { "rdi", &builtin_type_int64 }, | |
66 | { "rbp", &builtin_type_void_data_ptr }, | |
67 | { "rsp", &builtin_type_void_data_ptr }, | |
68 | ||
69 | /* %r8 is indeed register number 8. */ | |
70 | { "r8", &builtin_type_int64 }, | |
71 | { "r9", &builtin_type_int64 }, | |
72 | { "r10", &builtin_type_int64 }, | |
73 | { "r11", &builtin_type_int64 }, | |
74 | { "r12", &builtin_type_int64 }, | |
75 | { "r13", &builtin_type_int64 }, | |
76 | { "r14", &builtin_type_int64 }, | |
77 | { "r15", &builtin_type_int64 }, | |
78 | { "rip", &builtin_type_void_func_ptr }, | |
79 | { "eflags", &builtin_type_int32 }, | |
af233647 MK |
80 | { "cs", &builtin_type_int32 }, |
81 | { "ss", &builtin_type_int32 }, | |
c4f35dd8 MK |
82 | { "ds", &builtin_type_int32 }, |
83 | { "es", &builtin_type_int32 }, | |
84 | { "fs", &builtin_type_int32 }, | |
85 | { "gs", &builtin_type_int32 }, | |
86 | ||
af233647 | 87 | /* %st0 is register number 24. */ |
c4f35dd8 MK |
88 | { "st0", &builtin_type_i387_ext }, |
89 | { "st1", &builtin_type_i387_ext }, | |
90 | { "st2", &builtin_type_i387_ext }, | |
91 | { "st3", &builtin_type_i387_ext }, | |
92 | { "st4", &builtin_type_i387_ext }, | |
93 | { "st5", &builtin_type_i387_ext }, | |
94 | { "st6", &builtin_type_i387_ext }, | |
95 | { "st7", &builtin_type_i387_ext }, | |
96 | { "fctrl", &builtin_type_int32 }, | |
97 | { "fstat", &builtin_type_int32 }, | |
98 | { "ftag", &builtin_type_int32 }, | |
99 | { "fiseg", &builtin_type_int32 }, | |
100 | { "fioff", &builtin_type_int32 }, | |
101 | { "foseg", &builtin_type_int32 }, | |
102 | { "fooff", &builtin_type_int32 }, | |
103 | { "fop", &builtin_type_int32 }, | |
104 | ||
af233647 | 105 | /* %xmm0 is register number 40. */ |
c4f35dd8 MK |
106 | { "xmm0", &builtin_type_v4sf }, |
107 | { "xmm1", &builtin_type_v4sf }, | |
108 | { "xmm2", &builtin_type_v4sf }, | |
109 | { "xmm3", &builtin_type_v4sf }, | |
110 | { "xmm4", &builtin_type_v4sf }, | |
111 | { "xmm5", &builtin_type_v4sf }, | |
112 | { "xmm6", &builtin_type_v4sf }, | |
113 | { "xmm7", &builtin_type_v4sf }, | |
114 | { "xmm8", &builtin_type_v4sf }, | |
115 | { "xmm9", &builtin_type_v4sf }, | |
116 | { "xmm10", &builtin_type_v4sf }, | |
117 | { "xmm11", &builtin_type_v4sf }, | |
118 | { "xmm12", &builtin_type_v4sf }, | |
119 | { "xmm13", &builtin_type_v4sf }, | |
120 | { "xmm14", &builtin_type_v4sf }, | |
121 | { "xmm15", &builtin_type_v4sf }, | |
122 | { "mxcsr", &builtin_type_int32 } | |
0e04a514 ML |
123 | }; |
124 | ||
c4f35dd8 | 125 | /* Total number of registers. */ |
e53bef9f MK |
126 | #define AMD64_NUM_REGS \ |
127 | (sizeof (amd64_register_info) / sizeof (amd64_register_info[0])) | |
de220d0f | 128 | |
c4f35dd8 | 129 | /* Return the name of register REGNUM. */ |
b6779aa2 | 130 | |
c4f35dd8 | 131 | static const char * |
e53bef9f | 132 | amd64_register_name (int regnum) |
53e95fcf | 133 | { |
e53bef9f MK |
134 | if (regnum >= 0 && regnum < AMD64_NUM_REGS) |
135 | return amd64_register_info[regnum].name; | |
53e95fcf | 136 | |
c4f35dd8 | 137 | return NULL; |
53e95fcf JS |
138 | } |
139 | ||
140 | /* Return the GDB type object for the "standard" data type of data in | |
c4f35dd8 | 141 | register REGNUM. */ |
53e95fcf | 142 | |
c4f35dd8 | 143 | static struct type * |
e53bef9f | 144 | amd64_register_type (struct gdbarch *gdbarch, int regnum) |
53e95fcf | 145 | { |
e53bef9f | 146 | gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS); |
4657573b | 147 | |
e53bef9f | 148 | return *amd64_register_info[regnum].type; |
53e95fcf JS |
149 | } |
150 | ||
c4f35dd8 MK |
151 | /* DWARF Register Number Mapping as defined in the System V psABI, |
152 | section 3.6. */ | |
53e95fcf | 153 | |
e53bef9f | 154 | static int amd64_dwarf_regmap[] = |
0e04a514 | 155 | { |
c4f35dd8 | 156 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
90f90721 MK |
157 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
158 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, | |
159 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, | |
c4f35dd8 MK |
160 | |
161 | /* Frame Pointer Register RBP. */ | |
90f90721 | 162 | AMD64_RBP_REGNUM, |
c4f35dd8 MK |
163 | |
164 | /* Stack Pointer Register RSP. */ | |
90f90721 | 165 | AMD64_RSP_REGNUM, |
c4f35dd8 MK |
166 | |
167 | /* Extended Integer Registers 8 - 15. */ | |
168 | 8, 9, 10, 11, 12, 13, 14, 15, | |
169 | ||
59207364 | 170 | /* Return Address RA. Mapped to RIP. */ |
90f90721 | 171 | AMD64_RIP_REGNUM, |
c4f35dd8 MK |
172 | |
173 | /* SSE Registers 0 - 7. */ | |
90f90721 MK |
174 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
175 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
176 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
177 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
c4f35dd8 MK |
178 | |
179 | /* Extended SSE Registers 8 - 15. */ | |
90f90721 MK |
180 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
181 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, | |
182 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, | |
183 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, | |
c4f35dd8 MK |
184 | |
185 | /* Floating Point Registers 0-7. */ | |
90f90721 MK |
186 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
187 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, | |
188 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, | |
189 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7 | |
c4f35dd8 | 190 | }; |
0e04a514 | 191 | |
e53bef9f MK |
192 | static const int amd64_dwarf_regmap_len = |
193 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); | |
0e04a514 | 194 | |
c4f35dd8 MK |
195 | /* Convert DWARF register number REG to the appropriate register |
196 | number used by GDB. */ | |
26abbdc4 | 197 | |
c4f35dd8 | 198 | static int |
e53bef9f | 199 | amd64_dwarf_reg_to_regnum (int reg) |
53e95fcf | 200 | { |
c4f35dd8 | 201 | int regnum = -1; |
53e95fcf | 202 | |
e53bef9f MK |
203 | if (reg >= 0 || reg < amd64_dwarf_regmap_len) |
204 | regnum = amd64_dwarf_regmap[reg]; | |
53e95fcf | 205 | |
c4f35dd8 MK |
206 | if (regnum == -1) |
207 | warning ("Unmapped DWARF Register #%d encountered\n", reg); | |
208 | ||
209 | return regnum; | |
53e95fcf | 210 | } |
d532c08f MK |
211 | |
212 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
213 | needs any special handling. */ | |
214 | ||
215 | static int | |
e53bef9f | 216 | amd64_convert_register_p (int regnum, struct type *type) |
d532c08f MK |
217 | { |
218 | return i386_fp_regnum_p (regnum); | |
219 | } | |
53e95fcf JS |
220 | \f |
221 | ||
efb1c01c MK |
222 | /* Register classes as defined in the psABI. */ |
223 | ||
224 | enum amd64_reg_class | |
225 | { | |
226 | AMD64_INTEGER, | |
227 | AMD64_SSE, | |
228 | AMD64_SSEUP, | |
229 | AMD64_X87, | |
230 | AMD64_X87UP, | |
231 | AMD64_COMPLEX_X87, | |
232 | AMD64_NO_CLASS, | |
233 | AMD64_MEMORY | |
234 | }; | |
235 | ||
236 | /* Return the union class of CLASS1 and CLASS2. See the psABI for | |
237 | details. */ | |
238 | ||
239 | static enum amd64_reg_class | |
240 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) | |
241 | { | |
242 | /* Rule (a): If both classes are equal, this is the resulting class. */ | |
243 | if (class1 == class2) | |
244 | return class1; | |
245 | ||
246 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class | |
247 | is the other class. */ | |
248 | if (class1 == AMD64_NO_CLASS) | |
249 | return class2; | |
250 | if (class2 == AMD64_NO_CLASS) | |
251 | return class1; | |
252 | ||
253 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ | |
254 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) | |
255 | return AMD64_MEMORY; | |
256 | ||
257 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ | |
258 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) | |
259 | return AMD64_INTEGER; | |
260 | ||
261 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, | |
262 | MEMORY is used as class. */ | |
263 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP | |
264 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 | |
265 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) | |
266 | return AMD64_MEMORY; | |
267 | ||
268 | /* Rule (f): Otherwise class SSE is used. */ | |
269 | return AMD64_SSE; | |
270 | } | |
271 | ||
272 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); | |
273 | ||
79b1ab3d MK |
274 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
275 | ||
276 | static int | |
277 | amd64_non_pod_p (struct type *type) | |
278 | { | |
279 | /* ??? A class with a base class certainly isn't POD, but does this | |
280 | catch all non-POD structure types? */ | |
281 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) | |
282 | return 1; | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
efb1c01c MK |
287 | /* Classify TYPE according to the rules for aggregate (structures and |
288 | arrays) and union types, and store the result in CLASS. */ | |
c4f35dd8 MK |
289 | |
290 | static void | |
efb1c01c | 291 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
53e95fcf JS |
292 | { |
293 | int len = TYPE_LENGTH (type); | |
294 | ||
efb1c01c MK |
295 | /* 1. If the size of an object is larger than two eightbytes, or in |
296 | C++, is a non-POD structure or union type, or contains | |
297 | unaligned fields, it has class memory. */ | |
79b1ab3d | 298 | if (len > 16 || amd64_non_pod_p (type)) |
53e95fcf | 299 | { |
efb1c01c MK |
300 | class[0] = class[1] = AMD64_MEMORY; |
301 | return; | |
53e95fcf | 302 | } |
efb1c01c MK |
303 | |
304 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ | |
305 | class[0] = class[1] = AMD64_NO_CLASS; | |
306 | ||
307 | /* 3. Each field of an object is classified recursively so that | |
308 | always two fields are considered. The resulting class is | |
309 | calculated according to the classes of the fields in the | |
310 | eightbyte: */ | |
311 | ||
312 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
8ffd9b1b | 313 | { |
efb1c01c MK |
314 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
315 | ||
316 | /* All fields in an array have the same type. */ | |
317 | amd64_classify (subtype, class); | |
318 | if (len > 8 && class[1] == AMD64_NO_CLASS) | |
319 | class[1] = class[0]; | |
8ffd9b1b | 320 | } |
53e95fcf JS |
321 | else |
322 | { | |
efb1c01c | 323 | int i; |
53e95fcf | 324 | |
efb1c01c MK |
325 | /* Structure or union. */ |
326 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
327 | || TYPE_CODE (type) == TYPE_CODE_UNION); | |
328 | ||
329 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
53e95fcf | 330 | { |
efb1c01c MK |
331 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
332 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; | |
333 | enum amd64_reg_class subclass[2]; | |
334 | ||
562c50c2 MK |
335 | /* Ignore static fields. */ |
336 | if (TYPE_FIELD_STATIC (type, i)) | |
337 | continue; | |
338 | ||
efb1c01c MK |
339 | gdb_assert (pos == 0 || pos == 1); |
340 | ||
341 | amd64_classify (subtype, subclass); | |
342 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); | |
343 | if (pos == 0) | |
344 | class[1] = amd64_merge_classes (class[1], subclass[1]); | |
53e95fcf | 345 | } |
53e95fcf | 346 | } |
efb1c01c MK |
347 | |
348 | /* 4. Then a post merger cleanup is done: */ | |
349 | ||
350 | /* Rule (a): If one of the classes is MEMORY, the whole argument is | |
351 | passed in memory. */ | |
352 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) | |
353 | class[0] = class[1] = AMD64_MEMORY; | |
354 | ||
355 | /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to | |
356 | SSE. */ | |
357 | if (class[0] == AMD64_SSEUP) | |
358 | class[0] = AMD64_SSE; | |
359 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) | |
360 | class[1] = AMD64_SSE; | |
361 | } | |
362 | ||
363 | /* Classify TYPE, and store the result in CLASS. */ | |
364 | ||
365 | static void | |
366 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) | |
367 | { | |
368 | enum type_code code = TYPE_CODE (type); | |
369 | int len = TYPE_LENGTH (type); | |
370 | ||
371 | class[0] = class[1] = AMD64_NO_CLASS; | |
372 | ||
373 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, | |
374 | long, long long, and pointers are in the INTEGER class. */ | |
375 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM | |
376 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) | |
377 | && (len == 1 || len == 2 || len == 4 || len == 8)) | |
378 | class[0] = AMD64_INTEGER; | |
379 | ||
380 | /* Arguments of types float, double and __m64 are in class SSE. */ | |
381 | else if (code == TYPE_CODE_FLT && (len == 4 || len == 8)) | |
382 | /* FIXME: __m64 . */ | |
383 | class[0] = AMD64_SSE; | |
384 | ||
385 | /* Arguments of types __float128 and __m128 are split into two | |
386 | halves. The least significant ones belong to class SSE, the most | |
387 | significant one to class SSEUP. */ | |
388 | /* FIXME: __float128, __m128. */ | |
389 | ||
390 | /* The 64-bit mantissa of arguments of type long double belongs to | |
391 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to | |
392 | class X87UP. */ | |
393 | else if (code == TYPE_CODE_FLT && len == 16) | |
394 | /* Class X87 and X87UP. */ | |
395 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; | |
396 | ||
397 | /* Aggregates. */ | |
398 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT | |
399 | || code == TYPE_CODE_UNION) | |
400 | amd64_classify_aggregate (type, class); | |
401 | } | |
402 | ||
403 | static enum return_value_convention | |
404 | amd64_return_value (struct gdbarch *gdbarch, struct type *type, | |
405 | struct regcache *regcache, | |
406 | void *readbuf, const void *writebuf) | |
407 | { | |
408 | enum amd64_reg_class class[2]; | |
409 | int len = TYPE_LENGTH (type); | |
90f90721 MK |
410 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
411 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; | |
efb1c01c MK |
412 | int integer_reg = 0; |
413 | int sse_reg = 0; | |
414 | int i; | |
415 | ||
416 | gdb_assert (!(readbuf && writebuf)); | |
417 | ||
418 | /* 1. Classify the return type with the classification algorithm. */ | |
419 | amd64_classify (type, class); | |
420 | ||
421 | /* 2. If the type has class MEMORY, then the caller provides space | |
422 | for the return value and passes the address of this storage in | |
423 | %rdi as if it were the first argument to the function. In | |
424 | effect, this address becomes a hidden first argument. */ | |
425 | if (class[0] == AMD64_MEMORY) | |
426 | return RETURN_VALUE_STRUCT_CONVENTION; | |
427 | ||
428 | gdb_assert (class[1] != AMD64_MEMORY); | |
429 | gdb_assert (len <= 16); | |
430 | ||
431 | for (i = 0; len > 0; i++, len -= 8) | |
432 | { | |
433 | int regnum = -1; | |
434 | int offset = 0; | |
435 | ||
436 | switch (class[i]) | |
437 | { | |
438 | case AMD64_INTEGER: | |
439 | /* 3. If the class is INTEGER, the next available register | |
440 | of the sequence %rax, %rdx is used. */ | |
441 | regnum = integer_regnum[integer_reg++]; | |
442 | break; | |
443 | ||
444 | case AMD64_SSE: | |
445 | /* 4. If the class is SSE, the next available SSE register | |
446 | of the sequence %xmm0, %xmm1 is used. */ | |
447 | regnum = sse_regnum[sse_reg++]; | |
448 | break; | |
449 | ||
450 | case AMD64_SSEUP: | |
451 | /* 5. If the class is SSEUP, the eightbyte is passed in the | |
452 | upper half of the last used SSE register. */ | |
453 | gdb_assert (sse_reg > 0); | |
454 | regnum = sse_regnum[sse_reg - 1]; | |
455 | offset = 8; | |
456 | break; | |
457 | ||
458 | case AMD64_X87: | |
459 | /* 6. If the class is X87, the value is returned on the X87 | |
460 | stack in %st0 as 80-bit x87 number. */ | |
90f90721 | 461 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
462 | if (writebuf) |
463 | i387_return_value (gdbarch, regcache); | |
464 | break; | |
465 | ||
466 | case AMD64_X87UP: | |
467 | /* 7. If the class is X87UP, the value is returned together | |
468 | with the previous X87 value in %st0. */ | |
469 | gdb_assert (i > 0 && class[0] == AMD64_X87); | |
90f90721 | 470 | regnum = AMD64_ST0_REGNUM; |
efb1c01c MK |
471 | offset = 8; |
472 | len = 2; | |
473 | break; | |
474 | ||
475 | case AMD64_NO_CLASS: | |
476 | continue; | |
477 | ||
478 | default: | |
479 | gdb_assert (!"Unexpected register class."); | |
480 | } | |
481 | ||
482 | gdb_assert (regnum != -1); | |
483 | ||
484 | if (readbuf) | |
485 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), | |
486 | (char *) readbuf + i * 8); | |
487 | if (writebuf) | |
488 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), | |
489 | (const char *) writebuf + i * 8); | |
490 | } | |
491 | ||
492 | return RETURN_VALUE_REGISTER_CONVENTION; | |
53e95fcf JS |
493 | } |
494 | \f | |
495 | ||
720aa428 MK |
496 | static CORE_ADDR |
497 | amd64_push_arguments (struct regcache *regcache, int nargs, | |
6470d250 | 498 | struct value **args, CORE_ADDR sp, int struct_return) |
720aa428 MK |
499 | { |
500 | static int integer_regnum[] = | |
501 | { | |
90f90721 MK |
502 | AMD64_RDI_REGNUM, /* %rdi */ |
503 | AMD64_RSI_REGNUM, /* %rsi */ | |
504 | AMD64_RDX_REGNUM, /* %rdx */ | |
505 | AMD64_RCX_REGNUM, /* %rcx */ | |
506 | 8, /* %r8 */ | |
507 | 9 /* %r9 */ | |
720aa428 MK |
508 | }; |
509 | static int sse_regnum[] = | |
510 | { | |
511 | /* %xmm0 ... %xmm7 */ | |
90f90721 MK |
512 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
513 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, | |
514 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, | |
515 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, | |
720aa428 MK |
516 | }; |
517 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); | |
518 | int num_stack_args = 0; | |
519 | int num_elements = 0; | |
520 | int element = 0; | |
521 | int integer_reg = 0; | |
522 | int sse_reg = 0; | |
523 | int i; | |
524 | ||
6470d250 MK |
525 | /* Reserve a register for the "hidden" argument. */ |
526 | if (struct_return) | |
527 | integer_reg++; | |
528 | ||
720aa428 MK |
529 | for (i = 0; i < nargs; i++) |
530 | { | |
531 | struct type *type = VALUE_TYPE (args[i]); | |
532 | int len = TYPE_LENGTH (type); | |
533 | enum amd64_reg_class class[2]; | |
534 | int needed_integer_regs = 0; | |
535 | int needed_sse_regs = 0; | |
536 | int j; | |
537 | ||
538 | /* Classify argument. */ | |
539 | amd64_classify (type, class); | |
540 | ||
541 | /* Calculate the number of integer and SSE registers needed for | |
542 | this argument. */ | |
543 | for (j = 0; j < 2; j++) | |
544 | { | |
545 | if (class[j] == AMD64_INTEGER) | |
546 | needed_integer_regs++; | |
547 | else if (class[j] == AMD64_SSE) | |
548 | needed_sse_regs++; | |
549 | } | |
550 | ||
551 | /* Check whether enough registers are available, and if the | |
552 | argument should be passed in registers at all. */ | |
553 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) | |
554 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) | |
555 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) | |
556 | { | |
557 | /* The argument will be passed on the stack. */ | |
558 | num_elements += ((len + 7) / 8); | |
559 | stack_args[num_stack_args++] = args[i]; | |
560 | } | |
561 | else | |
562 | { | |
563 | /* The argument will be passed in registers. */ | |
564 | char *valbuf = VALUE_CONTENTS (args[i]); | |
565 | char buf[8]; | |
566 | ||
567 | gdb_assert (len <= 16); | |
568 | ||
569 | for (j = 0; len > 0; j++, len -= 8) | |
570 | { | |
571 | int regnum = -1; | |
572 | int offset = 0; | |
573 | ||
574 | switch (class[j]) | |
575 | { | |
576 | case AMD64_INTEGER: | |
577 | regnum = integer_regnum[integer_reg++]; | |
578 | break; | |
579 | ||
580 | case AMD64_SSE: | |
581 | regnum = sse_regnum[sse_reg++]; | |
582 | break; | |
583 | ||
584 | case AMD64_SSEUP: | |
585 | gdb_assert (sse_reg > 0); | |
586 | regnum = sse_regnum[sse_reg - 1]; | |
587 | offset = 8; | |
588 | break; | |
589 | ||
590 | default: | |
591 | gdb_assert (!"Unexpected register class."); | |
592 | } | |
593 | ||
594 | gdb_assert (regnum != -1); | |
595 | memset (buf, 0, sizeof buf); | |
596 | memcpy (buf, valbuf + j * 8, min (len, 8)); | |
597 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); | |
598 | } | |
599 | } | |
600 | } | |
601 | ||
602 | /* Allocate space for the arguments on the stack. */ | |
603 | sp -= num_elements * 8; | |
604 | ||
605 | /* The psABI says that "The end of the input argument area shall be | |
606 | aligned on a 16 byte boundary." */ | |
607 | sp &= ~0xf; | |
608 | ||
609 | /* Write out the arguments to the stack. */ | |
610 | for (i = 0; i < num_stack_args; i++) | |
611 | { | |
612 | struct type *type = VALUE_TYPE (stack_args[i]); | |
613 | char *valbuf = VALUE_CONTENTS (stack_args[i]); | |
614 | int len = TYPE_LENGTH (type); | |
615 | ||
616 | write_memory (sp + element * 8, valbuf, len); | |
617 | element += ((len + 7) / 8); | |
618 | } | |
619 | ||
620 | /* The psABI says that "For calls that may call functions that use | |
621 | varargs or stdargs (prototype-less calls or calls to functions | |
622 | containing ellipsis (...) in the declaration) %al is used as | |
623 | hidden argument to specify the number of SSE registers used. */ | |
90f90721 | 624 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
720aa428 MK |
625 | return sp; |
626 | } | |
627 | ||
c4f35dd8 | 628 | static CORE_ADDR |
e53bef9f MK |
629 | amd64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
630 | struct regcache *regcache, CORE_ADDR bp_addr, | |
631 | int nargs, struct value **args, CORE_ADDR sp, | |
632 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 633 | { |
c4f35dd8 MK |
634 | char buf[8]; |
635 | ||
636 | /* Pass arguments. */ | |
6470d250 | 637 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
c4f35dd8 MK |
638 | |
639 | /* Pass "hidden" argument". */ | |
640 | if (struct_return) | |
641 | { | |
642 | store_unsigned_integer (buf, 8, struct_addr); | |
90f90721 | 643 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
c4f35dd8 MK |
644 | } |
645 | ||
646 | /* Store return address. */ | |
647 | sp -= 8; | |
10f93086 | 648 | store_unsigned_integer (buf, 8, bp_addr); |
c4f35dd8 MK |
649 | write_memory (sp, buf, 8); |
650 | ||
651 | /* Finally, update the stack pointer... */ | |
652 | store_unsigned_integer (buf, 8, sp); | |
90f90721 | 653 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
654 | |
655 | /* ...and fake a frame pointer. */ | |
90f90721 | 656 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
c4f35dd8 | 657 | |
3e210248 | 658 | return sp + 16; |
53e95fcf | 659 | } |
c4f35dd8 MK |
660 | \f |
661 | ||
662 | /* The maximum number of saved registers. This should include %rip. */ | |
90f90721 | 663 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
c4f35dd8 | 664 | |
e53bef9f | 665 | struct amd64_frame_cache |
c4f35dd8 MK |
666 | { |
667 | /* Base address. */ | |
668 | CORE_ADDR base; | |
669 | CORE_ADDR sp_offset; | |
670 | CORE_ADDR pc; | |
671 | ||
672 | /* Saved registers. */ | |
e53bef9f | 673 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
c4f35dd8 MK |
674 | CORE_ADDR saved_sp; |
675 | ||
676 | /* Do we have a frame? */ | |
677 | int frameless_p; | |
678 | }; | |
8dda9770 | 679 | |
c4f35dd8 MK |
680 | /* Allocate and initialize a frame cache. */ |
681 | ||
e53bef9f MK |
682 | static struct amd64_frame_cache * |
683 | amd64_alloc_frame_cache (void) | |
8dda9770 | 684 | { |
e53bef9f | 685 | struct amd64_frame_cache *cache; |
c4f35dd8 MK |
686 | int i; |
687 | ||
e53bef9f | 688 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); |
8dda9770 | 689 | |
c4f35dd8 MK |
690 | /* Base address. */ |
691 | cache->base = 0; | |
692 | cache->sp_offset = -8; | |
693 | cache->pc = 0; | |
694 | ||
695 | /* Saved registers. We initialize these to -1 since zero is a valid | |
696 | offset (that's where %rbp is supposed to be stored). */ | |
e53bef9f | 697 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
698 | cache->saved_regs[i] = -1; |
699 | cache->saved_sp = 0; | |
700 | ||
701 | /* Frameless until proven otherwise. */ | |
702 | cache->frameless_p = 1; | |
703 | ||
704 | return cache; | |
8dda9770 | 705 | } |
53e95fcf | 706 | |
c4f35dd8 MK |
707 | /* Do a limited analysis of the prologue at PC and update CACHE |
708 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
709 | address where the analysis stopped. | |
710 | ||
711 | We will handle only functions beginning with: | |
712 | ||
713 | pushq %rbp 0x55 | |
714 | movq %rsp, %rbp 0x48 0x89 0xe5 | |
715 | ||
716 | Any function that doesn't start with this sequence will be assumed | |
717 | to have no prologue and thus no valid frame pointer in %rbp. */ | |
718 | ||
719 | static CORE_ADDR | |
e53bef9f MK |
720 | amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
721 | struct amd64_frame_cache *cache) | |
53e95fcf | 722 | { |
c4f35dd8 MK |
723 | static unsigned char proto[3] = { 0x48, 0x89, 0xe5 }; |
724 | unsigned char buf[3]; | |
725 | unsigned char op; | |
726 | ||
727 | if (current_pc <= pc) | |
728 | return current_pc; | |
729 | ||
730 | op = read_memory_unsigned_integer (pc, 1); | |
731 | ||
732 | if (op == 0x55) /* pushq %rbp */ | |
733 | { | |
734 | /* Take into account that we've executed the `pushq %rbp' that | |
735 | starts this instruction sequence. */ | |
90f90721 | 736 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
c4f35dd8 MK |
737 | cache->sp_offset += 8; |
738 | ||
739 | /* If that's all, return now. */ | |
740 | if (current_pc <= pc + 1) | |
741 | return current_pc; | |
742 | ||
743 | /* Check for `movq %rsp, %rbp'. */ | |
744 | read_memory (pc + 1, buf, 3); | |
745 | if (memcmp (buf, proto, 3) != 0) | |
746 | return pc + 1; | |
747 | ||
748 | /* OK, we actually have a frame. */ | |
749 | cache->frameless_p = 0; | |
750 | return pc + 4; | |
751 | } | |
752 | ||
753 | return pc; | |
53e95fcf JS |
754 | } |
755 | ||
c4f35dd8 MK |
756 | /* Return PC of first real instruction. */ |
757 | ||
758 | static CORE_ADDR | |
e53bef9f | 759 | amd64_skip_prologue (CORE_ADDR start_pc) |
53e95fcf | 760 | { |
e53bef9f | 761 | struct amd64_frame_cache cache; |
c4f35dd8 MK |
762 | CORE_ADDR pc; |
763 | ||
e53bef9f | 764 | pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache); |
c4f35dd8 MK |
765 | if (cache.frameless_p) |
766 | return start_pc; | |
767 | ||
768 | return pc; | |
53e95fcf | 769 | } |
c4f35dd8 | 770 | \f |
53e95fcf | 771 | |
c4f35dd8 MK |
772 | /* Normal frames. */ |
773 | ||
e53bef9f MK |
774 | static struct amd64_frame_cache * |
775 | amd64_frame_cache (struct frame_info *next_frame, void **this_cache) | |
6d686a84 | 776 | { |
e53bef9f | 777 | struct amd64_frame_cache *cache; |
c4f35dd8 | 778 | char buf[8]; |
6d686a84 | 779 | int i; |
6d686a84 | 780 | |
c4f35dd8 MK |
781 | if (*this_cache) |
782 | return *this_cache; | |
6d686a84 | 783 | |
e53bef9f | 784 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 MK |
785 | *this_cache = cache; |
786 | ||
c4f35dd8 MK |
787 | cache->pc = frame_func_unwind (next_frame); |
788 | if (cache->pc != 0) | |
e53bef9f | 789 | amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); |
c4f35dd8 MK |
790 | |
791 | if (cache->frameless_p) | |
792 | { | |
4a28816e MK |
793 | /* We didn't find a valid frame. If we're at the start of a |
794 | function, or somewhere half-way its prologue, the function's | |
795 | frame probably hasn't been fully setup yet. Try to | |
796 | reconstruct the base address for the stack frame by looking | |
797 | at the stack pointer. For truly "frameless" functions this | |
798 | might work too. */ | |
c4f35dd8 | 799 | |
90f90721 | 800 | frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
801 | cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; |
802 | } | |
35883a3f MK |
803 | else |
804 | { | |
90f90721 | 805 | frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); |
35883a3f MK |
806 | cache->base = extract_unsigned_integer (buf, 8); |
807 | } | |
c4f35dd8 MK |
808 | |
809 | /* Now that we have the base address for the stack frame we can | |
810 | calculate the value of %rsp in the calling frame. */ | |
811 | cache->saved_sp = cache->base + 16; | |
812 | ||
35883a3f MK |
813 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
814 | frame we find it at the same offset from the reconstructed base | |
815 | address. */ | |
90f90721 | 816 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; |
35883a3f | 817 | |
c4f35dd8 MK |
818 | /* Adjust all the saved registers such that they contain addresses |
819 | instead of offsets. */ | |
e53bef9f | 820 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
c4f35dd8 MK |
821 | if (cache->saved_regs[i] != -1) |
822 | cache->saved_regs[i] += cache->base; | |
823 | ||
824 | return cache; | |
6d686a84 ML |
825 | } |
826 | ||
c4f35dd8 | 827 | static void |
e53bef9f MK |
828 | amd64_frame_this_id (struct frame_info *next_frame, void **this_cache, |
829 | struct frame_id *this_id) | |
c4f35dd8 | 830 | { |
e53bef9f MK |
831 | struct amd64_frame_cache *cache = |
832 | amd64_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
833 | |
834 | /* This marks the outermost frame. */ | |
835 | if (cache->base == 0) | |
836 | return; | |
837 | ||
838 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
839 | } | |
e76e1718 | 840 | |
c4f35dd8 | 841 | static void |
e53bef9f MK |
842 | amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache, |
843 | int regnum, int *optimizedp, | |
844 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
845 | int *realnump, void *valuep) | |
53e95fcf | 846 | { |
e53bef9f MK |
847 | struct amd64_frame_cache *cache = |
848 | amd64_frame_cache (next_frame, this_cache); | |
e76e1718 | 849 | |
c4f35dd8 | 850 | gdb_assert (regnum >= 0); |
b1ab997b | 851 | |
c4f35dd8 MK |
852 | if (regnum == SP_REGNUM && cache->saved_sp) |
853 | { | |
854 | *optimizedp = 0; | |
855 | *lvalp = not_lval; | |
856 | *addrp = 0; | |
857 | *realnump = -1; | |
858 | if (valuep) | |
859 | { | |
860 | /* Store the value. */ | |
861 | store_unsigned_integer (valuep, 8, cache->saved_sp); | |
862 | } | |
863 | return; | |
864 | } | |
e76e1718 | 865 | |
e53bef9f | 866 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
c4f35dd8 MK |
867 | { |
868 | *optimizedp = 0; | |
869 | *lvalp = lval_memory; | |
870 | *addrp = cache->saved_regs[regnum]; | |
871 | *realnump = -1; | |
872 | if (valuep) | |
873 | { | |
874 | /* Read the value in from memory. */ | |
875 | read_memory (*addrp, valuep, | |
876 | register_size (current_gdbarch, regnum)); | |
877 | } | |
878 | return; | |
879 | } | |
e76e1718 | 880 | |
c4f35dd8 MK |
881 | frame_register_unwind (next_frame, regnum, |
882 | optimizedp, lvalp, addrp, realnump, valuep); | |
883 | } | |
e76e1718 | 884 | |
e53bef9f | 885 | static const struct frame_unwind amd64_frame_unwind = |
c4f35dd8 MK |
886 | { |
887 | NORMAL_FRAME, | |
e53bef9f MK |
888 | amd64_frame_this_id, |
889 | amd64_frame_prev_register | |
c4f35dd8 | 890 | }; |
e76e1718 | 891 | |
c4f35dd8 | 892 | static const struct frame_unwind * |
e53bef9f | 893 | amd64_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 | 894 | { |
e53bef9f | 895 | return &amd64_frame_unwind; |
c4f35dd8 MK |
896 | } |
897 | \f | |
e76e1718 | 898 | |
c4f35dd8 MK |
899 | /* Signal trampolines. */ |
900 | ||
901 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
902 | 64-bit variants. This would require using identical frame caches | |
903 | on both platforms. */ | |
904 | ||
e53bef9f MK |
905 | static struct amd64_frame_cache * |
906 | amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c4f35dd8 | 907 | { |
e53bef9f | 908 | struct amd64_frame_cache *cache; |
c4f35dd8 MK |
909 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
910 | CORE_ADDR addr; | |
911 | char buf[8]; | |
2b5e0749 | 912 | int i; |
c4f35dd8 MK |
913 | |
914 | if (*this_cache) | |
915 | return *this_cache; | |
916 | ||
e53bef9f | 917 | cache = amd64_alloc_frame_cache (); |
c4f35dd8 | 918 | |
90f90721 | 919 | frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); |
c4f35dd8 MK |
920 | cache->base = extract_unsigned_integer (buf, 8) - 8; |
921 | ||
922 | addr = tdep->sigcontext_addr (next_frame); | |
2b5e0749 | 923 | gdb_assert (tdep->sc_reg_offset); |
e53bef9f | 924 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); |
2b5e0749 MK |
925 | for (i = 0; i < tdep->sc_num_regs; i++) |
926 | if (tdep->sc_reg_offset[i] != -1) | |
927 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 MK |
928 | |
929 | *this_cache = cache; | |
930 | return cache; | |
53e95fcf JS |
931 | } |
932 | ||
c4f35dd8 | 933 | static void |
e53bef9f MK |
934 | amd64_sigtramp_frame_this_id (struct frame_info *next_frame, |
935 | void **this_cache, struct frame_id *this_id) | |
c4f35dd8 | 936 | { |
e53bef9f MK |
937 | struct amd64_frame_cache *cache = |
938 | amd64_sigtramp_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
939 | |
940 | (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); | |
941 | } | |
942 | ||
943 | static void | |
e53bef9f MK |
944 | amd64_sigtramp_frame_prev_register (struct frame_info *next_frame, |
945 | void **this_cache, | |
946 | int regnum, int *optimizedp, | |
947 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
948 | int *realnump, void *valuep) | |
c4f35dd8 MK |
949 | { |
950 | /* Make sure we've initialized the cache. */ | |
e53bef9f | 951 | amd64_sigtramp_frame_cache (next_frame, this_cache); |
c4f35dd8 | 952 | |
e53bef9f MK |
953 | amd64_frame_prev_register (next_frame, this_cache, regnum, |
954 | optimizedp, lvalp, addrp, realnump, valuep); | |
c4f35dd8 MK |
955 | } |
956 | ||
e53bef9f | 957 | static const struct frame_unwind amd64_sigtramp_frame_unwind = |
c4f35dd8 MK |
958 | { |
959 | SIGTRAMP_FRAME, | |
e53bef9f MK |
960 | amd64_sigtramp_frame_this_id, |
961 | amd64_sigtramp_frame_prev_register | |
c4f35dd8 MK |
962 | }; |
963 | ||
964 | static const struct frame_unwind * | |
e53bef9f | 965 | amd64_sigtramp_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 | 966 | { |
336d1bba | 967 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
c4f35dd8 MK |
968 | char *name; |
969 | ||
970 | find_pc_partial_function (pc, &name, NULL, NULL); | |
971 | if (PC_IN_SIGTRAMP (pc, name)) | |
1c3545ae MK |
972 | { |
973 | gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr); | |
974 | ||
e53bef9f | 975 | return &amd64_sigtramp_frame_unwind; |
1c3545ae | 976 | } |
c4f35dd8 MK |
977 | |
978 | return NULL; | |
979 | } | |
980 | \f | |
981 | ||
982 | static CORE_ADDR | |
e53bef9f | 983 | amd64_frame_base_address (struct frame_info *next_frame, void **this_cache) |
c4f35dd8 | 984 | { |
e53bef9f MK |
985 | struct amd64_frame_cache *cache = |
986 | amd64_frame_cache (next_frame, this_cache); | |
c4f35dd8 MK |
987 | |
988 | return cache->base; | |
989 | } | |
990 | ||
e53bef9f | 991 | static const struct frame_base amd64_frame_base = |
c4f35dd8 | 992 | { |
e53bef9f MK |
993 | &amd64_frame_unwind, |
994 | amd64_frame_base_address, | |
995 | amd64_frame_base_address, | |
996 | amd64_frame_base_address | |
c4f35dd8 MK |
997 | }; |
998 | ||
166f4c7b | 999 | static struct frame_id |
e53bef9f | 1000 | amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
166f4c7b | 1001 | { |
c4f35dd8 MK |
1002 | char buf[8]; |
1003 | CORE_ADDR fp; | |
1004 | ||
90f90721 | 1005 | frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); |
c4f35dd8 MK |
1006 | fp = extract_unsigned_integer (buf, 8); |
1007 | ||
1008 | return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); | |
166f4c7b ML |
1009 | } |
1010 | ||
8b148df9 AC |
1011 | /* 16 byte align the SP per frame requirements. */ |
1012 | ||
1013 | static CORE_ADDR | |
e53bef9f | 1014 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
8b148df9 AC |
1015 | { |
1016 | return sp & -(CORE_ADDR)16; | |
1017 | } | |
473f17b0 MK |
1018 | \f |
1019 | ||
1020 | /* Supply register REGNUM from the floating-point register set REGSET | |
1021 | to register cache REGCACHE. If REGNUM is -1, do this for all | |
1022 | registers in REGSET. */ | |
1023 | ||
1024 | static void | |
e53bef9f MK |
1025 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
1026 | int regnum, const void *fpregs, size_t len) | |
473f17b0 MK |
1027 | { |
1028 | const struct gdbarch_tdep *tdep = regset->descr; | |
1029 | ||
1030 | gdb_assert (len == tdep->sizeof_fpregset); | |
90f90721 | 1031 | amd64_supply_fxsave (regcache, regnum, fpregs); |
473f17b0 | 1032 | } |
8b148df9 | 1033 | |
c6b33596 MK |
1034 | /* Return the appropriate register set for the core section identified |
1035 | by SECT_NAME and SECT_SIZE. */ | |
1036 | ||
1037 | static const struct regset * | |
e53bef9f MK |
1038 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
1039 | const char *sect_name, size_t sect_size) | |
c6b33596 MK |
1040 | { |
1041 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1042 | ||
1043 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
1044 | { | |
1045 | if (tdep->fpregset == NULL) | |
1046 | { | |
1047 | tdep->fpregset = XMALLOC (struct regset); | |
1048 | tdep->fpregset->descr = tdep; | |
e53bef9f | 1049 | tdep->fpregset->supply_regset = amd64_supply_fpregset; |
c6b33596 MK |
1050 | } |
1051 | ||
1052 | return tdep->fpregset; | |
1053 | } | |
1054 | ||
1055 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); | |
1056 | } | |
1057 | \f | |
1058 | ||
2213a65d | 1059 | void |
90f90721 | 1060 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 1061 | { |
0c1a73d6 | 1062 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53e95fcf | 1063 | |
473f17b0 MK |
1064 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
1065 | floating-point registers. */ | |
1066 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
1067 | ||
5716833c | 1068 | /* AMD64 has an FPU and 16 SSE registers. */ |
90f90721 | 1069 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
0c1a73d6 | 1070 | tdep->num_xmm_regs = 16; |
53e95fcf | 1071 | |
0c1a73d6 | 1072 | /* This is what all the fuss is about. */ |
53e95fcf JS |
1073 | set_gdbarch_long_bit (gdbarch, 64); |
1074 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1075 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1076 | ||
e53bef9f MK |
1077 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
1078 | up 128 bits, even though it's still based on the i387 extended | |
1079 | floating-point format which has only 80 significant bits. */ | |
b83b026c MK |
1080 | set_gdbarch_long_double_bit (gdbarch, 128); |
1081 | ||
e53bef9f MK |
1082 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
1083 | set_gdbarch_register_name (gdbarch, amd64_register_name); | |
1084 | set_gdbarch_register_type (gdbarch, amd64_register_type); | |
b83b026c MK |
1085 | |
1086 | /* Register numbers of various important registers. */ | |
90f90721 MK |
1087 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
1088 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ | |
1089 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ | |
1090 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ | |
b83b026c | 1091 | |
e53bef9f MK |
1092 | /* The "default" register numbering scheme for AMD64 is referred to |
1093 | as the "DWARF Register Number Mapping" in the System V psABI. | |
1094 | The preferred debugging format for all known AMD64 targets is | |
1095 | actually DWARF2, and GCC doesn't seem to support DWARF (that is | |
1096 | DWARF-1), but we provide the same mapping just in case. This | |
1097 | mapping is also used for stabs, which GCC does support. */ | |
1098 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
1099 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
1100 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); | |
de220d0f | 1101 | |
c4f35dd8 | 1102 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
e53bef9f | 1103 | be in use on any of the supported AMD64 targets. */ |
53e95fcf | 1104 | |
c4f35dd8 | 1105 | /* Call dummy code. */ |
e53bef9f MK |
1106 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
1107 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); | |
8b148df9 | 1108 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
53e95fcf | 1109 | |
e53bef9f | 1110 | set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p); |
d532c08f MK |
1111 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
1112 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
1113 | ||
efb1c01c | 1114 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
53e95fcf | 1115 | |
e53bef9f | 1116 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
53e95fcf | 1117 | |
c4f35dd8 | 1118 | /* Avoid wiring in the MMX registers for now. */ |
2213a65d | 1119 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
5716833c | 1120 | tdep->mm0_regnum = -1; |
2213a65d | 1121 | |
e53bef9f | 1122 | set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id); |
53e95fcf | 1123 | |
b83b026c | 1124 | /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now, |
e53bef9f | 1125 | since all supported AMD64 targets are ELF, but that might change |
b83b026c | 1126 | in the future. */ |
8a8ab2b9 | 1127 | set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); |
c4f35dd8 | 1128 | |
e53bef9f MK |
1129 | frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer); |
1130 | frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer); | |
1131 | frame_base_set_default (gdbarch, &amd64_frame_base); | |
c6b33596 MK |
1132 | |
1133 | /* If we have a register mapping, enable the generic core file support. */ | |
1134 | if (tdep->gregset_reg_offset) | |
1135 | set_gdbarch_regset_from_core_section (gdbarch, | |
e53bef9f | 1136 | amd64_regset_from_core_section); |
c4f35dd8 MK |
1137 | } |
1138 | \f | |
1139 | ||
90f90721 | 1140 | #define I387_ST0_REGNUM AMD64_ST0_REGNUM |
c4f35dd8 | 1141 | |
41d041d6 MK |
1142 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
1143 | sense that the instruction pointer and data pointer are simply | |
1144 | 64-bit offsets into the code segment and the data segment instead | |
1145 | of a selector offset pair. The functions below store the upper 32 | |
1146 | bits of these pointers (instead of just the 16-bits of the segment | |
1147 | selector). */ | |
1148 | ||
1149 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
1150 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
1151 | -1, do this for all registers. This function masks off any of the | |
1152 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
1153 | |
1154 | void | |
90f90721 | 1155 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
41d041d6 | 1156 | const void *fxsave) |
c4f35dd8 | 1157 | { |
41d041d6 | 1158 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 MK |
1159 | |
1160 | if (fxsave) | |
1161 | { | |
41d041d6 MK |
1162 | const char *regs = fxsave; |
1163 | ||
0485f6ad | 1164 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) |
41d041d6 | 1165 | regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); |
0485f6ad | 1166 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) |
41d041d6 | 1167 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); |
c4f35dd8 | 1168 | } |
0c1a73d6 MK |
1169 | } |
1170 | ||
3c017e40 MK |
1171 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
1172 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
1173 | all registers. This function doesn't touch any of the reserved | |
1174 | bits in *FXSAVE. */ | |
1175 | ||
1176 | void | |
1177 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
1178 | void *fxsave) | |
1179 | { | |
1180 | char *regs = fxsave; | |
1181 | ||
1182 | i387_collect_fxsave (regcache, regnum, fxsave); | |
1183 | ||
1184 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) | |
1185 | regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12); | |
1186 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) | |
1187 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20); | |
1188 | } |