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90f90721 | 1 | /* Target-dependent definitions for AMD64. |
c4f35dd8 | 2 | |
b811d2c2 | 3 | Copyright (C) 2001-2020 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf | 20 | |
9c1488cb MK |
21 | #ifndef AMD64_TDEP_H |
22 | #define AMD64_TDEP_H | |
53e95fcf | 23 | |
da3331ec AC |
24 | struct gdbarch; |
25 | struct frame_info; | |
221c12ff | 26 | struct regcache; |
da3331ec | 27 | |
53e95fcf | 28 | #include "i386-tdep.h" |
53e95fcf | 29 | |
402ecd56 MK |
30 | /* Register numbers of various important registers. */ |
31 | ||
90f90721 MK |
32 | enum amd64_regnum |
33 | { | |
34 | AMD64_RAX_REGNUM, /* %rax */ | |
35 | AMD64_RBX_REGNUM, /* %rbx */ | |
36 | AMD64_RCX_REGNUM, /* %rcx */ | |
37 | AMD64_RDX_REGNUM, /* %rdx */ | |
38 | AMD64_RSI_REGNUM, /* %rsi */ | |
39 | AMD64_RDI_REGNUM, /* %rdi */ | |
40 | AMD64_RBP_REGNUM, /* %rbp */ | |
41 | AMD64_RSP_REGNUM, /* %rsp */ | |
e0c62198 L |
42 | AMD64_R8_REGNUM, /* %r8 */ |
43 | AMD64_R9_REGNUM, /* %r9 */ | |
44 | AMD64_R10_REGNUM, /* %r10 */ | |
45 | AMD64_R11_REGNUM, /* %r11 */ | |
46 | AMD64_R12_REGNUM, /* %r12 */ | |
47 | AMD64_R13_REGNUM, /* %r13 */ | |
48 | AMD64_R14_REGNUM, /* %r14 */ | |
49 | AMD64_R15_REGNUM, /* %r15 */ | |
90f90721 MK |
50 | AMD64_RIP_REGNUM, /* %rip */ |
51 | AMD64_EFLAGS_REGNUM, /* %eflags */ | |
296bc76f MK |
52 | AMD64_CS_REGNUM, /* %cs */ |
53 | AMD64_SS_REGNUM, /* %ss */ | |
54 | AMD64_DS_REGNUM, /* %ds */ | |
55 | AMD64_ES_REGNUM, /* %es */ | |
56 | AMD64_FS_REGNUM, /* %fs */ | |
57 | AMD64_GS_REGNUM, /* %gs */ | |
90f90721 | 58 | AMD64_ST0_REGNUM = 24, /* %st0 */ |
7f7930dd | 59 | AMD64_ST1_REGNUM, /* %st1 */ |
c6f4c129 JB |
60 | AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8, |
61 | AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9, | |
7f7930dd | 62 | AMD64_FTAG_REGNUM = AMD64_ST0_REGNUM + 10, |
90f90721 | 63 | AMD64_XMM0_REGNUM = 40, /* %xmm0 */ |
c6f4c129 | 64 | AMD64_XMM1_REGNUM, /* %xmm1 */ |
a055a187 L |
65 | AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16, |
66 | AMD64_YMM0H_REGNUM, /* %ymm0h */ | |
e43e105e WT |
67 | AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15, |
68 | AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1, | |
69 | AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3, | |
70 | AMD64_BNDCFGU_REGNUM, | |
01f9f808 MS |
71 | AMD64_BNDSTATUS_REGNUM, |
72 | AMD64_XMM16_REGNUM, | |
73 | AMD64_XMM31_REGNUM = AMD64_XMM16_REGNUM + 15, | |
74 | AMD64_YMM16H_REGNUM, | |
75 | AMD64_YMM31H_REGNUM = AMD64_YMM16H_REGNUM + 15, | |
76 | AMD64_K0_REGNUM, | |
77 | AMD64_K7_REGNUM = AMD64_K0_REGNUM + 7, | |
78 | AMD64_ZMM0H_REGNUM, | |
2735833d | 79 | AMD64_ZMM31H_REGNUM = AMD64_ZMM0H_REGNUM + 31, |
51547df6 | 80 | AMD64_PKRU_REGNUM, |
2735833d WT |
81 | AMD64_FSBASE_REGNUM, |
82 | AMD64_GSBASE_REGNUM | |
90f90721 | 83 | }; |
402ecd56 | 84 | |
c4f35dd8 | 85 | /* Number of general purpose registers. */ |
90f90721 | 86 | #define AMD64_NUM_GREGS 24 |
c4f35dd8 | 87 | |
2735833d | 88 | #define AMD64_NUM_REGS (AMD64_GSBASE_REGNUM + 1) |
a055a187 | 89 | |
35669430 DE |
90 | extern struct displaced_step_closure *amd64_displaced_step_copy_insn |
91 | (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, | |
92 | struct regcache *regs); | |
93 | extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch, | |
94 | struct displaced_step_closure *closure, | |
95 | CORE_ADDR from, CORE_ADDR to, | |
96 | struct regcache *regs); | |
97 | ||
c55a47e7 PA |
98 | /* Initialize the ABI for amd64. Uses DEFAULT_TDESC as fallback |
99 | tdesc, if INFO does not specify one. */ | |
100 | extern void amd64_init_abi (struct gdbarch_info info, | |
101 | struct gdbarch *gdbarch, | |
a04b5337 | 102 | const target_desc *default_tdesc); |
c55a47e7 PA |
103 | |
104 | /* Initialize the ABI for x32. Uses DEFAULT_TDESC as fallback tdesc, | |
105 | if INFO does not specify one. */ | |
fff4548b | 106 | extern void amd64_x32_init_abi (struct gdbarch_info info, |
c55a47e7 | 107 | struct gdbarch *gdbarch, |
a04b5337 | 108 | const target_desc *default_tdesc); |
de52b960 PA |
109 | extern const struct target_desc *amd64_target_description (uint64_t xcr0, |
110 | bool segments); | |
53e95fcf | 111 | |
41d041d6 | 112 | /* Fill register REGNUM in REGCACHE with the appropriate |
0485f6ad MK |
113 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
114 | -1, do this for all registers. This function masks off any of the | |
115 | reserved bits in *FXSAVE. */ | |
b64bbf8c | 116 | |
90f90721 MK |
117 | extern void amd64_supply_fxsave (struct regcache *regcache, int regnum, |
118 | const void *fxsave); | |
baed091b | 119 | |
a055a187 L |
120 | /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ |
121 | extern void amd64_supply_xsave (struct regcache *regcache, int regnum, | |
122 | const void *xsave); | |
123 | ||
3c017e40 MK |
124 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
125 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for | |
126 | all registers. This function doesn't touch any of the reserved | |
127 | bits in *FXSAVE. */ | |
128 | ||
129 | extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum, | |
130 | void *fxsave); | |
7a9dd1b2 | 131 | /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ |
a055a187 L |
132 | extern void amd64_collect_xsave (const struct regcache *regcache, |
133 | int regnum, void *xsave, int gcore); | |
b246147c | 134 | \f |
8f0435f7 AA |
135 | /* Floating-point register set. */ |
136 | extern const struct regset amd64_fpregset; | |
b246147c | 137 | |
6cd6a2ae L |
138 | /* Variables exported from amd64-linux-tdep.c. */ |
139 | extern int amd64_linux_gregset_reg_offset[]; | |
140 | ||
03b62bbb | 141 | /* Variables exported from amd64-nbsd-tdep.c. */ |
cced5e27 MK |
142 | extern int amd64nbsd_r_reg_offset[]; |
143 | ||
03b62bbb | 144 | /* Variables exported from amd64-obsd-tdep.c. */ |
971218cd MK |
145 | extern int amd64obsd_r_reg_offset[]; |
146 | ||
03b62bbb | 147 | /* Variables exported from amd64-fbsd-tdep.c. */ |
10fc94a4 MK |
148 | extern CORE_ADDR amd64fbsd_sigtramp_start_addr; |
149 | extern CORE_ADDR amd64fbsd_sigtramp_end_addr; | |
b246147c | 150 | extern int amd64fbsd_sc_reg_offset[]; |
53e95fcf | 151 | |
9c1488cb | 152 | #endif /* amd64-tdep.h */ |