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85102364 | 1 | /* Target dependent code for ARC architecture, for GDB. |
ad0a504f | 2 | |
b811d2c2 | 3 | Copyright 2005-2020 Free Software Foundation, Inc. |
ad0a504f AK |
4 | Contributed by Synopsys Inc. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* GDB header files. */ | |
22 | #include "defs.h" | |
23 | #include "arch-utils.h" | |
24 | #include "disasm.h" | |
82ca8957 | 25 | #include "dwarf2/frame.h" |
ad0a504f AK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
d55e5aa6 | 28 | #include "gdbcore.h" |
4de283e4 | 29 | #include "gdbcmd.h" |
ad0a504f | 30 | #include "objfiles.h" |
817a7585 | 31 | #include "osabi.h" |
fe5f7374 | 32 | #include "prologue-value.h" |
817a7585 | 33 | #include "target-descriptions.h" |
ad0a504f AK |
34 | #include "trad-frame.h" |
35 | ||
36 | /* ARC header files. */ | |
37 | #include "opcode/arc.h" | |
f16f7b7c | 38 | #include "opcodes/arc-dis.h" |
ad0a504f | 39 | #include "arc-tdep.h" |
817a7585 | 40 | #include "arch/arc.h" |
ad0a504f AK |
41 | |
42 | /* Standard headers. */ | |
43 | #include <algorithm> | |
44 | ||
fe5f7374 | 45 | /* The frame unwind cache for ARC. */ |
ad0a504f AK |
46 | |
47 | struct arc_frame_cache | |
48 | { | |
49 | /* The stack pointer at the time this frame was created; i.e. the caller's | |
50 | stack pointer when this function was called. It is used to identify this | |
51 | frame. */ | |
52 | CORE_ADDR prev_sp; | |
53 | ||
fe5f7374 AK |
54 | /* Register that is a base for this frame - FP for normal frame, SP for |
55 | non-FP frames. */ | |
56 | int frame_base_reg; | |
57 | ||
58 | /* Offset from the previous SP to the current frame base. If GCC uses | |
59 | `SUB SP,SP,offset` to allocate space for local variables, then it will be | |
60 | done after setting up a frame pointer, but it still will be considered | |
61 | part of prologue, therefore SP will be lesser than FP at the end of the | |
62 | prologue analysis. In this case that would be an offset from old SP to a | |
63 | new FP. But in case of non-FP frames, frame base is an SP and thus that | |
64 | would be an offset from old SP to new SP. What is important is that this | |
65 | is an offset from old SP to a known register, so it can be used to find | |
66 | old SP. | |
67 | ||
68 | Using FP is preferable, when possible, because SP can change in function | |
69 | body after prologue due to alloca, variadic arguments or other shenanigans. | |
70 | If that is the case in the caller frame, then PREV_SP will point to SP at | |
71 | the moment of function call, but it will be different from SP value at the | |
72 | end of the caller prologue. As a result it will not be possible to | |
73 | reconstruct caller's frame and go past it in the backtrace. Those things | |
74 | are unlikely to happen to FP - FP value at the moment of function call (as | |
75 | stored on stack in callee prologue) is also an FP value at the end of the | |
76 | caller's prologue. */ | |
77 | ||
78 | LONGEST frame_base_offset; | |
79 | ||
80 | /* Store addresses for registers saved in prologue. During prologue analysis | |
81 | GDB stores offsets relatively to "old SP", then after old SP is evaluated, | |
82 | offsets are replaced with absolute addresses. */ | |
ad0a504f AK |
83 | struct trad_frame_saved_reg *saved_regs; |
84 | }; | |
85 | ||
86 | /* Global debug flag. */ | |
87 | ||
88 | int arc_debug; | |
89 | ||
3be78afd AK |
90 | /* List of "maintenance print arc" commands. */ |
91 | ||
92 | static struct cmd_list_element *maintenance_print_arc_list = NULL; | |
93 | ||
ad0a504f AK |
94 | /* XML target description features. */ |
95 | ||
96 | static const char core_v2_feature_name[] = "org.gnu.gdb.arc.core.v2"; | |
97 | static const char | |
98 | core_reduced_v2_feature_name[] = "org.gnu.gdb.arc.core-reduced.v2"; | |
99 | static const char | |
100 | core_arcompact_feature_name[] = "org.gnu.gdb.arc.core.arcompact"; | |
101 | static const char aux_minimal_feature_name[] = "org.gnu.gdb.arc.aux-minimal"; | |
102 | ||
103 | /* XML target description known registers. */ | |
104 | ||
105 | static const char *const core_v2_register_names[] = { | |
106 | "r0", "r1", "r2", "r3", | |
107 | "r4", "r5", "r6", "r7", | |
108 | "r8", "r9", "r10", "r11", | |
109 | "r12", "r13", "r14", "r15", | |
110 | "r16", "r17", "r18", "r19", | |
111 | "r20", "r21", "r22", "r23", | |
112 | "r24", "r25", "gp", "fp", | |
113 | "sp", "ilink", "r30", "blink", | |
114 | "r32", "r33", "r34", "r35", | |
115 | "r36", "r37", "r38", "r39", | |
116 | "r40", "r41", "r42", "r43", | |
117 | "r44", "r45", "r46", "r47", | |
118 | "r48", "r49", "r50", "r51", | |
119 | "r52", "r53", "r54", "r55", | |
120 | "r56", "r57", "accl", "acch", | |
296ec4fa | 121 | "lp_count", "reserved", "limm", "pcl", |
ad0a504f AK |
122 | }; |
123 | ||
124 | static const char *const aux_minimal_register_names[] = { | |
125 | "pc", "status32", | |
126 | }; | |
127 | ||
128 | static const char *const core_arcompact_register_names[] = { | |
129 | "r0", "r1", "r2", "r3", | |
130 | "r4", "r5", "r6", "r7", | |
131 | "r8", "r9", "r10", "r11", | |
132 | "r12", "r13", "r14", "r15", | |
133 | "r16", "r17", "r18", "r19", | |
134 | "r20", "r21", "r22", "r23", | |
135 | "r24", "r25", "gp", "fp", | |
136 | "sp", "ilink1", "ilink2", "blink", | |
137 | "r32", "r33", "r34", "r35", | |
138 | "r36", "r37", "r38", "r39", | |
139 | "r40", "r41", "r42", "r43", | |
140 | "r44", "r45", "r46", "r47", | |
141 | "r48", "r49", "r50", "r51", | |
142 | "r52", "r53", "r54", "r55", | |
143 | "r56", "r57", "r58", "r59", | |
296ec4fa | 144 | "lp_count", "reserved", "limm", "pcl", |
ad0a504f AK |
145 | }; |
146 | ||
a87dc45a AK |
147 | static char *arc_disassembler_options = NULL; |
148 | ||
817a7585 AK |
149 | /* Possible arc target descriptors. */ |
150 | static struct target_desc *tdesc_arc_list[ARC_SYS_TYPE_NUM]; | |
151 | ||
fe5f7374 AK |
152 | /* Functions are sorted in the order as they are used in the |
153 | _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static | |
154 | functions are defined before the first invocation. */ | |
155 | ||
eea78757 AK |
156 | /* Returns an unsigned value of OPERAND_NUM in instruction INSN. |
157 | For relative branch instructions returned value is an offset, not an actual | |
158 | branch target. */ | |
159 | ||
160 | static ULONGEST | |
161 | arc_insn_get_operand_value (const struct arc_instruction &insn, | |
162 | unsigned int operand_num) | |
163 | { | |
164 | switch (insn.operands[operand_num].kind) | |
165 | { | |
166 | case ARC_OPERAND_KIND_LIMM: | |
167 | gdb_assert (insn.limm_p); | |
168 | return insn.limm_value; | |
169 | case ARC_OPERAND_KIND_SHIMM: | |
170 | return insn.operands[operand_num].value; | |
171 | default: | |
172 | /* Value in instruction is a register number. */ | |
173 | struct regcache *regcache = get_current_regcache (); | |
174 | ULONGEST value; | |
175 | regcache_cooked_read_unsigned (regcache, | |
176 | insn.operands[operand_num].value, | |
177 | &value); | |
178 | return value; | |
179 | } | |
180 | } | |
181 | ||
182 | /* Like arc_insn_get_operand_value, but returns a signed value. */ | |
183 | ||
184 | static LONGEST | |
185 | arc_insn_get_operand_value_signed (const struct arc_instruction &insn, | |
186 | unsigned int operand_num) | |
187 | { | |
188 | switch (insn.operands[operand_num].kind) | |
189 | { | |
190 | case ARC_OPERAND_KIND_LIMM: | |
191 | gdb_assert (insn.limm_p); | |
192 | /* Convert unsigned raw value to signed one. This assumes 2's | |
193 | complement arithmetic, but so is the LONG_MIN value from generic | |
194 | defs.h and that assumption is true for ARC. */ | |
195 | gdb_static_assert (sizeof (insn.limm_value) == sizeof (int)); | |
196 | return (((LONGEST) insn.limm_value) ^ INT_MIN) - INT_MIN; | |
197 | case ARC_OPERAND_KIND_SHIMM: | |
198 | /* Sign conversion has been done by binutils. */ | |
199 | return insn.operands[operand_num].value; | |
200 | default: | |
201 | /* Value in instruction is a register number. */ | |
202 | struct regcache *regcache = get_current_regcache (); | |
203 | LONGEST value; | |
204 | regcache_cooked_read_signed (regcache, | |
205 | insn.operands[operand_num].value, | |
206 | &value); | |
207 | return value; | |
208 | } | |
209 | } | |
210 | ||
211 | /* Get register with base address of memory operation. */ | |
212 | ||
cb8c24b6 | 213 | static int |
eea78757 AK |
214 | arc_insn_get_memory_base_reg (const struct arc_instruction &insn) |
215 | { | |
216 | /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */ | |
217 | if (insn.insn_class == PUSH || insn.insn_class == POP) | |
218 | return ARC_SP_REGNUM; | |
219 | ||
220 | gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); | |
221 | ||
222 | /* Other instructions all have at least two operands: operand 0 is data, | |
223 | operand 1 is address. Operand 2 is offset from address. However, see | |
224 | comment to arc_instruction.operands - in some cases, third operand may be | |
225 | missing, namely if it is 0. */ | |
226 | gdb_assert (insn.operands_count >= 2); | |
227 | return insn.operands[1].value; | |
228 | } | |
229 | ||
230 | /* Get offset of a memory operation INSN. */ | |
231 | ||
cb8c24b6 | 232 | static CORE_ADDR |
eea78757 AK |
233 | arc_insn_get_memory_offset (const struct arc_instruction &insn) |
234 | { | |
235 | /* POP_S and PUSH_S have offset as an implicit argument in a | |
236 | disassembler. */ | |
237 | if (insn.insn_class == POP) | |
238 | return 4; | |
239 | else if (insn.insn_class == PUSH) | |
240 | return -4; | |
241 | ||
242 | gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); | |
243 | ||
244 | /* Other instructions all have at least two operands: operand 0 is data, | |
245 | operand 1 is address. Operand 2 is offset from address. However, see | |
246 | comment to arc_instruction.operands - in some cases, third operand may be | |
247 | missing, namely if it is 0. */ | |
248 | if (insn.operands_count < 3) | |
249 | return 0; | |
250 | ||
251 | CORE_ADDR value = arc_insn_get_operand_value (insn, 2); | |
252 | /* Handle scaling. */ | |
253 | if (insn.writeback_mode == ARC_WRITEBACK_AS) | |
254 | { | |
255 | /* Byte data size is not valid for AS. Halfword means shift by 1 bit. | |
256 | Word and double word means shift by 2 bits. */ | |
257 | gdb_assert (insn.data_size_mode != ARC_SCALING_B); | |
258 | if (insn.data_size_mode == ARC_SCALING_H) | |
259 | value <<= 1; | |
260 | else | |
261 | value <<= 2; | |
262 | } | |
263 | return value; | |
264 | } | |
265 | ||
eea78757 AK |
266 | CORE_ADDR |
267 | arc_insn_get_branch_target (const struct arc_instruction &insn) | |
268 | { | |
269 | gdb_assert (insn.is_control_flow); | |
270 | ||
271 | /* BI [c]: PC = nextPC + (c << 2). */ | |
272 | if (insn.insn_class == BI) | |
273 | { | |
274 | ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); | |
275 | return arc_insn_get_linear_next_pc (insn) + (reg_value << 2); | |
276 | } | |
277 | /* BIH [c]: PC = nextPC + (c << 1). */ | |
278 | else if (insn.insn_class == BIH) | |
279 | { | |
280 | ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); | |
281 | return arc_insn_get_linear_next_pc (insn) + (reg_value << 1); | |
282 | } | |
283 | /* JLI and EI. */ | |
284 | /* JLI and EI depend on optional AUX registers. Not supported right now. */ | |
285 | else if (insn.insn_class == JLI) | |
286 | { | |
287 | fprintf_unfiltered (gdb_stderr, | |
288 | "JLI_S instruction is not supported by the GDB."); | |
289 | return 0; | |
290 | } | |
291 | else if (insn.insn_class == EI) | |
292 | { | |
293 | fprintf_unfiltered (gdb_stderr, | |
294 | "EI_S instruction is not supported by the GDB."); | |
295 | return 0; | |
296 | } | |
297 | /* LEAVE_S: PC = BLINK. */ | |
298 | else if (insn.insn_class == LEAVE) | |
299 | { | |
300 | struct regcache *regcache = get_current_regcache (); | |
301 | ULONGEST value; | |
302 | regcache_cooked_read_unsigned (regcache, ARC_BLINK_REGNUM, &value); | |
303 | return value; | |
304 | } | |
305 | /* BBIT0/1, BRcc: PC = currentPC + operand. */ | |
306 | else if (insn.insn_class == BBIT0 || insn.insn_class == BBIT1 | |
307 | || insn.insn_class == BRCC) | |
308 | { | |
309 | /* Most instructions has branch target as their sole argument. However | |
310 | conditional brcc/bbit has it as a third operand. */ | |
311 | CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 2); | |
312 | ||
313 | /* Offset is relative to the 4-byte aligned address of the current | |
314 | instruction, hence last two bits should be truncated. */ | |
315 | return pcrel_addr + align_down (insn.address, 4); | |
316 | } | |
317 | /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */ | |
318 | else if (insn.insn_class == BRANCH || insn.insn_class == LOOP) | |
319 | { | |
320 | CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 0); | |
321 | ||
322 | /* Offset is relative to the 4-byte aligned address of the current | |
323 | instruction, hence last two bits should be truncated. */ | |
324 | return pcrel_addr + align_down (insn.address, 4); | |
325 | } | |
326 | /* J, Jcc, JL, JLcc: PC = operand. */ | |
327 | else if (insn.insn_class == JUMP) | |
328 | { | |
329 | /* All jumps are single-operand. */ | |
330 | return arc_insn_get_operand_value (insn, 0); | |
331 | } | |
332 | ||
333 | /* This is some new and unknown instruction. */ | |
334 | gdb_assert_not_reached ("Unknown branch instruction."); | |
335 | } | |
336 | ||
337 | /* Dump INSN into gdb_stdlog. */ | |
338 | ||
cb8c24b6 | 339 | static void |
eea78757 AK |
340 | arc_insn_dump (const struct arc_instruction &insn) |
341 | { | |
342 | struct gdbarch *gdbarch = target_gdbarch (); | |
343 | ||
344 | arc_print ("Dumping arc_instruction at %s\n", | |
345 | paddress (gdbarch, insn.address)); | |
346 | arc_print ("\tlength = %u\n", insn.length); | |
347 | ||
348 | if (!insn.valid) | |
349 | { | |
350 | arc_print ("\tThis is not a valid ARC instruction.\n"); | |
351 | return; | |
352 | } | |
353 | ||
354 | arc_print ("\tlength_with_limm = %u\n", insn.length + (insn.limm_p ? 4 : 0)); | |
355 | arc_print ("\tcc = 0x%x\n", insn.condition_code); | |
356 | arc_print ("\tinsn_class = %u\n", insn.insn_class); | |
357 | arc_print ("\tis_control_flow = %i\n", insn.is_control_flow); | |
358 | arc_print ("\thas_delay_slot = %i\n", insn.has_delay_slot); | |
359 | ||
360 | CORE_ADDR next_pc = arc_insn_get_linear_next_pc (insn); | |
361 | arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch, next_pc)); | |
362 | ||
363 | if (insn.is_control_flow) | |
364 | { | |
365 | CORE_ADDR t = arc_insn_get_branch_target (insn); | |
366 | arc_print ("\tbranch_target = %s\n", paddress (gdbarch, t)); | |
367 | } | |
368 | ||
369 | arc_print ("\tlimm_p = %i\n", insn.limm_p); | |
370 | if (insn.limm_p) | |
371 | arc_print ("\tlimm_value = 0x%08x\n", insn.limm_value); | |
372 | ||
373 | if (insn.insn_class == STORE || insn.insn_class == LOAD | |
374 | || insn.insn_class == PUSH || insn.insn_class == POP) | |
375 | { | |
376 | arc_print ("\twriteback_mode = %u\n", insn.writeback_mode); | |
377 | arc_print ("\tdata_size_mode = %u\n", insn.data_size_mode); | |
378 | arc_print ("\tmemory_base_register = %s\n", | |
379 | gdbarch_register_name (gdbarch, | |
380 | arc_insn_get_memory_base_reg (insn))); | |
381 | /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a | |
382 | LONGEST for a nicer representation. */ | |
383 | arc_print ("\taddr_offset = %s\n", | |
384 | plongest (arc_insn_get_memory_offset (insn))); | |
385 | } | |
386 | ||
387 | arc_print ("\toperands_count = %u\n", insn.operands_count); | |
388 | for (unsigned int i = 0; i < insn.operands_count; ++i) | |
389 | { | |
390 | int is_reg = (insn.operands[i].kind == ARC_OPERAND_KIND_REG); | |
391 | ||
392 | arc_print ("\toperand[%u] = {\n", i); | |
393 | arc_print ("\t\tis_reg = %i\n", is_reg); | |
394 | if (is_reg) | |
395 | arc_print ("\t\tregister = %s\n", | |
396 | gdbarch_register_name (gdbarch, insn.operands[i].value)); | |
397 | /* Don't know if this value is signed or not, so print both | |
398 | representations. This tends to look quite ugly, especially for big | |
399 | numbers. */ | |
400 | arc_print ("\t\tunsigned value = %s\n", | |
401 | pulongest (arc_insn_get_operand_value (insn, i))); | |
402 | arc_print ("\t\tsigned value = %s\n", | |
403 | plongest (arc_insn_get_operand_value_signed (insn, i))); | |
404 | arc_print ("\t}\n"); | |
405 | } | |
406 | } | |
407 | ||
408 | CORE_ADDR | |
409 | arc_insn_get_linear_next_pc (const struct arc_instruction &insn) | |
410 | { | |
411 | /* In ARC long immediate is always 4 bytes. */ | |
412 | return (insn.address + insn.length + (insn.limm_p ? 4 : 0)); | |
413 | } | |
414 | ||
ad0a504f AK |
415 | /* Implement the "write_pc" gdbarch method. |
416 | ||
417 | In ARC PC register is a normal register so in most cases setting PC value | |
418 | is a straightforward process: debugger just writes PC value. However it | |
419 | gets trickier in case when current instruction is an instruction in delay | |
420 | slot. In this case CPU will execute instruction at current PC value, then | |
421 | will set PC to the current value of BTA register; also current instruction | |
422 | cannot be branch/jump and some of the other instruction types. Thus if | |
423 | debugger would try to just change PC value in this case, this instruction | |
424 | will get executed, but then core will "jump" to the original branch target. | |
425 | ||
426 | Whether current instruction is a delay-slot instruction or not is indicated | |
427 | by DE bit in STATUS32 register indicates if current instruction is a delay | |
428 | slot instruction. This bit is writable by debug host, which allows debug | |
429 | host to prevent core from jumping after the delay slot instruction. It | |
430 | also works in another direction: setting this bit will make core to treat | |
431 | any current instructions as a delay slot instruction and to set PC to the | |
432 | current value of BTA register. | |
433 | ||
434 | To workaround issues with changing PC register while in delay slot | |
435 | instruction, debugger should check for the STATUS32.DE bit and reset it if | |
436 | it is set. No other change is required in this function. Most common | |
437 | case, where this function might be required is calling inferior functions | |
438 | from debugger. Generic GDB logic handles this pretty well: current values | |
439 | of registers are stored, value of PC is changed (that is the job of this | |
440 | function), and after inferior function is executed, GDB restores all | |
441 | registers, include BTA and STATUS32, which also means that core is returned | |
442 | to its original state of being halted on delay slot instructions. | |
443 | ||
444 | This method is useless for ARC 600, because it doesn't have externally | |
445 | exposed BTA register. In the case of ARC 600 it is impossible to restore | |
446 | core to its state in all occasions thus core should never be halted (from | |
447 | the perspective of debugger host) in the delay slot. */ | |
448 | ||
449 | static void | |
450 | arc_write_pc (struct regcache *regcache, CORE_ADDR new_pc) | |
451 | { | |
ac7936df | 452 | struct gdbarch *gdbarch = regcache->arch (); |
ad0a504f AK |
453 | |
454 | if (arc_debug) | |
455 | debug_printf ("arc: Writing PC, new value=%s\n", | |
456 | paddress (gdbarch, new_pc)); | |
457 | ||
458 | regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), | |
459 | new_pc); | |
460 | ||
461 | ULONGEST status32; | |
462 | regcache_cooked_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), | |
463 | &status32); | |
464 | ||
465 | /* Mask for DE bit is 0x40. */ | |
466 | if (status32 & 0x40) | |
467 | { | |
468 | if (arc_debug) | |
469 | { | |
470 | debug_printf ("arc: Changing PC while in delay slot. Will " | |
471 | "reset STATUS32.DE bit to zero. Value of STATUS32 " | |
472 | "register is 0x%s\n", | |
473 | phex (status32, ARC_REGISTER_SIZE)); | |
474 | } | |
475 | ||
476 | /* Reset bit and write to the cache. */ | |
477 | status32 &= ~0x40; | |
478 | regcache_cooked_write_unsigned (regcache, gdbarch_ps_regnum (gdbarch), | |
479 | status32); | |
480 | } | |
481 | } | |
482 | ||
483 | /* Implement the "virtual_frame_pointer" gdbarch method. | |
484 | ||
485 | According to ABI the FP (r27) is used to point to the middle of the current | |
486 | stack frame, just below the saved FP and before local variables, register | |
487 | spill area and outgoing args. However for optimization levels above O2 and | |
488 | in any case in leaf functions, the frame pointer is usually not set at all. | |
489 | The exception being when handling nested functions. | |
490 | ||
491 | We use this function to return a "virtual" frame pointer, marking the start | |
492 | of the current stack frame as a register-offset pair. If the FP is not | |
493 | being used, then it should return SP, with an offset of the frame size. | |
494 | ||
495 | The current implementation doesn't actually know the frame size, nor | |
496 | whether the FP is actually being used, so for now we just return SP and an | |
497 | offset of zero. This is no worse than other architectures, but is needed | |
498 | to avoid assertion failures. | |
499 | ||
500 | TODO: Can we determine the frame size to get a correct offset? | |
501 | ||
502 | PC is a program counter where we need the virtual FP. REG_PTR is the base | |
503 | register used for the virtual FP. OFFSET_PTR is the offset used for the | |
504 | virtual FP. */ | |
505 | ||
506 | static void | |
507 | arc_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, | |
508 | int *reg_ptr, LONGEST *offset_ptr) | |
509 | { | |
510 | *reg_ptr = gdbarch_sp_regnum (gdbarch); | |
511 | *offset_ptr = 0; | |
512 | } | |
513 | ||
ad0a504f AK |
514 | /* Implement the "push_dummy_call" gdbarch method. |
515 | ||
516 | Stack Frame Layout | |
517 | ||
518 | This shows the layout of the stack frame for the general case of a | |
519 | function call; a given function might not have a variable number of | |
520 | arguments or local variables, or might not save any registers, so it would | |
521 | not have the corresponding frame areas. Additionally, a leaf function | |
522 | (i.e. one which calls no other functions) does not need to save the | |
523 | contents of the BLINK register (which holds its return address), and a | |
524 | function might not have a frame pointer. | |
525 | ||
526 | The stack grows downward, so SP points below FP in memory; SP always | |
527 | points to the last used word on the stack, not the first one. | |
528 | ||
529 | | | | | |
530 | | arg word N | | caller's | |
531 | | : | | frame | |
532 | | arg word 10 | | | |
533 | | arg word 9 | | | |
534 | old SP ---> +-----------------------+ --+ | |
535 | | | | | |
536 | | callee-saved | | | |
537 | | registers | | | |
538 | | including fp, blink | | | |
539 | | | | callee's | |
540 | new FP ---> +-----------------------+ | frame | |
541 | | | | | |
542 | | local | | | |
543 | | variables | | | |
544 | | | | | |
545 | | register | | | |
546 | | spill area | | | |
547 | | | | | |
548 | | outgoing args | | | |
549 | | | | | |
550 | new SP ---> +-----------------------+ --+ | |
551 | | | | |
552 | | unused | | |
553 | | | | |
554 | | | |
555 | | | |
556 | V | |
557 | downwards | |
558 | ||
559 | The list of arguments to be passed to a function is considered to be a | |
560 | sequence of _N_ words (as though all the parameters were stored in order in | |
561 | memory with each parameter occupying an integral number of words). Words | |
562 | 1..8 are passed in registers 0..7; if the function has more than 8 words of | |
563 | arguments then words 9..@em N are passed on the stack in the caller's frame. | |
564 | ||
565 | If the function has a variable number of arguments, e.g. it has a form such | |
566 | as `function (p1, p2, ...);' and _P_ words are required to hold the values | |
567 | of the named parameters (which are passed in registers 0..@em P -1), then | |
568 | the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the | |
569 | top of the frame so that the anonymous parameter words occupy a continuous | |
570 | region. | |
571 | ||
572 | Any arguments are already in target byte order. We just need to store | |
573 | them! | |
574 | ||
575 | BP_ADDR is the return address where breakpoint must be placed. NARGS is | |
576 | the number of arguments to the function. ARGS is the arguments values (in | |
577 | target byte order). SP is the Current value of SP register. STRUCT_RETURN | |
578 | is TRUE if structures are returned by the function. STRUCT_ADDR is the | |
579 | hidden address for returning a struct. Returns SP of a new frame. */ | |
580 | ||
581 | static CORE_ADDR | |
582 | arc_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
583 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
cf84fa6b AH |
584 | struct value **args, CORE_ADDR sp, |
585 | function_call_return_method return_method, | |
ad0a504f AK |
586 | CORE_ADDR struct_addr) |
587 | { | |
588 | if (arc_debug) | |
589 | debug_printf ("arc: push_dummy_call (nargs = %d)\n", nargs); | |
590 | ||
591 | int arg_reg = ARC_FIRST_ARG_REGNUM; | |
592 | ||
593 | /* Push the return address. */ | |
594 | regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, bp_addr); | |
595 | ||
596 | /* Are we returning a value using a structure return instead of a normal | |
597 | value return? If so, struct_addr is the address of the reserved space for | |
598 | the return structure to be written on the stack, and that address is | |
599 | passed to that function as a hidden first argument. */ | |
cf84fa6b | 600 | if (return_method == return_method_struct) |
ad0a504f AK |
601 | { |
602 | /* Pass the return address in the first argument register. */ | |
603 | regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); | |
604 | ||
605 | if (arc_debug) | |
606 | debug_printf ("arc: struct return address %s passed in R%d", | |
607 | print_core_address (gdbarch, struct_addr), arg_reg); | |
608 | ||
609 | arg_reg++; | |
610 | } | |
611 | ||
612 | if (nargs > 0) | |
613 | { | |
614 | unsigned int total_space = 0; | |
615 | ||
616 | /* How much space do the arguments occupy in total? Must round each | |
617 | argument's size up to an integral number of words. */ | |
618 | for (int i = 0; i < nargs; i++) | |
619 | { | |
620 | unsigned int len = TYPE_LENGTH (value_type (args[i])); | |
621 | unsigned int space = align_up (len, 4); | |
622 | ||
623 | total_space += space; | |
624 | ||
625 | if (arc_debug) | |
626 | debug_printf ("arc: arg %d: %u bytes -> %u\n", i, len, space); | |
627 | } | |
628 | ||
629 | /* Allocate a buffer to hold a memory image of the arguments. */ | |
630 | gdb_byte *memory_image = XCNEWVEC (gdb_byte, total_space); | |
631 | ||
632 | /* Now copy all of the arguments into the buffer, correctly aligned. */ | |
633 | gdb_byte *data = memory_image; | |
634 | for (int i = 0; i < nargs; i++) | |
635 | { | |
636 | unsigned int len = TYPE_LENGTH (value_type (args[i])); | |
637 | unsigned int space = align_up (len, 4); | |
638 | ||
639 | memcpy (data, value_contents (args[i]), (size_t) len); | |
640 | if (arc_debug) | |
641 | debug_printf ("arc: copying arg %d, val 0x%08x, len %d to mem\n", | |
642 | i, *((int *) value_contents (args[i])), len); | |
643 | ||
644 | data += space; | |
645 | } | |
646 | ||
647 | /* Now load as much as possible of the memory image into registers. */ | |
648 | data = memory_image; | |
649 | while (arg_reg <= ARC_LAST_ARG_REGNUM) | |
650 | { | |
651 | if (arc_debug) | |
652 | debug_printf ("arc: passing 0x%02x%02x%02x%02x in register R%d\n", | |
653 | data[0], data[1], data[2], data[3], arg_reg); | |
654 | ||
655 | /* Note we don't use write_unsigned here, since that would convert | |
656 | the byte order, but we are already in the correct byte order. */ | |
b66f5587 | 657 | regcache->cooked_write (arg_reg, data); |
ad0a504f AK |
658 | |
659 | data += ARC_REGISTER_SIZE; | |
660 | total_space -= ARC_REGISTER_SIZE; | |
661 | ||
662 | /* All the data is now in registers. */ | |
663 | if (total_space == 0) | |
664 | break; | |
665 | ||
666 | arg_reg++; | |
667 | } | |
668 | ||
669 | /* If there is any data left, push it onto the stack (in a single write | |
670 | operation). */ | |
671 | if (total_space > 0) | |
672 | { | |
673 | if (arc_debug) | |
674 | debug_printf ("arc: passing %d bytes on stack\n", total_space); | |
675 | ||
676 | sp -= total_space; | |
677 | write_memory (sp, data, (int) total_space); | |
678 | } | |
679 | ||
680 | xfree (memory_image); | |
681 | } | |
682 | ||
683 | /* Finally, update the SP register. */ | |
684 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); | |
685 | ||
686 | return sp; | |
687 | } | |
688 | ||
689 | /* Implement the "push_dummy_code" gdbarch method. | |
690 | ||
691 | We don't actually push any code. We just identify where a breakpoint can | |
692 | be inserted to which we are can return and the resume address where we | |
693 | should be called. | |
694 | ||
695 | ARC does not necessarily have an executable stack, so we can't put the | |
696 | return breakpoint there. Instead we put it at the entry point of the | |
697 | function. This means the SP is unchanged. | |
698 | ||
699 | SP is a current stack pointer FUNADDR is an address of the function to be | |
700 | called. ARGS is arguments to pass. NARGS is a number of args to pass. | |
701 | VALUE_TYPE is a type of value returned. REAL_PC is a resume address when | |
702 | the function is called. BP_ADDR is an address where breakpoint should be | |
703 | set. Returns the updated stack pointer. */ | |
704 | ||
705 | static CORE_ADDR | |
706 | arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
707 | struct value **args, int nargs, struct type *value_type, | |
708 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
709 | struct regcache *regcache) | |
710 | { | |
711 | *real_pc = funaddr; | |
712 | *bp_addr = entry_point_address (); | |
713 | return sp; | |
714 | } | |
715 | ||
716 | /* Implement the "cannot_fetch_register" gdbarch method. */ | |
717 | ||
718 | static int | |
719 | arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum) | |
720 | { | |
296ec4fa AK |
721 | /* Assume that register is readable if it is unknown. LIMM and RESERVED are |
722 | not real registers, but specific register numbers. They are available as | |
723 | regnums to align architectural register numbers with GDB internal regnums, | |
724 | but they shouldn't appear in target descriptions generated by | |
725 | GDB-servers. */ | |
726 | switch (regnum) | |
727 | { | |
728 | case ARC_RESERVED_REGNUM: | |
729 | case ARC_LIMM_REGNUM: | |
730 | return true; | |
731 | default: | |
732 | return false; | |
733 | } | |
ad0a504f AK |
734 | } |
735 | ||
736 | /* Implement the "cannot_store_register" gdbarch method. */ | |
737 | ||
738 | static int | |
739 | arc_cannot_store_register (struct gdbarch *gdbarch, int regnum) | |
740 | { | |
296ec4fa AK |
741 | /* Assume that register is writable if it is unknown. See comment in |
742 | arc_cannot_fetch_register about LIMM and RESERVED. */ | |
ad0a504f AK |
743 | switch (regnum) |
744 | { | |
296ec4fa AK |
745 | case ARC_RESERVED_REGNUM: |
746 | case ARC_LIMM_REGNUM: | |
ad0a504f | 747 | case ARC_PCL_REGNUM: |
296ec4fa | 748 | return true; |
ad0a504f | 749 | default: |
296ec4fa | 750 | return false; |
ad0a504f AK |
751 | } |
752 | } | |
753 | ||
754 | /* Get the return value of a function from the registers/memory used to | |
755 | return it, according to the convention used by the ABI - 4-bytes values are | |
756 | in the R0, while 8-byte values are in the R0-R1. | |
757 | ||
758 | TODO: This implementation ignores the case of "complex double", where | |
759 | according to ABI, value is returned in the R0-R3 registers. | |
760 | ||
761 | TYPE is a returned value's type. VALBUF is a buffer for the returned | |
762 | value. */ | |
763 | ||
764 | static void | |
765 | arc_extract_return_value (struct gdbarch *gdbarch, struct type *type, | |
766 | struct regcache *regcache, gdb_byte *valbuf) | |
767 | { | |
768 | unsigned int len = TYPE_LENGTH (type); | |
769 | ||
770 | if (arc_debug) | |
771 | debug_printf ("arc: extract_return_value\n"); | |
772 | ||
773 | if (len <= ARC_REGISTER_SIZE) | |
774 | { | |
775 | ULONGEST val; | |
776 | ||
777 | /* Get the return value from one register. */ | |
778 | regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &val); | |
779 | store_unsigned_integer (valbuf, (int) len, | |
780 | gdbarch_byte_order (gdbarch), val); | |
781 | ||
782 | if (arc_debug) | |
783 | debug_printf ("arc: returning 0x%s\n", phex (val, ARC_REGISTER_SIZE)); | |
784 | } | |
785 | else if (len <= ARC_REGISTER_SIZE * 2) | |
786 | { | |
787 | ULONGEST low, high; | |
788 | ||
789 | /* Get the return value from two registers. */ | |
790 | regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &low); | |
791 | regcache_cooked_read_unsigned (regcache, ARC_R1_REGNUM, &high); | |
792 | ||
793 | store_unsigned_integer (valbuf, ARC_REGISTER_SIZE, | |
794 | gdbarch_byte_order (gdbarch), low); | |
795 | store_unsigned_integer (valbuf + ARC_REGISTER_SIZE, | |
796 | (int) len - ARC_REGISTER_SIZE, | |
797 | gdbarch_byte_order (gdbarch), high); | |
798 | ||
799 | if (arc_debug) | |
800 | debug_printf ("arc: returning 0x%s%s\n", | |
801 | phex (high, ARC_REGISTER_SIZE), | |
802 | phex (low, ARC_REGISTER_SIZE)); | |
803 | } | |
804 | else | |
805 | error (_("arc: extract_return_value: type length %u too large"), len); | |
806 | } | |
807 | ||
808 | ||
809 | /* Store the return value of a function into the registers/memory used to | |
810 | return it, according to the convention used by the ABI. | |
811 | ||
812 | TODO: This implementation ignores the case of "complex double", where | |
813 | according to ABI, value is returned in the R0-R3 registers. | |
814 | ||
815 | TYPE is a returned value's type. VALBUF is a buffer with the value to | |
816 | return. */ | |
817 | ||
818 | static void | |
819 | arc_store_return_value (struct gdbarch *gdbarch, struct type *type, | |
820 | struct regcache *regcache, const gdb_byte *valbuf) | |
821 | { | |
822 | unsigned int len = TYPE_LENGTH (type); | |
823 | ||
824 | if (arc_debug) | |
825 | debug_printf ("arc: store_return_value\n"); | |
826 | ||
827 | if (len <= ARC_REGISTER_SIZE) | |
828 | { | |
829 | ULONGEST val; | |
830 | ||
831 | /* Put the return value into one register. */ | |
832 | val = extract_unsigned_integer (valbuf, (int) len, | |
833 | gdbarch_byte_order (gdbarch)); | |
834 | regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, val); | |
835 | ||
836 | if (arc_debug) | |
837 | debug_printf ("arc: storing 0x%s\n", phex (val, ARC_REGISTER_SIZE)); | |
838 | } | |
839 | else if (len <= ARC_REGISTER_SIZE * 2) | |
840 | { | |
841 | ULONGEST low, high; | |
842 | ||
843 | /* Put the return value into two registers. */ | |
844 | low = extract_unsigned_integer (valbuf, ARC_REGISTER_SIZE, | |
845 | gdbarch_byte_order (gdbarch)); | |
846 | high = extract_unsigned_integer (valbuf + ARC_REGISTER_SIZE, | |
847 | (int) len - ARC_REGISTER_SIZE, | |
848 | gdbarch_byte_order (gdbarch)); | |
849 | ||
850 | regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, low); | |
851 | regcache_cooked_write_unsigned (regcache, ARC_R1_REGNUM, high); | |
852 | ||
853 | if (arc_debug) | |
854 | debug_printf ("arc: storing 0x%s%s\n", | |
855 | phex (high, ARC_REGISTER_SIZE), | |
856 | phex (low, ARC_REGISTER_SIZE)); | |
857 | } | |
858 | else | |
859 | error (_("arc_store_return_value: type length too large.")); | |
860 | } | |
861 | ||
aaf43c48 AK |
862 | /* Implement the "get_longjmp_target" gdbarch method. */ |
863 | ||
864 | static int | |
865 | arc_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
866 | { | |
867 | if (arc_debug) | |
868 | debug_printf ("arc: get_longjmp_target\n"); | |
869 | ||
870 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
871 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
872 | int pc_offset = tdep->jb_pc * ARC_REGISTER_SIZE; | |
873 | gdb_byte buf[ARC_REGISTER_SIZE]; | |
874 | CORE_ADDR jb_addr = get_frame_register_unsigned (frame, ARC_FIRST_ARG_REGNUM); | |
875 | ||
876 | if (target_read_memory (jb_addr + pc_offset, buf, ARC_REGISTER_SIZE)) | |
877 | return 0; /* Failed to read from memory. */ | |
878 | ||
879 | *pc = extract_unsigned_integer (buf, ARC_REGISTER_SIZE, | |
880 | gdbarch_byte_order (gdbarch)); | |
881 | return 1; | |
882 | } | |
883 | ||
ad0a504f AK |
884 | /* Implement the "return_value" gdbarch method. */ |
885 | ||
886 | static enum return_value_convention | |
887 | arc_return_value (struct gdbarch *gdbarch, struct value *function, | |
888 | struct type *valtype, struct regcache *regcache, | |
889 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
890 | { | |
891 | /* If the return type is a struct, or a union, or would occupy more than two | |
892 | registers, the ABI uses the "struct return convention": the calling | |
893 | function passes a hidden first parameter to the callee (in R0). That | |
894 | parameter is the address at which the value being returned should be | |
895 | stored. Otherwise, the result is returned in registers. */ | |
896 | int is_struct_return = (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
897 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
898 | || TYPE_LENGTH (valtype) > 2 * ARC_REGISTER_SIZE); | |
899 | ||
900 | if (arc_debug) | |
fa42dd2e AK |
901 | debug_printf ("arc: return_value (readbuf = %s, writebuf = %s)\n", |
902 | host_address_to_string (readbuf), | |
903 | host_address_to_string (writebuf)); | |
ad0a504f AK |
904 | |
905 | if (writebuf != NULL) | |
906 | { | |
907 | /* Case 1. GDB should not ask us to set a struct return value: it | |
908 | should know the struct return location and write the value there | |
909 | itself. */ | |
910 | gdb_assert (!is_struct_return); | |
911 | arc_store_return_value (gdbarch, valtype, regcache, writebuf); | |
912 | } | |
913 | else if (readbuf != NULL) | |
914 | { | |
915 | /* Case 2. GDB should not ask us to get a struct return value: it | |
916 | should know the struct return location and read the value from there | |
917 | itself. */ | |
918 | gdb_assert (!is_struct_return); | |
919 | arc_extract_return_value (gdbarch, valtype, regcache, readbuf); | |
920 | } | |
921 | ||
922 | return (is_struct_return | |
923 | ? RETURN_VALUE_STRUCT_CONVENTION | |
924 | : RETURN_VALUE_REGISTER_CONVENTION); | |
925 | } | |
926 | ||
927 | /* Return the base address of the frame. For ARC, the base address is the | |
928 | frame pointer. */ | |
929 | ||
930 | static CORE_ADDR | |
931 | arc_frame_base_address (struct frame_info *this_frame, void **prologue_cache) | |
932 | { | |
933 | return (CORE_ADDR) get_frame_register_unsigned (this_frame, ARC_FP_REGNUM); | |
934 | } | |
935 | ||
fe5f7374 AK |
936 | /* Helper function that returns valid pv_t for an instruction operand: |
937 | either a register or a constant. */ | |
938 | ||
939 | static pv_t | |
940 | arc_pv_get_operand (pv_t *regs, const struct arc_instruction &insn, int operand) | |
941 | { | |
942 | if (insn.operands[operand].kind == ARC_OPERAND_KIND_REG) | |
943 | return regs[insn.operands[operand].value]; | |
944 | else | |
945 | return pv_constant (arc_insn_get_operand_value (insn, operand)); | |
946 | } | |
947 | ||
948 | /* Determine whether the given disassembled instruction may be part of a | |
949 | function prologue. If it is, the information in the frame unwind cache will | |
950 | be updated. */ | |
951 | ||
952 | static bool | |
953 | arc_is_in_prologue (struct gdbarch *gdbarch, const struct arc_instruction &insn, | |
954 | pv_t *regs, struct pv_area *stack) | |
955 | { | |
956 | /* It might be that currently analyzed address doesn't contain an | |
957 | instruction, hence INSN is not valid. It likely means that address points | |
958 | to a data, non-initialized memory, or middle of a 32-bit instruction. In | |
959 | practice this may happen if GDB connects to a remote target that has | |
960 | non-zeroed memory. GDB would read PC value and would try to analyze | |
961 | prologue, but there is no guarantee that memory contents at the address | |
962 | specified in PC is address is a valid instruction. There is not much that | |
963 | that can be done about that. */ | |
964 | if (!insn.valid) | |
965 | return false; | |
966 | ||
967 | /* Branch/jump or a predicated instruction. */ | |
968 | if (insn.is_control_flow || insn.condition_code != ARC_CC_AL) | |
969 | return false; | |
970 | ||
971 | /* Store of some register. May or may not update base address register. */ | |
972 | if (insn.insn_class == STORE || insn.insn_class == PUSH) | |
973 | { | |
30baf67b | 974 | /* There is definitely at least one operand - register/value being |
fe5f7374 AK |
975 | stored. */ |
976 | gdb_assert (insn.operands_count > 0); | |
977 | ||
978 | /* Store at some constant address. */ | |
979 | if (insn.operands_count > 1 | |
980 | && insn.operands[1].kind != ARC_OPERAND_KIND_REG) | |
981 | return false; | |
982 | ||
983 | /* Writeback modes: | |
984 | Mode Address used Writeback value | |
985 | -------------------------------------------------- | |
986 | No reg + offset no | |
987 | A/AW reg + offset reg + offset | |
988 | AB reg reg + offset | |
989 | AS reg + (offset << scaling) no | |
990 | ||
991 | "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However | |
992 | 16-bit PUSH_S is a distinct instruction encoding, where offset and | |
993 | base register are implied through opcode. */ | |
994 | ||
995 | /* Register with base memory address. */ | |
996 | int base_reg = arc_insn_get_memory_base_reg (insn); | |
997 | ||
998 | /* Address where to write. arc_insn_get_memory_offset returns scaled | |
999 | value for ARC_WRITEBACK_AS. */ | |
1000 | pv_t addr; | |
1001 | if (insn.writeback_mode == ARC_WRITEBACK_AB) | |
1002 | addr = regs[base_reg]; | |
1003 | else | |
1004 | addr = pv_add_constant (regs[base_reg], | |
1005 | arc_insn_get_memory_offset (insn)); | |
1006 | ||
f7b7ed97 | 1007 | if (stack->store_would_trash (addr)) |
fe5f7374 AK |
1008 | return false; |
1009 | ||
1010 | if (insn.data_size_mode != ARC_SCALING_D) | |
1011 | { | |
1012 | /* Find the value being stored. */ | |
1013 | pv_t store_value = arc_pv_get_operand (regs, insn, 0); | |
1014 | ||
1015 | /* What is the size of a the stored value? */ | |
1016 | CORE_ADDR size; | |
1017 | if (insn.data_size_mode == ARC_SCALING_B) | |
1018 | size = 1; | |
1019 | else if (insn.data_size_mode == ARC_SCALING_H) | |
1020 | size = 2; | |
1021 | else | |
1022 | size = ARC_REGISTER_SIZE; | |
1023 | ||
f7b7ed97 | 1024 | stack->store (addr, size, store_value); |
fe5f7374 AK |
1025 | } |
1026 | else | |
1027 | { | |
1028 | if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) | |
1029 | { | |
1030 | /* If this is a double store, than write N+1 register as well. */ | |
1031 | pv_t store_value1 = regs[insn.operands[0].value]; | |
1032 | pv_t store_value2 = regs[insn.operands[0].value + 1]; | |
f7b7ed97 TT |
1033 | stack->store (addr, ARC_REGISTER_SIZE, store_value1); |
1034 | stack->store (pv_add_constant (addr, ARC_REGISTER_SIZE), | |
1035 | ARC_REGISTER_SIZE, store_value2); | |
fe5f7374 AK |
1036 | } |
1037 | else | |
1038 | { | |
1039 | pv_t store_value | |
1040 | = pv_constant (arc_insn_get_operand_value (insn, 0)); | |
f7b7ed97 | 1041 | stack->store (addr, ARC_REGISTER_SIZE * 2, store_value); |
fe5f7374 AK |
1042 | } |
1043 | } | |
1044 | ||
1045 | /* Is base register updated? */ | |
1046 | if (insn.writeback_mode == ARC_WRITEBACK_A | |
1047 | || insn.writeback_mode == ARC_WRITEBACK_AB) | |
1048 | regs[base_reg] = pv_add_constant (regs[base_reg], | |
1049 | arc_insn_get_memory_offset (insn)); | |
1050 | ||
1051 | return true; | |
1052 | } | |
1053 | else if (insn.insn_class == MOVE) | |
1054 | { | |
1055 | gdb_assert (insn.operands_count == 2); | |
1056 | ||
1057 | /* Destination argument can be "0", so nothing will happen. */ | |
1058 | if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) | |
1059 | { | |
1060 | int dst_regnum = insn.operands[0].value; | |
1061 | regs[dst_regnum] = arc_pv_get_operand (regs, insn, 1); | |
1062 | } | |
1063 | return true; | |
1064 | } | |
1065 | else if (insn.insn_class == SUB) | |
1066 | { | |
1067 | gdb_assert (insn.operands_count == 3); | |
1068 | ||
1069 | /* SUB 0,b,c. */ | |
1070 | if (insn.operands[0].kind != ARC_OPERAND_KIND_REG) | |
1071 | return true; | |
1072 | ||
1073 | int dst_regnum = insn.operands[0].value; | |
1074 | regs[dst_regnum] = pv_subtract (arc_pv_get_operand (regs, insn, 1), | |
1075 | arc_pv_get_operand (regs, insn, 2)); | |
1076 | return true; | |
1077 | } | |
1078 | else if (insn.insn_class == ENTER) | |
1079 | { | |
1080 | /* ENTER_S is a prologue-in-instruction - it saves all callee-saved | |
1081 | registers according to given arguments thus greatly reducing code | |
1082 | size. Which registers will be actually saved depends on arguments. | |
1083 | ||
1084 | ENTER_S {R13-...,FP,BLINK} stores registers in following order: | |
1085 | ||
1086 | new SP -> | |
1087 | BLINK | |
1088 | R13 | |
1089 | R14 | |
1090 | R15 | |
1091 | ... | |
1092 | FP | |
1093 | old SP -> | |
1094 | ||
1095 | There are up to three arguments for this opcode, as presented by ARC | |
1096 | disassembler: | |
1097 | 1) amount of general-purpose registers to be saved - this argument is | |
1098 | always present even when it is 0; | |
1099 | 2) FP register number (27) if FP has to be stored, otherwise argument | |
1100 | is not present; | |
1101 | 3) BLINK register number (31) if BLINK has to be stored, otherwise | |
1102 | argument is not present. If both FP and BLINK are stored, then FP | |
1103 | is present before BLINK in argument list. */ | |
1104 | gdb_assert (insn.operands_count > 0); | |
1105 | ||
1106 | int regs_saved = arc_insn_get_operand_value (insn, 0); | |
1107 | ||
1108 | bool is_fp_saved; | |
1109 | if (insn.operands_count > 1) | |
1110 | is_fp_saved = (insn.operands[1].value == ARC_FP_REGNUM); | |
1111 | else | |
1112 | is_fp_saved = false; | |
1113 | ||
1114 | bool is_blink_saved; | |
1115 | if (insn.operands_count > 1) | |
1116 | is_blink_saved = (insn.operands[insn.operands_count - 1].value | |
1117 | == ARC_BLINK_REGNUM); | |
1118 | else | |
1119 | is_blink_saved = false; | |
1120 | ||
1121 | /* Amount of bytes to be allocated to store specified registers. */ | |
1122 | CORE_ADDR st_size = ((regs_saved + is_fp_saved + is_blink_saved) | |
1123 | * ARC_REGISTER_SIZE); | |
1124 | pv_t new_sp = pv_add_constant (regs[ARC_SP_REGNUM], -st_size); | |
1125 | ||
1126 | /* Assume that if the last register (closest to new SP) can be written, | |
1127 | then it is possible to write all of them. */ | |
f7b7ed97 | 1128 | if (stack->store_would_trash (new_sp)) |
fe5f7374 AK |
1129 | return false; |
1130 | ||
1131 | /* Current store address. */ | |
1132 | pv_t addr = regs[ARC_SP_REGNUM]; | |
1133 | ||
1134 | if (is_fp_saved) | |
1135 | { | |
1136 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); | |
f7b7ed97 | 1137 | stack->store (addr, ARC_REGISTER_SIZE, regs[ARC_FP_REGNUM]); |
fe5f7374 AK |
1138 | } |
1139 | ||
1140 | /* Registers are stored in backward order: from GP (R26) to R13. */ | |
1141 | for (int i = ARC_R13_REGNUM + regs_saved - 1; i >= ARC_R13_REGNUM; i--) | |
1142 | { | |
1143 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); | |
f7b7ed97 | 1144 | stack->store (addr, ARC_REGISTER_SIZE, regs[i]); |
fe5f7374 AK |
1145 | } |
1146 | ||
1147 | if (is_blink_saved) | |
1148 | { | |
1149 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); | |
f7b7ed97 TT |
1150 | stack->store (addr, ARC_REGISTER_SIZE, |
1151 | regs[ARC_BLINK_REGNUM]); | |
fe5f7374 AK |
1152 | } |
1153 | ||
1154 | gdb_assert (pv_is_identical (addr, new_sp)); | |
1155 | ||
1156 | regs[ARC_SP_REGNUM] = new_sp; | |
1157 | ||
1158 | if (is_fp_saved) | |
1159 | regs[ARC_FP_REGNUM] = regs[ARC_SP_REGNUM]; | |
1160 | ||
1161 | return true; | |
1162 | } | |
1163 | ||
1164 | /* Some other architectures, like nds32 or arm, try to continue as far as | |
1165 | possible when building a prologue cache (as opposed to when skipping | |
1166 | prologue), so that cache will be as full as possible. However current | |
1167 | code for ARC doesn't recognize some instructions that may modify SP, like | |
1168 | ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't | |
1169 | clobbered by the skipped instruction. Potential existence of extension | |
1170 | instruction, which may do anything they want makes this even more complex, | |
1171 | so it is just better to halt on a first unrecognized instruction. */ | |
1172 | ||
1173 | return false; | |
1174 | } | |
1175 | ||
eea78757 AK |
1176 | /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */ |
1177 | ||
1178 | static int ATTRIBUTE_PRINTF (2, 3) | |
1179 | arc_fprintf_disasm (void *stream, const char *format, ...) | |
1180 | { | |
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | struct disassemble_info | |
1185 | arc_disassemble_info (struct gdbarch *gdbarch) | |
1186 | { | |
1187 | struct disassemble_info di; | |
1188 | init_disassemble_info (&di, &null_stream, arc_fprintf_disasm); | |
1189 | di.arch = gdbarch_bfd_arch_info (gdbarch)->arch; | |
1190 | di.mach = gdbarch_bfd_arch_info (gdbarch)->mach; | |
1191 | di.endian = gdbarch_byte_order (gdbarch); | |
1192 | di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr, | |
1193 | unsigned int len, struct disassemble_info *info) | |
1194 | { | |
1195 | return target_read_code (memaddr, myaddr, len); | |
1196 | }; | |
1197 | return di; | |
1198 | } | |
1199 | ||
fe5f7374 AK |
1200 | /* Analyze the prologue and update the corresponding frame cache for the frame |
1201 | unwinder for unwinding frames that doesn't have debug info. In such | |
1202 | situation GDB attempts to parse instructions in the prologue to understand | |
1203 | where each register is saved. | |
1204 | ||
1205 | If CACHE is not NULL, then it will be filled with information about saved | |
1206 | registers. | |
1207 | ||
85102364 | 1208 | There are several variations of prologue which GDB may encounter. "Full" |
fe5f7374 AK |
1209 | prologue looks like this: |
1210 | ||
1211 | sub sp,sp,<imm> ; Space for variadic arguments. | |
1212 | push blink ; Store return address. | |
1213 | push r13 ; Store callee saved registers (up to R26/GP). | |
1214 | push r14 | |
1215 | push fp ; Store frame pointer. | |
1216 | mov fp,sp ; Update frame pointer. | |
1217 | sub sp,sp,<imm> ; Create space for local vars on the stack. | |
1218 | ||
1219 | Depending on compiler options lots of things may change: | |
1220 | ||
1221 | 1) BLINK is not saved in leaf functions. | |
1222 | 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used. | |
1223 | 3) 16-bit versions of those instructions may be used. | |
1224 | 4) Instead of a sequence of several push'es, compiler may instead prefer to | |
1225 | do one subtract on stack pointer and then store registers using normal | |
1226 | store, that doesn't update SP. Like this: | |
1227 | ||
1228 | ||
85102364 | 1229 | sub sp,sp,8 ; Create space for callee-saved registers. |
fe5f7374 AK |
1230 | st r13,[sp,4] ; Store callee saved registers (up to R26/GP). |
1231 | st r14,[sp,0] | |
1232 | ||
1233 | 5) ENTER_S instruction can encode most of prologue sequence in one | |
1234 | instruction (except for those subtracts for variadic arguments and local | |
1235 | variables). | |
1236 | 6) GCC may use "millicode" functions from libgcc to store callee-saved | |
1237 | registers with minimal code-size requirements. This function currently | |
1238 | doesn't support this. | |
1239 | ||
1240 | ENTRYPOINT is a function entry point where prologue starts. | |
1241 | ||
1242 | LIMIT_PC is a maximum possible end address of prologue (meaning address | |
1243 | of first instruction after the prologue). It might also point to the middle | |
1244 | of prologue if execution has been stopped by the breakpoint at this address | |
1245 | - in this case debugger should analyze prologue only up to this address, | |
1246 | because further instructions haven't been executed yet. | |
1247 | ||
1248 | Returns address of the first instruction after the prologue. */ | |
1249 | ||
1250 | static CORE_ADDR | |
1251 | arc_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR entrypoint, | |
1252 | const CORE_ADDR limit_pc, struct arc_frame_cache *cache) | |
1253 | { | |
1254 | if (arc_debug) | |
1255 | debug_printf ("arc: analyze_prologue (entrypoint=%s, limit_pc=%s)\n", | |
1256 | paddress (gdbarch, entrypoint), | |
1257 | paddress (gdbarch, limit_pc)); | |
1258 | ||
1259 | /* Prologue values. Only core registers can be stored. */ | |
1260 | pv_t regs[ARC_LAST_CORE_REGNUM + 1]; | |
1261 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) | |
1262 | regs[i] = pv_register (i, 0); | |
f7b7ed97 | 1263 | pv_area stack (ARC_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
fe5f7374 AK |
1264 | |
1265 | CORE_ADDR current_prologue_end = entrypoint; | |
1266 | ||
1267 | /* Look at each instruction in the prologue. */ | |
1268 | while (current_prologue_end < limit_pc) | |
1269 | { | |
1270 | struct arc_instruction insn; | |
1271 | struct disassemble_info di = arc_disassemble_info (gdbarch); | |
1272 | arc_insn_decode (current_prologue_end, &di, arc_delayed_print_insn, | |
1273 | &insn); | |
1274 | ||
1275 | if (arc_debug >= 2) | |
1276 | arc_insn_dump (insn); | |
1277 | ||
1278 | /* If this instruction is in the prologue, fields in the cache will be | |
1279 | updated, and the saved registers mask may be updated. */ | |
f7b7ed97 | 1280 | if (!arc_is_in_prologue (gdbarch, insn, regs, &stack)) |
fe5f7374 AK |
1281 | { |
1282 | /* Found an instruction that is not in the prologue. */ | |
1283 | if (arc_debug) | |
1284 | debug_printf ("arc: End of prologue reached at address %s\n", | |
1285 | paddress (gdbarch, insn.address)); | |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | current_prologue_end = arc_insn_get_linear_next_pc (insn); | |
1290 | } | |
1291 | ||
1292 | if (cache != NULL) | |
1293 | { | |
1294 | /* Figure out if it is a frame pointer or just a stack pointer. */ | |
1295 | if (pv_is_register (regs[ARC_FP_REGNUM], ARC_SP_REGNUM)) | |
1296 | { | |
1297 | cache->frame_base_reg = ARC_FP_REGNUM; | |
1298 | cache->frame_base_offset = -regs[ARC_FP_REGNUM].k; | |
1299 | } | |
1300 | else | |
1301 | { | |
1302 | cache->frame_base_reg = ARC_SP_REGNUM; | |
1303 | cache->frame_base_offset = -regs[ARC_SP_REGNUM].k; | |
1304 | } | |
1305 | ||
1306 | /* Assign offset from old SP to all saved registers. */ | |
1307 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) | |
1308 | { | |
1309 | CORE_ADDR offset; | |
f7b7ed97 | 1310 | if (stack.find_reg (gdbarch, i, &offset)) |
fe5f7374 AK |
1311 | cache->saved_regs[i].addr = offset; |
1312 | } | |
1313 | } | |
1314 | ||
fe5f7374 AK |
1315 | return current_prologue_end; |
1316 | } | |
1317 | ||
1318 | /* Estimated maximum prologue length in bytes. This should include: | |
1319 | 1) Store instruction for each callee-saved register (R25 - R13 + 1) | |
1320 | 2) Two instructions for FP | |
1321 | 3) One for BLINK | |
1322 | 4) Three substract instructions for SP (for variadic args, for | |
1323 | callee saved regs and for local vars) and assuming that those SUB use | |
1324 | long-immediate (hence double length). | |
1325 | 5) Stores of arguments registers are considered part of prologue too | |
1326 | (R7 - R1 + 1). | |
1327 | This is quite an extreme case, because even with -O0 GCC will collapse first | |
1328 | two SUBs into one and long immediate values are quite unlikely to appear in | |
1329 | this case, but still better to overshoot a bit - prologue analysis will | |
1330 | anyway stop at the first instruction that doesn't fit prologue, so this | |
1331 | limit will be rarely reached. */ | |
1332 | ||
1333 | const static int MAX_PROLOGUE_LENGTH | |
1334 | = 4 * (ARC_R25_REGNUM - ARC_R13_REGNUM + 1 + 2 + 1 + 6 | |
1335 | + ARC_LAST_ARG_REGNUM - ARC_FIRST_ARG_REGNUM + 1); | |
1336 | ||
ad0a504f AK |
1337 | /* Implement the "skip_prologue" gdbarch method. |
1338 | ||
1339 | Skip the prologue for the function at PC. This is done by checking from | |
1340 | the line information read from the DWARF, if possible; otherwise, we scan | |
1341 | the function prologue to find its end. */ | |
1342 | ||
1343 | static CORE_ADDR | |
1344 | arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1345 | { | |
1346 | if (arc_debug) | |
1347 | debug_printf ("arc: skip_prologue\n"); | |
1348 | ||
1349 | CORE_ADDR func_addr; | |
1350 | const char *func_name; | |
1351 | ||
1352 | /* See what the symbol table says. */ | |
1353 | if (find_pc_partial_function (pc, &func_name, &func_addr, NULL)) | |
1354 | { | |
1355 | /* Found a function. */ | |
1356 | CORE_ADDR postprologue_pc | |
1357 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1358 | ||
1359 | if (postprologue_pc != 0) | |
1360 | return std::max (pc, postprologue_pc); | |
1361 | } | |
1362 | ||
1363 | /* No prologue info in symbol table, have to analyze prologue. */ | |
1364 | ||
1365 | /* Find an upper limit on the function prologue using the debug | |
fe5f7374 AK |
1366 | information. If there is no debug information about prologue end, then |
1367 | skip_prologue_using_sal will return 0. */ | |
ad0a504f | 1368 | CORE_ADDR limit_pc = skip_prologue_using_sal (gdbarch, pc); |
fe5f7374 AK |
1369 | |
1370 | /* If there is no debug information at all, it is required to give some | |
1371 | semi-arbitrary hard limit on amount of bytes to scan during prologue | |
1372 | analysis. */ | |
1373 | if (limit_pc == 0) | |
1374 | limit_pc = pc + MAX_PROLOGUE_LENGTH; | |
1375 | ||
1376 | /* Find the address of the first instruction after the prologue by scanning | |
1377 | through it - no other information is needed, so pass NULL as a cache. */ | |
1378 | return arc_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
ad0a504f AK |
1379 | } |
1380 | ||
1381 | /* Implement the "print_insn" gdbarch method. | |
1382 | ||
1383 | arc_get_disassembler () may return different functions depending on bfd | |
1384 | type, so it is not possible to pass print_insn directly to | |
1385 | set_gdbarch_print_insn (). Instead this wrapper function is used. It also | |
1386 | may be used by other functions to get disassemble_info for address. It is | |
1387 | important to note, that those print_insn from opcodes always print | |
1388 | instruction to the stream specified in the INFO. If this is not desired, | |
1389 | then either `print_insn` function in INFO should be set to some function | |
1390 | that will not print, or `stream` should be different from standard | |
1391 | gdb_stdlog. */ | |
1392 | ||
eea78757 | 1393 | int |
ad0a504f AK |
1394 | arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info) |
1395 | { | |
85102364 | 1396 | /* Standard BFD "machine number" field allows libopcodes disassembler to |
a87dc45a AK |
1397 | distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM |
1398 | and HS, which have some difference between. There are two ways to specify | |
1399 | what is the target core: | |
1400 | 1) via the disassemble_info->disassembler_options; | |
1401 | 2) otherwise libopcodes will use private (architecture-specific) ELF | |
1402 | header. | |
1403 | ||
1404 | Using disassembler_options is preferable, because it comes directly from | |
1405 | GDBserver which scanned an actual ARC core identification info. However, | |
1406 | not all GDBservers report core architecture, so as a fallback GDB still | |
1407 | should support analysis of ELF header. The libopcodes disassembly code | |
1408 | uses the section to find the BFD and the BFD to find the ELF header, | |
1409 | therefore this function should set disassemble_info->section properly. | |
1410 | ||
1411 | disassembler_options was already set by non-target specific code with | |
1412 | proper options obtained via gdbarch_disassembler_options (). | |
1413 | ||
1414 | This function might be called multiple times in a sequence, reusing same | |
1415 | disassemble_info. */ | |
1416 | if ((info->disassembler_options == NULL) && (info->section == NULL)) | |
1417 | { | |
1418 | struct obj_section *s = find_pc_section (addr); | |
1419 | if (s != NULL) | |
1420 | info->section = s->the_bfd_section; | |
1421 | } | |
1422 | ||
1423 | return default_print_insn (addr, info); | |
ad0a504f AK |
1424 | } |
1425 | ||
1426 | /* Baremetal breakpoint instructions. | |
1427 | ||
1428 | ARC supports both big- and little-endian. However, instructions for | |
1429 | little-endian processors are encoded in the middle-endian: half-words are | |
1430 | in big-endian, while bytes inside the half-words are in little-endian; data | |
1431 | is represented in the "normal" little-endian. Big-endian processors treat | |
1432 | data and code identically. | |
1433 | ||
1434 | Assuming the number 0x01020304, it will be presented this way: | |
1435 | ||
1436 | Address : N N+1 N+2 N+3 | |
1437 | little-endian : 0x04 0x03 0x02 0x01 | |
1438 | big-endian : 0x01 0x02 0x03 0x04 | |
1439 | ARC middle-endian : 0x02 0x01 0x04 0x03 | |
1440 | */ | |
1441 | ||
1442 | static const gdb_byte arc_brk_s_be[] = { 0x7f, 0xff }; | |
1443 | static const gdb_byte arc_brk_s_le[] = { 0xff, 0x7f }; | |
1444 | static const gdb_byte arc_brk_be[] = { 0x25, 0x6f, 0x00, 0x3f }; | |
1445 | static const gdb_byte arc_brk_le[] = { 0x6f, 0x25, 0x3f, 0x00 }; | |
1446 | ||
d19280ad | 1447 | /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff |
ad0a504f AK |
1448 | (little endian) or 0xff7f (big endian). We used to insert BRK_S even |
1449 | instead of 32-bit instructions, which works mostly ok, unless breakpoint is | |
1450 | inserted into delay slot instruction. In this case if branch is taken | |
1451 | BLINK value will be set to address of instruction after delay slot, however | |
1452 | if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S, | |
1453 | then BLINK value will have an invalid value - it will point to the address | |
1454 | after the BRK_S (which was there at the moment of branch execution) while | |
1455 | it should point to the address after the 32-bit long instruction. To avoid | |
1456 | such issues this function disassembles instruction at target location and | |
1457 | evaluates it value. | |
1458 | ||
1459 | ARC 600 supports only 16-bit BRK_S. | |
1460 | ||
1461 | NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S] | |
1462 | is much better because it doesn't commit unlike TRAP_S, so it can be set in | |
1463 | delay slots; however it cannot be used in user-mode, hence usage of TRAP_S | |
d19280ad | 1464 | in GDB for user-space. */ |
ad0a504f | 1465 | |
d19280ad | 1466 | /* Implement the "breakpoint_kind_from_pc" gdbarch method. */ |
ad0a504f | 1467 | |
d19280ad YQ |
1468 | static int |
1469 | arc_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
ad0a504f AK |
1470 | { |
1471 | size_t length_with_limm = gdb_insn_length (gdbarch, *pcptr); | |
1472 | ||
1473 | /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with | |
1474 | BRK. LIMM is part of instruction length, so it can be either 4 or 8 | |
1475 | bytes for 32-bit instructions. */ | |
1476 | if ((length_with_limm == 4 || length_with_limm == 8) | |
1477 | && !arc_mach_is_arc600 (gdbarch)) | |
d19280ad YQ |
1478 | return sizeof (arc_brk_le); |
1479 | else | |
1480 | return sizeof (arc_brk_s_le); | |
1481 | } | |
1482 | ||
1483 | /* Implement the "sw_breakpoint_from_kind" gdbarch method. */ | |
1484 | ||
1485 | static const gdb_byte * | |
1486 | arc_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
1487 | { | |
1488 | *size = kind; | |
1489 | ||
1490 | if (kind == sizeof (arc_brk_le)) | |
ad0a504f | 1491 | { |
ad0a504f AK |
1492 | return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1493 | ? arc_brk_be | |
1494 | : arc_brk_le); | |
1495 | } | |
1496 | else | |
1497 | { | |
ad0a504f AK |
1498 | return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1499 | ? arc_brk_s_be | |
1500 | : arc_brk_s_le); | |
1501 | } | |
1502 | } | |
1503 | ||
ad0a504f AK |
1504 | /* Implement the "frame_align" gdbarch method. */ |
1505 | ||
1506 | static CORE_ADDR | |
1507 | arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1508 | { | |
1509 | return align_down (sp, 4); | |
1510 | } | |
1511 | ||
fe5f7374 AK |
1512 | /* Dump the frame info. Used for internal debugging only. */ |
1513 | ||
1514 | static void | |
a121b7c1 | 1515 | arc_print_frame_cache (struct gdbarch *gdbarch, const char *message, |
fe5f7374 AK |
1516 | struct arc_frame_cache *cache, int addresses_known) |
1517 | { | |
1518 | debug_printf ("arc: frame_info %s\n", message); | |
1519 | debug_printf ("arc: prev_sp = %s\n", paddress (gdbarch, cache->prev_sp)); | |
1520 | debug_printf ("arc: frame_base_reg = %i\n", cache->frame_base_reg); | |
1521 | debug_printf ("arc: frame_base_offset = %s\n", | |
1522 | plongest (cache->frame_base_offset)); | |
1523 | ||
1524 | for (int i = 0; i <= ARC_BLINK_REGNUM; i++) | |
1525 | { | |
1526 | if (trad_frame_addr_p (cache->saved_regs, i)) | |
1527 | debug_printf ("arc: saved register %s at %s %s\n", | |
1528 | gdbarch_register_name (gdbarch, i), | |
1529 | (addresses_known) ? "address" : "offset", | |
1530 | paddress (gdbarch, cache->saved_regs[i].addr)); | |
1531 | } | |
1532 | } | |
1533 | ||
ad0a504f AK |
1534 | /* Frame unwinder for normal frames. */ |
1535 | ||
1536 | static struct arc_frame_cache * | |
1537 | arc_make_frame_cache (struct frame_info *this_frame) | |
1538 | { | |
1539 | if (arc_debug) | |
1540 | debug_printf ("arc: frame_cache\n"); | |
1541 | ||
1542 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1543 | ||
1544 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
ad0a504f AK |
1545 | CORE_ADDR entrypoint, prologue_end; |
1546 | if (find_pc_partial_function (block_addr, NULL, &entrypoint, &prologue_end)) | |
1547 | { | |
1548 | struct symtab_and_line sal = find_pc_line (entrypoint, 0); | |
fe5f7374 | 1549 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
ad0a504f AK |
1550 | if (sal.line == 0) |
1551 | /* No line info so use current PC. */ | |
1552 | prologue_end = prev_pc; | |
1553 | else if (sal.end < prologue_end) | |
1554 | /* The next line begins after the function end. */ | |
1555 | prologue_end = sal.end; | |
1556 | ||
1557 | prologue_end = std::min (prologue_end, prev_pc); | |
1558 | } | |
1559 | else | |
1560 | { | |
fe5f7374 AK |
1561 | /* If find_pc_partial_function returned nothing then there is no symbol |
1562 | information at all for this PC. Currently it is assumed in this case | |
1563 | that current PC is entrypoint to function and try to construct the | |
1564 | frame from that. This is, probably, suboptimal, for example ARM | |
1565 | assumes in this case that program is inside the normal frame (with | |
1566 | frame pointer). ARC, perhaps, should try to do the same. */ | |
ad0a504f AK |
1567 | entrypoint = get_frame_register_unsigned (this_frame, |
1568 | gdbarch_pc_regnum (gdbarch)); | |
fe5f7374 | 1569 | prologue_end = entrypoint + MAX_PROLOGUE_LENGTH; |
ad0a504f AK |
1570 | } |
1571 | ||
1572 | /* Allocate new frame cache instance and space for saved register info. | |
fe5f7374 | 1573 | FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */ |
ad0a504f AK |
1574 | struct arc_frame_cache *cache |
1575 | = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache); | |
1576 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1577 | ||
fe5f7374 AK |
1578 | arc_analyze_prologue (gdbarch, entrypoint, prologue_end, cache); |
1579 | ||
1580 | if (arc_debug) | |
1581 | arc_print_frame_cache (gdbarch, "after prologue", cache, false); | |
1582 | ||
1583 | CORE_ADDR unwound_fb = get_frame_register_unsigned (this_frame, | |
1584 | cache->frame_base_reg); | |
1585 | if (unwound_fb == 0) | |
1586 | return cache; | |
1587 | cache->prev_sp = unwound_fb + cache->frame_base_offset; | |
1588 | ||
1589 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) | |
1590 | { | |
1591 | if (trad_frame_addr_p (cache->saved_regs, i)) | |
1592 | cache->saved_regs[i].addr += cache->prev_sp; | |
1593 | } | |
1594 | ||
1595 | if (arc_debug) | |
1596 | arc_print_frame_cache (gdbarch, "after previous SP found", cache, true); | |
ad0a504f AK |
1597 | |
1598 | return cache; | |
1599 | } | |
1600 | ||
1601 | /* Implement the "this_id" frame_unwind method. */ | |
1602 | ||
1603 | static void | |
1604 | arc_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
1605 | struct frame_id *this_id) | |
1606 | { | |
1607 | if (arc_debug) | |
1608 | debug_printf ("arc: frame_this_id\n"); | |
1609 | ||
1610 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1611 | ||
1612 | if (*this_cache == NULL) | |
1613 | *this_cache = arc_make_frame_cache (this_frame); | |
1614 | struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); | |
1615 | ||
1616 | CORE_ADDR stack_addr = cache->prev_sp; | |
1617 | ||
1618 | /* There are 4 possible situation which decide how frame_id->code_addr is | |
1619 | evaluated: | |
1620 | ||
1621 | 1) Function is compiled with option -g. Then frame_id will be created | |
1622 | in dwarf_* function and not in this function. NB: even if target | |
1623 | binary is compiled with -g, some std functions like __start and _init | |
1624 | are not, so they still will follow one of the following choices. | |
1625 | ||
1626 | 2) Function is compiled without -g and binary hasn't been stripped in | |
1627 | any way. In this case GDB still has enough information to evaluate | |
1628 | frame code_addr properly. This case is covered by call to | |
1629 | get_frame_func (). | |
1630 | ||
1631 | 3) Binary has been striped with option -g (strip debug symbols). In | |
1632 | this case there is still enough symbols for get_frame_func () to work | |
1633 | properly, so this case is also covered by it. | |
1634 | ||
1635 | 4) Binary has been striped with option -s (strip all symbols). In this | |
1636 | case GDB cannot get function start address properly, so we return current | |
1637 | PC value instead. | |
1638 | */ | |
1639 | CORE_ADDR code_addr = get_frame_func (this_frame); | |
1640 | if (code_addr == 0) | |
1641 | code_addr = get_frame_register_unsigned (this_frame, | |
1642 | gdbarch_pc_regnum (gdbarch)); | |
1643 | ||
1644 | *this_id = frame_id_build (stack_addr, code_addr); | |
1645 | } | |
1646 | ||
1647 | /* Implement the "prev_register" frame_unwind method. */ | |
1648 | ||
1649 | static struct value * | |
1650 | arc_frame_prev_register (struct frame_info *this_frame, | |
1651 | void **this_cache, int regnum) | |
1652 | { | |
ad0a504f AK |
1653 | if (*this_cache == NULL) |
1654 | *this_cache = arc_make_frame_cache (this_frame); | |
1655 | struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); | |
1656 | ||
1657 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1658 | ||
1659 | /* If we are asked to unwind the PC, then we need to return BLINK instead: | |
1660 | the saved value of PC points into this frame's function's prologue, not | |
1661 | the next frame's function's resume location. */ | |
1662 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
1663 | regnum = ARC_BLINK_REGNUM; | |
1664 | ||
1665 | /* SP is a special case - we should return prev_sp, because | |
1666 | trad_frame_get_prev_register will return _current_ SP value. | |
1667 | Alternatively we could have stored cache->prev_sp in the cache->saved | |
1668 | regs, but here we follow the lead of AArch64, ARM and Xtensa and will | |
1669 | leave that logic in this function, instead of prologue analyzers. That I | |
1670 | think is a bit more clear as `saved_regs` should contain saved regs, not | |
1671 | computable. | |
1672 | ||
1673 | Because value has been computed, "got_constant" should be used, so that | |
1674 | returned value will be a "not_lval" - immutable. */ | |
1675 | ||
1676 | if (regnum == gdbarch_sp_regnum (gdbarch)) | |
1677 | return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp); | |
1678 | ||
1679 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum); | |
1680 | } | |
1681 | ||
1682 | /* Implement the "init_reg" dwarf2_frame method. */ | |
1683 | ||
1684 | static void | |
1685 | arc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1686 | struct dwarf2_frame_state_reg *reg, | |
1687 | struct frame_info *info) | |
1688 | { | |
1689 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
1690 | /* The return address column. */ | |
1691 | reg->how = DWARF2_FRAME_REG_RA; | |
1692 | else if (regnum == gdbarch_sp_regnum (gdbarch)) | |
1693 | /* The call frame address. */ | |
1694 | reg->how = DWARF2_FRAME_REG_CFA; | |
1695 | } | |
1696 | ||
1697 | /* Structure defining the ARC ordinary frame unwind functions. Since we are | |
1698 | the fallback unwinder, we use the default frame sniffer, which always | |
1699 | accepts the frame. */ | |
1700 | ||
1701 | static const struct frame_unwind arc_frame_unwind = { | |
1702 | NORMAL_FRAME, | |
1703 | default_frame_unwind_stop_reason, | |
1704 | arc_frame_this_id, | |
1705 | arc_frame_prev_register, | |
1706 | NULL, | |
1707 | default_frame_sniffer, | |
1708 | NULL, | |
1709 | NULL | |
1710 | }; | |
1711 | ||
1712 | ||
1713 | static const struct frame_base arc_normal_base = { | |
1714 | &arc_frame_unwind, | |
1715 | arc_frame_base_address, | |
1716 | arc_frame_base_address, | |
1717 | arc_frame_base_address | |
1718 | }; | |
1719 | ||
1720 | /* Initialize target description for the ARC. | |
1721 | ||
1722 | Returns TRUE if input tdesc was valid and in this case it will assign TDESC | |
1723 | and TDESC_DATA output parameters. */ | |
1724 | ||
fbdf05a1 | 1725 | static bool |
ad0a504f AK |
1726 | arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc, |
1727 | struct tdesc_arch_data **tdesc_data) | |
1728 | { | |
1729 | if (arc_debug) | |
1730 | debug_printf ("arc: Target description initialization.\n"); | |
1731 | ||
1732 | const struct target_desc *tdesc_loc = info.target_desc; | |
1733 | ||
1734 | /* Depending on whether this is ARCompact or ARCv2 we will assign | |
1735 | different default registers sets (which will differ in exactly two core | |
1736 | registers). GDB will also refuse to accept register feature from invalid | |
1737 | ISA - v2 features can be used only with v2 ARChitecture. We read | |
1738 | bfd_arch_info, which looks like to be a safe bet here, as it looks like it | |
1739 | is always initialized even when we don't pass any elf file to GDB at all | |
1740 | (it uses default arch in this case). Also GDB will call this function | |
1741 | multiple times, and if XML target description file contains architecture | |
1742 | specifications, then GDB will set this architecture to info.bfd_arch_info, | |
1743 | overriding value from ELF file if they are different. That means that, | |
1744 | where matters, this value is always our best guess on what CPU we are | |
1745 | debugging. It has been noted that architecture specified in tdesc file | |
1746 | has higher precedence over ELF and even "set architecture" - that is, | |
1747 | using "set architecture" command will have no effect when tdesc has "arch" | |
1748 | tag. */ | |
1749 | /* Cannot use arc_mach_is_arcv2 (), because gdbarch is not created yet. */ | |
1750 | const int is_arcv2 = (info.bfd_arch_info->mach == bfd_mach_arc_arcv2); | |
fa9c2a59 | 1751 | bool is_reduced_rf; |
ad0a504f AK |
1752 | const char *const *core_regs; |
1753 | const char *core_feature_name; | |
1754 | ||
817a7585 | 1755 | /* If target doesn't provide a description, use the default ones. */ |
ad0a504f AK |
1756 | if (!tdesc_has_registers (tdesc_loc)) |
1757 | { | |
1758 | if (is_arcv2) | |
817a7585 | 1759 | tdesc_loc = arc_read_description (ARC_SYS_TYPE_ARCV2); |
ad0a504f | 1760 | else |
817a7585 | 1761 | tdesc_loc = arc_read_description (ARC_SYS_TYPE_ARCOMPACT); |
ad0a504f AK |
1762 | } |
1763 | else | |
1764 | { | |
1765 | if (arc_debug) | |
1766 | debug_printf ("arc: Using provided register set.\n"); | |
1767 | } | |
1768 | gdb_assert (tdesc_loc != NULL); | |
1769 | ||
1770 | /* Now we can search for base registers. Core registers can be either full | |
1771 | or reduced. Summary: | |
1772 | ||
1773 | - core.v2 + aux-minimal | |
1774 | - core-reduced.v2 + aux-minimal | |
1775 | - core.arcompact + aux-minimal | |
1776 | ||
1777 | NB: It is entirely feasible to have ARCompact with reduced core regs, but | |
1778 | we ignore that because GCC doesn't support that and at the same time | |
1779 | ARCompact is considered obsolete, so there is not much reason to support | |
1780 | that. */ | |
1781 | const struct tdesc_feature *feature | |
1782 | = tdesc_find_feature (tdesc_loc, core_v2_feature_name); | |
1783 | if (feature != NULL) | |
1784 | { | |
1785 | /* Confirm that register and architecture match, to prevent accidents in | |
1786 | some situations. This code will trigger an error if: | |
1787 | ||
1788 | 1. XML tdesc doesn't specify arch explicitly, registers are for arch | |
1789 | X, but ELF specifies arch Y. | |
1790 | ||
1791 | 2. XML tdesc specifies arch X, but contains registers for arch Y. | |
1792 | ||
1793 | It will not protect from case where XML or ELF specify arch X, | |
1794 | registers are for the same arch X, but the real target is arch Y. To | |
1795 | detect this case we need to check IDENTITY register. */ | |
1796 | if (!is_arcv2) | |
1797 | { | |
1798 | arc_print (_("Error: ARC v2 target description supplied for " | |
1799 | "non-ARCv2 target.\n")); | |
fbdf05a1 | 1800 | return false; |
ad0a504f AK |
1801 | } |
1802 | ||
fa9c2a59 | 1803 | is_reduced_rf = false; |
ad0a504f AK |
1804 | core_feature_name = core_v2_feature_name; |
1805 | core_regs = core_v2_register_names; | |
1806 | } | |
1807 | else | |
1808 | { | |
1809 | feature = tdesc_find_feature (tdesc_loc, core_reduced_v2_feature_name); | |
1810 | if (feature != NULL) | |
1811 | { | |
1812 | if (!is_arcv2) | |
1813 | { | |
1814 | arc_print (_("Error: ARC v2 target description supplied for " | |
1815 | "non-ARCv2 target.\n")); | |
fbdf05a1 | 1816 | return false; |
ad0a504f AK |
1817 | } |
1818 | ||
fa9c2a59 | 1819 | is_reduced_rf = true; |
ad0a504f AK |
1820 | core_feature_name = core_reduced_v2_feature_name; |
1821 | core_regs = core_v2_register_names; | |
1822 | } | |
1823 | else | |
1824 | { | |
1825 | feature = tdesc_find_feature (tdesc_loc, | |
1826 | core_arcompact_feature_name); | |
1827 | if (feature != NULL) | |
1828 | { | |
1829 | if (is_arcv2) | |
1830 | { | |
1831 | arc_print (_("Error: ARCompact target description supplied " | |
1832 | "for non-ARCompact target.\n")); | |
fbdf05a1 | 1833 | return false; |
ad0a504f AK |
1834 | } |
1835 | ||
fa9c2a59 | 1836 | is_reduced_rf = false; |
ad0a504f AK |
1837 | core_feature_name = core_arcompact_feature_name; |
1838 | core_regs = core_arcompact_register_names; | |
1839 | } | |
1840 | else | |
1841 | { | |
1842 | arc_print (_("Error: Couldn't find core register feature in " | |
1843 | "supplied target description.")); | |
fbdf05a1 | 1844 | return false; |
ad0a504f AK |
1845 | } |
1846 | } | |
1847 | } | |
1848 | ||
1849 | struct tdesc_arch_data *tdesc_data_loc = tdesc_data_alloc (); | |
1850 | ||
1851 | gdb_assert (feature != NULL); | |
1852 | int valid_p = 1; | |
1853 | ||
1854 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) | |
1855 | { | |
1856 | /* If rf16, then skip extra registers. */ | |
1857 | if (is_reduced_rf && ((i >= ARC_R4_REGNUM && i <= ARC_R9_REGNUM) | |
1858 | || (i >= ARC_R16_REGNUM && i <= ARC_R25_REGNUM))) | |
1859 | continue; | |
1860 | ||
1861 | valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, | |
1862 | core_regs[i]); | |
1863 | ||
1864 | /* - Ignore errors in extension registers - they are optional. | |
1865 | - Ignore missing ILINK because it doesn't make sense for Linux. | |
1866 | - Ignore missing ILINK2 when architecture is ARCompact, because it | |
1867 | doesn't make sense for Linux targets. | |
1868 | ||
1869 | In theory those optional registers should be in separate features, but | |
1870 | that would create numerous but tiny features, which looks like an | |
1871 | overengineering of a rather simple task. */ | |
1872 | if (!valid_p && (i <= ARC_SP_REGNUM || i == ARC_BLINK_REGNUM | |
1873 | || i == ARC_LP_COUNT_REGNUM || i == ARC_PCL_REGNUM | |
1874 | || (i == ARC_R30_REGNUM && is_arcv2))) | |
1875 | { | |
1876 | arc_print (_("Error: Cannot find required register `%s' in " | |
1877 | "feature `%s'.\n"), core_regs[i], core_feature_name); | |
1878 | tdesc_data_cleanup (tdesc_data_loc); | |
fbdf05a1 | 1879 | return false; |
ad0a504f AK |
1880 | } |
1881 | } | |
1882 | ||
30baf67b | 1883 | /* Mandatory AUX registers are intentionally few and are common between |
ad0a504f AK |
1884 | ARCompact and ARC v2, so same code can be used for both. */ |
1885 | feature = tdesc_find_feature (tdesc_loc, aux_minimal_feature_name); | |
1886 | if (feature == NULL) | |
1887 | { | |
1888 | arc_print (_("Error: Cannot find required feature `%s' in supplied " | |
1889 | "target description.\n"), aux_minimal_feature_name); | |
1890 | tdesc_data_cleanup (tdesc_data_loc); | |
fbdf05a1 | 1891 | return false; |
ad0a504f AK |
1892 | } |
1893 | ||
1894 | for (int i = ARC_FIRST_AUX_REGNUM; i <= ARC_LAST_AUX_REGNUM; i++) | |
1895 | { | |
1896 | const char *name = aux_minimal_register_names[i - ARC_FIRST_AUX_REGNUM]; | |
1897 | valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, name); | |
1898 | if (!valid_p) | |
1899 | { | |
1900 | arc_print (_("Error: Cannot find required register `%s' " | |
1901 | "in feature `%s'.\n"), | |
1902 | name, tdesc_feature_name (feature)); | |
1903 | tdesc_data_cleanup (tdesc_data_loc); | |
fbdf05a1 | 1904 | return false; |
ad0a504f AK |
1905 | } |
1906 | } | |
1907 | ||
1908 | *tdesc = tdesc_loc; | |
1909 | *tdesc_data = tdesc_data_loc; | |
1910 | ||
fbdf05a1 | 1911 | return true; |
ad0a504f AK |
1912 | } |
1913 | ||
e11fb955 TT |
1914 | /* Implement the type_align gdbarch function. */ |
1915 | ||
1916 | static ULONGEST | |
1917 | arc_type_align (struct gdbarch *gdbarch, struct type *type) | |
1918 | { | |
5561fc30 AB |
1919 | switch (TYPE_CODE (type)) |
1920 | { | |
1921 | case TYPE_CODE_PTR: | |
1922 | case TYPE_CODE_FUNC: | |
1923 | case TYPE_CODE_FLAGS: | |
1924 | case TYPE_CODE_INT: | |
1925 | case TYPE_CODE_RANGE: | |
1926 | case TYPE_CODE_FLT: | |
1927 | case TYPE_CODE_ENUM: | |
1928 | case TYPE_CODE_REF: | |
1929 | case TYPE_CODE_RVALUE_REF: | |
1930 | case TYPE_CODE_CHAR: | |
1931 | case TYPE_CODE_BOOL: | |
1932 | case TYPE_CODE_DECFLOAT: | |
1933 | case TYPE_CODE_METHODPTR: | |
1934 | case TYPE_CODE_MEMBERPTR: | |
1935 | type = check_typedef (type); | |
1936 | return std::min<ULONGEST> (4, TYPE_LENGTH (type)); | |
1937 | default: | |
1938 | return 0; | |
1939 | } | |
e11fb955 TT |
1940 | } |
1941 | ||
ad0a504f AK |
1942 | /* Implement the "init" gdbarch method. */ |
1943 | ||
1944 | static struct gdbarch * | |
1945 | arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1946 | { | |
1947 | const struct target_desc *tdesc; | |
1948 | struct tdesc_arch_data *tdesc_data; | |
1949 | ||
1950 | if (arc_debug) | |
1951 | debug_printf ("arc: Architecture initialization.\n"); | |
1952 | ||
1953 | if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) | |
1954 | return NULL; | |
1955 | ||
b845c31e AK |
1956 | /* Allocate the ARC-private target-dependent information structure, and the |
1957 | GDB target-independent information structure. */ | |
1958 | struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); | |
aaf43c48 | 1959 | tdep->jb_pc = -1; /* No longjmp support by default. */ |
b845c31e | 1960 | struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); |
ad0a504f AK |
1961 | |
1962 | /* Data types. */ | |
1963 | set_gdbarch_short_bit (gdbarch, 16); | |
1964 | set_gdbarch_int_bit (gdbarch, 32); | |
1965 | set_gdbarch_long_bit (gdbarch, 32); | |
1966 | set_gdbarch_long_long_bit (gdbarch, 64); | |
e11fb955 | 1967 | set_gdbarch_type_align (gdbarch, arc_type_align); |
ad0a504f AK |
1968 | set_gdbarch_float_bit (gdbarch, 32); |
1969 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1970 | set_gdbarch_double_bit (gdbarch, 64); | |
1971 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1972 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1973 | set_gdbarch_addr_bit (gdbarch, 32); | |
1974 | set_gdbarch_char_signed (gdbarch, 0); | |
1975 | ||
1976 | set_gdbarch_write_pc (gdbarch, arc_write_pc); | |
1977 | ||
1978 | set_gdbarch_virtual_frame_pointer (gdbarch, arc_virtual_frame_pointer); | |
1979 | ||
1980 | /* tdesc_use_registers expects gdbarch_num_regs to return number of registers | |
1981 | parsed by gdbarch_init, and then it will add all of the remaining | |
1982 | registers and will increase number of registers. */ | |
1983 | set_gdbarch_num_regs (gdbarch, ARC_LAST_REGNUM + 1); | |
1984 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
1985 | set_gdbarch_sp_regnum (gdbarch, ARC_SP_REGNUM); | |
1986 | set_gdbarch_pc_regnum (gdbarch, ARC_PC_REGNUM); | |
1987 | set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM); | |
1988 | set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */ | |
1989 | ||
ad0a504f AK |
1990 | set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call); |
1991 | set_gdbarch_push_dummy_code (gdbarch, arc_push_dummy_code); | |
1992 | ||
1993 | set_gdbarch_cannot_fetch_register (gdbarch, arc_cannot_fetch_register); | |
1994 | set_gdbarch_cannot_store_register (gdbarch, arc_cannot_store_register); | |
1995 | ||
1996 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
1997 | ||
1998 | set_gdbarch_return_value (gdbarch, arc_return_value); | |
1999 | ||
2000 | set_gdbarch_skip_prologue (gdbarch, arc_skip_prologue); | |
2001 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2002 | ||
04180708 YQ |
2003 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arc_breakpoint_kind_from_pc); |
2004 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arc_sw_breakpoint_from_kind); | |
ad0a504f AK |
2005 | |
2006 | /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */ | |
2007 | if (!arc_mach_is_arc600 (gdbarch)) | |
2008 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2009 | else | |
2010 | set_gdbarch_decr_pc_after_break (gdbarch, 2); | |
2011 | ||
ad0a504f AK |
2012 | set_gdbarch_frame_align (gdbarch, arc_frame_align); |
2013 | ||
a87dc45a AK |
2014 | set_gdbarch_print_insn (gdbarch, arc_delayed_print_insn); |
2015 | ||
ad0a504f AK |
2016 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
2017 | ||
2018 | /* "nonsteppable" watchpoint means that watchpoint triggers before | |
2019 | instruction is committed, therefore it is required to remove watchpoint | |
2020 | to step though instruction that triggers it. ARC watchpoints trigger | |
2021 | only after instruction is committed, thus there is no need to remove | |
2022 | them. In fact on ARC watchpoint for memory writes may trigger with more | |
2023 | significant delay, like one or two instructions, depending on type of | |
2024 | memory where write is performed (CCM or external) and next instruction | |
2025 | after the memory write. */ | |
2026 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 0); | |
2027 | ||
2028 | /* This doesn't include possible long-immediate value. */ | |
2029 | set_gdbarch_max_insn_length (gdbarch, 4); | |
2030 | ||
2031 | /* Frame unwinders and sniffers. */ | |
2032 | dwarf2_frame_set_init_reg (gdbarch, arc_dwarf2_frame_init_reg); | |
2033 | dwarf2_append_unwinders (gdbarch); | |
2034 | frame_unwind_append_unwinder (gdbarch, &arc_frame_unwind); | |
2035 | frame_base_set_default (gdbarch, &arc_normal_base); | |
2036 | ||
2037 | /* Setup stuff specific to a particular environment (baremetal or Linux). | |
2038 | It can override functions set earlier. */ | |
2039 | gdbarch_init_osabi (info, gdbarch); | |
2040 | ||
aaf43c48 AK |
2041 | if (tdep->jb_pc >= 0) |
2042 | set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target); | |
2043 | ||
a87dc45a AK |
2044 | /* Disassembler options. Enforce CPU if it was specified in XML target |
2045 | description, otherwise use default method of determining CPU (ELF private | |
2046 | header). */ | |
2047 | if (info.target_desc != NULL) | |
2048 | { | |
2049 | const struct bfd_arch_info *tdesc_arch | |
2050 | = tdesc_architecture (info.target_desc); | |
2051 | if (tdesc_arch != NULL) | |
2052 | { | |
2053 | xfree (arc_disassembler_options); | |
2054 | /* FIXME: It is not really good to change disassembler options | |
2055 | behind the scene, because that might override options | |
2056 | specified by the user. However as of now ARC doesn't support | |
2057 | `set disassembler-options' hence this code is the only place | |
2058 | where options are changed. It also changes options for all | |
2059 | existing gdbarches, which also can be problematic, if | |
2060 | arc_gdbarch_init will start reusing existing gdbarch | |
2061 | instances. */ | |
56d704da AK |
2062 | /* Target description specifies a BFD architecture, which is |
2063 | different from ARC cpu, as accepted by disassembler (and most | |
2064 | other ARC tools), because cpu values are much more fine grained - | |
2065 | there can be multiple cpu values per single BFD architecture. As | |
2066 | a result this code should translate architecture to some cpu | |
2067 | value. Since there is no info on exact cpu configuration, it is | |
2068 | best to use the most feature-rich CPU, so that disassembler will | |
2069 | recognize all instructions available to the specified | |
2070 | architecture. */ | |
2071 | switch (tdesc_arch->mach) | |
2072 | { | |
2073 | case bfd_mach_arc_arc601: | |
2074 | arc_disassembler_options = xstrdup ("cpu=arc601"); | |
2075 | break; | |
2076 | case bfd_mach_arc_arc600: | |
2077 | arc_disassembler_options = xstrdup ("cpu=arc600"); | |
2078 | break; | |
2079 | case bfd_mach_arc_arc700: | |
2080 | arc_disassembler_options = xstrdup ("cpu=arc700"); | |
2081 | break; | |
2082 | case bfd_mach_arc_arcv2: | |
2083 | /* Machine arcv2 has three arches: ARCv2, EM and HS; where ARCv2 | |
2084 | is treated as EM. */ | |
2085 | if (arc_arch_is_hs (tdesc_arch)) | |
2086 | arc_disassembler_options = xstrdup ("cpu=hs38_linux"); | |
2087 | else | |
2088 | arc_disassembler_options = xstrdup ("cpu=em4_fpuda"); | |
2089 | break; | |
2090 | default: | |
2091 | arc_disassembler_options = NULL; | |
2092 | break; | |
2093 | } | |
a87dc45a AK |
2094 | set_gdbarch_disassembler_options (gdbarch, |
2095 | &arc_disassembler_options); | |
2096 | } | |
2097 | } | |
2098 | ||
ad0a504f AK |
2099 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
2100 | ||
2101 | return gdbarch; | |
2102 | } | |
2103 | ||
2104 | /* Implement the "dump_tdep" gdbarch method. */ | |
2105 | ||
2106 | static void | |
2107 | arc_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
2108 | { | |
aaf43c48 AK |
2109 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2110 | ||
2111 | fprintf_unfiltered (file, "arc_dump_tdep: jb_pc = %i\n", tdep->jb_pc); | |
ad0a504f AK |
2112 | } |
2113 | ||
3be78afd AK |
2114 | /* Wrapper for "maintenance print arc" list of commands. */ |
2115 | ||
2116 | static void | |
981a3fb3 | 2117 | maintenance_print_arc_command (const char *args, int from_tty) |
3be78afd AK |
2118 | { |
2119 | cmd_show_list (maintenance_print_arc_list, from_tty, ""); | |
2120 | } | |
2121 | ||
eea78757 AK |
2122 | /* This command accepts single argument - address of instruction to |
2123 | disassemble. */ | |
2124 | ||
2125 | static void | |
57f5a81b | 2126 | dump_arc_instruction_command (const char *args, int from_tty) |
eea78757 AK |
2127 | { |
2128 | struct value *val; | |
2129 | if (args != NULL && strlen (args) > 0) | |
2130 | val = evaluate_expression (parse_expression (args).get ()); | |
2131 | else | |
2132 | val = access_value_history (0); | |
2133 | record_latest_value (val); | |
2134 | ||
2135 | CORE_ADDR address = value_as_address (val); | |
2136 | struct arc_instruction insn; | |
2137 | struct disassemble_info di = arc_disassemble_info (target_gdbarch ()); | |
2138 | arc_insn_decode (address, &di, arc_delayed_print_insn, &insn); | |
2139 | arc_insn_dump (insn); | |
2140 | } | |
2141 | ||
817a7585 AK |
2142 | /* See arc-tdep.h. */ |
2143 | ||
2144 | const target_desc * | |
2145 | arc_read_description (arc_sys_type sys_type) | |
2146 | { | |
2147 | if (arc_debug) | |
2148 | debug_printf ("arc: Reading target description for \"%s\".\n", | |
2149 | arc_sys_type_to_str (sys_type)); | |
2150 | ||
2151 | gdb_assert ((sys_type >= 0) && (sys_type < ARC_SYS_TYPE_NUM)); | |
2152 | struct target_desc *tdesc = tdesc_arc_list[sys_type]; | |
2153 | ||
2154 | if (tdesc == nullptr) | |
2155 | { | |
2156 | tdesc = arc_create_target_description (sys_type); | |
2157 | tdesc_arc_list[sys_type] = tdesc; | |
2158 | ||
2159 | if (arc_debug) | |
2160 | { | |
2161 | const char *arch = tdesc_architecture_name (tdesc); | |
2162 | const char *abi = tdesc_osabi_name (tdesc); | |
2163 | arch = arch != NULL ? arch : ""; | |
2164 | abi = abi != NULL ? abi : ""; | |
2165 | debug_printf ("arc: Created target description for " | |
2166 | "\"%s\": arch=\"%s\", ABI=\"%s\"\n", | |
2167 | arc_sys_type_to_str (sys_type), arch, abi); | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | return tdesc; | |
2172 | } | |
2173 | ||
6c265988 | 2174 | void _initialize_arc_tdep (); |
ad0a504f | 2175 | void |
6c265988 | 2176 | _initialize_arc_tdep () |
ad0a504f AK |
2177 | { |
2178 | gdbarch_register (bfd_arch_arc, arc_gdbarch_init, arc_dump_tdep); | |
2179 | ||
ad0a504f AK |
2180 | /* Register ARC-specific commands with gdb. */ |
2181 | ||
3be78afd AK |
2182 | /* Add root prefix command for "maintenance print arc" commands. */ |
2183 | add_prefix_cmd ("arc", class_maintenance, maintenance_print_arc_command, | |
2184 | _("ARC-specific maintenance commands for printing GDB " | |
2185 | "internal state."), | |
2186 | &maintenance_print_arc_list, "maintenance print arc ", 0, | |
2187 | &maintenanceprintlist); | |
2188 | ||
eea78757 AK |
2189 | add_cmd ("arc-instruction", class_maintenance, |
2190 | dump_arc_instruction_command, | |
2191 | _("Dump arc_instruction structure for specified address."), | |
2192 | &maintenance_print_arc_list); | |
2193 | ||
ad0a504f AK |
2194 | /* Debug internals for ARC GDB. */ |
2195 | add_setshow_zinteger_cmd ("arc", class_maintenance, | |
2196 | &arc_debug, | |
2197 | _("Set ARC specific debugging."), | |
2198 | _("Show ARC specific debugging."), | |
2199 | _("Non-zero enables ARC specific debugging."), | |
2200 | NULL, NULL, &setdebuglist, &showdebuglist); | |
2201 | } |