Commit | Line | Data |
---|---|---|
85102364 | 1 | /* Target dependent code for ARC architecture, for GDB. |
ad0a504f | 2 | |
b811d2c2 | 3 | Copyright 2005-2020 Free Software Foundation, Inc. |
ad0a504f AK |
4 | Contributed by Synopsys Inc. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef ARC_TDEP_H | |
22 | #define ARC_TDEP_H | |
23 | ||
24 | /* Need disassemble_info. */ | |
25 | #include "dis-asm.h" | |
22459524 | 26 | #include "gdbarch.h" |
817a7585 | 27 | #include "arch/arc.h" |
ad0a504f | 28 | |
296ec4fa AK |
29 | /* To simplify GDB code this enum assumes that internal regnums should be same |
30 | as architectural register numbers, i.e. PCL regnum is 63. This allows to | |
31 | use internal GDB regnums as architectural numbers when dealing with | |
32 | instruction encodings, for example when analyzing what are the registers | |
33 | saved in function prologue. */ | |
34 | ||
ad0a504f AK |
35 | enum arc_regnum |
36 | { | |
37 | /* Core registers. */ | |
38 | ARC_R0_REGNUM = 0, | |
ad0a504f AK |
39 | ARC_R1_REGNUM = 1, |
40 | ARC_R4_REGNUM = 4, | |
41 | ARC_R7_REGNUM = 7, | |
42 | ARC_R9_REGNUM = 9, | |
43 | ARC_R13_REGNUM = 13, | |
44 | ARC_R16_REGNUM = 16, | |
45 | ARC_R25_REGNUM = 25, | |
46 | /* Global data pointer. */ | |
47 | ARC_GP_REGNUM, | |
48 | /* Frame pointer. */ | |
49 | ARC_FP_REGNUM, | |
50 | /* Stack pointer. */ | |
51 | ARC_SP_REGNUM, | |
52 | /* Return address from interrupt. */ | |
53 | ARC_ILINK_REGNUM, | |
54 | ARC_R30_REGNUM, | |
55 | /* Return address from function. */ | |
56 | ARC_BLINK_REGNUM, | |
995d3a19 SV |
57 | /* Accumulator registers. */ |
58 | ARC_R58_REGNUM = 58, | |
59 | ARC_R59_REGNUM, | |
ad0a504f AK |
60 | /* Zero-delay loop counter. */ |
61 | ARC_LP_COUNT_REGNUM = 60, | |
296ec4fa AK |
62 | /* Reserved register number. There should never be a register with such |
63 | number, this name is needed only for a sanity check in | |
64 | arc_cannot_(fetch|store)_register. */ | |
65 | ARC_RESERVED_REGNUM, | |
66 | /* Long-immediate value. This is not a physical register - if instruction | |
67 | has register 62 as an operand, then this operand is a literal value | |
68 | stored in the instruction memory right after the instruction itself. | |
69 | This value is required in this enumeration as an architectural number | |
70 | for instruction analysis. */ | |
71 | ARC_LIMM_REGNUM, | |
ad0a504f AK |
72 | /* Program counter, aligned to 4-bytes, read-only. */ |
73 | ARC_PCL_REGNUM, | |
74 | ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM, | |
995d3a19 | 75 | |
ad0a504f AK |
76 | /* AUX registers. */ |
77 | /* Actual program counter. */ | |
78 | ARC_PC_REGNUM, | |
79 | ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM, | |
80 | /* Status register. */ | |
81 | ARC_STATUS32_REGNUM, | |
995d3a19 SV |
82 | /* Zero-delay loop start instruction. */ |
83 | ARC_LP_START_REGNUM, | |
84 | /* Zero-delay loop next-after-last instruction. */ | |
85 | ARC_LP_END_REGNUM, | |
86 | /* Branch target address. */ | |
87 | ARC_BTA_REGNUM, | |
88 | ARC_LAST_AUX_REGNUM = ARC_BTA_REGNUM, | |
89 | ARC_LAST_REGNUM = ARC_LAST_AUX_REGNUM, | |
ad0a504f AK |
90 | |
91 | /* Additional ABI constants. */ | |
92 | ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM, | |
93 | ARC_LAST_ARG_REGNUM = ARC_R7_REGNUM, | |
94 | ARC_FIRST_CALLEE_SAVED_REGNUM = ARC_R13_REGNUM, | |
95 | ARC_LAST_CALLEE_SAVED_REGNUM = ARC_R25_REGNUM, | |
96 | }; | |
97 | ||
98 | /* Number of bytes in ARC register. All ARC registers are considered 32-bit. | |
99 | Those registers, which are actually shorter has zero-on-read for extra bits. | |
100 | Longer registers are represented as pairs of 32-bit registers. */ | |
101 | #define ARC_REGISTER_SIZE 4 | |
102 | ||
8d7f0635 AK |
103 | /* STATUS32 register: hardware loops disabled bit. */ |
104 | #define ARC_STATUS32_L_MASK (1 << 12) | |
105 | /* STATUS32 register: current instruction is a delay slot. */ | |
106 | #define ARC_STATUS32_DE_MASK (1 << 6) | |
107 | ||
ad0a504f AK |
108 | #define arc_print(fmt, args...) fprintf_unfiltered (gdb_stdlog, fmt, ##args) |
109 | ||
110 | extern int arc_debug; | |
111 | ||
b845c31e AK |
112 | /* Target-dependent information. */ |
113 | ||
114 | struct gdbarch_tdep | |
115 | { | |
aaf43c48 AK |
116 | /* Offset to PC value in jump buffer. If this is negative, longjmp |
117 | support will be disabled. */ | |
118 | int jb_pc; | |
fdd8731b SV |
119 | |
120 | /* Whether target has hardware (aka zero-delay) loops. */ | |
121 | bool has_hw_loops; | |
b845c31e AK |
122 | }; |
123 | ||
ad0a504f AK |
124 | /* Utility functions used by other ARC-specific modules. */ |
125 | ||
126 | static inline int | |
127 | arc_mach_is_arc600 (struct gdbarch *gdbarch) | |
128 | { | |
129 | return (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc600 | |
130 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc601); | |
131 | } | |
132 | ||
133 | static inline int | |
134 | arc_mach_is_arc700 (struct gdbarch *gdbarch) | |
135 | { | |
136 | return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc700; | |
137 | } | |
138 | ||
139 | static inline int | |
140 | arc_mach_is_arcv2 (struct gdbarch *gdbarch) | |
141 | { | |
142 | return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2; | |
143 | } | |
144 | ||
56d704da AK |
145 | /* ARC EM and ARC HS are unique BFD arches, however they share the same machine |
146 | number as "ARCv2". */ | |
147 | ||
148 | static inline bool | |
149 | arc_arch_is_hs (const struct bfd_arch_info* arch) | |
150 | { | |
151 | return startswith (arch->printable_name, "HS"); | |
152 | } | |
153 | ||
154 | static inline bool | |
155 | arc_arch_is_em (const struct bfd_arch_info* arch) | |
156 | { | |
157 | return startswith (arch->printable_name, "EM"); | |
158 | } | |
159 | ||
eea78757 AK |
160 | /* Function to access ARC disassembler. Underlying opcodes disassembler will |
161 | print an instruction into stream specified in the INFO, so if it is | |
162 | undesired, then this stream should be set to some invisible stream, but it | |
163 | can't be set to an actual NULL value - that would cause a crash. */ | |
164 | int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info); | |
165 | ||
166 | /* Return properly initialized disassemble_info for ARC disassembler - it will | |
167 | not print disassembled instructions to stderr. */ | |
168 | ||
169 | struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch); | |
170 | ||
171 | /* Get branch/jump target address for the INSN. Note that this function | |
172 | returns branch target and doesn't evaluate if this branch is taken or not. | |
173 | For the indirect jumps value depends in register state, hence can change. | |
174 | It is an error to call this function for a non-branch instruction. */ | |
175 | ||
176 | CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn); | |
177 | ||
178 | /* Get address of next instruction after INSN, assuming linear execution (no | |
179 | taken branches). If instruction has a delay slot, then returned value will | |
180 | point at the instruction in delay slot. That is - "address of instruction + | |
181 | instruction length with LIMM". */ | |
182 | ||
183 | CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn); | |
184 | ||
ad0a504f | 185 | #endif /* ARC_TDEP_H */ |