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1 | /* Copyright (C) 2009-2015 Free Software Foundation, Inc. |
2 | Contributed by ARM Ltd. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "common-defs.h" | |
20 | #include "aarch64-insn.h" | |
21 | ||
22 | /* Toggle this file's internal debugging dump. */ | |
23 | int aarch64_debug = 0; | |
24 | ||
25 | /* Extract a signed value from a bit field within an instruction | |
26 | encoding. | |
27 | ||
28 | INSN is the instruction opcode. | |
29 | ||
30 | WIDTH specifies the width of the bit field to extract (in bits). | |
31 | ||
32 | OFFSET specifies the least significant bit of the field where bits | |
33 | are numbered zero counting from least to most significant. */ | |
34 | ||
35 | static int32_t | |
36 | extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset) | |
37 | { | |
38 | unsigned shift_l = sizeof (int32_t) * 8 - (offset + width); | |
39 | unsigned shift_r = sizeof (int32_t) * 8 - width; | |
40 | ||
41 | return ((int32_t) insn << shift_l) >> shift_r; | |
42 | } | |
43 | ||
44 | /* Determine if specified bits within an instruction opcode matches a | |
45 | specific pattern. | |
46 | ||
47 | INSN is the instruction opcode. | |
48 | ||
49 | MASK specifies the bits within the opcode that are to be tested | |
50 | agsinst for a match with PATTERN. */ | |
51 | ||
52 | static int | |
53 | decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern) | |
54 | { | |
55 | return (insn & mask) == pattern; | |
56 | } | |
57 | ||
6ec5f4be | 58 | /* Decode an opcode if it represents an ADR or ADRP instruction. |
787749ea PL |
59 | |
60 | ADDR specifies the address of the opcode. | |
61 | INSN specifies the opcode to test. | |
6ec5f4be | 62 | IS_ADRP receives the 'op' field from the decoded instruction. |
787749ea | 63 | RD receives the 'rd' field from the decoded instruction. |
6ec5f4be | 64 | OFFSET receives the 'immhi:immlo' field from the decoded instruction. |
787749ea PL |
65 | |
66 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
67 | ||
68 | int | |
6ec5f4be PL |
69 | aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp, |
70 | unsigned *rd, int32_t *offset) | |
787749ea | 71 | { |
6ec5f4be PL |
72 | /* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */ |
73 | /* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */ | |
74 | if (decode_masked_match (insn, 0x1f000000, 0x10000000)) | |
787749ea | 75 | { |
6ec5f4be PL |
76 | uint32_t immlo = (insn >> 29) & 0x3; |
77 | int32_t immhi = extract_signed_bitfield (insn, 19, 5) << 2; | |
78 | ||
79 | *is_adrp = (insn >> 31) & 0x1; | |
787749ea PL |
80 | *rd = (insn >> 0) & 0x1f; |
81 | ||
6ec5f4be PL |
82 | if (*is_adrp) |
83 | { | |
84 | /* The ADRP instruction has an offset with a -/+ 4GB range, | |
85 | encoded as (immhi:immlo * 4096). */ | |
86 | *offset = (immhi | immlo) * 4096; | |
87 | } | |
88 | else | |
89 | *offset = (immhi | immlo); | |
90 | ||
787749ea PL |
91 | if (aarch64_debug) |
92 | { | |
6ec5f4be PL |
93 | debug_printf ("decode: 0x%s 0x%x %s x%u, #?\n", |
94 | core_addr_to_string_nz (addr), insn, | |
95 | *is_adrp ? "adrp" : "adr", *rd); | |
787749ea PL |
96 | } |
97 | return 1; | |
98 | } | |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* Decode an opcode if it represents an branch immediate or branch | |
103 | and link immediate instruction. | |
104 | ||
105 | ADDR specifies the address of the opcode. | |
106 | INSN specifies the opcode to test. | |
107 | IS_BL receives the 'op' bit from the decoded instruction. | |
108 | OFFSET receives the immediate offset from the decoded instruction. | |
109 | ||
110 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
111 | ||
112 | int | |
113 | aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, | |
114 | int32_t *offset) | |
115 | { | |
116 | /* b 0001 01ii iiii iiii iiii iiii iiii iiii */ | |
117 | /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */ | |
118 | if (decode_masked_match (insn, 0x7c000000, 0x14000000)) | |
119 | { | |
120 | *is_bl = (insn >> 31) & 0x1; | |
121 | *offset = extract_signed_bitfield (insn, 26, 0) << 2; | |
122 | ||
123 | if (aarch64_debug) | |
124 | { | |
125 | debug_printf ("decode: 0x%s 0x%x %s 0x%s\n", | |
126 | core_addr_to_string_nz (addr), insn, | |
127 | *is_bl ? "bl" : "b", | |
128 | core_addr_to_string_nz (addr + *offset)); | |
129 | } | |
130 | ||
131 | return 1; | |
132 | } | |
133 | return 0; | |
134 | } | |
135 | ||
136 | /* Decode an opcode if it represents a conditional branch instruction. | |
137 | ||
138 | ADDR specifies the address of the opcode. | |
139 | INSN specifies the opcode to test. | |
140 | COND receives the branch condition field from the decoded | |
141 | instruction. | |
142 | OFFSET receives the immediate offset from the decoded instruction. | |
143 | ||
144 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
145 | ||
146 | int | |
147 | aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, | |
148 | int32_t *offset) | |
149 | { | |
150 | /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */ | |
151 | if (decode_masked_match (insn, 0xff000010, 0x54000000)) | |
152 | { | |
153 | *cond = (insn >> 0) & 0xf; | |
154 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
155 | ||
156 | if (aarch64_debug) | |
157 | { | |
158 | debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n", | |
159 | core_addr_to_string_nz (addr), insn, *cond, | |
160 | core_addr_to_string_nz (addr + *offset)); | |
161 | } | |
162 | return 1; | |
163 | } | |
164 | return 0; | |
165 | } | |
166 | ||
167 | /* Decode an opcode if it represents a CBZ or CBNZ instruction. | |
168 | ||
169 | ADDR specifies the address of the opcode. | |
170 | INSN specifies the opcode to test. | |
171 | IS64 receives the 'sf' field from the decoded instruction. | |
172 | IS_CBNZ receives the 'op' field from the decoded instruction. | |
173 | RN receives the 'rn' field from the decoded instruction. | |
174 | OFFSET receives the 'imm19' field from the decoded instruction. | |
175 | ||
176 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
177 | ||
178 | int | |
179 | aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz, | |
180 | unsigned *rn, int32_t *offset) | |
181 | { | |
182 | /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
183 | /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */ | |
184 | if (decode_masked_match (insn, 0x7e000000, 0x34000000)) | |
185 | { | |
186 | *rn = (insn >> 0) & 0x1f; | |
187 | *is64 = (insn >> 31) & 0x1; | |
188 | *is_cbnz = (insn >> 24) & 0x1; | |
189 | *offset = extract_signed_bitfield (insn, 19, 5) << 2; | |
190 | ||
191 | if (aarch64_debug) | |
192 | { | |
193 | debug_printf ("decode: 0x%s 0x%x %s 0x%s\n", | |
194 | core_addr_to_string_nz (addr), insn, | |
195 | *is_cbnz ? "cbnz" : "cbz", | |
196 | core_addr_to_string_nz (addr + *offset)); | |
197 | } | |
198 | return 1; | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* Decode an opcode if it represents a TBZ or TBNZ instruction. | |
204 | ||
205 | ADDR specifies the address of the opcode. | |
206 | INSN specifies the opcode to test. | |
207 | IS_TBNZ receives the 'op' field from the decoded instruction. | |
208 | BIT receives the bit position field from the decoded instruction. | |
209 | RT receives 'rt' field from the decoded instruction. | |
210 | IMM receives 'imm' field from the decoded instruction. | |
211 | ||
212 | Return 1 if the opcodes matches and is decoded, otherwise 0. */ | |
213 | ||
214 | int | |
215 | aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, | |
216 | unsigned *bit, unsigned *rt, int32_t *imm) | |
217 | { | |
218 | /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */ | |
219 | /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */ | |
220 | if (decode_masked_match (insn, 0x7e000000, 0x36000000)) | |
221 | { | |
222 | *rt = (insn >> 0) & 0x1f; | |
223 | *is_tbnz = (insn >> 24) & 0x1; | |
224 | *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f); | |
225 | *imm = extract_signed_bitfield (insn, 14, 5) << 2; | |
226 | ||
227 | if (aarch64_debug) | |
228 | { | |
229 | debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n", | |
230 | core_addr_to_string_nz (addr), insn, | |
231 | *is_tbnz ? "tbnz" : "tbz", *rt, *bit, | |
232 | core_addr_to_string_nz (addr + *imm)); | |
233 | } | |
234 | return 1; | |
235 | } | |
236 | return 0; | |
237 | } |