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787749ea PL |
1 | /* Copyright (C) 2009-2015 Free Software Foundation, Inc. |
2 | Contributed by ARM Ltd. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #ifndef AARCH64_INSN_H | |
20 | #define AARCH64_INSN_H 1 | |
21 | ||
22 | extern int aarch64_debug; | |
23 | ||
6ec5f4be PL |
24 | int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp, |
25 | unsigned *rd, int32_t *offset); | |
787749ea PL |
26 | |
27 | int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, | |
28 | int32_t *offset); | |
29 | ||
30 | int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, | |
31 | int32_t *offset); | |
32 | ||
33 | int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, | |
34 | int *is_cbnz, unsigned *rn, int32_t *offset); | |
35 | ||
36 | int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, | |
37 | unsigned *bit, unsigned *rt, int32_t *imm); | |
38 | ||
246994ce YQ |
39 | int aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w, |
40 | int *is64, unsigned *rt, int32_t *offset); | |
41 | ||
42 | /* Data passed to each method of aarch64_insn_visitor. */ | |
43 | ||
44 | struct aarch64_insn_data | |
45 | { | |
46 | /* The instruction address. */ | |
47 | CORE_ADDR insn_addr; | |
48 | }; | |
49 | ||
50 | /* Visit different instructions by different methods. */ | |
51 | ||
52 | struct aarch64_insn_visitor | |
53 | { | |
54 | /* Visit instruction B/BL OFFSET. */ | |
55 | void (*b) (const int is_bl, const int32_t offset, | |
56 | struct aarch64_insn_data *data); | |
57 | ||
58 | /* Visit instruction B.COND OFFSET. */ | |
59 | void (*b_cond) (const unsigned cond, const int32_t offset, | |
60 | struct aarch64_insn_data *data); | |
61 | ||
62 | /* Visit instruction CBZ/CBNZ Rn, OFFSET. */ | |
63 | void (*cb) (const int32_t offset, const int is_cbnz, | |
64 | const unsigned rn, int is64, | |
65 | struct aarch64_insn_data *data); | |
66 | ||
67 | /* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET. */ | |
68 | void (*tb) (const int32_t offset, int is_tbnz, | |
69 | const unsigned rt, unsigned bit, | |
70 | struct aarch64_insn_data *data); | |
71 | ||
72 | /* Visit instruction ADR/ADRP Rd, OFFSET. */ | |
73 | void (*adr) (const int32_t offset, const unsigned rd, | |
74 | const int is_adrp, struct aarch64_insn_data *data); | |
75 | ||
76 | /* Visit instruction LDR/LDRSW Rt, OFFSET. */ | |
77 | void (*ldr_literal) (const int32_t offset, const int is_sw, | |
78 | const unsigned rt, const int is64, | |
79 | struct aarch64_insn_data *data); | |
80 | ||
81 | /* Visit instruction INSN of other kinds. */ | |
82 | void (*others) (const uint32_t insn, struct aarch64_insn_data *data); | |
83 | }; | |
84 | ||
85 | void aarch64_relocate_instruction (uint32_t insn, | |
86 | const struct aarch64_insn_visitor *visitor, | |
87 | struct aarch64_insn_data *data); | |
88 | ||
787749ea | 89 | #endif |