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cc628f3d AH |
1 | /* Common target-dependent functionality for AArch64. |
2 | ||
3666a048 | 3 | Copyright (C) 2017-2021 Free Software Foundation, Inc. |
cc628f3d AH |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef ARCH_AARCH64_H | |
21 | #define ARCH_AARCH64_H | |
22 | ||
268a13a5 | 23 | #include "gdbsupport/tdesc.h" |
da434ccb | 24 | |
eb79b231 LM |
25 | /* Holds information on what architectural features are available. This is |
26 | used to select register sets. */ | |
27 | struct aarch64_features | |
28 | { | |
29 | bool sve = false; | |
30 | bool pauth = false; | |
31 | bool mte = false; | |
32 | }; | |
33 | ||
95228a0d AH |
34 | /* Create the aarch64 target description. A non zero VQ value indicates both |
35 | the presence of SVE and the Vector Quotient - the number of 128bit chunks in | |
6dc0ebde | 36 | an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH |
c1bd443b | 37 | feature. |
95228a0d | 38 | |
c1bd443b LM |
39 | MTE_P indicates the presence of the Memory Tagging Extension feature. */ |
40 | ||
41 | target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p, | |
42 | bool mte_p); | |
da434ccb | 43 | |
739e8682 AH |
44 | /* Register numbers of various important registers. |
45 | Note that on SVE, the Z registers reuse the V register numbers and the V | |
46 | registers become pseudo registers. */ | |
cc628f3d AH |
47 | enum aarch64_regnum |
48 | { | |
49 | AARCH64_X0_REGNUM, /* First integer register. */ | |
50 | AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */ | |
51 | AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */ | |
52 | AARCH64_SP_REGNUM, /* Stack pointer. */ | |
53 | AARCH64_PC_REGNUM, /* Program counter. */ | |
54 | AARCH64_CPSR_REGNUM, /* Current Program Status Register. */ | |
55 | AARCH64_V0_REGNUM, /* First fp/vec register. */ | |
56 | AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */ | |
739e8682 AH |
57 | AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */ |
58 | AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */ | |
cc628f3d AH |
59 | AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */ |
60 | AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */ | |
739e8682 AH |
61 | AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */ |
62 | AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate | |
63 | register. */ | |
64 | AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */ | |
9758a8f8 | 65 | AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */ |
cc628f3d AH |
66 | |
67 | /* Other useful registers. */ | |
68 | AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7, | |
69 | AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8, | |
70 | AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7 | |
71 | }; | |
72 | ||
6afcd2d4 LM |
73 | #define V_REGISTER_SIZE 16 |
74 | ||
c74e7cb9 AH |
75 | /* Pseudo register base numbers. */ |
76 | #define AARCH64_Q0_REGNUM 0 | |
77 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT) | |
78 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) | |
79 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
80 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
81 | #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32) | |
82 | ||
76bed0fd AH |
83 | #define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base) |
84 | #define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1) | |
1ef53e6b | 85 | #define AARCH64_PAUTH_REGS_SIZE (16) |
76bed0fd | 86 | |
cc628f3d AH |
87 | #define AARCH64_X_REGS_NUM 31 |
88 | #define AARCH64_V_REGS_NUM 32 | |
739e8682 AH |
89 | #define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM |
90 | #define AARCH64_SVE_P_REGS_NUM 16 | |
cc628f3d | 91 | #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1 |
739e8682 AH |
92 | #define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1 |
93 | ||
cc628f3d | 94 | |
122394f1 AH |
95 | /* There are a number of ways of expressing the current SVE vector size: |
96 | ||
97 | VL : Vector Length. | |
98 | The number of bytes in an SVE Z register. | |
99 | VQ : Vector Quotient. | |
100 | The number of 128bit chunks in an SVE Z register. | |
9758a8f8 | 101 | VG : Vector Granule. |
122394f1 AH |
102 | The number of 64bit chunks in an SVE Z register. */ |
103 | ||
104 | #define sve_vg_from_vl(vl) ((vl) / 8) | |
105 | #define sve_vl_from_vg(vg) ((vg) * 8) | |
e5a77256 | 106 | #ifndef sve_vq_from_vl |
122394f1 | 107 | #define sve_vq_from_vl(vl) ((vl) / 0x10) |
e5a77256 SDJ |
108 | #endif |
109 | #ifndef sve_vl_from_vq | |
122394f1 | 110 | #define sve_vl_from_vq(vq) ((vq) * 0x10) |
e5a77256 | 111 | #endif |
122394f1 AH |
112 | #define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg))) |
113 | #define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq))) | |
114 | ||
115 | ||
95228a0d AH |
116 | /* Maximum supported VQ value. Increase if required. */ |
117 | #define AARCH64_MAX_SVE_VQ 16 | |
118 | ||
cc628f3d | 119 | #endif /* ARCH_AARCH64_H */ |