[deliverable/binutils-gdb.git] / gdb / arch / arm.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 1988-2016 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_H
#define ARM_H

/* Register numbers of various important registers.  */

enum gdb_regnum {
  ARM_A1_REGNUM = 0,		/* first integer-like argument */
  ARM_A4_REGNUM = 3,		/* last integer-like argument */
  ARM_AP_REGNUM = 11,
  ARM_IP_REGNUM = 12,
  ARM_SP_REGNUM = 13,		/* Contains address of top of stack */
  ARM_LR_REGNUM = 14,		/* address to return to from a function call */
  ARM_PC_REGNUM = 15,		/* Contains program counter */
  ARM_F0_REGNUM = 16,		/* first floating point register */
  ARM_F3_REGNUM = 19,		/* last floating point argument register */
  ARM_F7_REGNUM = 23, 		/* last floating point register */
  ARM_FPS_REGNUM = 24,		/* floating point status register */
  ARM_PS_REGNUM = 25,		/* Contains processor status */
  ARM_WR0_REGNUM,		/* WMMX data registers.  */
  ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  ARM_WC0_REGNUM,		/* WMMX control registers.  */
  ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  ARM_WCGR0_REGNUM,		/* WMMX general purpose registers.  */
  ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  ARM_D0_REGNUM,		/* VFP double-precision registers.  */
  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  ARM_FPSCR_REGNUM,

  ARM_NUM_REGS,

  /* Other useful registers.  */
  ARM_FP_REGNUM = 11,		/* Frame register in ARM code, if used.  */
  THUMB_FP_REGNUM = 7,		/* Frame register in Thumb code, if used.  */
  ARM_NUM_ARG_REGS = 4, 
  ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  ARM_NUM_FP_ARG_REGS = 4,
  ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
};

/* Instruction condition field values.  */
#define INST_EQ		0x0
#define INST_NE		0x1
#define INST_CS		0x2
#define INST_CC		0x3
#define INST_MI		0x4
#define INST_PL		0x5
#define INST_VS		0x6
#define INST_VC		0x7
#define INST_HI		0x8
#define INST_LS		0x9
#define INST_GE		0xa
#define INST_LT		0xb
#define INST_GT		0xc
#define INST_LE		0xd
#define INST_AL		0xe
#define INST_NV		0xf

#define FLAG_N		0x80000000
#define FLAG_Z		0x40000000
#define FLAG_C		0x20000000
#define FLAG_V		0x10000000

#define CPSR_T		0x20

#define XPSR_T		0x01000000

/* Size of integer registers.  */
#define INT_REGISTER_SIZE		4

/* Addresses for calling Thumb functions have the bit 0 set.
   Here are some macros to test, set, or clear bit 0 of addresses.  */
#define IS_THUMB_ADDR(addr)    ((addr) & 1)
#define MAKE_THUMB_ADDR(addr)  ((addr) | 1)
#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)

/* Support routines for instruction parsing.  */
#define submask(x) ((1L << ((x) + 1)) - 1)
#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
#define bit(obj,st) (((obj) >> (st)) & 1)
#define sbits(obj,st,fn) \
  ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
#define BranchDest(addr,instr) \
  ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))

/* Forward declaration.  */
struct regcache;

/* Return the size in bytes of the complete Thumb instruction whose
   first halfword is INST1.  */
int thumb_insn_size (unsigned short inst1);

/* Returns true if the condition evaluates to true.  */
int condition_true (unsigned long cond, unsigned long status_reg);

/* Return number of 1-bits in VAL.  */
int bitcount (unsigned long val);

/* Return 1 if THIS_INSTR might change control flow, 0 otherwise.  */
int arm_instruction_changes_pc (uint32_t this_instr);

/* Return 1 if the 16-bit Thumb instruction INST might change
   control flow, 0 otherwise.  */
int thumb_instruction_changes_pc (unsigned short inst);

/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
   might change control flow, 0 otherwise.  */
int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2);

/* Advance the state of the IT block and return that state.  */
int thumb_advance_itstate (unsigned int itstate);

/* Decode shifted register value.  */

unsigned long shifted_reg_val (struct regcache *regcache,
			       unsigned long inst,
			       int carry,
			       unsigned long pc_val,
			       unsigned long status_reg);

#endif
Commit	Line	Data
ec741292	1	/* Common target dependent code for GDB on ARM systems.
618f726f	2	Copyright (C) 1988-2016 Free Software Foundation, Inc.
ec741292 YQ	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	18
	19	#ifndef ARM_H
	20	#define ARM_H
	21
	22	/* Register numbers of various important registers. */
	23
	24	enum gdb_regnum {
	25	ARM_A1_REGNUM = 0, /* first integer-like argument */
	26	ARM_A4_REGNUM = 3, /* last integer-like argument */
	27	ARM_AP_REGNUM = 11,
	28	ARM_IP_REGNUM = 12,
	29	ARM_SP_REGNUM = 13, /* Contains address of top of stack */
	30	ARM_LR_REGNUM = 14, /* address to return to from a function call */
	31	ARM_PC_REGNUM = 15, /* Contains program counter */
	32	ARM_F0_REGNUM = 16, /* first floating point register */
	33	ARM_F3_REGNUM = 19, /* last floating point argument register */
	34	ARM_F7_REGNUM = 23, /* last floating point register */
	35	ARM_FPS_REGNUM = 24, /* floating point status register */
	36	ARM_PS_REGNUM = 25, /* Contains processor status */
	37	ARM_WR0_REGNUM, /* WMMX data registers. */
	38	ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
	39	ARM_WC0_REGNUM, /* WMMX control registers. */
	40	ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
	41	ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
	42	ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
	43	ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
	44	ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
	45	ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
	46	ARM_D0_REGNUM, /* VFP double-precision registers. */
	47	ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
	48	ARM_FPSCR_REGNUM,
	49
	50	ARM_NUM_REGS,
	51
	52	/* Other useful registers. */
	53	ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
	54	THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
	55	ARM_NUM_ARG_REGS = 4,
	56	ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
	57	ARM_NUM_FP_ARG_REGS = 4,
	58	ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
	59	};
	60
cba7e83f AT	61	/* Instruction condition field values. */
	62	#define INST_EQ 0x0
	63	#define INST_NE 0x1
	64	#define INST_CS 0x2
	65	#define INST_CC 0x3
	66	#define INST_MI 0x4
	67	#define INST_PL 0x5
	68	#define INST_VS 0x6
	69	#define INST_VC 0x7
	70	#define INST_HI 0x8
	71	#define INST_LS 0x9
	72	#define INST_GE 0xa
	73	#define INST_LT 0xb
	74	#define INST_GT 0xc
	75	#define INST_LE 0xd
	76	#define INST_AL 0xe
	77	#define INST_NV 0xf
	78
	79	#define FLAG_N 0x80000000
	80	#define FLAG_Z 0x40000000
	81	#define FLAG_C 0x20000000
	82	#define FLAG_V 0x10000000
	83
	84	#define CPSR_T 0x20
	85
	86	#define XPSR_T 0x01000000
	87
	88	/* Size of integer registers. */
	89	#define INT_REGISTER_SIZE 4
	90
8689682c AT	91	/* Addresses for calling Thumb functions have the bit 0 set.
	92	Here are some macros to test, set, or clear bit 0 of addresses. */
	93	#define IS_THUMB_ADDR(addr) ((addr) & 1)
	94	#define MAKE_THUMB_ADDR(addr) ((addr) \| 1)
	95	#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
	96
d9311bfa AT	97	/* Support routines for instruction parsing. */
	98	#define submask(x) ((1L << ((x) + 1)) - 1)
	99	#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
	100	#define bit(obj,st) (((obj) >> (st)) & 1)
	101	#define sbits(obj,st,fn) \
	102	((long) (bits(obj,st,fn) \| ((long) bit(obj,fn) * ~ submask (fn - st))))
	103	#define BranchDest(addr,instr) \
	104	((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
	105
	106	/* Forward declaration. */
	107	struct regcache;
	108
8689682c AT	109	/* Return the size in bytes of the complete Thumb instruction whose
	110	first halfword is INST1. */
	111	int thumb_insn_size (unsigned short inst1);
	112
cba7e83f AT	113	/* Returns true if the condition evaluates to true. */
	114	int condition_true (unsigned long cond, unsigned long status_reg);
	115
	116	/* Return number of 1-bits in VAL. */
	117	int bitcount (unsigned long val);
	118
d9311bfa AT	119	/* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
	120	int arm_instruction_changes_pc (uint32_t this_instr);
	121
	122	/* Return 1 if the 16-bit Thumb instruction INST might change
	123	control flow, 0 otherwise. */
	124	int thumb_instruction_changes_pc (unsigned short inst);
	125
	126	/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
	127	might change control flow, 0 otherwise. */
	128	int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2);
	129
	130	/* Advance the state of the IT block and return that state. */
	131	int thumb_advance_itstate (unsigned int itstate);
	132
	133	/* Decode shifted register value. */
	134
	135	unsigned long shifted_reg_val (struct regcache *regcache,
	136	unsigned long inst,
	137	int carry,
	138	unsigned long pc_val,
	139	unsigned long status_reg);
	140
ec741292	141	#endif