Commit | Line | Data |
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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
ecd75fc8 | 2 | Copyright (C) 1999-2014 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
0e9f083f | 22 | #include <string.h> |
4e052eda | 23 | #include "regcache.h" |
10d6c8cd DJ |
24 | #include "target.h" |
25 | #include "linux-nat.h" | |
05a4558a | 26 | #include "target-descriptions.h" |
3b273a55 | 27 | #include "auxv.h" |
e3039479 UW |
28 | #include "observer.h" |
29 | #include "gdbthread.h" | |
ed9a39eb | 30 | |
aeb98c60 | 31 | #include "arm-tdep.h" |
cb587d83 | 32 | #include "arm-linux-tdep.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb JM |
35 | #include <sys/user.h> |
36 | #include <sys/ptrace.h> | |
37 | #include <sys/utsname.h> | |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
0963b4bd | 40 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
41 | #include "gregset.h" |
42 | ||
9308fc88 DJ |
43 | /* Defines ps_err_e, struct ps_prochandle. */ |
44 | #include "gdb_proc_service.h" | |
45 | ||
46 | #ifndef PTRACE_GET_THREAD_AREA | |
47 | #define PTRACE_GET_THREAD_AREA 22 | |
48 | #endif | |
49 | ||
05a4558a DJ |
50 | #ifndef PTRACE_GETWMMXREGS |
51 | #define PTRACE_GETWMMXREGS 18 | |
52 | #define PTRACE_SETWMMXREGS 19 | |
53 | #endif | |
54 | ||
3b273a55 RE |
55 | #ifndef PTRACE_GETVFPREGS |
56 | #define PTRACE_GETVFPREGS 27 | |
57 | #define PTRACE_SETVFPREGS 28 | |
58 | #endif | |
59 | ||
e3039479 UW |
60 | #ifndef PTRACE_GETHBPREGS |
61 | #define PTRACE_GETHBPREGS 29 | |
62 | #define PTRACE_SETHBPREGS 30 | |
63 | #endif | |
64 | ||
05a4558a DJ |
65 | /* A flag for whether the WMMX registers are available. */ |
66 | static int arm_linux_has_wmmx_registers; | |
67 | ||
3b273a55 | 68 | /* The number of 64-bit VFP registers we have (expect this to be 0, |
0963b4bd | 69 | 16, or 32). */ |
3b273a55 RE |
70 | static int arm_linux_vfp_register_count; |
71 | ||
ed9a39eb JM |
72 | extern int arm_apcs_32; |
73 | ||
fdf39c9a | 74 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
41c49b06 | 75 | case we may be tracing more than one process at a time. In that |
39f77062 | 76 | case, inferior_ptid will contain the main process ID and the |
fdf39c9a RE |
77 | individual thread (process) ID. get_thread_id () is used to get |
78 | the thread id if it's available, and the process id otherwise. */ | |
41c49b06 | 79 | |
4e841acf | 80 | static int |
39f77062 | 81 | get_thread_id (ptid_t ptid) |
41c49b06 | 82 | { |
dfd4cc63 | 83 | int tid = ptid_get_lwp (ptid); |
39f77062 | 84 | if (0 == tid) |
dfd4cc63 | 85 | tid = ptid_get_pid (ptid); |
41c49b06 SB |
86 | return tid; |
87 | } | |
3b273a55 | 88 | |
05a4558a | 89 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) |
41c49b06 | 90 | |
41c49b06 | 91 | /* Get the value of a particular register from the floating point |
c6b92abd | 92 | state of the process and store it into regcache. */ |
41c49b06 SB |
93 | |
94 | static void | |
56be3814 | 95 | fetch_fpregister (struct regcache *regcache, int regno) |
41c49b06 SB |
96 | { |
97 | int ret, tid; | |
cb587d83 | 98 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
99 | |
100 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 101 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
102 | |
103 | /* Read the floating point state. */ | |
cb587d83 | 104 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
105 | if (ret < 0) |
106 | { | |
edefbb7c | 107 | warning (_("Unable to fetch floating point register.")); |
41c49b06 SB |
108 | return; |
109 | } | |
110 | ||
111 | /* Fetch fpsr. */ | |
34e8f22d | 112 | if (ARM_FPS_REGNUM == regno) |
56be3814 | 113 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 114 | fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
115 | |
116 | /* Fetch the floating point register. */ | |
34e8f22d | 117 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 118 | supply_nwfpe_register (regcache, regno, fp); |
41c49b06 SB |
119 | } |
120 | ||
121 | /* Get the whole floating point state of the process and store it | |
c6b92abd | 122 | into regcache. */ |
ed9a39eb JM |
123 | |
124 | static void | |
56be3814 | 125 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 126 | { |
41c49b06 | 127 | int ret, regno, tid; |
cb587d83 | 128 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 129 | |
41c49b06 | 130 | /* Get the thread id for the ptrace call. */ |
39f77062 | 131 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 | 132 | |
ed9a39eb | 133 | /* Read the floating point state. */ |
cb587d83 | 134 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
ed9a39eb JM |
135 | if (ret < 0) |
136 | { | |
edefbb7c | 137 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
138 | return; |
139 | } | |
140 | ||
141 | /* Fetch fpsr. */ | |
56be3814 | 142 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 143 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
144 | |
145 | /* Fetch the floating point registers. */ | |
34e8f22d | 146 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 147 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
148 | } |
149 | ||
41c49b06 | 150 | /* Save a particular register into the floating point state of the |
c6b92abd | 151 | process using the contents from regcache. */ |
41c49b06 SB |
152 | |
153 | static void | |
56be3814 | 154 | store_fpregister (const struct regcache *regcache, int regno) |
41c49b06 SB |
155 | { |
156 | int ret, tid; | |
cb587d83 | 157 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
158 | |
159 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 160 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
161 | |
162 | /* Read the floating point state. */ | |
cb587d83 | 163 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
164 | if (ret < 0) |
165 | { | |
edefbb7c | 166 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
167 | return; |
168 | } | |
169 | ||
170 | /* Store fpsr. */ | |
672c9795 YQ |
171 | if (ARM_FPS_REGNUM == regno |
172 | && REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) | |
56be3814 | 173 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
174 | |
175 | /* Store the floating point register. */ | |
34e8f22d | 176 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 177 | collect_nwfpe_register (regcache, regno, fp); |
41c49b06 | 178 | |
cb587d83 | 179 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
41c49b06 SB |
180 | if (ret < 0) |
181 | { | |
edefbb7c | 182 | warning (_("Unable to store floating point register.")); |
41c49b06 SB |
183 | return; |
184 | } | |
185 | } | |
186 | ||
ed9a39eb | 187 | /* Save the whole floating point state of the process using |
c6b92abd | 188 | the contents from regcache. */ |
ed9a39eb JM |
189 | |
190 | static void | |
56be3814 | 191 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 192 | { |
41c49b06 | 193 | int ret, regno, tid; |
cb587d83 | 194 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 195 | |
41c49b06 | 196 | /* Get the thread id for the ptrace call. */ |
39f77062 | 197 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
198 | |
199 | /* Read the floating point state. */ | |
cb587d83 | 200 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
201 | if (ret < 0) |
202 | { | |
edefbb7c | 203 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
204 | return; |
205 | } | |
206 | ||
ed9a39eb | 207 | /* Store fpsr. */ |
672c9795 | 208 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 209 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
210 | |
211 | /* Store the floating point registers. */ | |
34e8f22d | 212 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 213 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 214 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 215 | |
cb587d83 | 216 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
ed9a39eb JM |
217 | if (ret < 0) |
218 | { | |
edefbb7c | 219 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
220 | return; |
221 | } | |
222 | } | |
223 | ||
41c49b06 | 224 | /* Fetch a general register of the process and store into |
c6b92abd | 225 | regcache. */ |
41c49b06 SB |
226 | |
227 | static void | |
56be3814 | 228 | fetch_register (struct regcache *regcache, int regno) |
41c49b06 SB |
229 | { |
230 | int ret, tid; | |
c2152441 | 231 | elf_gregset_t regs; |
41c49b06 SB |
232 | |
233 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 234 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
235 | |
236 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
237 | if (ret < 0) | |
238 | { | |
edefbb7c | 239 | warning (_("Unable to fetch general register.")); |
41c49b06 SB |
240 | return; |
241 | } | |
242 | ||
34e8f22d | 243 | if (regno >= ARM_A1_REGNUM && regno < ARM_PC_REGNUM) |
56be3814 | 244 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
41c49b06 | 245 | |
34e8f22d | 246 | if (ARM_PS_REGNUM == regno) |
41c49b06 SB |
247 | { |
248 | if (arm_apcs_32) | |
56be3814 | 249 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 250 | (char *) ®s[ARM_CPSR_GREGNUM]); |
41c49b06 | 251 | else |
56be3814 | 252 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 253 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
254 | } |
255 | ||
34e8f22d | 256 | if (ARM_PC_REGNUM == regno) |
41c49b06 | 257 | { |
bf6ae464 | 258 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 UW |
259 | (get_regcache_arch (regcache), |
260 | regs[ARM_PC_REGNUM]); | |
56be3814 | 261 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 262 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
263 | } |
264 | } | |
265 | ||
ed9a39eb | 266 | /* Fetch all general registers of the process and store into |
c6b92abd | 267 | regcache. */ |
ed9a39eb JM |
268 | |
269 | static void | |
56be3814 | 270 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 271 | { |
41c49b06 | 272 | int ret, regno, tid; |
c2152441 | 273 | elf_gregset_t regs; |
ed9a39eb | 274 | |
41c49b06 | 275 | /* Get the thread id for the ptrace call. */ |
39f77062 | 276 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
277 | |
278 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
ed9a39eb JM |
279 | if (ret < 0) |
280 | { | |
edefbb7c | 281 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
282 | return; |
283 | } | |
284 | ||
34e8f22d | 285 | for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++) |
56be3814 | 286 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
287 | |
288 | if (arm_apcs_32) | |
56be3814 | 289 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 290 | (char *) ®s[ARM_CPSR_GREGNUM]); |
ed9a39eb | 291 | else |
56be3814 | 292 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 293 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb | 294 | |
bf6ae464 | 295 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 | 296 | (get_regcache_arch (regcache), regs[ARM_PC_REGNUM]); |
56be3814 | 297 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 298 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb JM |
299 | } |
300 | ||
301 | /* Store all general registers of the process from the values in | |
c6b92abd | 302 | regcache. */ |
ed9a39eb | 303 | |
41c49b06 | 304 | static void |
56be3814 | 305 | store_register (const struct regcache *regcache, int regno) |
41c49b06 SB |
306 | { |
307 | int ret, tid; | |
c2152441 | 308 | elf_gregset_t regs; |
41c49b06 | 309 | |
672c9795 | 310 | if (REG_VALID != regcache_register_status (regcache, regno)) |
41c49b06 SB |
311 | return; |
312 | ||
313 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 314 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
315 | |
316 | /* Get the general registers from the process. */ | |
317 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
318 | if (ret < 0) | |
319 | { | |
edefbb7c | 320 | warning (_("Unable to fetch general registers.")); |
41c49b06 SB |
321 | return; |
322 | } | |
323 | ||
34e8f22d | 324 | if (regno >= ARM_A1_REGNUM && regno <= ARM_PC_REGNUM) |
56be3814 | 325 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
adb8a87c | 326 | else if (arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 327 | regcache_raw_collect (regcache, regno, |
17c12639 | 328 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 329 | else if (!arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 330 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
adb8a87c | 331 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
332 | |
333 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
334 | if (ret < 0) | |
335 | { | |
edefbb7c | 336 | warning (_("Unable to store general register.")); |
41c49b06 SB |
337 | return; |
338 | } | |
339 | } | |
340 | ||
ed9a39eb | 341 | static void |
56be3814 | 342 | store_regs (const struct regcache *regcache) |
ed9a39eb | 343 | { |
41c49b06 | 344 | int ret, regno, tid; |
c2152441 | 345 | elf_gregset_t regs; |
ed9a39eb | 346 | |
41c49b06 | 347 | /* Get the thread id for the ptrace call. */ |
39f77062 | 348 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
349 | |
350 | /* Fetch the general registers. */ | |
351 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
ed9a39eb JM |
352 | if (ret < 0) |
353 | { | |
edefbb7c | 354 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
355 | return; |
356 | } | |
357 | ||
34e8f22d | 358 | for (regno = ARM_A1_REGNUM; regno <= ARM_PC_REGNUM; regno++) |
ed9a39eb | 359 | { |
672c9795 | 360 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 361 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
362 | } |
363 | ||
672c9795 | 364 | if (arm_apcs_32 && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM)) |
56be3814 | 365 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
17c12639 | 366 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 367 | |
41c49b06 | 368 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); |
ed9a39eb JM |
369 | |
370 | if (ret < 0) | |
371 | { | |
edefbb7c | 372 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
373 | return; |
374 | } | |
375 | } | |
376 | ||
05a4558a DJ |
377 | /* Fetch all WMMX registers of the process and store into |
378 | regcache. */ | |
379 | ||
380 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
381 | ||
382 | static void | |
56be3814 | 383 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
384 | { |
385 | char regbuf[IWMMXT_REGS_SIZE]; | |
386 | int ret, regno, tid; | |
387 | ||
388 | /* Get the thread id for the ptrace call. */ | |
389 | tid = GET_THREAD_ID (inferior_ptid); | |
390 | ||
391 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
392 | if (ret < 0) | |
393 | { | |
394 | warning (_("Unable to fetch WMMX registers.")); | |
395 | return; | |
396 | } | |
397 | ||
398 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 399 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
400 | ®buf[regno * 8]); |
401 | ||
402 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 403 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
404 | ®buf[16 * 8 + regno * 4]); |
405 | ||
406 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 407 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
408 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
409 | } | |
410 | ||
411 | static void | |
56be3814 | 412 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
413 | { |
414 | char regbuf[IWMMXT_REGS_SIZE]; | |
415 | int ret, regno, tid; | |
416 | ||
417 | /* Get the thread id for the ptrace call. */ | |
418 | tid = GET_THREAD_ID (inferior_ptid); | |
419 | ||
420 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
421 | if (ret < 0) | |
422 | { | |
423 | warning (_("Unable to fetch WMMX registers.")); | |
424 | return; | |
425 | } | |
426 | ||
427 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
428 | if (REG_VALID == regcache_register_status (regcache, |
429 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 430 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
431 | ®buf[regno * 8]); |
432 | ||
433 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
434 | if (REG_VALID == regcache_register_status (regcache, |
435 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 436 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
437 | ®buf[16 * 8 + regno * 4]); |
438 | ||
439 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
440 | if (REG_VALID == regcache_register_status (regcache, |
441 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 442 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
443 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
444 | ||
445 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
446 | ||
447 | if (ret < 0) | |
448 | { | |
449 | warning (_("Unable to store WMMX registers.")); | |
450 | return; | |
451 | } | |
452 | } | |
453 | ||
3b273a55 RE |
454 | /* Fetch and store VFP Registers. The kernel object has space for 32 |
455 | 64-bit registers, and the FPSCR. This is even when on a VFPv2 or | |
456 | VFPv3D16 target. */ | |
457 | #define VFP_REGS_SIZE (32 * 8 + 4) | |
458 | ||
459 | static void | |
460 | fetch_vfp_regs (struct regcache *regcache) | |
461 | { | |
462 | char regbuf[VFP_REGS_SIZE]; | |
463 | int ret, regno, tid; | |
464 | ||
465 | /* Get the thread id for the ptrace call. */ | |
466 | tid = GET_THREAD_ID (inferior_ptid); | |
467 | ||
468 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
469 | if (ret < 0) | |
470 | { | |
471 | warning (_("Unable to fetch VFP registers.")); | |
472 | return; | |
473 | } | |
474 | ||
475 | for (regno = 0; regno < arm_linux_vfp_register_count; regno++) | |
476 | regcache_raw_supply (regcache, regno + ARM_D0_REGNUM, | |
477 | (char *) regbuf + regno * 8); | |
478 | ||
479 | regcache_raw_supply (regcache, ARM_FPSCR_REGNUM, | |
480 | (char *) regbuf + 32 * 8); | |
481 | } | |
482 | ||
483 | static void | |
484 | store_vfp_regs (const struct regcache *regcache) | |
485 | { | |
486 | char regbuf[VFP_REGS_SIZE]; | |
487 | int ret, regno, tid; | |
488 | ||
489 | /* Get the thread id for the ptrace call. */ | |
490 | tid = GET_THREAD_ID (inferior_ptid); | |
491 | ||
492 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
493 | if (ret < 0) | |
494 | { | |
495 | warning (_("Unable to fetch VFP registers (for update).")); | |
496 | return; | |
497 | } | |
498 | ||
499 | for (regno = 0; regno < arm_linux_vfp_register_count; regno++) | |
500 | regcache_raw_collect (regcache, regno + ARM_D0_REGNUM, | |
501 | (char *) regbuf + regno * 8); | |
502 | ||
503 | regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, | |
504 | (char *) regbuf + 32 * 8); | |
505 | ||
506 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
507 | ||
508 | if (ret < 0) | |
509 | { | |
510 | warning (_("Unable to store VFP registers.")); | |
511 | return; | |
512 | } | |
513 | } | |
514 | ||
ed9a39eb JM |
515 | /* Fetch registers from the child process. Fetch all registers if |
516 | regno == -1, otherwise fetch all general registers or all floating | |
517 | point registers depending upon the value of regno. */ | |
518 | ||
10d6c8cd | 519 | static void |
28439f5e PA |
520 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
521 | struct regcache *regcache, int regno) | |
ed9a39eb | 522 | { |
41c49b06 SB |
523 | if (-1 == regno) |
524 | { | |
56be3814 UW |
525 | fetch_regs (regcache); |
526 | fetch_fpregs (regcache); | |
05a4558a | 527 | if (arm_linux_has_wmmx_registers) |
56be3814 | 528 | fetch_wmmx_regs (regcache); |
3b273a55 RE |
529 | if (arm_linux_vfp_register_count > 0) |
530 | fetch_vfp_regs (regcache); | |
41c49b06 SB |
531 | } |
532 | else | |
533 | { | |
05a4558a | 534 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 535 | fetch_register (regcache, regno); |
05a4558a | 536 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
56be3814 | 537 | fetch_fpregister (regcache, regno); |
05a4558a DJ |
538 | else if (arm_linux_has_wmmx_registers |
539 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) | |
56be3814 | 540 | fetch_wmmx_regs (regcache); |
3b273a55 RE |
541 | else if (arm_linux_vfp_register_count > 0 |
542 | && regno >= ARM_D0_REGNUM | |
543 | && regno <= ARM_D0_REGNUM + arm_linux_vfp_register_count) | |
544 | fetch_vfp_regs (regcache); | |
41c49b06 | 545 | } |
ed9a39eb JM |
546 | } |
547 | ||
548 | /* Store registers back into the inferior. Store all registers if | |
549 | regno == -1, otherwise store all general registers or all floating | |
550 | point registers depending upon the value of regno. */ | |
551 | ||
10d6c8cd | 552 | static void |
28439f5e PA |
553 | arm_linux_store_inferior_registers (struct target_ops *ops, |
554 | struct regcache *regcache, int regno) | |
ed9a39eb | 555 | { |
41c49b06 SB |
556 | if (-1 == regno) |
557 | { | |
56be3814 UW |
558 | store_regs (regcache); |
559 | store_fpregs (regcache); | |
05a4558a | 560 | if (arm_linux_has_wmmx_registers) |
56be3814 | 561 | store_wmmx_regs (regcache); |
3b273a55 RE |
562 | if (arm_linux_vfp_register_count > 0) |
563 | store_vfp_regs (regcache); | |
41c49b06 SB |
564 | } |
565 | else | |
566 | { | |
05a4558a | 567 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 568 | store_register (regcache, regno); |
05a4558a | 569 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
56be3814 | 570 | store_fpregister (regcache, regno); |
05a4558a DJ |
571 | else if (arm_linux_has_wmmx_registers |
572 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) | |
56be3814 | 573 | store_wmmx_regs (regcache); |
3b273a55 RE |
574 | else if (arm_linux_vfp_register_count > 0 |
575 | && regno >= ARM_D0_REGNUM | |
576 | && regno <= ARM_D0_REGNUM + arm_linux_vfp_register_count) | |
577 | store_vfp_regs (regcache); | |
41c49b06 | 578 | } |
ed9a39eb JM |
579 | } |
580 | ||
cb587d83 DJ |
581 | /* Wrapper functions for the standard regset handling, used by |
582 | thread debugging. */ | |
41c49b06 SB |
583 | |
584 | void | |
7f7fe91e UW |
585 | fill_gregset (const struct regcache *regcache, |
586 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 587 | { |
7f7fe91e | 588 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
589 | } |
590 | ||
41c49b06 | 591 | void |
7f7fe91e | 592 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 593 | { |
7f7fe91e | 594 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
595 | } |
596 | ||
41c49b06 | 597 | void |
7f7fe91e UW |
598 | fill_fpregset (const struct regcache *regcache, |
599 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 600 | { |
7f7fe91e | 601 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
602 | } |
603 | ||
604 | /* Fill GDB's register array with the floating-point register values | |
605 | in *fpregsetp. */ | |
606 | ||
607 | void | |
7f7fe91e | 608 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 609 | { |
7f7fe91e | 610 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
611 | } |
612 | ||
9308fc88 DJ |
613 | /* Fetch the thread-local storage pointer for libthread_db. */ |
614 | ||
615 | ps_err_e | |
616 | ps_get_thread_area (const struct ps_prochandle *ph, | |
617 | lwpid_t lwpid, int idx, void **base) | |
618 | { | |
619 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
620 | return PS_ERR; | |
621 | ||
622 | /* IDX is the bias from the thread pointer to the beginning of the | |
623 | thread descriptor. It has to be subtracted due to implementation | |
624 | quirks in libthread_db. */ | |
625 | *base = (void *) ((char *)*base - idx); | |
626 | ||
627 | return PS_OK; | |
628 | } | |
629 | ||
81adfced DJ |
630 | static const struct target_desc * |
631 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 632 | { |
3b273a55 RE |
633 | CORE_ADDR arm_hwcap = 0; |
634 | arm_linux_has_wmmx_registers = 0; | |
635 | arm_linux_vfp_register_count = 0; | |
05a4558a | 636 | |
3b273a55 RE |
637 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
638 | { | |
2117c711 | 639 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 640 | } |
81adfced | 641 | |
3b273a55 RE |
642 | if (arm_hwcap & HWCAP_IWMMXT) |
643 | { | |
644 | arm_linux_has_wmmx_registers = 1; | |
3b273a55 RE |
645 | return tdesc_arm_with_iwmmxt; |
646 | } | |
647 | ||
648 | if (arm_hwcap & HWCAP_VFP) | |
649 | { | |
650 | int pid; | |
651 | char *buf; | |
652 | const struct target_desc * result = NULL; | |
653 | ||
654 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
655 | Neon with VFPv3-D32. */ | |
656 | if (arm_hwcap & HWCAP_NEON) | |
657 | { | |
658 | arm_linux_vfp_register_count = 32; | |
3b273a55 RE |
659 | result = tdesc_arm_with_neon; |
660 | } | |
661 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) | |
662 | { | |
663 | arm_linux_vfp_register_count = 32; | |
3b273a55 RE |
664 | result = tdesc_arm_with_vfpv3; |
665 | } | |
666 | else | |
667 | { | |
668 | arm_linux_vfp_register_count = 16; | |
3b273a55 RE |
669 | result = tdesc_arm_with_vfpv2; |
670 | } | |
671 | ||
672 | /* Now make sure that the kernel supports reading these | |
673 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 674 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
675 | errno = 0; |
676 | buf = alloca (VFP_REGS_SIZE); | |
677 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
678 | && errno == EIO) | |
679 | result = NULL; | |
680 | ||
681 | return result; | |
682 | } | |
683 | ||
2117c711 | 684 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
685 | } |
686 | ||
e3039479 UW |
687 | /* Information describing the hardware breakpoint capabilities. */ |
688 | struct arm_linux_hwbp_cap | |
689 | { | |
690 | gdb_byte arch; | |
691 | gdb_byte max_wp_length; | |
692 | gdb_byte wp_count; | |
693 | gdb_byte bp_count; | |
694 | }; | |
695 | ||
638c5f49 OJ |
696 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
697 | assume a maximum number of supported break-/watchpoints. */ | |
698 | #define MAX_BPTS 16 | |
699 | #define MAX_WPTS 16 | |
700 | ||
e3039479 UW |
701 | /* Get hold of the Hardware Breakpoint information for the target we are |
702 | attached to. Returns NULL if the kernel doesn't support Hardware | |
703 | breakpoints at all, or a pointer to the information structure. */ | |
704 | static const struct arm_linux_hwbp_cap * | |
705 | arm_linux_get_hwbp_cap (void) | |
706 | { | |
707 | /* The info structure we return. */ | |
708 | static struct arm_linux_hwbp_cap info; | |
709 | ||
710 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
711 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
712 | means INFO is in an initialized state. */ | |
713 | static int available = -1; | |
714 | ||
715 | if (available == -1) | |
716 | { | |
717 | int tid; | |
718 | unsigned int val; | |
719 | ||
720 | tid = GET_THREAD_ID (inferior_ptid); | |
721 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
722 | available = 0; | |
723 | else | |
724 | { | |
725 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
726 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
727 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
728 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
729 | |
730 | if (info.wp_count > MAX_WPTS) | |
731 | { | |
732 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
733 | supports %d"), MAX_WPTS, info.wp_count); | |
734 | info.wp_count = MAX_WPTS; | |
735 | } | |
736 | ||
737 | if (info.bp_count > MAX_BPTS) | |
738 | { | |
739 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
740 | supports %d"), MAX_BPTS, info.bp_count); | |
741 | info.bp_count = MAX_BPTS; | |
742 | } | |
e3039479 UW |
743 | available = (info.arch != 0); |
744 | } | |
745 | } | |
746 | ||
747 | return available == 1 ? &info : NULL; | |
748 | } | |
749 | ||
750 | /* How many hardware breakpoints are available? */ | |
751 | static int | |
752 | arm_linux_get_hw_breakpoint_count (void) | |
753 | { | |
754 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
755 | return cap != NULL ? cap->bp_count : 0; | |
756 | } | |
757 | ||
758 | /* How many hardware watchpoints are available? */ | |
759 | static int | |
760 | arm_linux_get_hw_watchpoint_count (void) | |
761 | { | |
762 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
763 | return cap != NULL ? cap->wp_count : 0; | |
764 | } | |
765 | ||
766 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
767 | there is not an appropriate resource available, otherwise returns 1. */ | |
768 | static int | |
5461485a TT |
769 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
770 | int type, int cnt, int ot) | |
e3039479 UW |
771 | { |
772 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
773 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
774 | { | |
775 | if (cnt + ot > arm_linux_get_hw_watchpoint_count ()) | |
776 | return -1; | |
777 | } | |
778 | else if (type == bp_hardware_breakpoint) | |
779 | { | |
780 | if (cnt > arm_linux_get_hw_breakpoint_count ()) | |
781 | return -1; | |
782 | } | |
783 | else | |
784 | gdb_assert (FALSE); | |
785 | ||
786 | return 1; | |
787 | } | |
788 | ||
789 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
790 | typedef enum | |
791 | { | |
792 | arm_hwbp_break = 0, | |
793 | arm_hwbp_load = 1, | |
794 | arm_hwbp_store = 2, | |
795 | arm_hwbp_access = 3 | |
796 | } arm_hwbp_type; | |
797 | ||
798 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
799 | typedef unsigned int arm_hwbp_control_t; | |
800 | ||
801 | /* Structure used to keep track of hardware break-/watch-points. */ | |
802 | struct arm_linux_hw_breakpoint | |
803 | { | |
804 | /* Address to break on, or being watched. */ | |
805 | unsigned int address; | |
806 | /* Control register for break-/watch- point. */ | |
807 | arm_hwbp_control_t control; | |
808 | }; | |
809 | ||
638c5f49 OJ |
810 | /* Structure containing arrays of per process hardware break-/watchpoints |
811 | for caching address and control information. | |
e3039479 UW |
812 | |
813 | The Linux ptrace interface to hardware break-/watch-points presents the | |
814 | values in a vector centred around 0 (which is used fo generic information). | |
815 | Positive indicies refer to breakpoint addresses/control registers, negative | |
816 | indices to watchpoint addresses/control registers. | |
817 | ||
818 | The Linux vector is indexed as follows: | |
819 | -((i << 1) + 2): Control register for watchpoint i. | |
820 | -((i << 1) + 1): Address register for watchpoint i. | |
821 | 0: Information register. | |
822 | ((i << 1) + 1): Address register for breakpoint i. | |
823 | ((i << 1) + 2): Control register for breakpoint i. | |
824 | ||
825 | This structure is used as a per-thread cache of the state stored by the | |
826 | kernel, so that we don't need to keep calling into the kernel to find a | |
827 | free breakpoint. | |
828 | ||
829 | We treat break-/watch-points with their enable bit clear as being deleted. | |
830 | */ | |
638c5f49 | 831 | struct arm_linux_debug_reg_state |
e3039479 | 832 | { |
638c5f49 OJ |
833 | /* Hardware breakpoints for this process. */ |
834 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
835 | /* Hardware watchpoints for this process. */ | |
836 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
837 | }; | |
838 | ||
839 | /* Per-process arch-specific data we want to keep. */ | |
840 | struct arm_linux_process_info | |
e3039479 | 841 | { |
638c5f49 OJ |
842 | /* Linked list. */ |
843 | struct arm_linux_process_info *next; | |
844 | /* The process identifier. */ | |
845 | pid_t pid; | |
846 | /* Hardware break-/watchpoints state information. */ | |
847 | struct arm_linux_debug_reg_state state; | |
e3039479 | 848 | |
638c5f49 OJ |
849 | }; |
850 | ||
851 | /* Per-thread arch-specific data we want to keep. */ | |
852 | struct arch_lwp_info | |
853 | { | |
854 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
855 | char bpts_changed[MAX_BPTS]; | |
856 | char wpts_changed[MAX_WPTS]; | |
857 | }; | |
858 | ||
859 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
860 | ||
861 | /* Find process data for process PID. */ | |
862 | ||
863 | static struct arm_linux_process_info * | |
864 | arm_linux_find_process_pid (pid_t pid) | |
865 | { | |
866 | struct arm_linux_process_info *proc; | |
867 | ||
868 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
869 | if (proc->pid == pid) | |
870 | return proc; | |
871 | ||
872 | return NULL; | |
873 | } | |
874 | ||
875 | /* Add process data for process PID. Returns newly allocated info | |
876 | object. */ | |
877 | ||
878 | static struct arm_linux_process_info * | |
879 | arm_linux_add_process (pid_t pid) | |
880 | { | |
881 | struct arm_linux_process_info *proc; | |
e3039479 | 882 | |
638c5f49 OJ |
883 | proc = xcalloc (1, sizeof (*proc)); |
884 | proc->pid = pid; | |
e3039479 | 885 | |
638c5f49 OJ |
886 | proc->next = arm_linux_process_list; |
887 | arm_linux_process_list = proc; | |
888 | ||
889 | return proc; | |
890 | } | |
891 | ||
892 | /* Get data specific info for process PID, creating it if necessary. | |
893 | Never returns NULL. */ | |
894 | ||
895 | static struct arm_linux_process_info * | |
896 | arm_linux_process_info_get (pid_t pid) | |
897 | { | |
898 | struct arm_linux_process_info *proc; | |
899 | ||
900 | proc = arm_linux_find_process_pid (pid); | |
901 | if (proc == NULL) | |
902 | proc = arm_linux_add_process (pid); | |
903 | ||
904 | return proc; | |
905 | } | |
906 | ||
907 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
908 | data structures that keep track of debug register state. */ | |
909 | ||
910 | static void | |
911 | arm_linux_forget_process (pid_t pid) | |
912 | { | |
913 | struct arm_linux_process_info *proc, **proc_link; | |
914 | ||
915 | proc = arm_linux_process_list; | |
916 | proc_link = &arm_linux_process_list; | |
917 | ||
918 | while (proc != NULL) | |
919 | { | |
920 | if (proc->pid == pid) | |
e3039479 | 921 | { |
638c5f49 OJ |
922 | *proc_link = proc->next; |
923 | ||
924 | xfree (proc); | |
925 | return; | |
e3039479 UW |
926 | } |
927 | ||
638c5f49 OJ |
928 | proc_link = &proc->next; |
929 | proc = *proc_link; | |
930 | } | |
931 | } | |
932 | ||
933 | /* Get hardware break-/watchpoint state for process PID. */ | |
934 | ||
935 | static struct arm_linux_debug_reg_state * | |
936 | arm_linux_get_debug_reg_state (pid_t pid) | |
937 | { | |
938 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
939 | } |
940 | ||
941 | /* Initialize an ARM hardware break-/watch-point control register value. | |
942 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
943 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
944 | */ | |
945 | static arm_hwbp_control_t | |
946 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
947 | arm_hwbp_type hwbp_type, | |
948 | int enable) | |
949 | { | |
950 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
951 | gdb_assert (hwbp_type != arm_hwbp_break | |
952 | || ((byte_address_select & 0xfU) != 0)); | |
953 | ||
954 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
955 | } | |
956 | ||
957 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
958 | static int | |
959 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
960 | { | |
961 | return control & 0x1; | |
962 | } | |
963 | ||
964 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
965 | static arm_hwbp_control_t | |
966 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
967 | { | |
968 | return control & ~0x1; | |
969 | } | |
970 | ||
971 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
972 | enabled, and will point to the placed address of BP_TGT. */ | |
973 | static void | |
974 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
975 | struct bp_target_info *bp_tgt, | |
976 | struct arm_linux_hw_breakpoint *p) | |
977 | { | |
978 | unsigned mask; | |
979 | CORE_ADDR address = bp_tgt->placed_address; | |
980 | ||
981 | /* We have to create a mask for the control register which says which bits | |
982 | of the word pointed to by address to break on. */ | |
983 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
984 | { |
985 | mask = 0x3; | |
986 | address &= ~1; | |
987 | } | |
e3039479 | 988 | else |
fcf303ab UW |
989 | { |
990 | mask = 0xf; | |
991 | address &= ~3; | |
992 | } | |
e3039479 | 993 | |
fcf303ab | 994 | p->address = (unsigned int) address; |
e3039479 UW |
995 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
996 | } | |
997 | ||
998 | /* Get the ARM hardware breakpoint type from the RW value we're given when | |
999 | asked to set a watchpoint. */ | |
1000 | static arm_hwbp_type | |
1001 | arm_linux_get_hwbp_type (int rw) | |
1002 | { | |
1003 | if (rw == hw_read) | |
1004 | return arm_hwbp_load; | |
1005 | else if (rw == hw_write) | |
1006 | return arm_hwbp_store; | |
1007 | else | |
1008 | return arm_hwbp_access; | |
1009 | } | |
1010 | ||
1011 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
1012 | to LEN. The type of watchpoint is given in RW. */ | |
1013 | static void | |
1014 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, int rw, | |
1015 | struct arm_linux_hw_breakpoint *p) | |
1016 | { | |
1017 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1018 | unsigned mask; | |
1019 | ||
1020 | gdb_assert (cap != NULL); | |
1021 | gdb_assert (cap->max_wp_length != 0); | |
1022 | ||
1023 | mask = (1 << len) - 1; | |
1024 | ||
1025 | p->address = (unsigned int) addr; | |
1026 | p->control = arm_hwbp_control_initialize (mask, | |
1027 | arm_linux_get_hwbp_type (rw), 1); | |
1028 | } | |
1029 | ||
1030 | /* Are two break-/watch-points equal? */ | |
1031 | static int | |
1032 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
1033 | const struct arm_linux_hw_breakpoint *p2) | |
1034 | { | |
1035 | return p1->address == p2->address && p1->control == p2->control; | |
1036 | } | |
1037 | ||
638c5f49 OJ |
1038 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
1039 | the current process. */ | |
1040 | ||
1041 | struct update_registers_data | |
1042 | { | |
1043 | int watch; | |
1044 | int index; | |
1045 | }; | |
1046 | ||
1047 | static int | |
1048 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
1049 | { | |
1050 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
1051 | ||
1052 | if (lwp->arch_private == NULL) | |
1053 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
1054 | ||
1055 | /* The actual update is done later just before resuming the lwp, | |
1056 | we just mark that the registers need updating. */ | |
1057 | if (data->watch) | |
1058 | lwp->arch_private->wpts_changed[data->index] = 1; | |
1059 | else | |
1060 | lwp->arch_private->bpts_changed[data->index] = 1; | |
1061 | ||
1062 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
1063 | we can update its breakpoint registers. */ | |
1064 | if (!lwp->stopped) | |
1065 | linux_stop_lwp (lwp); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
e3039479 UW |
1070 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
1071 | =1) BPT for thread TID. */ | |
1072 | static void | |
1073 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 1074 | int watchpoint) |
e3039479 | 1075 | { |
638c5f49 OJ |
1076 | int pid; |
1077 | ptid_t pid_ptid; | |
e3039479 UW |
1078 | gdb_byte count, i; |
1079 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1080 | struct update_registers_data data; |
e3039479 | 1081 | |
638c5f49 OJ |
1082 | pid = ptid_get_pid (inferior_ptid); |
1083 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1084 | |
1085 | if (watchpoint) | |
1086 | { | |
1087 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1088 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1089 | } |
1090 | else | |
1091 | { | |
1092 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1093 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1094 | } |
1095 | ||
1096 | for (i = 0; i < count; ++i) | |
1097 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1098 | { | |
638c5f49 OJ |
1099 | data.watch = watchpoint; |
1100 | data.index = i; | |
1101 | bpts[i] = *bpt; | |
1102 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1103 | break; | |
e3039479 UW |
1104 | } |
1105 | ||
1106 | gdb_assert (i != count); | |
1107 | } | |
1108 | ||
1109 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1110 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1111 | static void | |
1112 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1113 | int watchpoint) |
e3039479 | 1114 | { |
638c5f49 | 1115 | int pid; |
e3039479 | 1116 | gdb_byte count, i; |
638c5f49 OJ |
1117 | ptid_t pid_ptid; |
1118 | struct arm_linux_hw_breakpoint* bpts; | |
1119 | struct update_registers_data data; | |
e3039479 | 1120 | |
638c5f49 OJ |
1121 | pid = ptid_get_pid (inferior_ptid); |
1122 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1123 | |
1124 | if (watchpoint) | |
1125 | { | |
1126 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1127 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1128 | } |
1129 | else | |
1130 | { | |
1131 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1132 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1133 | } |
1134 | ||
1135 | for (i = 0; i < count; ++i) | |
1136 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1137 | { | |
638c5f49 OJ |
1138 | data.watch = watchpoint; |
1139 | data.index = i; | |
1140 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1141 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1142 | break; | |
e3039479 UW |
1143 | } |
1144 | ||
1145 | gdb_assert (i != count); | |
1146 | } | |
1147 | ||
1148 | /* Insert a Hardware breakpoint. */ | |
1149 | static int | |
23a26771 TT |
1150 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1151 | struct gdbarch *gdbarch, | |
e3039479 UW |
1152 | struct bp_target_info *bp_tgt) |
1153 | { | |
e3039479 UW |
1154 | struct lwp_info *lp; |
1155 | struct arm_linux_hw_breakpoint p; | |
1156 | ||
1157 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1158 | return -1; | |
1159 | ||
1160 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1161 | |
1162 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1163 | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* Remove a hardware breakpoint. */ | |
1168 | static int | |
a64dc96c TT |
1169 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1170 | struct gdbarch *gdbarch, | |
e3039479 UW |
1171 | struct bp_target_info *bp_tgt) |
1172 | { | |
e3039479 UW |
1173 | struct lwp_info *lp; |
1174 | struct arm_linux_hw_breakpoint p; | |
1175 | ||
1176 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1177 | return -1; | |
1178 | ||
1179 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1180 | |
1181 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1182 | |
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1187 | ADDR? */ | |
1188 | static int | |
31568a15 TT |
1189 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1190 | CORE_ADDR addr, int len) | |
e3039479 UW |
1191 | { |
1192 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1193 | CORE_ADDR max_wp_length, aligned_addr; | |
1194 | ||
1195 | /* Can not set watchpoints for zero or negative lengths. */ | |
1196 | if (len <= 0) | |
1197 | return 0; | |
1198 | ||
1199 | /* Need to be able to use the ptrace interface. */ | |
1200 | if (cap == NULL || cap->wp_count == 0) | |
1201 | return 0; | |
1202 | ||
1203 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1204 | range covered by a watchpoint. */ | |
1205 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1206 | aligned_addr = addr & ~(max_wp_length - 1); | |
1207 | ||
1208 | if (aligned_addr + max_wp_length < addr + len) | |
1209 | return 0; | |
1210 | ||
1211 | /* The current ptrace interface can only handle watchpoints that are a | |
1212 | power of 2. */ | |
1213 | if ((len & (len - 1)) != 0) | |
1214 | return 0; | |
1215 | ||
1216 | /* All tests passed so we must be able to set a watchpoint. */ | |
1217 | return 1; | |
1218 | } | |
1219 | ||
1220 | /* Insert a Hardware breakpoint. */ | |
1221 | static int | |
7bb99c53 TT |
1222 | arm_linux_insert_watchpoint (struct target_ops *self, |
1223 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1224 | struct expression *cond) |
1225 | { | |
e3039479 UW |
1226 | struct lwp_info *lp; |
1227 | struct arm_linux_hw_breakpoint p; | |
1228 | ||
1229 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1230 | return -1; | |
1231 | ||
1232 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1233 | |
1234 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | /* Remove a hardware breakpoint. */ | |
1240 | static int | |
11b5219a TT |
1241 | arm_linux_remove_watchpoint (struct target_ops *self, |
1242 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1243 | struct expression *cond) |
1244 | { | |
e3039479 UW |
1245 | struct lwp_info *lp; |
1246 | struct arm_linux_hw_breakpoint p; | |
1247 | ||
1248 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1249 | return -1; | |
1250 | ||
1251 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1252 | |
1253 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1254 | |
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | /* What was the data address the target was stopped on accessing. */ | |
1259 | static int | |
1260 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1261 | { | |
f865ee35 JK |
1262 | siginfo_t siginfo; |
1263 | int slot; | |
1264 | ||
1265 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1266 | return 0; | |
e3039479 UW |
1267 | |
1268 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1269 | if (siginfo.si_signo != SIGTRAP |
1270 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1271 | return 0; |
1272 | ||
1273 | /* We must be able to set hardware watchpoints. */ | |
1274 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1275 | return 0; | |
1276 | ||
f865ee35 JK |
1277 | slot = siginfo.si_errno; |
1278 | ||
e3039479 UW |
1279 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1280 | a watchpoint. */ | |
1281 | if (slot >= 0) | |
1282 | return 0; | |
1283 | ||
f865ee35 | 1284 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1285 | return 1; |
1286 | } | |
1287 | ||
1288 | /* Has the target been stopped by hitting a watchpoint? */ | |
1289 | static int | |
6a109b6b | 1290 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1291 | { |
1292 | CORE_ADDR addr; | |
6a109b6b | 1293 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1294 | } |
1295 | ||
1296 | static int | |
1297 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1298 | CORE_ADDR addr, | |
1299 | CORE_ADDR start, int length) | |
1300 | { | |
1301 | return start <= addr && start + length - 1 >= addr; | |
1302 | } | |
1303 | ||
1304 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1305 | in the parent thread to the child thread. */ | |
1306 | static void | |
7b50312a | 1307 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1308 | { |
638c5f49 OJ |
1309 | int i; |
1310 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1311 | ||
1312 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1313 | for this thread need to be initialized. */ | |
e3039479 | 1314 | |
638c5f49 | 1315 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1316 | { |
638c5f49 OJ |
1317 | info->bpts_changed[i] = 1; |
1318 | info->wpts_changed[i] = 1; | |
e3039479 | 1319 | } |
638c5f49 OJ |
1320 | |
1321 | lp->arch_private = info; | |
e3039479 UW |
1322 | } |
1323 | ||
638c5f49 OJ |
1324 | /* Called when resuming a thread. |
1325 | The hardware debug registers are updated when there is any change. */ | |
1326 | ||
e3039479 | 1327 | static void |
638c5f49 | 1328 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1329 | { |
638c5f49 OJ |
1330 | int pid, i; |
1331 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1332 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1333 | ||
1334 | pid = ptid_get_lwp (lwp->ptid); | |
1335 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1336 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1337 | ||
1338 | /* NULL means this is the main thread still going through the shell, | |
1339 | or, no watchpoint has been set yet. In that case, there's | |
1340 | nothing to do. */ | |
1341 | if (arm_lwp_info == NULL) | |
1342 | return; | |
e3039479 | 1343 | |
638c5f49 OJ |
1344 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1345 | if (arm_lwp_info->bpts_changed[i]) | |
1346 | { | |
1347 | errno = 0; | |
1348 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1349 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1350 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1351 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1352 | ||
1353 | if (bpts[i].control != 0) | |
1354 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1355 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1356 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1357 | ||
1358 | arm_lwp_info->bpts_changed[i] = 0; | |
1359 | } | |
e3039479 | 1360 | |
638c5f49 OJ |
1361 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1362 | if (arm_lwp_info->wpts_changed[i]) | |
1363 | { | |
1364 | errno = 0; | |
1365 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1366 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1367 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1368 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1369 | ||
1370 | if (wpts[i].control != 0) | |
1371 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1372 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1373 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1374 | ||
1375 | arm_lwp_info->wpts_changed[i] = 0; | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | /* linux_nat_new_fork hook. */ | |
1380 | ||
1381 | static void | |
1382 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1383 | { | |
1384 | pid_t parent_pid; | |
1385 | struct arm_linux_debug_reg_state *parent_state; | |
1386 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1387 | |
638c5f49 OJ |
1388 | /* NULL means no watchpoint has ever been set in the parent. In |
1389 | that case, there's nothing to do. */ | |
1390 | if (parent->arch_private == NULL) | |
1391 | return; | |
e3039479 | 1392 | |
638c5f49 OJ |
1393 | /* GDB core assumes the child inherits the watchpoints/hw |
1394 | breakpoints of the parent, and will remove them all from the | |
1395 | forked off process. Copy the debug registers mirrors into the | |
1396 | new process so that all breakpoints and watchpoints can be | |
1397 | removed together. */ | |
e3039479 | 1398 | |
638c5f49 OJ |
1399 | parent_pid = ptid_get_pid (parent->ptid); |
1400 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1401 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1402 | *child_state = *parent_state; | |
e3039479 UW |
1403 | } |
1404 | ||
10d6c8cd DJ |
1405 | void _initialize_arm_linux_nat (void); |
1406 | ||
ed9a39eb JM |
1407 | void |
1408 | _initialize_arm_linux_nat (void) | |
1409 | { | |
10d6c8cd DJ |
1410 | struct target_ops *t; |
1411 | ||
10d6c8cd DJ |
1412 | /* Fill in the generic GNU/Linux methods. */ |
1413 | t = linux_target (); | |
1414 | ||
1415 | /* Add our register access methods. */ | |
1416 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1417 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1418 | ||
e3039479 UW |
1419 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1420 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1421 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1422 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1423 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1424 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1425 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1426 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1427 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1428 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1429 | ||
81adfced | 1430 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1431 | |
10d6c8cd | 1432 | /* Register the target. */ |
f973ed9c | 1433 | linux_nat_add_target (t); |
e3039479 | 1434 | |
638c5f49 | 1435 | /* Handle thread creation and exit. */ |
e3039479 | 1436 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1437 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1438 | ||
1439 | /* Handle process creation and exit. */ | |
1440 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1441 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1442 | } |