Commit | Line | Data |
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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
42a4f53d | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
4de283e4 TT |
20 | #include "inferior.h" |
21 | #include "gdbcore.h" | |
22 | #include "regcache.h" | |
23 | #include "target.h" | |
24 | #include "linux-nat.h" | |
25 | #include "target-descriptions.h" | |
26 | #include "auxv.h" | |
27 | #include "observable.h" | |
28 | #include "gdbthread.h" | |
29 | ||
d105cce5 | 30 | #include "aarch32-tdep.h" |
4de283e4 TT |
31 | #include "arm-tdep.h" |
32 | #include "arm-linux-tdep.h" | |
33 | #include "aarch32-linux-nat.h" | |
aeb98c60 | 34 | |
3b273a55 | 35 | #include <elf/common.h> |
ed9a39eb | 36 | #include <sys/user.h> |
4de283e4 | 37 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 38 | #include <sys/utsname.h> |
4de283e4 | 39 | #include <sys/procfs.h> |
ed9a39eb | 40 | |
d55e5aa6 | 41 | #include "nat/linux-ptrace.h" |
4de283e4 | 42 | #include "linux-tdep.h" |
95855ca8 | 43 | |
0963b4bd | 44 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
45 | #include "gregset.h" |
46 | ||
9308fc88 DJ |
47 | /* Defines ps_err_e, struct ps_prochandle. */ |
48 | #include "gdb_proc_service.h" | |
49 | ||
50 | #ifndef PTRACE_GET_THREAD_AREA | |
51 | #define PTRACE_GET_THREAD_AREA 22 | |
52 | #endif | |
53 | ||
05a4558a DJ |
54 | #ifndef PTRACE_GETWMMXREGS |
55 | #define PTRACE_GETWMMXREGS 18 | |
56 | #define PTRACE_SETWMMXREGS 19 | |
57 | #endif | |
58 | ||
3b273a55 RE |
59 | #ifndef PTRACE_GETVFPREGS |
60 | #define PTRACE_GETVFPREGS 27 | |
61 | #define PTRACE_SETVFPREGS 28 | |
62 | #endif | |
63 | ||
e3039479 UW |
64 | #ifndef PTRACE_GETHBPREGS |
65 | #define PTRACE_GETHBPREGS 29 | |
66 | #define PTRACE_SETHBPREGS 30 | |
67 | #endif | |
68 | ||
ed9a39eb JM |
69 | extern int arm_apcs_32; |
70 | ||
f6ac5f3d PA |
71 | class arm_linux_nat_target final : public linux_nat_target |
72 | { | |
73 | public: | |
74 | /* Add our register access methods. */ | |
75 | void fetch_registers (struct regcache *, int) override; | |
76 | void store_registers (struct regcache *, int) override; | |
77 | ||
78 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
79 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
80 | ||
81 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
82 | ||
83 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
84 | ||
85 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
86 | ||
87 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
88 | struct expression *) override; | |
89 | ||
90 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
91 | struct expression *) override; | |
57810aa7 | 92 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 93 | |
57810aa7 | 94 | bool stopped_data_address (CORE_ADDR *) override; |
f6ac5f3d | 95 | |
57810aa7 | 96 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d PA |
97 | |
98 | const struct target_desc *read_description () override; | |
135340af PA |
99 | |
100 | /* Override linux_nat_target low methods. */ | |
101 | ||
102 | /* Handle thread creation and exit. */ | |
103 | void low_new_thread (struct lwp_info *lp) override; | |
104 | void low_delete_thread (struct arch_lwp_info *lp) override; | |
105 | void low_prepare_to_resume (struct lwp_info *lp) override; | |
106 | ||
107 | /* Handle process creation and exit. */ | |
108 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
109 | void low_forget_process (pid_t pid) override; | |
f6ac5f3d PA |
110 | }; |
111 | ||
112 | static arm_linux_nat_target the_arm_linux_nat_target; | |
113 | ||
41c49b06 | 114 | /* Get the whole floating point state of the process and store it |
c6b92abd | 115 | into regcache. */ |
ed9a39eb JM |
116 | |
117 | static void | |
56be3814 | 118 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 119 | { |
41c49b06 | 120 | int ret, regno, tid; |
cb587d83 | 121 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 122 | |
41c49b06 | 123 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 124 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 125 | |
ed9a39eb | 126 | /* Read the floating point state. */ |
0bdb2f78 | 127 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
128 | { |
129 | struct iovec iov; | |
130 | ||
131 | iov.iov_base = &fp; | |
132 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
133 | ||
134 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
135 | } | |
136 | else | |
137 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
138 | ||
ed9a39eb | 139 | if (ret < 0) |
d86feca3 | 140 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
141 | |
142 | /* Fetch fpsr. */ | |
73e1c03f | 143 | regcache->raw_supply (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
144 | |
145 | /* Fetch the floating point registers. */ | |
34e8f22d | 146 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 147 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
148 | } |
149 | ||
150 | /* Save the whole floating point state of the process using | |
c6b92abd | 151 | the contents from regcache. */ |
ed9a39eb JM |
152 | |
153 | static void | |
56be3814 | 154 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 155 | { |
41c49b06 | 156 | int ret, regno, tid; |
cb587d83 | 157 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 158 | |
41c49b06 | 159 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 160 | tid = regcache->ptid ().lwp (); |
df9d7ec9 | 161 | |
41c49b06 | 162 | /* Read the floating point state. */ |
0bdb2f78 | 163 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
164 | { |
165 | elf_fpregset_t fpregs; | |
166 | struct iovec iov; | |
167 | ||
168 | iov.iov_base = &fpregs; | |
169 | iov.iov_len = sizeof (fpregs); | |
170 | ||
171 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
172 | } | |
173 | else | |
174 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
175 | ||
41c49b06 | 176 | if (ret < 0) |
d86feca3 | 177 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 178 | |
ed9a39eb | 179 | /* Store fpsr. */ |
0ec9f114 | 180 | if (REG_VALID == regcache->get_register_status (ARM_FPS_REGNUM)) |
34a79281 | 181 | regcache->raw_collect (ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
182 | |
183 | /* Store the floating point registers. */ | |
34e8f22d | 184 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
0ec9f114 | 185 | if (REG_VALID == regcache->get_register_status (regno)) |
56be3814 | 186 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 187 | |
0bdb2f78 | 188 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
189 | { |
190 | struct iovec iov; | |
191 | ||
192 | iov.iov_base = &fp; | |
193 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
194 | ||
195 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
196 | } | |
197 | else | |
198 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
199 | ||
ed9a39eb | 200 | if (ret < 0) |
d86feca3 | 201 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
202 | } |
203 | ||
204 | /* Fetch all general registers of the process and store into | |
c6b92abd | 205 | regcache. */ |
ed9a39eb JM |
206 | |
207 | static void | |
56be3814 | 208 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 209 | { |
cf4088a9 | 210 | int ret, tid; |
c2152441 | 211 | elf_gregset_t regs; |
ed9a39eb | 212 | |
41c49b06 | 213 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 214 | tid = regcache->ptid ().lwp (); |
10766686 | 215 | |
0bdb2f78 | 216 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
217 | { |
218 | struct iovec iov; | |
219 | ||
220 | iov.iov_base = ®s; | |
221 | iov.iov_len = sizeof (regs); | |
222 | ||
223 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
224 | } | |
225 | else | |
226 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
227 | ||
ed9a39eb | 228 | if (ret < 0) |
d86feca3 | 229 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 230 | |
f1b67888 | 231 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
232 | } |
233 | ||
ed9a39eb | 234 | static void |
56be3814 | 235 | store_regs (const struct regcache *regcache) |
ed9a39eb | 236 | { |
cf4088a9 | 237 | int ret, tid; |
c2152441 | 238 | elf_gregset_t regs; |
ed9a39eb | 239 | |
41c49b06 | 240 | /* Get the thread id for the ptrace call. */ |
e38504b3 | 241 | tid = regcache->ptid ().lwp (); |
10766686 | 242 | |
41c49b06 | 243 | /* Fetch the general registers. */ |
0bdb2f78 | 244 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
245 | { |
246 | struct iovec iov; | |
247 | ||
248 | iov.iov_base = ®s; | |
249 | iov.iov_len = sizeof (regs); | |
250 | ||
251 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
252 | } | |
253 | else | |
254 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
255 | ||
ed9a39eb | 256 | if (ret < 0) |
d86feca3 | 257 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 258 | |
f1b67888 | 259 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 260 | |
0bdb2f78 | 261 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
262 | { |
263 | struct iovec iov; | |
264 | ||
265 | iov.iov_base = ®s; | |
266 | iov.iov_len = sizeof (regs); | |
267 | ||
268 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
269 | } | |
270 | else | |
271 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
272 | |
273 | if (ret < 0) | |
d86feca3 | 274 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
275 | } |
276 | ||
05a4558a DJ |
277 | /* Fetch all WMMX registers of the process and store into |
278 | regcache. */ | |
279 | ||
05a4558a | 280 | static void |
56be3814 | 281 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
282 | { |
283 | char regbuf[IWMMXT_REGS_SIZE]; | |
284 | int ret, regno, tid; | |
285 | ||
286 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 287 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
288 | |
289 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
290 | if (ret < 0) | |
d86feca3 | 291 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
292 | |
293 | for (regno = 0; regno < 16; regno++) | |
73e1c03f | 294 | regcache->raw_supply (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
295 | |
296 | for (regno = 0; regno < 2; regno++) | |
73e1c03f SM |
297 | regcache->raw_supply (regno + ARM_WCSSF_REGNUM, |
298 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
299 | |
300 | for (regno = 0; regno < 4; regno++) | |
73e1c03f SM |
301 | regcache->raw_supply (regno + ARM_WCGR0_REGNUM, |
302 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
303 | } |
304 | ||
305 | static void | |
56be3814 | 306 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
307 | { |
308 | char regbuf[IWMMXT_REGS_SIZE]; | |
309 | int ret, regno, tid; | |
310 | ||
311 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 312 | tid = regcache->ptid ().lwp (); |
05a4558a DJ |
313 | |
314 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
315 | if (ret < 0) | |
d86feca3 | 316 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
317 | |
318 | for (regno = 0; regno < 16; regno++) | |
0ec9f114 | 319 | if (REG_VALID == regcache->get_register_status (regno + ARM_WR0_REGNUM)) |
34a79281 | 320 | regcache->raw_collect (regno + ARM_WR0_REGNUM, ®buf[regno * 8]); |
05a4558a DJ |
321 | |
322 | for (regno = 0; regno < 2; regno++) | |
0ec9f114 | 323 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCSSF_REGNUM)) |
34a79281 SM |
324 | regcache->raw_collect (regno + ARM_WCSSF_REGNUM, |
325 | ®buf[16 * 8 + regno * 4]); | |
05a4558a DJ |
326 | |
327 | for (regno = 0; regno < 4; regno++) | |
0ec9f114 | 328 | if (REG_VALID == regcache->get_register_status (regno + ARM_WCGR0_REGNUM)) |
34a79281 SM |
329 | regcache->raw_collect (regno + ARM_WCGR0_REGNUM, |
330 | ®buf[16 * 8 + 2 * 4 + regno * 4]); | |
05a4558a DJ |
331 | |
332 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
333 | ||
334 | if (ret < 0) | |
d86feca3 | 335 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
336 | } |
337 | ||
3b273a55 RE |
338 | static void |
339 | fetch_vfp_regs (struct regcache *regcache) | |
340 | { | |
350fab54 | 341 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 342 | int ret, tid; |
ac7936df | 343 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 344 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
345 | |
346 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 347 | tid = regcache->ptid ().lwp (); |
3b273a55 | 348 | |
0bdb2f78 | 349 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
350 | { |
351 | struct iovec iov; | |
352 | ||
353 | iov.iov_base = regbuf; | |
350fab54 | 354 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
355 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
356 | } | |
357 | else | |
358 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
359 | ||
3b273a55 | 360 | if (ret < 0) |
d86feca3 | 361 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 362 | |
f1b67888 YQ |
363 | aarch32_vfp_regcache_supply (regcache, regbuf, |
364 | tdep->vfp_register_count); | |
3b273a55 RE |
365 | } |
366 | ||
367 | static void | |
368 | store_vfp_regs (const struct regcache *regcache) | |
369 | { | |
350fab54 | 370 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
cf4088a9 | 371 | int ret, tid; |
ac7936df | 372 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 | 373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3b273a55 RE |
374 | |
375 | /* Get the thread id for the ptrace call. */ | |
e38504b3 | 376 | tid = regcache->ptid ().lwp (); |
3b273a55 | 377 | |
0bdb2f78 | 378 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
379 | { |
380 | struct iovec iov; | |
381 | ||
382 | iov.iov_base = regbuf; | |
350fab54 | 383 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
384 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); |
385 | } | |
386 | else | |
387 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
388 | ||
3b273a55 | 389 | if (ret < 0) |
d86feca3 | 390 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 391 | |
f1b67888 YQ |
392 | aarch32_vfp_regcache_collect (regcache, regbuf, |
393 | tdep->vfp_register_count); | |
3b273a55 | 394 | |
0bdb2f78 | 395 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
396 | { |
397 | struct iovec iov; | |
398 | ||
399 | iov.iov_base = regbuf; | |
350fab54 | 400 | iov.iov_len = ARM_VFP3_REGS_SIZE; |
bd16da51 YQ |
401 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); |
402 | } | |
403 | else | |
404 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
405 | |
406 | if (ret < 0) | |
d86feca3 | 407 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
408 | } |
409 | ||
ed9a39eb JM |
410 | /* Fetch registers from the child process. Fetch all registers if |
411 | regno == -1, otherwise fetch all general registers or all floating | |
412 | point registers depending upon the value of regno. */ | |
413 | ||
f6ac5f3d PA |
414 | void |
415 | arm_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 416 | { |
ac7936df | 417 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
418 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
419 | ||
41c49b06 SB |
420 | if (-1 == regno) |
421 | { | |
56be3814 | 422 | fetch_regs (regcache); |
a56cc1ce | 423 | if (tdep->have_wmmx_registers) |
56be3814 | 424 | fetch_wmmx_regs (regcache); |
330c6ca9 | 425 | if (tdep->vfp_register_count > 0) |
3b273a55 | 426 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
427 | if (tdep->have_fpa_registers) |
428 | fetch_fpregs (regcache); | |
41c49b06 | 429 | } |
4bd2e1b2 | 430 | else |
41c49b06 | 431 | { |
05a4558a | 432 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 433 | fetch_regs (regcache); |
05a4558a | 434 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 435 | fetch_fpregs (regcache); |
a56cc1ce | 436 | else if (tdep->have_wmmx_registers |
05a4558a | 437 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 438 | fetch_wmmx_regs (regcache); |
330c6ca9 | 439 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 440 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
441 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
442 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 443 | fetch_vfp_regs (regcache); |
41c49b06 | 444 | } |
ed9a39eb JM |
445 | } |
446 | ||
447 | /* Store registers back into the inferior. Store all registers if | |
448 | regno == -1, otherwise store all general registers or all floating | |
449 | point registers depending upon the value of regno. */ | |
450 | ||
f6ac5f3d PA |
451 | void |
452 | arm_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
ed9a39eb | 453 | { |
ac7936df | 454 | struct gdbarch *gdbarch = regcache->arch (); |
330c6ca9 YQ |
455 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
456 | ||
41c49b06 SB |
457 | if (-1 == regno) |
458 | { | |
56be3814 | 459 | store_regs (regcache); |
a56cc1ce | 460 | if (tdep->have_wmmx_registers) |
56be3814 | 461 | store_wmmx_regs (regcache); |
330c6ca9 | 462 | if (tdep->vfp_register_count > 0) |
3b273a55 | 463 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
464 | if (tdep->have_fpa_registers) |
465 | store_fpregs (regcache); | |
41c49b06 SB |
466 | } |
467 | else | |
468 | { | |
05a4558a | 469 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 470 | store_regs (regcache); |
05a4558a | 471 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 472 | store_fpregs (regcache); |
a56cc1ce | 473 | else if (tdep->have_wmmx_registers |
05a4558a | 474 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 475 | store_wmmx_regs (regcache); |
330c6ca9 | 476 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 477 | && regno >= ARM_D0_REGNUM |
02ad7fc2 YQ |
478 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count |
479 | || regno == ARM_FPSCR_REGNUM)) | |
3b273a55 | 480 | store_vfp_regs (regcache); |
41c49b06 | 481 | } |
ed9a39eb JM |
482 | } |
483 | ||
cb587d83 DJ |
484 | /* Wrapper functions for the standard regset handling, used by |
485 | thread debugging. */ | |
41c49b06 SB |
486 | |
487 | void | |
7f7fe91e UW |
488 | fill_gregset (const struct regcache *regcache, |
489 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 490 | { |
7f7fe91e | 491 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
492 | } |
493 | ||
41c49b06 | 494 | void |
7f7fe91e | 495 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 496 | { |
7f7fe91e | 497 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
498 | } |
499 | ||
41c49b06 | 500 | void |
7f7fe91e UW |
501 | fill_fpregset (const struct regcache *regcache, |
502 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 503 | { |
7f7fe91e | 504 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
505 | } |
506 | ||
507 | /* Fill GDB's register array with the floating-point register values | |
508 | in *fpregsetp. */ | |
509 | ||
510 | void | |
7f7fe91e | 511 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 512 | { |
7f7fe91e | 513 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
514 | } |
515 | ||
9308fc88 DJ |
516 | /* Fetch the thread-local storage pointer for libthread_db. */ |
517 | ||
518 | ps_err_e | |
754653a7 | 519 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
520 | lwpid_t lwpid, int idx, void **base) |
521 | { | |
522 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
523 | return PS_ERR; | |
524 | ||
525 | /* IDX is the bias from the thread pointer to the beginning of the | |
526 | thread descriptor. It has to be subtracted due to implementation | |
527 | quirks in libthread_db. */ | |
528 | *base = (void *) ((char *)*base - idx); | |
529 | ||
530 | return PS_OK; | |
531 | } | |
532 | ||
f6ac5f3d PA |
533 | const struct target_desc * |
534 | arm_linux_nat_target::read_description () | |
05a4558a | 535 | { |
0f83012e | 536 | CORE_ADDR arm_hwcap = linux_get_hwcap (this); |
05a4558a | 537 | |
0bdb2f78 | 538 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
539 | { |
540 | elf_gregset_t gpregs; | |
541 | struct iovec iov; | |
e38504b3 | 542 | int tid = inferior_ptid.lwp (); |
7efe48d1 YQ |
543 | |
544 | iov.iov_base = &gpregs; | |
545 | iov.iov_len = sizeof (gpregs); | |
546 | ||
547 | /* Check if PTRACE_GETREGSET works. */ | |
548 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 549 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 550 | else |
0bdb2f78 | 551 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
552 | } |
553 | ||
3b273a55 | 554 | if (arm_hwcap & HWCAP_IWMMXT) |
d105cce5 | 555 | return arm_read_description (ARM_FP_TYPE_IWMMXT); |
3b273a55 RE |
556 | |
557 | if (arm_hwcap & HWCAP_VFP) | |
558 | { | |
166a82be AH |
559 | /* Make sure that the kernel supports reading VFP registers. Support was |
560 | added in 2.6.30. */ | |
561 | int pid = inferior_ptid.lwp (); | |
562 | errno = 0; | |
563 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
564 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
565 | return nullptr; | |
3b273a55 RE |
566 | |
567 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
568 | Neon with VFPv3-D32. */ | |
569 | if (arm_hwcap & HWCAP_NEON) | |
d105cce5 | 570 | return aarch32_read_description (); |
3b273a55 | 571 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
d105cce5 AH |
572 | return arm_read_description (ARM_FP_TYPE_VFPV3); |
573 | ||
574 | return arm_read_description (ARM_FP_TYPE_VFPV2); | |
3b273a55 RE |
575 | } |
576 | ||
4360561f | 577 | return this->beneath ()->read_description (); |
05a4558a DJ |
578 | } |
579 | ||
e3039479 UW |
580 | /* Information describing the hardware breakpoint capabilities. */ |
581 | struct arm_linux_hwbp_cap | |
582 | { | |
583 | gdb_byte arch; | |
584 | gdb_byte max_wp_length; | |
585 | gdb_byte wp_count; | |
586 | gdb_byte bp_count; | |
587 | }; | |
588 | ||
638c5f49 OJ |
589 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
590 | assume a maximum number of supported break-/watchpoints. */ | |
591 | #define MAX_BPTS 16 | |
592 | #define MAX_WPTS 16 | |
593 | ||
e3039479 UW |
594 | /* Get hold of the Hardware Breakpoint information for the target we are |
595 | attached to. Returns NULL if the kernel doesn't support Hardware | |
596 | breakpoints at all, or a pointer to the information structure. */ | |
597 | static const struct arm_linux_hwbp_cap * | |
598 | arm_linux_get_hwbp_cap (void) | |
599 | { | |
600 | /* The info structure we return. */ | |
601 | static struct arm_linux_hwbp_cap info; | |
602 | ||
603 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
604 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
605 | means INFO is in an initialized state. */ | |
606 | static int available = -1; | |
607 | ||
608 | if (available == -1) | |
609 | { | |
610 | int tid; | |
611 | unsigned int val; | |
612 | ||
e38504b3 | 613 | tid = inferior_ptid.lwp (); |
e3039479 UW |
614 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
615 | available = 0; | |
616 | else | |
617 | { | |
618 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
619 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
620 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
621 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
622 | |
623 | if (info.wp_count > MAX_WPTS) | |
624 | { | |
625 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
626 | supports %d"), MAX_WPTS, info.wp_count); | |
627 | info.wp_count = MAX_WPTS; | |
628 | } | |
629 | ||
630 | if (info.bp_count > MAX_BPTS) | |
631 | { | |
632 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
633 | supports %d"), MAX_BPTS, info.bp_count); | |
634 | info.bp_count = MAX_BPTS; | |
635 | } | |
e3039479 UW |
636 | available = (info.arch != 0); |
637 | } | |
638 | } | |
639 | ||
640 | return available == 1 ? &info : NULL; | |
641 | } | |
642 | ||
643 | /* How many hardware breakpoints are available? */ | |
644 | static int | |
645 | arm_linux_get_hw_breakpoint_count (void) | |
646 | { | |
647 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
648 | return cap != NULL ? cap->bp_count : 0; | |
649 | } | |
650 | ||
651 | /* How many hardware watchpoints are available? */ | |
652 | static int | |
653 | arm_linux_get_hw_watchpoint_count (void) | |
654 | { | |
655 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
656 | return cap != NULL ? cap->wp_count : 0; | |
657 | } | |
658 | ||
659 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
660 | there is not an appropriate resource available, otherwise returns 1. */ | |
f6ac5f3d PA |
661 | int |
662 | arm_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
663 | int cnt, int ot) | |
e3039479 UW |
664 | { |
665 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
666 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
667 | { | |
dbbf180a YQ |
668 | int count = arm_linux_get_hw_watchpoint_count (); |
669 | ||
670 | if (count == 0) | |
671 | return 0; | |
672 | else if (cnt + ot > count) | |
e3039479 UW |
673 | return -1; |
674 | } | |
675 | else if (type == bp_hardware_breakpoint) | |
676 | { | |
dbbf180a YQ |
677 | int count = arm_linux_get_hw_breakpoint_count (); |
678 | ||
679 | if (count == 0) | |
680 | return 0; | |
681 | else if (cnt > count) | |
e3039479 UW |
682 | return -1; |
683 | } | |
684 | else | |
06d16ec9 | 685 | gdb_assert_not_reached ("unknown breakpoint type"); |
e3039479 UW |
686 | |
687 | return 1; | |
688 | } | |
689 | ||
690 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
691 | typedef enum | |
692 | { | |
693 | arm_hwbp_break = 0, | |
694 | arm_hwbp_load = 1, | |
695 | arm_hwbp_store = 2, | |
696 | arm_hwbp_access = 3 | |
697 | } arm_hwbp_type; | |
698 | ||
699 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
700 | typedef unsigned int arm_hwbp_control_t; | |
701 | ||
702 | /* Structure used to keep track of hardware break-/watch-points. */ | |
703 | struct arm_linux_hw_breakpoint | |
704 | { | |
705 | /* Address to break on, or being watched. */ | |
706 | unsigned int address; | |
707 | /* Control register for break-/watch- point. */ | |
708 | arm_hwbp_control_t control; | |
709 | }; | |
710 | ||
638c5f49 OJ |
711 | /* Structure containing arrays of per process hardware break-/watchpoints |
712 | for caching address and control information. | |
e3039479 UW |
713 | |
714 | The Linux ptrace interface to hardware break-/watch-points presents the | |
715 | values in a vector centred around 0 (which is used fo generic information). | |
716 | Positive indicies refer to breakpoint addresses/control registers, negative | |
717 | indices to watchpoint addresses/control registers. | |
718 | ||
719 | The Linux vector is indexed as follows: | |
720 | -((i << 1) + 2): Control register for watchpoint i. | |
721 | -((i << 1) + 1): Address register for watchpoint i. | |
722 | 0: Information register. | |
723 | ((i << 1) + 1): Address register for breakpoint i. | |
724 | ((i << 1) + 2): Control register for breakpoint i. | |
725 | ||
726 | This structure is used as a per-thread cache of the state stored by the | |
727 | kernel, so that we don't need to keep calling into the kernel to find a | |
728 | free breakpoint. | |
729 | ||
730 | We treat break-/watch-points with their enable bit clear as being deleted. | |
731 | */ | |
638c5f49 | 732 | struct arm_linux_debug_reg_state |
e3039479 | 733 | { |
638c5f49 OJ |
734 | /* Hardware breakpoints for this process. */ |
735 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
736 | /* Hardware watchpoints for this process. */ | |
737 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
738 | }; | |
739 | ||
740 | /* Per-process arch-specific data we want to keep. */ | |
741 | struct arm_linux_process_info | |
e3039479 | 742 | { |
638c5f49 OJ |
743 | /* Linked list. */ |
744 | struct arm_linux_process_info *next; | |
745 | /* The process identifier. */ | |
746 | pid_t pid; | |
747 | /* Hardware break-/watchpoints state information. */ | |
748 | struct arm_linux_debug_reg_state state; | |
e3039479 | 749 | |
638c5f49 OJ |
750 | }; |
751 | ||
752 | /* Per-thread arch-specific data we want to keep. */ | |
753 | struct arch_lwp_info | |
754 | { | |
755 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
756 | char bpts_changed[MAX_BPTS]; | |
757 | char wpts_changed[MAX_WPTS]; | |
758 | }; | |
759 | ||
760 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
761 | ||
762 | /* Find process data for process PID. */ | |
763 | ||
764 | static struct arm_linux_process_info * | |
765 | arm_linux_find_process_pid (pid_t pid) | |
766 | { | |
767 | struct arm_linux_process_info *proc; | |
768 | ||
769 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
770 | if (proc->pid == pid) | |
771 | return proc; | |
772 | ||
773 | return NULL; | |
774 | } | |
775 | ||
776 | /* Add process data for process PID. Returns newly allocated info | |
777 | object. */ | |
778 | ||
779 | static struct arm_linux_process_info * | |
780 | arm_linux_add_process (pid_t pid) | |
781 | { | |
782 | struct arm_linux_process_info *proc; | |
e3039479 | 783 | |
8d749320 | 784 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 785 | proc->pid = pid; |
e3039479 | 786 | |
638c5f49 OJ |
787 | proc->next = arm_linux_process_list; |
788 | arm_linux_process_list = proc; | |
789 | ||
790 | return proc; | |
791 | } | |
792 | ||
793 | /* Get data specific info for process PID, creating it if necessary. | |
794 | Never returns NULL. */ | |
795 | ||
796 | static struct arm_linux_process_info * | |
797 | arm_linux_process_info_get (pid_t pid) | |
798 | { | |
799 | struct arm_linux_process_info *proc; | |
800 | ||
801 | proc = arm_linux_find_process_pid (pid); | |
802 | if (proc == NULL) | |
803 | proc = arm_linux_add_process (pid); | |
804 | ||
805 | return proc; | |
806 | } | |
807 | ||
808 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
809 | data structures that keep track of debug register state. */ | |
810 | ||
135340af PA |
811 | void |
812 | arm_linux_nat_target::low_forget_process (pid_t pid) | |
638c5f49 OJ |
813 | { |
814 | struct arm_linux_process_info *proc, **proc_link; | |
815 | ||
816 | proc = arm_linux_process_list; | |
817 | proc_link = &arm_linux_process_list; | |
818 | ||
819 | while (proc != NULL) | |
820 | { | |
821 | if (proc->pid == pid) | |
e3039479 | 822 | { |
638c5f49 OJ |
823 | *proc_link = proc->next; |
824 | ||
825 | xfree (proc); | |
826 | return; | |
e3039479 UW |
827 | } |
828 | ||
638c5f49 OJ |
829 | proc_link = &proc->next; |
830 | proc = *proc_link; | |
831 | } | |
832 | } | |
833 | ||
834 | /* Get hardware break-/watchpoint state for process PID. */ | |
835 | ||
836 | static struct arm_linux_debug_reg_state * | |
837 | arm_linux_get_debug_reg_state (pid_t pid) | |
838 | { | |
839 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
840 | } |
841 | ||
842 | /* Initialize an ARM hardware break-/watch-point control register value. | |
843 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
844 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
845 | */ | |
846 | static arm_hwbp_control_t | |
847 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
848 | arm_hwbp_type hwbp_type, | |
849 | int enable) | |
850 | { | |
851 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
852 | gdb_assert (hwbp_type != arm_hwbp_break | |
853 | || ((byte_address_select & 0xfU) != 0)); | |
854 | ||
855 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
856 | } | |
857 | ||
858 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
859 | static int | |
860 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
861 | { | |
862 | return control & 0x1; | |
863 | } | |
864 | ||
865 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
866 | static arm_hwbp_control_t | |
867 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
868 | { | |
869 | return control & ~0x1; | |
870 | } | |
871 | ||
872 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
873 | enabled, and will point to the placed address of BP_TGT. */ | |
874 | static void | |
875 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
876 | struct bp_target_info *bp_tgt, | |
877 | struct arm_linux_hw_breakpoint *p) | |
878 | { | |
879 | unsigned mask; | |
0d5ed153 | 880 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
881 | |
882 | /* We have to create a mask for the control register which says which bits | |
883 | of the word pointed to by address to break on. */ | |
884 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
885 | { |
886 | mask = 0x3; | |
887 | address &= ~1; | |
888 | } | |
e3039479 | 889 | else |
fcf303ab UW |
890 | { |
891 | mask = 0xf; | |
892 | address &= ~3; | |
893 | } | |
e3039479 | 894 | |
fcf303ab | 895 | p->address = (unsigned int) address; |
e3039479 UW |
896 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
897 | } | |
898 | ||
8156fe7f | 899 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 900 | given when asked to set a watchpoint. */ |
e3039479 | 901 | static arm_hwbp_type |
f486487f | 902 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 903 | { |
8156fe7f | 904 | if (type == hw_read) |
e3039479 | 905 | return arm_hwbp_load; |
8156fe7f | 906 | else if (type == hw_write) |
e3039479 UW |
907 | return arm_hwbp_store; |
908 | else | |
909 | return arm_hwbp_access; | |
910 | } | |
911 | ||
912 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
913 | to LEN. The type of watchpoint is given in RW. */ | |
914 | static void | |
f486487f SM |
915 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
916 | enum target_hw_bp_type type, | |
e3039479 UW |
917 | struct arm_linux_hw_breakpoint *p) |
918 | { | |
919 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
920 | unsigned mask; | |
921 | ||
922 | gdb_assert (cap != NULL); | |
923 | gdb_assert (cap->max_wp_length != 0); | |
924 | ||
925 | mask = (1 << len) - 1; | |
926 | ||
927 | p->address = (unsigned int) addr; | |
928 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 929 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
930 | } |
931 | ||
932 | /* Are two break-/watch-points equal? */ | |
933 | static int | |
934 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
935 | const struct arm_linux_hw_breakpoint *p2) | |
936 | { | |
937 | return p1->address == p2->address && p1->control == p2->control; | |
938 | } | |
939 | ||
638c5f49 OJ |
940 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
941 | the current process. */ | |
942 | ||
638c5f49 | 943 | static int |
d3a70e03 | 944 | update_registers_callback (struct lwp_info *lwp, int watch, int index) |
638c5f49 | 945 | { |
638c5f49 OJ |
946 | if (lwp->arch_private == NULL) |
947 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
948 | ||
949 | /* The actual update is done later just before resuming the lwp, | |
950 | we just mark that the registers need updating. */ | |
d3a70e03 TT |
951 | if (watch) |
952 | lwp->arch_private->wpts_changed[index] = 1; | |
638c5f49 | 953 | else |
d3a70e03 | 954 | lwp->arch_private->bpts_changed[index] = 1; |
638c5f49 OJ |
955 | |
956 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
957 | we can update its breakpoint registers. */ | |
958 | if (!lwp->stopped) | |
959 | linux_stop_lwp (lwp); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
e3039479 UW |
964 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
965 | =1) BPT for thread TID. */ | |
966 | static void | |
967 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 968 | int watchpoint) |
e3039479 | 969 | { |
638c5f49 OJ |
970 | int pid; |
971 | ptid_t pid_ptid; | |
e3039479 UW |
972 | gdb_byte count, i; |
973 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 974 | |
e99b03dc | 975 | pid = inferior_ptid.pid (); |
f2907e49 | 976 | pid_ptid = ptid_t (pid); |
e3039479 UW |
977 | |
978 | if (watchpoint) | |
979 | { | |
980 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 981 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
982 | } |
983 | else | |
984 | { | |
985 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 986 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
987 | } |
988 | ||
989 | for (i = 0; i < count; ++i) | |
990 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
991 | { | |
638c5f49 | 992 | bpts[i] = *bpt; |
d3a70e03 TT |
993 | iterate_over_lwps (pid_ptid, |
994 | [=] (struct lwp_info *info) | |
995 | { | |
3a0e45b2 AH |
996 | return update_registers_callback (info, watchpoint, |
997 | i); | |
d3a70e03 | 998 | }); |
638c5f49 | 999 | break; |
e3039479 UW |
1000 | } |
1001 | ||
1002 | gdb_assert (i != count); | |
1003 | } | |
1004 | ||
1005 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1006 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1007 | static void | |
1008 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1009 | int watchpoint) |
e3039479 | 1010 | { |
638c5f49 | 1011 | int pid; |
e3039479 | 1012 | gdb_byte count, i; |
638c5f49 OJ |
1013 | ptid_t pid_ptid; |
1014 | struct arm_linux_hw_breakpoint* bpts; | |
e3039479 | 1015 | |
e99b03dc | 1016 | pid = inferior_ptid.pid (); |
f2907e49 | 1017 | pid_ptid = ptid_t (pid); |
e3039479 UW |
1018 | |
1019 | if (watchpoint) | |
1020 | { | |
1021 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1022 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1023 | } |
1024 | else | |
1025 | { | |
1026 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1027 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1028 | } |
1029 | ||
1030 | for (i = 0; i < count; ++i) | |
1031 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1032 | { | |
638c5f49 | 1033 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); |
3a0e45b2 AH |
1034 | iterate_over_lwps (pid_ptid, |
1035 | [=] (struct lwp_info *info) | |
1036 | { | |
1037 | return update_registers_callback (info, watchpoint, | |
1038 | i); | |
1039 | }); | |
638c5f49 | 1040 | break; |
e3039479 UW |
1041 | } |
1042 | ||
1043 | gdb_assert (i != count); | |
1044 | } | |
1045 | ||
1046 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1047 | int |
1048 | arm_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
1049 | struct bp_target_info *bp_tgt) | |
e3039479 | 1050 | { |
e3039479 UW |
1051 | struct arm_linux_hw_breakpoint p; |
1052 | ||
1053 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1054 | return -1; | |
1055 | ||
1056 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1057 | |
1058 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1059 | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1064 | int |
1065 | arm_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
1066 | struct bp_target_info *bp_tgt) | |
e3039479 | 1067 | { |
e3039479 UW |
1068 | struct arm_linux_hw_breakpoint p; |
1069 | ||
1070 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1071 | return -1; | |
1072 | ||
1073 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1074 | |
1075 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1076 | |
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1081 | ADDR? */ | |
f6ac5f3d PA |
1082 | int |
1083 | arm_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e3039479 UW |
1084 | { |
1085 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1086 | CORE_ADDR max_wp_length, aligned_addr; | |
1087 | ||
1088 | /* Can not set watchpoints for zero or negative lengths. */ | |
1089 | if (len <= 0) | |
1090 | return 0; | |
1091 | ||
1092 | /* Need to be able to use the ptrace interface. */ | |
1093 | if (cap == NULL || cap->wp_count == 0) | |
1094 | return 0; | |
1095 | ||
1096 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1097 | range covered by a watchpoint. */ | |
1098 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1099 | aligned_addr = addr & ~(max_wp_length - 1); | |
1100 | ||
1101 | if (aligned_addr + max_wp_length < addr + len) | |
1102 | return 0; | |
1103 | ||
1104 | /* The current ptrace interface can only handle watchpoints that are a | |
1105 | power of 2. */ | |
1106 | if ((len & (len - 1)) != 0) | |
1107 | return 0; | |
1108 | ||
1109 | /* All tests passed so we must be able to set a watchpoint. */ | |
1110 | return 1; | |
1111 | } | |
1112 | ||
1113 | /* Insert a Hardware breakpoint. */ | |
f6ac5f3d PA |
1114 | int |
1115 | arm_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
1116 | enum target_hw_bp_type rw, | |
1117 | struct expression *cond) | |
e3039479 | 1118 | { |
e3039479 UW |
1119 | struct arm_linux_hw_breakpoint p; |
1120 | ||
1121 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1122 | return -1; | |
1123 | ||
1124 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1125 | |
1126 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1127 | |
1128 | return 0; | |
1129 | } | |
1130 | ||
1131 | /* Remove a hardware breakpoint. */ | |
f6ac5f3d PA |
1132 | int |
1133 | arm_linux_nat_target::remove_watchpoint (CORE_ADDR addr, | |
1134 | int len, enum target_hw_bp_type rw, | |
1135 | struct expression *cond) | |
e3039479 | 1136 | { |
e3039479 UW |
1137 | struct arm_linux_hw_breakpoint p; |
1138 | ||
1139 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1140 | return -1; | |
1141 | ||
1142 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1143 | |
1144 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1145 | |
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | /* What was the data address the target was stopped on accessing. */ | |
57810aa7 | 1150 | bool |
f6ac5f3d | 1151 | arm_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
e3039479 | 1152 | { |
f865ee35 JK |
1153 | siginfo_t siginfo; |
1154 | int slot; | |
1155 | ||
1156 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 1157 | return false; |
e3039479 UW |
1158 | |
1159 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1160 | if (siginfo.si_signo != SIGTRAP |
1161 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 1162 | return false; |
e3039479 UW |
1163 | |
1164 | /* We must be able to set hardware watchpoints. */ | |
1165 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1166 | return 0; | |
1167 | ||
f865ee35 JK |
1168 | slot = siginfo.si_errno; |
1169 | ||
e3039479 UW |
1170 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1171 | a watchpoint. */ | |
1172 | if (slot >= 0) | |
57810aa7 | 1173 | return false; |
e3039479 | 1174 | |
f865ee35 | 1175 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 1176 | return true; |
e3039479 UW |
1177 | } |
1178 | ||
1179 | /* Has the target been stopped by hitting a watchpoint? */ | |
57810aa7 | 1180 | bool |
f6ac5f3d | 1181 | arm_linux_nat_target::stopped_by_watchpoint () |
e3039479 UW |
1182 | { |
1183 | CORE_ADDR addr; | |
f6ac5f3d | 1184 | return stopped_data_address (&addr); |
e3039479 UW |
1185 | } |
1186 | ||
57810aa7 | 1187 | bool |
f6ac5f3d PA |
1188 | arm_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
1189 | CORE_ADDR start, | |
1190 | int length) | |
e3039479 UW |
1191 | { |
1192 | return start <= addr && start + length - 1 >= addr; | |
1193 | } | |
1194 | ||
1195 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1196 | in the parent thread to the child thread. */ | |
135340af PA |
1197 | void |
1198 | arm_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
e3039479 | 1199 | { |
638c5f49 OJ |
1200 | int i; |
1201 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1202 | ||
1203 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1204 | for this thread need to be initialized. */ | |
e3039479 | 1205 | |
638c5f49 | 1206 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1207 | { |
638c5f49 OJ |
1208 | info->bpts_changed[i] = 1; |
1209 | info->wpts_changed[i] = 1; | |
e3039479 | 1210 | } |
638c5f49 OJ |
1211 | |
1212 | lp->arch_private = info; | |
e3039479 UW |
1213 | } |
1214 | ||
466eecee SM |
1215 | /* Function to call when a thread is being deleted. */ |
1216 | ||
135340af PA |
1217 | void |
1218 | arm_linux_nat_target::low_delete_thread (struct arch_lwp_info *arch_lwp) | |
466eecee SM |
1219 | { |
1220 | xfree (arch_lwp); | |
1221 | } | |
1222 | ||
638c5f49 OJ |
1223 | /* Called when resuming a thread. |
1224 | The hardware debug registers are updated when there is any change. */ | |
1225 | ||
135340af PA |
1226 | void |
1227 | arm_linux_nat_target::low_prepare_to_resume (struct lwp_info *lwp) | |
e3039479 | 1228 | { |
638c5f49 OJ |
1229 | int pid, i; |
1230 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1231 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1232 | ||
e38504b3 | 1233 | pid = lwp->ptid.lwp (); |
e99b03dc TT |
1234 | bpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->bpts; |
1235 | wpts = arm_linux_get_debug_reg_state (lwp->ptid.pid ())->wpts; | |
638c5f49 OJ |
1236 | |
1237 | /* NULL means this is the main thread still going through the shell, | |
1238 | or, no watchpoint has been set yet. In that case, there's | |
1239 | nothing to do. */ | |
1240 | if (arm_lwp_info == NULL) | |
1241 | return; | |
e3039479 | 1242 | |
638c5f49 OJ |
1243 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1244 | if (arm_lwp_info->bpts_changed[i]) | |
1245 | { | |
1246 | errno = 0; | |
1247 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1248 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1249 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1250 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1251 | ||
1252 | if (bpts[i].control != 0) | |
1253 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1254 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1255 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1256 | ||
1257 | arm_lwp_info->bpts_changed[i] = 0; | |
1258 | } | |
e3039479 | 1259 | |
638c5f49 OJ |
1260 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1261 | if (arm_lwp_info->wpts_changed[i]) | |
1262 | { | |
1263 | errno = 0; | |
1264 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1265 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1266 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1267 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1268 | ||
1269 | if (wpts[i].control != 0) | |
1270 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1271 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1272 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1273 | ||
1274 | arm_lwp_info->wpts_changed[i] = 0; | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | /* linux_nat_new_fork hook. */ | |
1279 | ||
135340af PA |
1280 | void |
1281 | arm_linux_nat_target::low_new_fork (struct lwp_info *parent, pid_t child_pid) | |
638c5f49 OJ |
1282 | { |
1283 | pid_t parent_pid; | |
1284 | struct arm_linux_debug_reg_state *parent_state; | |
1285 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1286 | |
638c5f49 OJ |
1287 | /* NULL means no watchpoint has ever been set in the parent. In |
1288 | that case, there's nothing to do. */ | |
1289 | if (parent->arch_private == NULL) | |
1290 | return; | |
e3039479 | 1291 | |
638c5f49 OJ |
1292 | /* GDB core assumes the child inherits the watchpoints/hw |
1293 | breakpoints of the parent, and will remove them all from the | |
1294 | forked off process. Copy the debug registers mirrors into the | |
1295 | new process so that all breakpoints and watchpoints can be | |
1296 | removed together. */ | |
e3039479 | 1297 | |
e99b03dc | 1298 | parent_pid = parent->ptid.pid (); |
638c5f49 OJ |
1299 | parent_state = arm_linux_get_debug_reg_state (parent_pid); |
1300 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1301 | *child_state = *parent_state; | |
e3039479 UW |
1302 | } |
1303 | ||
ed9a39eb JM |
1304 | void |
1305 | _initialize_arm_linux_nat (void) | |
1306 | { | |
10d6c8cd | 1307 | /* Register the target. */ |
f6ac5f3d | 1308 | linux_target = &the_arm_linux_nat_target; |
d9f719f1 | 1309 | add_inf_child_target (&the_arm_linux_nat_target); |
ed9a39eb | 1310 | } |