Commit | Line | Data |
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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
32d0add0 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
aeb98c60 | 32 | |
3b273a55 | 33 | #include <elf/common.h> |
ed9a39eb JM |
34 | #include <sys/user.h> |
35 | #include <sys/ptrace.h> | |
36 | #include <sys/utsname.h> | |
41c49b06 | 37 | #include <sys/procfs.h> |
ed9a39eb | 38 | |
0963b4bd | 39 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
40 | #include "gregset.h" |
41 | ||
9308fc88 DJ |
42 | /* Defines ps_err_e, struct ps_prochandle. */ |
43 | #include "gdb_proc_service.h" | |
44 | ||
45 | #ifndef PTRACE_GET_THREAD_AREA | |
46 | #define PTRACE_GET_THREAD_AREA 22 | |
47 | #endif | |
48 | ||
05a4558a DJ |
49 | #ifndef PTRACE_GETWMMXREGS |
50 | #define PTRACE_GETWMMXREGS 18 | |
51 | #define PTRACE_SETWMMXREGS 19 | |
52 | #endif | |
53 | ||
3b273a55 RE |
54 | #ifndef PTRACE_GETVFPREGS |
55 | #define PTRACE_GETVFPREGS 27 | |
56 | #define PTRACE_SETVFPREGS 28 | |
57 | #endif | |
58 | ||
e3039479 UW |
59 | #ifndef PTRACE_GETHBPREGS |
60 | #define PTRACE_GETHBPREGS 29 | |
61 | #define PTRACE_SETHBPREGS 30 | |
62 | #endif | |
63 | ||
ed9a39eb JM |
64 | extern int arm_apcs_32; |
65 | ||
fdf39c9a | 66 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
41c49b06 | 67 | case we may be tracing more than one process at a time. In that |
39f77062 | 68 | case, inferior_ptid will contain the main process ID and the |
fdf39c9a RE |
69 | individual thread (process) ID. get_thread_id () is used to get |
70 | the thread id if it's available, and the process id otherwise. */ | |
41c49b06 | 71 | |
4e841acf | 72 | static int |
39f77062 | 73 | get_thread_id (ptid_t ptid) |
41c49b06 | 74 | { |
dfd4cc63 | 75 | int tid = ptid_get_lwp (ptid); |
39f77062 | 76 | if (0 == tid) |
dfd4cc63 | 77 | tid = ptid_get_pid (ptid); |
41c49b06 SB |
78 | return tid; |
79 | } | |
3b273a55 | 80 | |
05a4558a | 81 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) |
41c49b06 | 82 | |
41c49b06 | 83 | /* Get the value of a particular register from the floating point |
c6b92abd | 84 | state of the process and store it into regcache. */ |
41c49b06 SB |
85 | |
86 | static void | |
56be3814 | 87 | fetch_fpregister (struct regcache *regcache, int regno) |
41c49b06 SB |
88 | { |
89 | int ret, tid; | |
cb587d83 | 90 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
91 | |
92 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 93 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
94 | |
95 | /* Read the floating point state. */ | |
cb587d83 | 96 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
97 | if (ret < 0) |
98 | { | |
edefbb7c | 99 | warning (_("Unable to fetch floating point register.")); |
41c49b06 SB |
100 | return; |
101 | } | |
102 | ||
103 | /* Fetch fpsr. */ | |
34e8f22d | 104 | if (ARM_FPS_REGNUM == regno) |
56be3814 | 105 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 106 | fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
107 | |
108 | /* Fetch the floating point register. */ | |
34e8f22d | 109 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 110 | supply_nwfpe_register (regcache, regno, fp); |
41c49b06 SB |
111 | } |
112 | ||
113 | /* Get the whole floating point state of the process and store it | |
c6b92abd | 114 | into regcache. */ |
ed9a39eb JM |
115 | |
116 | static void | |
56be3814 | 117 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 118 | { |
41c49b06 | 119 | int ret, regno, tid; |
cb587d83 | 120 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 121 | |
41c49b06 | 122 | /* Get the thread id for the ptrace call. */ |
39f77062 | 123 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 | 124 | |
ed9a39eb | 125 | /* Read the floating point state. */ |
cb587d83 | 126 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
ed9a39eb JM |
127 | if (ret < 0) |
128 | { | |
edefbb7c | 129 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
130 | return; |
131 | } | |
132 | ||
133 | /* Fetch fpsr. */ | |
56be3814 | 134 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 135 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
136 | |
137 | /* Fetch the floating point registers. */ | |
34e8f22d | 138 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 139 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
140 | } |
141 | ||
41c49b06 | 142 | /* Save a particular register into the floating point state of the |
c6b92abd | 143 | process using the contents from regcache. */ |
41c49b06 SB |
144 | |
145 | static void | |
56be3814 | 146 | store_fpregister (const struct regcache *regcache, int regno) |
41c49b06 SB |
147 | { |
148 | int ret, tid; | |
cb587d83 | 149 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
150 | |
151 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 152 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
153 | |
154 | /* Read the floating point state. */ | |
cb587d83 | 155 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
156 | if (ret < 0) |
157 | { | |
edefbb7c | 158 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
159 | return; |
160 | } | |
161 | ||
162 | /* Store fpsr. */ | |
672c9795 YQ |
163 | if (ARM_FPS_REGNUM == regno |
164 | && REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) | |
56be3814 | 165 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
166 | |
167 | /* Store the floating point register. */ | |
34e8f22d | 168 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 169 | collect_nwfpe_register (regcache, regno, fp); |
41c49b06 | 170 | |
cb587d83 | 171 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
41c49b06 SB |
172 | if (ret < 0) |
173 | { | |
edefbb7c | 174 | warning (_("Unable to store floating point register.")); |
41c49b06 SB |
175 | return; |
176 | } | |
177 | } | |
178 | ||
ed9a39eb | 179 | /* Save the whole floating point state of the process using |
c6b92abd | 180 | the contents from regcache. */ |
ed9a39eb JM |
181 | |
182 | static void | |
56be3814 | 183 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 184 | { |
41c49b06 | 185 | int ret, regno, tid; |
cb587d83 | 186 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 187 | |
41c49b06 | 188 | /* Get the thread id for the ptrace call. */ |
39f77062 | 189 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
190 | |
191 | /* Read the floating point state. */ | |
cb587d83 | 192 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
193 | if (ret < 0) |
194 | { | |
edefbb7c | 195 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
196 | return; |
197 | } | |
198 | ||
ed9a39eb | 199 | /* Store fpsr. */ |
672c9795 | 200 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 201 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
202 | |
203 | /* Store the floating point registers. */ | |
34e8f22d | 204 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 205 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 206 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 207 | |
cb587d83 | 208 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
ed9a39eb JM |
209 | if (ret < 0) |
210 | { | |
edefbb7c | 211 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
212 | return; |
213 | } | |
214 | } | |
215 | ||
41c49b06 | 216 | /* Fetch a general register of the process and store into |
c6b92abd | 217 | regcache. */ |
41c49b06 SB |
218 | |
219 | static void | |
56be3814 | 220 | fetch_register (struct regcache *regcache, int regno) |
41c49b06 SB |
221 | { |
222 | int ret, tid; | |
c2152441 | 223 | elf_gregset_t regs; |
41c49b06 SB |
224 | |
225 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 226 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 YQ |
227 | |
228 | if (have_ptrace_getregset) | |
229 | { | |
230 | struct iovec iov; | |
231 | ||
232 | iov.iov_base = ®s; | |
233 | iov.iov_len = sizeof (regs); | |
234 | ||
235 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
236 | } | |
237 | else | |
238 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
239 | ||
41c49b06 SB |
240 | if (ret < 0) |
241 | { | |
edefbb7c | 242 | warning (_("Unable to fetch general register.")); |
41c49b06 SB |
243 | return; |
244 | } | |
245 | ||
34e8f22d | 246 | if (regno >= ARM_A1_REGNUM && regno < ARM_PC_REGNUM) |
56be3814 | 247 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
41c49b06 | 248 | |
34e8f22d | 249 | if (ARM_PS_REGNUM == regno) |
41c49b06 SB |
250 | { |
251 | if (arm_apcs_32) | |
56be3814 | 252 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 253 | (char *) ®s[ARM_CPSR_GREGNUM]); |
41c49b06 | 254 | else |
56be3814 | 255 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 256 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
257 | } |
258 | ||
34e8f22d | 259 | if (ARM_PC_REGNUM == regno) |
41c49b06 | 260 | { |
bf6ae464 | 261 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 UW |
262 | (get_regcache_arch (regcache), |
263 | regs[ARM_PC_REGNUM]); | |
56be3814 | 264 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 265 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
266 | } |
267 | } | |
268 | ||
ed9a39eb | 269 | /* Fetch all general registers of the process and store into |
c6b92abd | 270 | regcache. */ |
ed9a39eb JM |
271 | |
272 | static void | |
56be3814 | 273 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 274 | { |
41c49b06 | 275 | int ret, regno, tid; |
c2152441 | 276 | elf_gregset_t regs; |
ed9a39eb | 277 | |
41c49b06 | 278 | /* Get the thread id for the ptrace call. */ |
39f77062 | 279 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 YQ |
280 | |
281 | if (have_ptrace_getregset) | |
282 | { | |
283 | struct iovec iov; | |
284 | ||
285 | iov.iov_base = ®s; | |
286 | iov.iov_len = sizeof (regs); | |
287 | ||
288 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
289 | } | |
290 | else | |
291 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
292 | ||
ed9a39eb JM |
293 | if (ret < 0) |
294 | { | |
edefbb7c | 295 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
296 | return; |
297 | } | |
298 | ||
34e8f22d | 299 | for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++) |
56be3814 | 300 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
301 | |
302 | if (arm_apcs_32) | |
56be3814 | 303 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 304 | (char *) ®s[ARM_CPSR_GREGNUM]); |
ed9a39eb | 305 | else |
56be3814 | 306 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 307 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb | 308 | |
bf6ae464 | 309 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 | 310 | (get_regcache_arch (regcache), regs[ARM_PC_REGNUM]); |
56be3814 | 311 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 312 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb JM |
313 | } |
314 | ||
315 | /* Store all general registers of the process from the values in | |
c6b92abd | 316 | regcache. */ |
ed9a39eb | 317 | |
41c49b06 | 318 | static void |
56be3814 | 319 | store_register (const struct regcache *regcache, int regno) |
41c49b06 SB |
320 | { |
321 | int ret, tid; | |
c2152441 | 322 | elf_gregset_t regs; |
41c49b06 | 323 | |
672c9795 | 324 | if (REG_VALID != regcache_register_status (regcache, regno)) |
41c49b06 SB |
325 | return; |
326 | ||
327 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 328 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 329 | |
41c49b06 | 330 | /* Get the general registers from the process. */ |
10766686 YQ |
331 | if (have_ptrace_getregset) |
332 | { | |
333 | struct iovec iov; | |
334 | ||
335 | iov.iov_base = ®s; | |
336 | iov.iov_len = sizeof (regs); | |
337 | ||
338 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
339 | } | |
340 | else | |
341 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
342 | ||
41c49b06 SB |
343 | if (ret < 0) |
344 | { | |
edefbb7c | 345 | warning (_("Unable to fetch general registers.")); |
41c49b06 SB |
346 | return; |
347 | } | |
348 | ||
34e8f22d | 349 | if (regno >= ARM_A1_REGNUM && regno <= ARM_PC_REGNUM) |
56be3814 | 350 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
adb8a87c | 351 | else if (arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 352 | regcache_raw_collect (regcache, regno, |
17c12639 | 353 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 354 | else if (!arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 355 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
adb8a87c | 356 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 | 357 | |
10766686 YQ |
358 | if (have_ptrace_getregset) |
359 | { | |
360 | struct iovec iov; | |
361 | ||
362 | iov.iov_base = ®s; | |
363 | iov.iov_len = sizeof (regs); | |
364 | ||
365 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
366 | } | |
367 | else | |
368 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
369 | ||
41c49b06 SB |
370 | if (ret < 0) |
371 | { | |
edefbb7c | 372 | warning (_("Unable to store general register.")); |
41c49b06 SB |
373 | return; |
374 | } | |
375 | } | |
376 | ||
ed9a39eb | 377 | static void |
56be3814 | 378 | store_regs (const struct regcache *regcache) |
ed9a39eb | 379 | { |
41c49b06 | 380 | int ret, regno, tid; |
c2152441 | 381 | elf_gregset_t regs; |
ed9a39eb | 382 | |
41c49b06 | 383 | /* Get the thread id for the ptrace call. */ |
39f77062 | 384 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 385 | |
41c49b06 | 386 | /* Fetch the general registers. */ |
10766686 YQ |
387 | if (have_ptrace_getregset) |
388 | { | |
389 | struct iovec iov; | |
390 | ||
391 | iov.iov_base = ®s; | |
392 | iov.iov_len = sizeof (regs); | |
393 | ||
394 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
395 | } | |
396 | else | |
397 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
398 | ||
ed9a39eb JM |
399 | if (ret < 0) |
400 | { | |
edefbb7c | 401 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
402 | return; |
403 | } | |
404 | ||
34e8f22d | 405 | for (regno = ARM_A1_REGNUM; regno <= ARM_PC_REGNUM; regno++) |
ed9a39eb | 406 | { |
672c9795 | 407 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 408 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
409 | } |
410 | ||
672c9795 | 411 | if (arm_apcs_32 && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM)) |
56be3814 | 412 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
17c12639 | 413 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 414 | |
10766686 YQ |
415 | if (have_ptrace_getregset) |
416 | { | |
417 | struct iovec iov; | |
418 | ||
419 | iov.iov_base = ®s; | |
420 | iov.iov_len = sizeof (regs); | |
421 | ||
422 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
423 | } | |
424 | else | |
425 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
426 | |
427 | if (ret < 0) | |
428 | { | |
edefbb7c | 429 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
430 | return; |
431 | } | |
432 | } | |
433 | ||
05a4558a DJ |
434 | /* Fetch all WMMX registers of the process and store into |
435 | regcache. */ | |
436 | ||
437 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
438 | ||
439 | static void | |
56be3814 | 440 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
441 | { |
442 | char regbuf[IWMMXT_REGS_SIZE]; | |
443 | int ret, regno, tid; | |
444 | ||
445 | /* Get the thread id for the ptrace call. */ | |
446 | tid = GET_THREAD_ID (inferior_ptid); | |
447 | ||
448 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
449 | if (ret < 0) | |
450 | { | |
451 | warning (_("Unable to fetch WMMX registers.")); | |
452 | return; | |
453 | } | |
454 | ||
455 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 456 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
457 | ®buf[regno * 8]); |
458 | ||
459 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 460 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
461 | ®buf[16 * 8 + regno * 4]); |
462 | ||
463 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 464 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
465 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
466 | } | |
467 | ||
468 | static void | |
56be3814 | 469 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
470 | { |
471 | char regbuf[IWMMXT_REGS_SIZE]; | |
472 | int ret, regno, tid; | |
473 | ||
474 | /* Get the thread id for the ptrace call. */ | |
475 | tid = GET_THREAD_ID (inferior_ptid); | |
476 | ||
477 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
478 | if (ret < 0) | |
479 | { | |
480 | warning (_("Unable to fetch WMMX registers.")); | |
481 | return; | |
482 | } | |
483 | ||
484 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
485 | if (REG_VALID == regcache_register_status (regcache, |
486 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 487 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
488 | ®buf[regno * 8]); |
489 | ||
490 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
491 | if (REG_VALID == regcache_register_status (regcache, |
492 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 493 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
494 | ®buf[16 * 8 + regno * 4]); |
495 | ||
496 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
497 | if (REG_VALID == regcache_register_status (regcache, |
498 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 499 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
500 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
501 | ||
502 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
503 | ||
504 | if (ret < 0) | |
505 | { | |
506 | warning (_("Unable to store WMMX registers.")); | |
507 | return; | |
508 | } | |
509 | } | |
510 | ||
3b273a55 RE |
511 | /* Fetch and store VFP Registers. The kernel object has space for 32 |
512 | 64-bit registers, and the FPSCR. This is even when on a VFPv2 or | |
513 | VFPv3D16 target. */ | |
514 | #define VFP_REGS_SIZE (32 * 8 + 4) | |
515 | ||
516 | static void | |
517 | fetch_vfp_regs (struct regcache *regcache) | |
518 | { | |
519 | char regbuf[VFP_REGS_SIZE]; | |
520 | int ret, regno, tid; | |
330c6ca9 YQ |
521 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
522 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
523 | |
524 | /* Get the thread id for the ptrace call. */ | |
525 | tid = GET_THREAD_ID (inferior_ptid); | |
526 | ||
527 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
528 | if (ret < 0) | |
529 | { | |
530 | warning (_("Unable to fetch VFP registers.")); | |
531 | return; | |
532 | } | |
533 | ||
330c6ca9 | 534 | for (regno = 0; regno < tdep->vfp_register_count; regno++) |
3b273a55 RE |
535 | regcache_raw_supply (regcache, regno + ARM_D0_REGNUM, |
536 | (char *) regbuf + regno * 8); | |
537 | ||
538 | regcache_raw_supply (regcache, ARM_FPSCR_REGNUM, | |
539 | (char *) regbuf + 32 * 8); | |
540 | } | |
541 | ||
542 | static void | |
543 | store_vfp_regs (const struct regcache *regcache) | |
544 | { | |
545 | char regbuf[VFP_REGS_SIZE]; | |
546 | int ret, regno, tid; | |
330c6ca9 YQ |
547 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
548 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
549 | |
550 | /* Get the thread id for the ptrace call. */ | |
551 | tid = GET_THREAD_ID (inferior_ptid); | |
552 | ||
553 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
554 | if (ret < 0) | |
555 | { | |
556 | warning (_("Unable to fetch VFP registers (for update).")); | |
557 | return; | |
558 | } | |
559 | ||
330c6ca9 | 560 | for (regno = 0; regno < tdep->vfp_register_count; regno++) |
3b273a55 RE |
561 | regcache_raw_collect (regcache, regno + ARM_D0_REGNUM, |
562 | (char *) regbuf + regno * 8); | |
563 | ||
564 | regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, | |
565 | (char *) regbuf + 32 * 8); | |
566 | ||
567 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
568 | ||
569 | if (ret < 0) | |
570 | { | |
571 | warning (_("Unable to store VFP registers.")); | |
572 | return; | |
573 | } | |
574 | } | |
575 | ||
ed9a39eb JM |
576 | /* Fetch registers from the child process. Fetch all registers if |
577 | regno == -1, otherwise fetch all general registers or all floating | |
578 | point registers depending upon the value of regno. */ | |
579 | ||
10d6c8cd | 580 | static void |
28439f5e PA |
581 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
582 | struct regcache *regcache, int regno) | |
ed9a39eb | 583 | { |
330c6ca9 YQ |
584 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
585 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
586 | ||
41c49b06 SB |
587 | if (-1 == regno) |
588 | { | |
56be3814 UW |
589 | fetch_regs (regcache); |
590 | fetch_fpregs (regcache); | |
a56cc1ce | 591 | if (tdep->have_wmmx_registers) |
56be3814 | 592 | fetch_wmmx_regs (regcache); |
330c6ca9 | 593 | if (tdep->vfp_register_count > 0) |
3b273a55 | 594 | fetch_vfp_regs (regcache); |
41c49b06 SB |
595 | } |
596 | else | |
597 | { | |
05a4558a | 598 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 599 | fetch_register (regcache, regno); |
05a4558a | 600 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
56be3814 | 601 | fetch_fpregister (regcache, regno); |
a56cc1ce | 602 | else if (tdep->have_wmmx_registers |
05a4558a | 603 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 604 | fetch_wmmx_regs (regcache); |
330c6ca9 | 605 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 606 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 607 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 608 | fetch_vfp_regs (regcache); |
41c49b06 | 609 | } |
ed9a39eb JM |
610 | } |
611 | ||
612 | /* Store registers back into the inferior. Store all registers if | |
613 | regno == -1, otherwise store all general registers or all floating | |
614 | point registers depending upon the value of regno. */ | |
615 | ||
10d6c8cd | 616 | static void |
28439f5e PA |
617 | arm_linux_store_inferior_registers (struct target_ops *ops, |
618 | struct regcache *regcache, int regno) | |
ed9a39eb | 619 | { |
330c6ca9 YQ |
620 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
621 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
622 | ||
41c49b06 SB |
623 | if (-1 == regno) |
624 | { | |
56be3814 UW |
625 | store_regs (regcache); |
626 | store_fpregs (regcache); | |
a56cc1ce | 627 | if (tdep->have_wmmx_registers) |
56be3814 | 628 | store_wmmx_regs (regcache); |
330c6ca9 | 629 | if (tdep->vfp_register_count > 0) |
3b273a55 | 630 | store_vfp_regs (regcache); |
41c49b06 SB |
631 | } |
632 | else | |
633 | { | |
05a4558a | 634 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 635 | store_register (regcache, regno); |
05a4558a | 636 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
56be3814 | 637 | store_fpregister (regcache, regno); |
a56cc1ce | 638 | else if (tdep->have_wmmx_registers |
05a4558a | 639 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 640 | store_wmmx_regs (regcache); |
330c6ca9 | 641 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 642 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 643 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 644 | store_vfp_regs (regcache); |
41c49b06 | 645 | } |
ed9a39eb JM |
646 | } |
647 | ||
cb587d83 DJ |
648 | /* Wrapper functions for the standard regset handling, used by |
649 | thread debugging. */ | |
41c49b06 SB |
650 | |
651 | void | |
7f7fe91e UW |
652 | fill_gregset (const struct regcache *regcache, |
653 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 654 | { |
7f7fe91e | 655 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
656 | } |
657 | ||
41c49b06 | 658 | void |
7f7fe91e | 659 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 660 | { |
7f7fe91e | 661 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
662 | } |
663 | ||
41c49b06 | 664 | void |
7f7fe91e UW |
665 | fill_fpregset (const struct regcache *regcache, |
666 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 667 | { |
7f7fe91e | 668 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
669 | } |
670 | ||
671 | /* Fill GDB's register array with the floating-point register values | |
672 | in *fpregsetp. */ | |
673 | ||
674 | void | |
7f7fe91e | 675 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 676 | { |
7f7fe91e | 677 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
678 | } |
679 | ||
9308fc88 DJ |
680 | /* Fetch the thread-local storage pointer for libthread_db. */ |
681 | ||
682 | ps_err_e | |
683 | ps_get_thread_area (const struct ps_prochandle *ph, | |
684 | lwpid_t lwpid, int idx, void **base) | |
685 | { | |
686 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
687 | return PS_ERR; | |
688 | ||
689 | /* IDX is the bias from the thread pointer to the beginning of the | |
690 | thread descriptor. It has to be subtracted due to implementation | |
691 | quirks in libthread_db. */ | |
692 | *base = (void *) ((char *)*base - idx); | |
693 | ||
694 | return PS_OK; | |
695 | } | |
696 | ||
81adfced DJ |
697 | static const struct target_desc * |
698 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 699 | { |
3b273a55 | 700 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 701 | |
7efe48d1 YQ |
702 | if (have_ptrace_getregset == -1) |
703 | { | |
704 | elf_gregset_t gpregs; | |
705 | struct iovec iov; | |
706 | int tid = GET_THREAD_ID (inferior_ptid); | |
707 | ||
708 | iov.iov_base = &gpregs; | |
709 | iov.iov_len = sizeof (gpregs); | |
710 | ||
711 | /* Check if PTRACE_GETREGSET works. */ | |
712 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
713 | have_ptrace_getregset = 0; | |
714 | else | |
715 | have_ptrace_getregset = 1; | |
716 | } | |
717 | ||
3b273a55 RE |
718 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
719 | { | |
2117c711 | 720 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 721 | } |
81adfced | 722 | |
3b273a55 | 723 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 724 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
725 | |
726 | if (arm_hwcap & HWCAP_VFP) | |
727 | { | |
728 | int pid; | |
729 | char *buf; | |
730 | const struct target_desc * result = NULL; | |
731 | ||
732 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
733 | Neon with VFPv3-D32. */ | |
734 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 735 | result = tdesc_arm_with_neon; |
3b273a55 | 736 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 737 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 738 | else |
330c6ca9 | 739 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
740 | |
741 | /* Now make sure that the kernel supports reading these | |
742 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 743 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
744 | errno = 0; |
745 | buf = alloca (VFP_REGS_SIZE); | |
746 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
747 | && errno == EIO) | |
748 | result = NULL; | |
749 | ||
750 | return result; | |
751 | } | |
752 | ||
2117c711 | 753 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
754 | } |
755 | ||
e3039479 UW |
756 | /* Information describing the hardware breakpoint capabilities. */ |
757 | struct arm_linux_hwbp_cap | |
758 | { | |
759 | gdb_byte arch; | |
760 | gdb_byte max_wp_length; | |
761 | gdb_byte wp_count; | |
762 | gdb_byte bp_count; | |
763 | }; | |
764 | ||
638c5f49 OJ |
765 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
766 | assume a maximum number of supported break-/watchpoints. */ | |
767 | #define MAX_BPTS 16 | |
768 | #define MAX_WPTS 16 | |
769 | ||
e3039479 UW |
770 | /* Get hold of the Hardware Breakpoint information for the target we are |
771 | attached to. Returns NULL if the kernel doesn't support Hardware | |
772 | breakpoints at all, or a pointer to the information structure. */ | |
773 | static const struct arm_linux_hwbp_cap * | |
774 | arm_linux_get_hwbp_cap (void) | |
775 | { | |
776 | /* The info structure we return. */ | |
777 | static struct arm_linux_hwbp_cap info; | |
778 | ||
779 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
780 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
781 | means INFO is in an initialized state. */ | |
782 | static int available = -1; | |
783 | ||
784 | if (available == -1) | |
785 | { | |
786 | int tid; | |
787 | unsigned int val; | |
788 | ||
789 | tid = GET_THREAD_ID (inferior_ptid); | |
790 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
791 | available = 0; | |
792 | else | |
793 | { | |
794 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
795 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
796 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
797 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
798 | |
799 | if (info.wp_count > MAX_WPTS) | |
800 | { | |
801 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
802 | supports %d"), MAX_WPTS, info.wp_count); | |
803 | info.wp_count = MAX_WPTS; | |
804 | } | |
805 | ||
806 | if (info.bp_count > MAX_BPTS) | |
807 | { | |
808 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
809 | supports %d"), MAX_BPTS, info.bp_count); | |
810 | info.bp_count = MAX_BPTS; | |
811 | } | |
e3039479 UW |
812 | available = (info.arch != 0); |
813 | } | |
814 | } | |
815 | ||
816 | return available == 1 ? &info : NULL; | |
817 | } | |
818 | ||
819 | /* How many hardware breakpoints are available? */ | |
820 | static int | |
821 | arm_linux_get_hw_breakpoint_count (void) | |
822 | { | |
823 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
824 | return cap != NULL ? cap->bp_count : 0; | |
825 | } | |
826 | ||
827 | /* How many hardware watchpoints are available? */ | |
828 | static int | |
829 | arm_linux_get_hw_watchpoint_count (void) | |
830 | { | |
831 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
832 | return cap != NULL ? cap->wp_count : 0; | |
833 | } | |
834 | ||
835 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
836 | there is not an appropriate resource available, otherwise returns 1. */ | |
837 | static int | |
5461485a TT |
838 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
839 | int type, int cnt, int ot) | |
e3039479 UW |
840 | { |
841 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
842 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
843 | { | |
dbbf180a YQ |
844 | int count = arm_linux_get_hw_watchpoint_count (); |
845 | ||
846 | if (count == 0) | |
847 | return 0; | |
848 | else if (cnt + ot > count) | |
e3039479 UW |
849 | return -1; |
850 | } | |
851 | else if (type == bp_hardware_breakpoint) | |
852 | { | |
dbbf180a YQ |
853 | int count = arm_linux_get_hw_breakpoint_count (); |
854 | ||
855 | if (count == 0) | |
856 | return 0; | |
857 | else if (cnt > count) | |
e3039479 UW |
858 | return -1; |
859 | } | |
860 | else | |
861 | gdb_assert (FALSE); | |
862 | ||
863 | return 1; | |
864 | } | |
865 | ||
866 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
867 | typedef enum | |
868 | { | |
869 | arm_hwbp_break = 0, | |
870 | arm_hwbp_load = 1, | |
871 | arm_hwbp_store = 2, | |
872 | arm_hwbp_access = 3 | |
873 | } arm_hwbp_type; | |
874 | ||
875 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
876 | typedef unsigned int arm_hwbp_control_t; | |
877 | ||
878 | /* Structure used to keep track of hardware break-/watch-points. */ | |
879 | struct arm_linux_hw_breakpoint | |
880 | { | |
881 | /* Address to break on, or being watched. */ | |
882 | unsigned int address; | |
883 | /* Control register for break-/watch- point. */ | |
884 | arm_hwbp_control_t control; | |
885 | }; | |
886 | ||
638c5f49 OJ |
887 | /* Structure containing arrays of per process hardware break-/watchpoints |
888 | for caching address and control information. | |
e3039479 UW |
889 | |
890 | The Linux ptrace interface to hardware break-/watch-points presents the | |
891 | values in a vector centred around 0 (which is used fo generic information). | |
892 | Positive indicies refer to breakpoint addresses/control registers, negative | |
893 | indices to watchpoint addresses/control registers. | |
894 | ||
895 | The Linux vector is indexed as follows: | |
896 | -((i << 1) + 2): Control register for watchpoint i. | |
897 | -((i << 1) + 1): Address register for watchpoint i. | |
898 | 0: Information register. | |
899 | ((i << 1) + 1): Address register for breakpoint i. | |
900 | ((i << 1) + 2): Control register for breakpoint i. | |
901 | ||
902 | This structure is used as a per-thread cache of the state stored by the | |
903 | kernel, so that we don't need to keep calling into the kernel to find a | |
904 | free breakpoint. | |
905 | ||
906 | We treat break-/watch-points with their enable bit clear as being deleted. | |
907 | */ | |
638c5f49 | 908 | struct arm_linux_debug_reg_state |
e3039479 | 909 | { |
638c5f49 OJ |
910 | /* Hardware breakpoints for this process. */ |
911 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
912 | /* Hardware watchpoints for this process. */ | |
913 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
914 | }; | |
915 | ||
916 | /* Per-process arch-specific data we want to keep. */ | |
917 | struct arm_linux_process_info | |
e3039479 | 918 | { |
638c5f49 OJ |
919 | /* Linked list. */ |
920 | struct arm_linux_process_info *next; | |
921 | /* The process identifier. */ | |
922 | pid_t pid; | |
923 | /* Hardware break-/watchpoints state information. */ | |
924 | struct arm_linux_debug_reg_state state; | |
e3039479 | 925 | |
638c5f49 OJ |
926 | }; |
927 | ||
928 | /* Per-thread arch-specific data we want to keep. */ | |
929 | struct arch_lwp_info | |
930 | { | |
931 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
932 | char bpts_changed[MAX_BPTS]; | |
933 | char wpts_changed[MAX_WPTS]; | |
934 | }; | |
935 | ||
936 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
937 | ||
938 | /* Find process data for process PID. */ | |
939 | ||
940 | static struct arm_linux_process_info * | |
941 | arm_linux_find_process_pid (pid_t pid) | |
942 | { | |
943 | struct arm_linux_process_info *proc; | |
944 | ||
945 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
946 | if (proc->pid == pid) | |
947 | return proc; | |
948 | ||
949 | return NULL; | |
950 | } | |
951 | ||
952 | /* Add process data for process PID. Returns newly allocated info | |
953 | object. */ | |
954 | ||
955 | static struct arm_linux_process_info * | |
956 | arm_linux_add_process (pid_t pid) | |
957 | { | |
958 | struct arm_linux_process_info *proc; | |
e3039479 | 959 | |
638c5f49 OJ |
960 | proc = xcalloc (1, sizeof (*proc)); |
961 | proc->pid = pid; | |
e3039479 | 962 | |
638c5f49 OJ |
963 | proc->next = arm_linux_process_list; |
964 | arm_linux_process_list = proc; | |
965 | ||
966 | return proc; | |
967 | } | |
968 | ||
969 | /* Get data specific info for process PID, creating it if necessary. | |
970 | Never returns NULL. */ | |
971 | ||
972 | static struct arm_linux_process_info * | |
973 | arm_linux_process_info_get (pid_t pid) | |
974 | { | |
975 | struct arm_linux_process_info *proc; | |
976 | ||
977 | proc = arm_linux_find_process_pid (pid); | |
978 | if (proc == NULL) | |
979 | proc = arm_linux_add_process (pid); | |
980 | ||
981 | return proc; | |
982 | } | |
983 | ||
984 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
985 | data structures that keep track of debug register state. */ | |
986 | ||
987 | static void | |
988 | arm_linux_forget_process (pid_t pid) | |
989 | { | |
990 | struct arm_linux_process_info *proc, **proc_link; | |
991 | ||
992 | proc = arm_linux_process_list; | |
993 | proc_link = &arm_linux_process_list; | |
994 | ||
995 | while (proc != NULL) | |
996 | { | |
997 | if (proc->pid == pid) | |
e3039479 | 998 | { |
638c5f49 OJ |
999 | *proc_link = proc->next; |
1000 | ||
1001 | xfree (proc); | |
1002 | return; | |
e3039479 UW |
1003 | } |
1004 | ||
638c5f49 OJ |
1005 | proc_link = &proc->next; |
1006 | proc = *proc_link; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | /* Get hardware break-/watchpoint state for process PID. */ | |
1011 | ||
1012 | static struct arm_linux_debug_reg_state * | |
1013 | arm_linux_get_debug_reg_state (pid_t pid) | |
1014 | { | |
1015 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
1016 | } |
1017 | ||
1018 | /* Initialize an ARM hardware break-/watch-point control register value. | |
1019 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
1020 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
1021 | */ | |
1022 | static arm_hwbp_control_t | |
1023 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
1024 | arm_hwbp_type hwbp_type, | |
1025 | int enable) | |
1026 | { | |
1027 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
1028 | gdb_assert (hwbp_type != arm_hwbp_break | |
1029 | || ((byte_address_select & 0xfU) != 0)); | |
1030 | ||
1031 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
1032 | } | |
1033 | ||
1034 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
1035 | static int | |
1036 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
1037 | { | |
1038 | return control & 0x1; | |
1039 | } | |
1040 | ||
1041 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
1042 | static arm_hwbp_control_t | |
1043 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
1044 | { | |
1045 | return control & ~0x1; | |
1046 | } | |
1047 | ||
1048 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
1049 | enabled, and will point to the placed address of BP_TGT. */ | |
1050 | static void | |
1051 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
1052 | struct bp_target_info *bp_tgt, | |
1053 | struct arm_linux_hw_breakpoint *p) | |
1054 | { | |
1055 | unsigned mask; | |
0d5ed153 | 1056 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
1057 | |
1058 | /* We have to create a mask for the control register which says which bits | |
1059 | of the word pointed to by address to break on. */ | |
1060 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
1061 | { |
1062 | mask = 0x3; | |
1063 | address &= ~1; | |
1064 | } | |
e3039479 | 1065 | else |
fcf303ab UW |
1066 | { |
1067 | mask = 0xf; | |
1068 | address &= ~3; | |
1069 | } | |
e3039479 | 1070 | |
fcf303ab | 1071 | p->address = (unsigned int) address; |
e3039479 UW |
1072 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
1073 | } | |
1074 | ||
1075 | /* Get the ARM hardware breakpoint type from the RW value we're given when | |
1076 | asked to set a watchpoint. */ | |
1077 | static arm_hwbp_type | |
1078 | arm_linux_get_hwbp_type (int rw) | |
1079 | { | |
1080 | if (rw == hw_read) | |
1081 | return arm_hwbp_load; | |
1082 | else if (rw == hw_write) | |
1083 | return arm_hwbp_store; | |
1084 | else | |
1085 | return arm_hwbp_access; | |
1086 | } | |
1087 | ||
1088 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
1089 | to LEN. The type of watchpoint is given in RW. */ | |
1090 | static void | |
1091 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, int rw, | |
1092 | struct arm_linux_hw_breakpoint *p) | |
1093 | { | |
1094 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1095 | unsigned mask; | |
1096 | ||
1097 | gdb_assert (cap != NULL); | |
1098 | gdb_assert (cap->max_wp_length != 0); | |
1099 | ||
1100 | mask = (1 << len) - 1; | |
1101 | ||
1102 | p->address = (unsigned int) addr; | |
1103 | p->control = arm_hwbp_control_initialize (mask, | |
1104 | arm_linux_get_hwbp_type (rw), 1); | |
1105 | } | |
1106 | ||
1107 | /* Are two break-/watch-points equal? */ | |
1108 | static int | |
1109 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
1110 | const struct arm_linux_hw_breakpoint *p2) | |
1111 | { | |
1112 | return p1->address == p2->address && p1->control == p2->control; | |
1113 | } | |
1114 | ||
638c5f49 OJ |
1115 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
1116 | the current process. */ | |
1117 | ||
1118 | struct update_registers_data | |
1119 | { | |
1120 | int watch; | |
1121 | int index; | |
1122 | }; | |
1123 | ||
1124 | static int | |
1125 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
1126 | { | |
1127 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
1128 | ||
1129 | if (lwp->arch_private == NULL) | |
1130 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
1131 | ||
1132 | /* The actual update is done later just before resuming the lwp, | |
1133 | we just mark that the registers need updating. */ | |
1134 | if (data->watch) | |
1135 | lwp->arch_private->wpts_changed[data->index] = 1; | |
1136 | else | |
1137 | lwp->arch_private->bpts_changed[data->index] = 1; | |
1138 | ||
1139 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
1140 | we can update its breakpoint registers. */ | |
1141 | if (!lwp->stopped) | |
1142 | linux_stop_lwp (lwp); | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
e3039479 UW |
1147 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
1148 | =1) BPT for thread TID. */ | |
1149 | static void | |
1150 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 1151 | int watchpoint) |
e3039479 | 1152 | { |
638c5f49 OJ |
1153 | int pid; |
1154 | ptid_t pid_ptid; | |
e3039479 UW |
1155 | gdb_byte count, i; |
1156 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1157 | struct update_registers_data data; |
e3039479 | 1158 | |
638c5f49 OJ |
1159 | pid = ptid_get_pid (inferior_ptid); |
1160 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1161 | |
1162 | if (watchpoint) | |
1163 | { | |
1164 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1165 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1166 | } |
1167 | else | |
1168 | { | |
1169 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1170 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1171 | } |
1172 | ||
1173 | for (i = 0; i < count; ++i) | |
1174 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1175 | { | |
638c5f49 OJ |
1176 | data.watch = watchpoint; |
1177 | data.index = i; | |
1178 | bpts[i] = *bpt; | |
1179 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1180 | break; | |
e3039479 UW |
1181 | } |
1182 | ||
1183 | gdb_assert (i != count); | |
1184 | } | |
1185 | ||
1186 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1187 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1188 | static void | |
1189 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1190 | int watchpoint) |
e3039479 | 1191 | { |
638c5f49 | 1192 | int pid; |
e3039479 | 1193 | gdb_byte count, i; |
638c5f49 OJ |
1194 | ptid_t pid_ptid; |
1195 | struct arm_linux_hw_breakpoint* bpts; | |
1196 | struct update_registers_data data; | |
e3039479 | 1197 | |
638c5f49 OJ |
1198 | pid = ptid_get_pid (inferior_ptid); |
1199 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1200 | |
1201 | if (watchpoint) | |
1202 | { | |
1203 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1204 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1205 | } |
1206 | else | |
1207 | { | |
1208 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1209 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1210 | } |
1211 | ||
1212 | for (i = 0; i < count; ++i) | |
1213 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1214 | { | |
638c5f49 OJ |
1215 | data.watch = watchpoint; |
1216 | data.index = i; | |
1217 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1218 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1219 | break; | |
e3039479 UW |
1220 | } |
1221 | ||
1222 | gdb_assert (i != count); | |
1223 | } | |
1224 | ||
1225 | /* Insert a Hardware breakpoint. */ | |
1226 | static int | |
23a26771 TT |
1227 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1228 | struct gdbarch *gdbarch, | |
e3039479 UW |
1229 | struct bp_target_info *bp_tgt) |
1230 | { | |
e3039479 UW |
1231 | struct lwp_info *lp; |
1232 | struct arm_linux_hw_breakpoint p; | |
1233 | ||
1234 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1235 | return -1; | |
1236 | ||
1237 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1238 | |
1239 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1240 | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | /* Remove a hardware breakpoint. */ | |
1245 | static int | |
a64dc96c TT |
1246 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1247 | struct gdbarch *gdbarch, | |
e3039479 UW |
1248 | struct bp_target_info *bp_tgt) |
1249 | { | |
e3039479 UW |
1250 | struct lwp_info *lp; |
1251 | struct arm_linux_hw_breakpoint p; | |
1252 | ||
1253 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1254 | return -1; | |
1255 | ||
1256 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1257 | |
1258 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1259 | |
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1264 | ADDR? */ | |
1265 | static int | |
31568a15 TT |
1266 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1267 | CORE_ADDR addr, int len) | |
e3039479 UW |
1268 | { |
1269 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1270 | CORE_ADDR max_wp_length, aligned_addr; | |
1271 | ||
1272 | /* Can not set watchpoints for zero or negative lengths. */ | |
1273 | if (len <= 0) | |
1274 | return 0; | |
1275 | ||
1276 | /* Need to be able to use the ptrace interface. */ | |
1277 | if (cap == NULL || cap->wp_count == 0) | |
1278 | return 0; | |
1279 | ||
1280 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1281 | range covered by a watchpoint. */ | |
1282 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1283 | aligned_addr = addr & ~(max_wp_length - 1); | |
1284 | ||
1285 | if (aligned_addr + max_wp_length < addr + len) | |
1286 | return 0; | |
1287 | ||
1288 | /* The current ptrace interface can only handle watchpoints that are a | |
1289 | power of 2. */ | |
1290 | if ((len & (len - 1)) != 0) | |
1291 | return 0; | |
1292 | ||
1293 | /* All tests passed so we must be able to set a watchpoint. */ | |
1294 | return 1; | |
1295 | } | |
1296 | ||
1297 | /* Insert a Hardware breakpoint. */ | |
1298 | static int | |
7bb99c53 TT |
1299 | arm_linux_insert_watchpoint (struct target_ops *self, |
1300 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1301 | struct expression *cond) |
1302 | { | |
e3039479 UW |
1303 | struct lwp_info *lp; |
1304 | struct arm_linux_hw_breakpoint p; | |
1305 | ||
1306 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1307 | return -1; | |
1308 | ||
1309 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1310 | |
1311 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1312 | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | /* Remove a hardware breakpoint. */ | |
1317 | static int | |
11b5219a TT |
1318 | arm_linux_remove_watchpoint (struct target_ops *self, |
1319 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1320 | struct expression *cond) |
1321 | { | |
e3039479 UW |
1322 | struct lwp_info *lp; |
1323 | struct arm_linux_hw_breakpoint p; | |
1324 | ||
1325 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1326 | return -1; | |
1327 | ||
1328 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1329 | |
1330 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1331 | |
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | /* What was the data address the target was stopped on accessing. */ | |
1336 | static int | |
1337 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1338 | { | |
f865ee35 JK |
1339 | siginfo_t siginfo; |
1340 | int slot; | |
1341 | ||
1342 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1343 | return 0; | |
e3039479 UW |
1344 | |
1345 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1346 | if (siginfo.si_signo != SIGTRAP |
1347 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1348 | return 0; |
1349 | ||
1350 | /* We must be able to set hardware watchpoints. */ | |
1351 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1352 | return 0; | |
1353 | ||
f865ee35 JK |
1354 | slot = siginfo.si_errno; |
1355 | ||
e3039479 UW |
1356 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1357 | a watchpoint. */ | |
1358 | if (slot >= 0) | |
1359 | return 0; | |
1360 | ||
f865ee35 | 1361 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1362 | return 1; |
1363 | } | |
1364 | ||
1365 | /* Has the target been stopped by hitting a watchpoint? */ | |
1366 | static int | |
6a109b6b | 1367 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1368 | { |
1369 | CORE_ADDR addr; | |
6a109b6b | 1370 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1371 | } |
1372 | ||
1373 | static int | |
1374 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1375 | CORE_ADDR addr, | |
1376 | CORE_ADDR start, int length) | |
1377 | { | |
1378 | return start <= addr && start + length - 1 >= addr; | |
1379 | } | |
1380 | ||
1381 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1382 | in the parent thread to the child thread. */ | |
1383 | static void | |
7b50312a | 1384 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1385 | { |
638c5f49 OJ |
1386 | int i; |
1387 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1388 | ||
1389 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1390 | for this thread need to be initialized. */ | |
e3039479 | 1391 | |
638c5f49 | 1392 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1393 | { |
638c5f49 OJ |
1394 | info->bpts_changed[i] = 1; |
1395 | info->wpts_changed[i] = 1; | |
e3039479 | 1396 | } |
638c5f49 OJ |
1397 | |
1398 | lp->arch_private = info; | |
e3039479 UW |
1399 | } |
1400 | ||
638c5f49 OJ |
1401 | /* Called when resuming a thread. |
1402 | The hardware debug registers are updated when there is any change. */ | |
1403 | ||
e3039479 | 1404 | static void |
638c5f49 | 1405 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1406 | { |
638c5f49 OJ |
1407 | int pid, i; |
1408 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1409 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1410 | ||
1411 | pid = ptid_get_lwp (lwp->ptid); | |
1412 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1413 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1414 | ||
1415 | /* NULL means this is the main thread still going through the shell, | |
1416 | or, no watchpoint has been set yet. In that case, there's | |
1417 | nothing to do. */ | |
1418 | if (arm_lwp_info == NULL) | |
1419 | return; | |
e3039479 | 1420 | |
638c5f49 OJ |
1421 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1422 | if (arm_lwp_info->bpts_changed[i]) | |
1423 | { | |
1424 | errno = 0; | |
1425 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1426 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1427 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1428 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1429 | ||
1430 | if (bpts[i].control != 0) | |
1431 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1432 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1433 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1434 | ||
1435 | arm_lwp_info->bpts_changed[i] = 0; | |
1436 | } | |
e3039479 | 1437 | |
638c5f49 OJ |
1438 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1439 | if (arm_lwp_info->wpts_changed[i]) | |
1440 | { | |
1441 | errno = 0; | |
1442 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1443 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1444 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1445 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1446 | ||
1447 | if (wpts[i].control != 0) | |
1448 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1449 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1450 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1451 | ||
1452 | arm_lwp_info->wpts_changed[i] = 0; | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /* linux_nat_new_fork hook. */ | |
1457 | ||
1458 | static void | |
1459 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1460 | { | |
1461 | pid_t parent_pid; | |
1462 | struct arm_linux_debug_reg_state *parent_state; | |
1463 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1464 | |
638c5f49 OJ |
1465 | /* NULL means no watchpoint has ever been set in the parent. In |
1466 | that case, there's nothing to do. */ | |
1467 | if (parent->arch_private == NULL) | |
1468 | return; | |
e3039479 | 1469 | |
638c5f49 OJ |
1470 | /* GDB core assumes the child inherits the watchpoints/hw |
1471 | breakpoints of the parent, and will remove them all from the | |
1472 | forked off process. Copy the debug registers mirrors into the | |
1473 | new process so that all breakpoints and watchpoints can be | |
1474 | removed together. */ | |
e3039479 | 1475 | |
638c5f49 OJ |
1476 | parent_pid = ptid_get_pid (parent->ptid); |
1477 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1478 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1479 | *child_state = *parent_state; | |
e3039479 UW |
1480 | } |
1481 | ||
10d6c8cd DJ |
1482 | void _initialize_arm_linux_nat (void); |
1483 | ||
ed9a39eb JM |
1484 | void |
1485 | _initialize_arm_linux_nat (void) | |
1486 | { | |
10d6c8cd DJ |
1487 | struct target_ops *t; |
1488 | ||
10d6c8cd DJ |
1489 | /* Fill in the generic GNU/Linux methods. */ |
1490 | t = linux_target (); | |
1491 | ||
1492 | /* Add our register access methods. */ | |
1493 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1494 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1495 | ||
e3039479 UW |
1496 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1497 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1498 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1499 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1500 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1501 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1502 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1503 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1504 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1505 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1506 | ||
81adfced | 1507 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1508 | |
10d6c8cd | 1509 | /* Register the target. */ |
f973ed9c | 1510 | linux_nat_add_target (t); |
e3039479 | 1511 | |
638c5f49 | 1512 | /* Handle thread creation and exit. */ |
e3039479 | 1513 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1514 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1515 | ||
1516 | /* Handle process creation and exit. */ | |
1517 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1518 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1519 | } |