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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
32d0add0 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
f1b67888 | 32 | #include "aarch32-linux-nat.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb JM |
35 | #include <sys/user.h> |
36 | #include <sys/ptrace.h> | |
37 | #include <sys/utsname.h> | |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
95855ca8 MS |
40 | #include "nat/linux-ptrace.h" |
41 | ||
0963b4bd | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
43 | #include "gregset.h" |
44 | ||
9308fc88 DJ |
45 | /* Defines ps_err_e, struct ps_prochandle. */ |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
05a4558a DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
3b273a55 RE |
57 | #ifndef PTRACE_GETVFPREGS |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
e3039479 UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
ed9a39eb JM |
67 | extern int arm_apcs_32; |
68 | ||
fdf39c9a | 69 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
41c49b06 | 70 | case we may be tracing more than one process at a time. In that |
39f77062 | 71 | case, inferior_ptid will contain the main process ID and the |
fdf39c9a RE |
72 | individual thread (process) ID. get_thread_id () is used to get |
73 | the thread id if it's available, and the process id otherwise. */ | |
41c49b06 | 74 | |
4e841acf | 75 | static int |
39f77062 | 76 | get_thread_id (ptid_t ptid) |
41c49b06 | 77 | { |
dfd4cc63 | 78 | int tid = ptid_get_lwp (ptid); |
39f77062 | 79 | if (0 == tid) |
dfd4cc63 | 80 | tid = ptid_get_pid (ptid); |
41c49b06 SB |
81 | return tid; |
82 | } | |
3b273a55 | 83 | |
05a4558a | 84 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) |
41c49b06 | 85 | |
41c49b06 | 86 | /* Get the whole floating point state of the process and store it |
c6b92abd | 87 | into regcache. */ |
ed9a39eb JM |
88 | |
89 | static void | |
56be3814 | 90 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 91 | { |
41c49b06 | 92 | int ret, regno, tid; |
cb587d83 | 93 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 94 | |
41c49b06 | 95 | /* Get the thread id for the ptrace call. */ |
39f77062 | 96 | tid = GET_THREAD_ID (inferior_ptid); |
df9d7ec9 | 97 | |
ed9a39eb | 98 | /* Read the floating point state. */ |
0bdb2f78 | 99 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
100 | { |
101 | struct iovec iov; | |
102 | ||
103 | iov.iov_base = &fp; | |
104 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
105 | ||
106 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
107 | } | |
108 | else | |
109 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
110 | ||
ed9a39eb JM |
111 | if (ret < 0) |
112 | { | |
edefbb7c | 113 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
114 | return; |
115 | } | |
116 | ||
117 | /* Fetch fpsr. */ | |
56be3814 | 118 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 119 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
120 | |
121 | /* Fetch the floating point registers. */ | |
34e8f22d | 122 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 123 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
124 | } |
125 | ||
126 | /* Save the whole floating point state of the process using | |
c6b92abd | 127 | the contents from regcache. */ |
ed9a39eb JM |
128 | |
129 | static void | |
56be3814 | 130 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 131 | { |
41c49b06 | 132 | int ret, regno, tid; |
cb587d83 | 133 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 134 | |
41c49b06 | 135 | /* Get the thread id for the ptrace call. */ |
39f77062 | 136 | tid = GET_THREAD_ID (inferior_ptid); |
df9d7ec9 | 137 | |
41c49b06 | 138 | /* Read the floating point state. */ |
0bdb2f78 | 139 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
140 | { |
141 | elf_fpregset_t fpregs; | |
142 | struct iovec iov; | |
143 | ||
144 | iov.iov_base = &fpregs; | |
145 | iov.iov_len = sizeof (fpregs); | |
146 | ||
147 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
148 | } | |
149 | else | |
150 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
151 | ||
41c49b06 SB |
152 | if (ret < 0) |
153 | { | |
edefbb7c | 154 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
155 | return; |
156 | } | |
157 | ||
ed9a39eb | 158 | /* Store fpsr. */ |
672c9795 | 159 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 160 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
161 | |
162 | /* Store the floating point registers. */ | |
34e8f22d | 163 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 164 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 165 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 166 | |
0bdb2f78 | 167 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
168 | { |
169 | struct iovec iov; | |
170 | ||
171 | iov.iov_base = &fp; | |
172 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
173 | ||
174 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
175 | } | |
176 | else | |
177 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
178 | ||
ed9a39eb JM |
179 | if (ret < 0) |
180 | { | |
edefbb7c | 181 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
182 | return; |
183 | } | |
184 | } | |
185 | ||
186 | /* Fetch all general registers of the process and store into | |
c6b92abd | 187 | regcache. */ |
ed9a39eb JM |
188 | |
189 | static void | |
56be3814 | 190 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 191 | { |
41c49b06 | 192 | int ret, regno, tid; |
c2152441 | 193 | elf_gregset_t regs; |
ed9a39eb | 194 | |
41c49b06 | 195 | /* Get the thread id for the ptrace call. */ |
39f77062 | 196 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 197 | |
0bdb2f78 | 198 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
199 | { |
200 | struct iovec iov; | |
201 | ||
202 | iov.iov_base = ®s; | |
203 | iov.iov_len = sizeof (regs); | |
204 | ||
205 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
206 | } | |
207 | else | |
208 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
209 | ||
ed9a39eb JM |
210 | if (ret < 0) |
211 | { | |
edefbb7c | 212 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
213 | return; |
214 | } | |
215 | ||
f1b67888 | 216 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
217 | } |
218 | ||
ed9a39eb | 219 | static void |
56be3814 | 220 | store_regs (const struct regcache *regcache) |
ed9a39eb | 221 | { |
41c49b06 | 222 | int ret, regno, tid; |
c2152441 | 223 | elf_gregset_t regs; |
ed9a39eb | 224 | |
41c49b06 | 225 | /* Get the thread id for the ptrace call. */ |
39f77062 | 226 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 227 | |
41c49b06 | 228 | /* Fetch the general registers. */ |
0bdb2f78 | 229 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
230 | { |
231 | struct iovec iov; | |
232 | ||
233 | iov.iov_base = ®s; | |
234 | iov.iov_len = sizeof (regs); | |
235 | ||
236 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
237 | } | |
238 | else | |
239 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
240 | ||
ed9a39eb JM |
241 | if (ret < 0) |
242 | { | |
edefbb7c | 243 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
244 | return; |
245 | } | |
246 | ||
f1b67888 | 247 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 248 | |
0bdb2f78 | 249 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
250 | { |
251 | struct iovec iov; | |
252 | ||
253 | iov.iov_base = ®s; | |
254 | iov.iov_len = sizeof (regs); | |
255 | ||
256 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
257 | } | |
258 | else | |
259 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
260 | |
261 | if (ret < 0) | |
262 | { | |
edefbb7c | 263 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
264 | return; |
265 | } | |
266 | } | |
267 | ||
05a4558a DJ |
268 | /* Fetch all WMMX registers of the process and store into |
269 | regcache. */ | |
270 | ||
271 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
272 | ||
273 | static void | |
56be3814 | 274 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
275 | { |
276 | char regbuf[IWMMXT_REGS_SIZE]; | |
277 | int ret, regno, tid; | |
278 | ||
279 | /* Get the thread id for the ptrace call. */ | |
280 | tid = GET_THREAD_ID (inferior_ptid); | |
281 | ||
282 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
283 | if (ret < 0) | |
284 | { | |
285 | warning (_("Unable to fetch WMMX registers.")); | |
286 | return; | |
287 | } | |
288 | ||
289 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 290 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
291 | ®buf[regno * 8]); |
292 | ||
293 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 294 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
295 | ®buf[16 * 8 + regno * 4]); |
296 | ||
297 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 298 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
299 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
300 | } | |
301 | ||
302 | static void | |
56be3814 | 303 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
304 | { |
305 | char regbuf[IWMMXT_REGS_SIZE]; | |
306 | int ret, regno, tid; | |
307 | ||
308 | /* Get the thread id for the ptrace call. */ | |
309 | tid = GET_THREAD_ID (inferior_ptid); | |
310 | ||
311 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
312 | if (ret < 0) | |
313 | { | |
314 | warning (_("Unable to fetch WMMX registers.")); | |
315 | return; | |
316 | } | |
317 | ||
318 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
319 | if (REG_VALID == regcache_register_status (regcache, |
320 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 321 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
322 | ®buf[regno * 8]); |
323 | ||
324 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
325 | if (REG_VALID == regcache_register_status (regcache, |
326 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 327 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
328 | ®buf[16 * 8 + regno * 4]); |
329 | ||
330 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
331 | if (REG_VALID == regcache_register_status (regcache, |
332 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 333 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
334 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
335 | ||
336 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
337 | ||
338 | if (ret < 0) | |
339 | { | |
340 | warning (_("Unable to store WMMX registers.")); | |
341 | return; | |
342 | } | |
343 | } | |
344 | ||
3b273a55 RE |
345 | /* Fetch and store VFP Registers. The kernel object has space for 32 |
346 | 64-bit registers, and the FPSCR. This is even when on a VFPv2 or | |
347 | VFPv3D16 target. */ | |
348 | #define VFP_REGS_SIZE (32 * 8 + 4) | |
349 | ||
350 | static void | |
351 | fetch_vfp_regs (struct regcache *regcache) | |
352 | { | |
f1b67888 | 353 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 354 | int ret, regno, tid; |
330c6ca9 YQ |
355 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
356 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
357 | |
358 | /* Get the thread id for the ptrace call. */ | |
359 | tid = GET_THREAD_ID (inferior_ptid); | |
360 | ||
0bdb2f78 | 361 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
362 | { |
363 | struct iovec iov; | |
364 | ||
365 | iov.iov_base = regbuf; | |
366 | iov.iov_len = VFP_REGS_SIZE; | |
367 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
368 | } | |
369 | else | |
370 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
371 | ||
3b273a55 RE |
372 | if (ret < 0) |
373 | { | |
374 | warning (_("Unable to fetch VFP registers.")); | |
375 | return; | |
376 | } | |
377 | ||
f1b67888 YQ |
378 | aarch32_vfp_regcache_supply (regcache, regbuf, |
379 | tdep->vfp_register_count); | |
3b273a55 RE |
380 | } |
381 | ||
382 | static void | |
383 | store_vfp_regs (const struct regcache *regcache) | |
384 | { | |
f1b67888 | 385 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 386 | int ret, regno, tid; |
330c6ca9 YQ |
387 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
388 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
389 | |
390 | /* Get the thread id for the ptrace call. */ | |
391 | tid = GET_THREAD_ID (inferior_ptid); | |
392 | ||
0bdb2f78 | 393 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
394 | { |
395 | struct iovec iov; | |
396 | ||
397 | iov.iov_base = regbuf; | |
398 | iov.iov_len = VFP_REGS_SIZE; | |
399 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
400 | } | |
401 | else | |
402 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
403 | ||
3b273a55 RE |
404 | if (ret < 0) |
405 | { | |
406 | warning (_("Unable to fetch VFP registers (for update).")); | |
407 | return; | |
408 | } | |
409 | ||
f1b67888 YQ |
410 | aarch32_vfp_regcache_collect (regcache, regbuf, |
411 | tdep->vfp_register_count); | |
3b273a55 | 412 | |
0bdb2f78 | 413 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
414 | { |
415 | struct iovec iov; | |
416 | ||
417 | iov.iov_base = regbuf; | |
418 | iov.iov_len = VFP_REGS_SIZE; | |
419 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
420 | } | |
421 | else | |
422 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
423 | |
424 | if (ret < 0) | |
425 | { | |
426 | warning (_("Unable to store VFP registers.")); | |
427 | return; | |
428 | } | |
429 | } | |
430 | ||
ed9a39eb JM |
431 | /* Fetch registers from the child process. Fetch all registers if |
432 | regno == -1, otherwise fetch all general registers or all floating | |
433 | point registers depending upon the value of regno. */ | |
434 | ||
10d6c8cd | 435 | static void |
28439f5e PA |
436 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
437 | struct regcache *regcache, int regno) | |
ed9a39eb | 438 | { |
330c6ca9 YQ |
439 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
440 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
441 | ||
41c49b06 SB |
442 | if (-1 == regno) |
443 | { | |
56be3814 UW |
444 | fetch_regs (regcache); |
445 | fetch_fpregs (regcache); | |
a56cc1ce | 446 | if (tdep->have_wmmx_registers) |
56be3814 | 447 | fetch_wmmx_regs (regcache); |
330c6ca9 | 448 | if (tdep->vfp_register_count > 0) |
3b273a55 | 449 | fetch_vfp_regs (regcache); |
41c49b06 SB |
450 | } |
451 | else | |
452 | { | |
05a4558a | 453 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 454 | fetch_regs (regcache); |
05a4558a | 455 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 456 | fetch_fpregs (regcache); |
a56cc1ce | 457 | else if (tdep->have_wmmx_registers |
05a4558a | 458 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 459 | fetch_wmmx_regs (regcache); |
330c6ca9 | 460 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 461 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 462 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 463 | fetch_vfp_regs (regcache); |
41c49b06 | 464 | } |
ed9a39eb JM |
465 | } |
466 | ||
467 | /* Store registers back into the inferior. Store all registers if | |
468 | regno == -1, otherwise store all general registers or all floating | |
469 | point registers depending upon the value of regno. */ | |
470 | ||
10d6c8cd | 471 | static void |
28439f5e PA |
472 | arm_linux_store_inferior_registers (struct target_ops *ops, |
473 | struct regcache *regcache, int regno) | |
ed9a39eb | 474 | { |
330c6ca9 YQ |
475 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
476 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
477 | ||
41c49b06 SB |
478 | if (-1 == regno) |
479 | { | |
56be3814 UW |
480 | store_regs (regcache); |
481 | store_fpregs (regcache); | |
a56cc1ce | 482 | if (tdep->have_wmmx_registers) |
56be3814 | 483 | store_wmmx_regs (regcache); |
330c6ca9 | 484 | if (tdep->vfp_register_count > 0) |
3b273a55 | 485 | store_vfp_regs (regcache); |
41c49b06 SB |
486 | } |
487 | else | |
488 | { | |
05a4558a | 489 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 490 | store_regs (regcache); |
05a4558a | 491 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 492 | store_fpregs (regcache); |
a56cc1ce | 493 | else if (tdep->have_wmmx_registers |
05a4558a | 494 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 495 | store_wmmx_regs (regcache); |
330c6ca9 | 496 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 497 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 498 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 499 | store_vfp_regs (regcache); |
41c49b06 | 500 | } |
ed9a39eb JM |
501 | } |
502 | ||
cb587d83 DJ |
503 | /* Wrapper functions for the standard regset handling, used by |
504 | thread debugging. */ | |
41c49b06 SB |
505 | |
506 | void | |
7f7fe91e UW |
507 | fill_gregset (const struct regcache *regcache, |
508 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 509 | { |
7f7fe91e | 510 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
511 | } |
512 | ||
41c49b06 | 513 | void |
7f7fe91e | 514 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 515 | { |
7f7fe91e | 516 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
517 | } |
518 | ||
41c49b06 | 519 | void |
7f7fe91e UW |
520 | fill_fpregset (const struct regcache *regcache, |
521 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 522 | { |
7f7fe91e | 523 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
524 | } |
525 | ||
526 | /* Fill GDB's register array with the floating-point register values | |
527 | in *fpregsetp. */ | |
528 | ||
529 | void | |
7f7fe91e | 530 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 531 | { |
7f7fe91e | 532 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
533 | } |
534 | ||
9308fc88 DJ |
535 | /* Fetch the thread-local storage pointer for libthread_db. */ |
536 | ||
537 | ps_err_e | |
538 | ps_get_thread_area (const struct ps_prochandle *ph, | |
539 | lwpid_t lwpid, int idx, void **base) | |
540 | { | |
541 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
542 | return PS_ERR; | |
543 | ||
544 | /* IDX is the bias from the thread pointer to the beginning of the | |
545 | thread descriptor. It has to be subtracted due to implementation | |
546 | quirks in libthread_db. */ | |
547 | *base = (void *) ((char *)*base - idx); | |
548 | ||
549 | return PS_OK; | |
550 | } | |
551 | ||
81adfced DJ |
552 | static const struct target_desc * |
553 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 554 | { |
3b273a55 | 555 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 556 | |
0bdb2f78 | 557 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
558 | { |
559 | elf_gregset_t gpregs; | |
560 | struct iovec iov; | |
561 | int tid = GET_THREAD_ID (inferior_ptid); | |
562 | ||
563 | iov.iov_base = &gpregs; | |
564 | iov.iov_len = sizeof (gpregs); | |
565 | ||
566 | /* Check if PTRACE_GETREGSET works. */ | |
567 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 568 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 569 | else |
0bdb2f78 | 570 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
571 | } |
572 | ||
3b273a55 RE |
573 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
574 | { | |
2117c711 | 575 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 576 | } |
81adfced | 577 | |
3b273a55 | 578 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 579 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
580 | |
581 | if (arm_hwcap & HWCAP_VFP) | |
582 | { | |
583 | int pid; | |
584 | char *buf; | |
585 | const struct target_desc * result = NULL; | |
586 | ||
587 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
588 | Neon with VFPv3-D32. */ | |
589 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 590 | result = tdesc_arm_with_neon; |
3b273a55 | 591 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 592 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 593 | else |
330c6ca9 | 594 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
595 | |
596 | /* Now make sure that the kernel supports reading these | |
597 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 598 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
599 | errno = 0; |
600 | buf = alloca (VFP_REGS_SIZE); | |
601 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
602 | && errno == EIO) | |
603 | result = NULL; | |
604 | ||
605 | return result; | |
606 | } | |
607 | ||
2117c711 | 608 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
609 | } |
610 | ||
e3039479 UW |
611 | /* Information describing the hardware breakpoint capabilities. */ |
612 | struct arm_linux_hwbp_cap | |
613 | { | |
614 | gdb_byte arch; | |
615 | gdb_byte max_wp_length; | |
616 | gdb_byte wp_count; | |
617 | gdb_byte bp_count; | |
618 | }; | |
619 | ||
638c5f49 OJ |
620 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
621 | assume a maximum number of supported break-/watchpoints. */ | |
622 | #define MAX_BPTS 16 | |
623 | #define MAX_WPTS 16 | |
624 | ||
e3039479 UW |
625 | /* Get hold of the Hardware Breakpoint information for the target we are |
626 | attached to. Returns NULL if the kernel doesn't support Hardware | |
627 | breakpoints at all, or a pointer to the information structure. */ | |
628 | static const struct arm_linux_hwbp_cap * | |
629 | arm_linux_get_hwbp_cap (void) | |
630 | { | |
631 | /* The info structure we return. */ | |
632 | static struct arm_linux_hwbp_cap info; | |
633 | ||
634 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
635 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
636 | means INFO is in an initialized state. */ | |
637 | static int available = -1; | |
638 | ||
639 | if (available == -1) | |
640 | { | |
641 | int tid; | |
642 | unsigned int val; | |
643 | ||
644 | tid = GET_THREAD_ID (inferior_ptid); | |
645 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
646 | available = 0; | |
647 | else | |
648 | { | |
649 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
650 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
651 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
652 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
653 | |
654 | if (info.wp_count > MAX_WPTS) | |
655 | { | |
656 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
657 | supports %d"), MAX_WPTS, info.wp_count); | |
658 | info.wp_count = MAX_WPTS; | |
659 | } | |
660 | ||
661 | if (info.bp_count > MAX_BPTS) | |
662 | { | |
663 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
664 | supports %d"), MAX_BPTS, info.bp_count); | |
665 | info.bp_count = MAX_BPTS; | |
666 | } | |
e3039479 UW |
667 | available = (info.arch != 0); |
668 | } | |
669 | } | |
670 | ||
671 | return available == 1 ? &info : NULL; | |
672 | } | |
673 | ||
674 | /* How many hardware breakpoints are available? */ | |
675 | static int | |
676 | arm_linux_get_hw_breakpoint_count (void) | |
677 | { | |
678 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
679 | return cap != NULL ? cap->bp_count : 0; | |
680 | } | |
681 | ||
682 | /* How many hardware watchpoints are available? */ | |
683 | static int | |
684 | arm_linux_get_hw_watchpoint_count (void) | |
685 | { | |
686 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
687 | return cap != NULL ? cap->wp_count : 0; | |
688 | } | |
689 | ||
690 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
691 | there is not an appropriate resource available, otherwise returns 1. */ | |
692 | static int | |
5461485a TT |
693 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
694 | int type, int cnt, int ot) | |
e3039479 UW |
695 | { |
696 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
697 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
698 | { | |
dbbf180a YQ |
699 | int count = arm_linux_get_hw_watchpoint_count (); |
700 | ||
701 | if (count == 0) | |
702 | return 0; | |
703 | else if (cnt + ot > count) | |
e3039479 UW |
704 | return -1; |
705 | } | |
706 | else if (type == bp_hardware_breakpoint) | |
707 | { | |
dbbf180a YQ |
708 | int count = arm_linux_get_hw_breakpoint_count (); |
709 | ||
710 | if (count == 0) | |
711 | return 0; | |
712 | else if (cnt > count) | |
e3039479 UW |
713 | return -1; |
714 | } | |
715 | else | |
716 | gdb_assert (FALSE); | |
717 | ||
718 | return 1; | |
719 | } | |
720 | ||
721 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
722 | typedef enum | |
723 | { | |
724 | arm_hwbp_break = 0, | |
725 | arm_hwbp_load = 1, | |
726 | arm_hwbp_store = 2, | |
727 | arm_hwbp_access = 3 | |
728 | } arm_hwbp_type; | |
729 | ||
730 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
731 | typedef unsigned int arm_hwbp_control_t; | |
732 | ||
733 | /* Structure used to keep track of hardware break-/watch-points. */ | |
734 | struct arm_linux_hw_breakpoint | |
735 | { | |
736 | /* Address to break on, or being watched. */ | |
737 | unsigned int address; | |
738 | /* Control register for break-/watch- point. */ | |
739 | arm_hwbp_control_t control; | |
740 | }; | |
741 | ||
638c5f49 OJ |
742 | /* Structure containing arrays of per process hardware break-/watchpoints |
743 | for caching address and control information. | |
e3039479 UW |
744 | |
745 | The Linux ptrace interface to hardware break-/watch-points presents the | |
746 | values in a vector centred around 0 (which is used fo generic information). | |
747 | Positive indicies refer to breakpoint addresses/control registers, negative | |
748 | indices to watchpoint addresses/control registers. | |
749 | ||
750 | The Linux vector is indexed as follows: | |
751 | -((i << 1) + 2): Control register for watchpoint i. | |
752 | -((i << 1) + 1): Address register for watchpoint i. | |
753 | 0: Information register. | |
754 | ((i << 1) + 1): Address register for breakpoint i. | |
755 | ((i << 1) + 2): Control register for breakpoint i. | |
756 | ||
757 | This structure is used as a per-thread cache of the state stored by the | |
758 | kernel, so that we don't need to keep calling into the kernel to find a | |
759 | free breakpoint. | |
760 | ||
761 | We treat break-/watch-points with their enable bit clear as being deleted. | |
762 | */ | |
638c5f49 | 763 | struct arm_linux_debug_reg_state |
e3039479 | 764 | { |
638c5f49 OJ |
765 | /* Hardware breakpoints for this process. */ |
766 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
767 | /* Hardware watchpoints for this process. */ | |
768 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
769 | }; | |
770 | ||
771 | /* Per-process arch-specific data we want to keep. */ | |
772 | struct arm_linux_process_info | |
e3039479 | 773 | { |
638c5f49 OJ |
774 | /* Linked list. */ |
775 | struct arm_linux_process_info *next; | |
776 | /* The process identifier. */ | |
777 | pid_t pid; | |
778 | /* Hardware break-/watchpoints state information. */ | |
779 | struct arm_linux_debug_reg_state state; | |
e3039479 | 780 | |
638c5f49 OJ |
781 | }; |
782 | ||
783 | /* Per-thread arch-specific data we want to keep. */ | |
784 | struct arch_lwp_info | |
785 | { | |
786 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
787 | char bpts_changed[MAX_BPTS]; | |
788 | char wpts_changed[MAX_WPTS]; | |
789 | }; | |
790 | ||
791 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
792 | ||
793 | /* Find process data for process PID. */ | |
794 | ||
795 | static struct arm_linux_process_info * | |
796 | arm_linux_find_process_pid (pid_t pid) | |
797 | { | |
798 | struct arm_linux_process_info *proc; | |
799 | ||
800 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
801 | if (proc->pid == pid) | |
802 | return proc; | |
803 | ||
804 | return NULL; | |
805 | } | |
806 | ||
807 | /* Add process data for process PID. Returns newly allocated info | |
808 | object. */ | |
809 | ||
810 | static struct arm_linux_process_info * | |
811 | arm_linux_add_process (pid_t pid) | |
812 | { | |
813 | struct arm_linux_process_info *proc; | |
e3039479 | 814 | |
638c5f49 OJ |
815 | proc = xcalloc (1, sizeof (*proc)); |
816 | proc->pid = pid; | |
e3039479 | 817 | |
638c5f49 OJ |
818 | proc->next = arm_linux_process_list; |
819 | arm_linux_process_list = proc; | |
820 | ||
821 | return proc; | |
822 | } | |
823 | ||
824 | /* Get data specific info for process PID, creating it if necessary. | |
825 | Never returns NULL. */ | |
826 | ||
827 | static struct arm_linux_process_info * | |
828 | arm_linux_process_info_get (pid_t pid) | |
829 | { | |
830 | struct arm_linux_process_info *proc; | |
831 | ||
832 | proc = arm_linux_find_process_pid (pid); | |
833 | if (proc == NULL) | |
834 | proc = arm_linux_add_process (pid); | |
835 | ||
836 | return proc; | |
837 | } | |
838 | ||
839 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
840 | data structures that keep track of debug register state. */ | |
841 | ||
842 | static void | |
843 | arm_linux_forget_process (pid_t pid) | |
844 | { | |
845 | struct arm_linux_process_info *proc, **proc_link; | |
846 | ||
847 | proc = arm_linux_process_list; | |
848 | proc_link = &arm_linux_process_list; | |
849 | ||
850 | while (proc != NULL) | |
851 | { | |
852 | if (proc->pid == pid) | |
e3039479 | 853 | { |
638c5f49 OJ |
854 | *proc_link = proc->next; |
855 | ||
856 | xfree (proc); | |
857 | return; | |
e3039479 UW |
858 | } |
859 | ||
638c5f49 OJ |
860 | proc_link = &proc->next; |
861 | proc = *proc_link; | |
862 | } | |
863 | } | |
864 | ||
865 | /* Get hardware break-/watchpoint state for process PID. */ | |
866 | ||
867 | static struct arm_linux_debug_reg_state * | |
868 | arm_linux_get_debug_reg_state (pid_t pid) | |
869 | { | |
870 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
871 | } |
872 | ||
873 | /* Initialize an ARM hardware break-/watch-point control register value. | |
874 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
875 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
876 | */ | |
877 | static arm_hwbp_control_t | |
878 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
879 | arm_hwbp_type hwbp_type, | |
880 | int enable) | |
881 | { | |
882 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
883 | gdb_assert (hwbp_type != arm_hwbp_break | |
884 | || ((byte_address_select & 0xfU) != 0)); | |
885 | ||
886 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
887 | } | |
888 | ||
889 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
890 | static int | |
891 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
892 | { | |
893 | return control & 0x1; | |
894 | } | |
895 | ||
896 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
897 | static arm_hwbp_control_t | |
898 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
899 | { | |
900 | return control & ~0x1; | |
901 | } | |
902 | ||
903 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
904 | enabled, and will point to the placed address of BP_TGT. */ | |
905 | static void | |
906 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
907 | struct bp_target_info *bp_tgt, | |
908 | struct arm_linux_hw_breakpoint *p) | |
909 | { | |
910 | unsigned mask; | |
0d5ed153 | 911 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
912 | |
913 | /* We have to create a mask for the control register which says which bits | |
914 | of the word pointed to by address to break on. */ | |
915 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
916 | { |
917 | mask = 0x3; | |
918 | address &= ~1; | |
919 | } | |
e3039479 | 920 | else |
fcf303ab UW |
921 | { |
922 | mask = 0xf; | |
923 | address &= ~3; | |
924 | } | |
e3039479 | 925 | |
fcf303ab | 926 | p->address = (unsigned int) address; |
e3039479 UW |
927 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
928 | } | |
929 | ||
930 | /* Get the ARM hardware breakpoint type from the RW value we're given when | |
931 | asked to set a watchpoint. */ | |
932 | static arm_hwbp_type | |
933 | arm_linux_get_hwbp_type (int rw) | |
934 | { | |
935 | if (rw == hw_read) | |
936 | return arm_hwbp_load; | |
937 | else if (rw == hw_write) | |
938 | return arm_hwbp_store; | |
939 | else | |
940 | return arm_hwbp_access; | |
941 | } | |
942 | ||
943 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
944 | to LEN. The type of watchpoint is given in RW. */ | |
945 | static void | |
946 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, int rw, | |
947 | struct arm_linux_hw_breakpoint *p) | |
948 | { | |
949 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
950 | unsigned mask; | |
951 | ||
952 | gdb_assert (cap != NULL); | |
953 | gdb_assert (cap->max_wp_length != 0); | |
954 | ||
955 | mask = (1 << len) - 1; | |
956 | ||
957 | p->address = (unsigned int) addr; | |
958 | p->control = arm_hwbp_control_initialize (mask, | |
959 | arm_linux_get_hwbp_type (rw), 1); | |
960 | } | |
961 | ||
962 | /* Are two break-/watch-points equal? */ | |
963 | static int | |
964 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
965 | const struct arm_linux_hw_breakpoint *p2) | |
966 | { | |
967 | return p1->address == p2->address && p1->control == p2->control; | |
968 | } | |
969 | ||
638c5f49 OJ |
970 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
971 | the current process. */ | |
972 | ||
973 | struct update_registers_data | |
974 | { | |
975 | int watch; | |
976 | int index; | |
977 | }; | |
978 | ||
979 | static int | |
980 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
981 | { | |
982 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
983 | ||
984 | if (lwp->arch_private == NULL) | |
985 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
986 | ||
987 | /* The actual update is done later just before resuming the lwp, | |
988 | we just mark that the registers need updating. */ | |
989 | if (data->watch) | |
990 | lwp->arch_private->wpts_changed[data->index] = 1; | |
991 | else | |
992 | lwp->arch_private->bpts_changed[data->index] = 1; | |
993 | ||
994 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
995 | we can update its breakpoint registers. */ | |
996 | if (!lwp->stopped) | |
997 | linux_stop_lwp (lwp); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
e3039479 UW |
1002 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
1003 | =1) BPT for thread TID. */ | |
1004 | static void | |
1005 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 1006 | int watchpoint) |
e3039479 | 1007 | { |
638c5f49 OJ |
1008 | int pid; |
1009 | ptid_t pid_ptid; | |
e3039479 UW |
1010 | gdb_byte count, i; |
1011 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1012 | struct update_registers_data data; |
e3039479 | 1013 | |
638c5f49 OJ |
1014 | pid = ptid_get_pid (inferior_ptid); |
1015 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1016 | |
1017 | if (watchpoint) | |
1018 | { | |
1019 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1020 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1021 | } |
1022 | else | |
1023 | { | |
1024 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1025 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1026 | } |
1027 | ||
1028 | for (i = 0; i < count; ++i) | |
1029 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1030 | { | |
638c5f49 OJ |
1031 | data.watch = watchpoint; |
1032 | data.index = i; | |
1033 | bpts[i] = *bpt; | |
1034 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1035 | break; | |
e3039479 UW |
1036 | } |
1037 | ||
1038 | gdb_assert (i != count); | |
1039 | } | |
1040 | ||
1041 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1042 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1043 | static void | |
1044 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1045 | int watchpoint) |
e3039479 | 1046 | { |
638c5f49 | 1047 | int pid; |
e3039479 | 1048 | gdb_byte count, i; |
638c5f49 OJ |
1049 | ptid_t pid_ptid; |
1050 | struct arm_linux_hw_breakpoint* bpts; | |
1051 | struct update_registers_data data; | |
e3039479 | 1052 | |
638c5f49 OJ |
1053 | pid = ptid_get_pid (inferior_ptid); |
1054 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1055 | |
1056 | if (watchpoint) | |
1057 | { | |
1058 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1059 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1060 | } |
1061 | else | |
1062 | { | |
1063 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1064 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1065 | } |
1066 | ||
1067 | for (i = 0; i < count; ++i) | |
1068 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1069 | { | |
638c5f49 OJ |
1070 | data.watch = watchpoint; |
1071 | data.index = i; | |
1072 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1073 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1074 | break; | |
e3039479 UW |
1075 | } |
1076 | ||
1077 | gdb_assert (i != count); | |
1078 | } | |
1079 | ||
1080 | /* Insert a Hardware breakpoint. */ | |
1081 | static int | |
23a26771 TT |
1082 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1083 | struct gdbarch *gdbarch, | |
e3039479 UW |
1084 | struct bp_target_info *bp_tgt) |
1085 | { | |
e3039479 UW |
1086 | struct lwp_info *lp; |
1087 | struct arm_linux_hw_breakpoint p; | |
1088 | ||
1089 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1090 | return -1; | |
1091 | ||
1092 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1093 | |
1094 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1095 | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | /* Remove a hardware breakpoint. */ | |
1100 | static int | |
a64dc96c TT |
1101 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1102 | struct gdbarch *gdbarch, | |
e3039479 UW |
1103 | struct bp_target_info *bp_tgt) |
1104 | { | |
e3039479 UW |
1105 | struct lwp_info *lp; |
1106 | struct arm_linux_hw_breakpoint p; | |
1107 | ||
1108 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1109 | return -1; | |
1110 | ||
1111 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1112 | |
1113 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1114 | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1119 | ADDR? */ | |
1120 | static int | |
31568a15 TT |
1121 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1122 | CORE_ADDR addr, int len) | |
e3039479 UW |
1123 | { |
1124 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1125 | CORE_ADDR max_wp_length, aligned_addr; | |
1126 | ||
1127 | /* Can not set watchpoints for zero or negative lengths. */ | |
1128 | if (len <= 0) | |
1129 | return 0; | |
1130 | ||
1131 | /* Need to be able to use the ptrace interface. */ | |
1132 | if (cap == NULL || cap->wp_count == 0) | |
1133 | return 0; | |
1134 | ||
1135 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1136 | range covered by a watchpoint. */ | |
1137 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1138 | aligned_addr = addr & ~(max_wp_length - 1); | |
1139 | ||
1140 | if (aligned_addr + max_wp_length < addr + len) | |
1141 | return 0; | |
1142 | ||
1143 | /* The current ptrace interface can only handle watchpoints that are a | |
1144 | power of 2. */ | |
1145 | if ((len & (len - 1)) != 0) | |
1146 | return 0; | |
1147 | ||
1148 | /* All tests passed so we must be able to set a watchpoint. */ | |
1149 | return 1; | |
1150 | } | |
1151 | ||
1152 | /* Insert a Hardware breakpoint. */ | |
1153 | static int | |
7bb99c53 TT |
1154 | arm_linux_insert_watchpoint (struct target_ops *self, |
1155 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1156 | struct expression *cond) |
1157 | { | |
e3039479 UW |
1158 | struct lwp_info *lp; |
1159 | struct arm_linux_hw_breakpoint p; | |
1160 | ||
1161 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1162 | return -1; | |
1163 | ||
1164 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1165 | |
1166 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1167 | |
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | /* Remove a hardware breakpoint. */ | |
1172 | static int | |
11b5219a TT |
1173 | arm_linux_remove_watchpoint (struct target_ops *self, |
1174 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1175 | struct expression *cond) |
1176 | { | |
e3039479 UW |
1177 | struct lwp_info *lp; |
1178 | struct arm_linux_hw_breakpoint p; | |
1179 | ||
1180 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1181 | return -1; | |
1182 | ||
1183 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1184 | |
1185 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1186 | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | /* What was the data address the target was stopped on accessing. */ | |
1191 | static int | |
1192 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1193 | { | |
f865ee35 JK |
1194 | siginfo_t siginfo; |
1195 | int slot; | |
1196 | ||
1197 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1198 | return 0; | |
e3039479 UW |
1199 | |
1200 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1201 | if (siginfo.si_signo != SIGTRAP |
1202 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1203 | return 0; |
1204 | ||
1205 | /* We must be able to set hardware watchpoints. */ | |
1206 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1207 | return 0; | |
1208 | ||
f865ee35 JK |
1209 | slot = siginfo.si_errno; |
1210 | ||
e3039479 UW |
1211 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1212 | a watchpoint. */ | |
1213 | if (slot >= 0) | |
1214 | return 0; | |
1215 | ||
f865ee35 | 1216 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1217 | return 1; |
1218 | } | |
1219 | ||
1220 | /* Has the target been stopped by hitting a watchpoint? */ | |
1221 | static int | |
6a109b6b | 1222 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1223 | { |
1224 | CORE_ADDR addr; | |
6a109b6b | 1225 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1226 | } |
1227 | ||
1228 | static int | |
1229 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1230 | CORE_ADDR addr, | |
1231 | CORE_ADDR start, int length) | |
1232 | { | |
1233 | return start <= addr && start + length - 1 >= addr; | |
1234 | } | |
1235 | ||
1236 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1237 | in the parent thread to the child thread. */ | |
1238 | static void | |
7b50312a | 1239 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1240 | { |
638c5f49 OJ |
1241 | int i; |
1242 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1243 | ||
1244 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1245 | for this thread need to be initialized. */ | |
e3039479 | 1246 | |
638c5f49 | 1247 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1248 | { |
638c5f49 OJ |
1249 | info->bpts_changed[i] = 1; |
1250 | info->wpts_changed[i] = 1; | |
e3039479 | 1251 | } |
638c5f49 OJ |
1252 | |
1253 | lp->arch_private = info; | |
e3039479 UW |
1254 | } |
1255 | ||
638c5f49 OJ |
1256 | /* Called when resuming a thread. |
1257 | The hardware debug registers are updated when there is any change. */ | |
1258 | ||
e3039479 | 1259 | static void |
638c5f49 | 1260 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1261 | { |
638c5f49 OJ |
1262 | int pid, i; |
1263 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1264 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1265 | ||
1266 | pid = ptid_get_lwp (lwp->ptid); | |
1267 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1268 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1269 | ||
1270 | /* NULL means this is the main thread still going through the shell, | |
1271 | or, no watchpoint has been set yet. In that case, there's | |
1272 | nothing to do. */ | |
1273 | if (arm_lwp_info == NULL) | |
1274 | return; | |
e3039479 | 1275 | |
638c5f49 OJ |
1276 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1277 | if (arm_lwp_info->bpts_changed[i]) | |
1278 | { | |
1279 | errno = 0; | |
1280 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1281 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1282 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1283 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1284 | ||
1285 | if (bpts[i].control != 0) | |
1286 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1287 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1288 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1289 | ||
1290 | arm_lwp_info->bpts_changed[i] = 0; | |
1291 | } | |
e3039479 | 1292 | |
638c5f49 OJ |
1293 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1294 | if (arm_lwp_info->wpts_changed[i]) | |
1295 | { | |
1296 | errno = 0; | |
1297 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1298 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1299 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1300 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1301 | ||
1302 | if (wpts[i].control != 0) | |
1303 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1304 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1305 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1306 | ||
1307 | arm_lwp_info->wpts_changed[i] = 0; | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | /* linux_nat_new_fork hook. */ | |
1312 | ||
1313 | static void | |
1314 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1315 | { | |
1316 | pid_t parent_pid; | |
1317 | struct arm_linux_debug_reg_state *parent_state; | |
1318 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1319 | |
638c5f49 OJ |
1320 | /* NULL means no watchpoint has ever been set in the parent. In |
1321 | that case, there's nothing to do. */ | |
1322 | if (parent->arch_private == NULL) | |
1323 | return; | |
e3039479 | 1324 | |
638c5f49 OJ |
1325 | /* GDB core assumes the child inherits the watchpoints/hw |
1326 | breakpoints of the parent, and will remove them all from the | |
1327 | forked off process. Copy the debug registers mirrors into the | |
1328 | new process so that all breakpoints and watchpoints can be | |
1329 | removed together. */ | |
e3039479 | 1330 | |
638c5f49 OJ |
1331 | parent_pid = ptid_get_pid (parent->ptid); |
1332 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1333 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1334 | *child_state = *parent_state; | |
e3039479 UW |
1335 | } |
1336 | ||
10d6c8cd DJ |
1337 | void _initialize_arm_linux_nat (void); |
1338 | ||
ed9a39eb JM |
1339 | void |
1340 | _initialize_arm_linux_nat (void) | |
1341 | { | |
10d6c8cd DJ |
1342 | struct target_ops *t; |
1343 | ||
10d6c8cd DJ |
1344 | /* Fill in the generic GNU/Linux methods. */ |
1345 | t = linux_target (); | |
1346 | ||
1347 | /* Add our register access methods. */ | |
1348 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1349 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1350 | ||
e3039479 UW |
1351 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1352 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1353 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1354 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1355 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1356 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1357 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1358 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1359 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1360 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1361 | ||
81adfced | 1362 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1363 | |
10d6c8cd | 1364 | /* Register the target. */ |
f973ed9c | 1365 | linux_nat_add_target (t); |
e3039479 | 1366 | |
638c5f49 | 1367 | /* Handle thread creation and exit. */ |
e3039479 | 1368 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1369 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1370 | ||
1371 | /* Handle process creation and exit. */ | |
1372 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1373 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1374 | } |