Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
61baf725 | 2 | Copyright (C) 1999-2017 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
f1b67888 | 32 | #include "aarch32-linux-nat.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb | 35 | #include <sys/user.h> |
5826e159 | 36 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 37 | #include <sys/utsname.h> |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
95855ca8 MS |
40 | #include "nat/linux-ptrace.h" |
41 | ||
0963b4bd | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
43 | #include "gregset.h" |
44 | ||
9308fc88 DJ |
45 | /* Defines ps_err_e, struct ps_prochandle. */ |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
05a4558a DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
3b273a55 RE |
57 | #ifndef PTRACE_GETVFPREGS |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
e3039479 UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
ed9a39eb JM |
67 | extern int arm_apcs_32; |
68 | ||
41c49b06 | 69 | /* Get the whole floating point state of the process and store it |
c6b92abd | 70 | into regcache. */ |
ed9a39eb JM |
71 | |
72 | static void | |
56be3814 | 73 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 74 | { |
41c49b06 | 75 | int ret, regno, tid; |
cb587d83 | 76 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 77 | |
41c49b06 | 78 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 79 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
df9d7ec9 | 80 | |
ed9a39eb | 81 | /* Read the floating point state. */ |
0bdb2f78 | 82 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
83 | { |
84 | struct iovec iov; | |
85 | ||
86 | iov.iov_base = &fp; | |
87 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
88 | ||
89 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
90 | } | |
91 | else | |
92 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
93 | ||
ed9a39eb | 94 | if (ret < 0) |
d86feca3 | 95 | perror_with_name (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
96 | |
97 | /* Fetch fpsr. */ | |
56be3814 | 98 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 99 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
100 | |
101 | /* Fetch the floating point registers. */ | |
34e8f22d | 102 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 103 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
104 | } |
105 | ||
106 | /* Save the whole floating point state of the process using | |
c6b92abd | 107 | the contents from regcache. */ |
ed9a39eb JM |
108 | |
109 | static void | |
56be3814 | 110 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 111 | { |
41c49b06 | 112 | int ret, regno, tid; |
cb587d83 | 113 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 114 | |
41c49b06 | 115 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 116 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
df9d7ec9 | 117 | |
41c49b06 | 118 | /* Read the floating point state. */ |
0bdb2f78 | 119 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
120 | { |
121 | elf_fpregset_t fpregs; | |
122 | struct iovec iov; | |
123 | ||
124 | iov.iov_base = &fpregs; | |
125 | iov.iov_len = sizeof (fpregs); | |
126 | ||
127 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
128 | } | |
129 | else | |
130 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
131 | ||
41c49b06 | 132 | if (ret < 0) |
d86feca3 | 133 | perror_with_name (_("Unable to fetch the floating point registers.")); |
41c49b06 | 134 | |
ed9a39eb | 135 | /* Store fpsr. */ |
672c9795 | 136 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 137 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
138 | |
139 | /* Store the floating point registers. */ | |
34e8f22d | 140 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 141 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 142 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 143 | |
0bdb2f78 | 144 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
145 | { |
146 | struct iovec iov; | |
147 | ||
148 | iov.iov_base = &fp; | |
149 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
150 | ||
151 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
152 | } | |
153 | else | |
154 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
155 | ||
ed9a39eb | 156 | if (ret < 0) |
d86feca3 | 157 | perror_with_name (_("Unable to store floating point registers.")); |
ed9a39eb JM |
158 | } |
159 | ||
160 | /* Fetch all general registers of the process and store into | |
c6b92abd | 161 | regcache. */ |
ed9a39eb JM |
162 | |
163 | static void | |
56be3814 | 164 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 165 | { |
41c49b06 | 166 | int ret, regno, tid; |
c2152441 | 167 | elf_gregset_t regs; |
ed9a39eb | 168 | |
41c49b06 | 169 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 170 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
10766686 | 171 | |
0bdb2f78 | 172 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
173 | { |
174 | struct iovec iov; | |
175 | ||
176 | iov.iov_base = ®s; | |
177 | iov.iov_len = sizeof (regs); | |
178 | ||
179 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
180 | } | |
181 | else | |
182 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
183 | ||
ed9a39eb | 184 | if (ret < 0) |
d86feca3 | 185 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 186 | |
f1b67888 | 187 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
188 | } |
189 | ||
ed9a39eb | 190 | static void |
56be3814 | 191 | store_regs (const struct regcache *regcache) |
ed9a39eb | 192 | { |
41c49b06 | 193 | int ret, regno, tid; |
c2152441 | 194 | elf_gregset_t regs; |
ed9a39eb | 195 | |
41c49b06 | 196 | /* Get the thread id for the ptrace call. */ |
4ac4bb6a | 197 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
10766686 | 198 | |
41c49b06 | 199 | /* Fetch the general registers. */ |
0bdb2f78 | 200 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
201 | { |
202 | struct iovec iov; | |
203 | ||
204 | iov.iov_base = ®s; | |
205 | iov.iov_len = sizeof (regs); | |
206 | ||
207 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
208 | } | |
209 | else | |
210 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
211 | ||
ed9a39eb | 212 | if (ret < 0) |
d86feca3 | 213 | perror_with_name (_("Unable to fetch general registers.")); |
ed9a39eb | 214 | |
f1b67888 | 215 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 216 | |
0bdb2f78 | 217 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
218 | { |
219 | struct iovec iov; | |
220 | ||
221 | iov.iov_base = ®s; | |
222 | iov.iov_len = sizeof (regs); | |
223 | ||
224 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
225 | } | |
226 | else | |
227 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
228 | |
229 | if (ret < 0) | |
d86feca3 | 230 | perror_with_name (_("Unable to store general registers.")); |
ed9a39eb JM |
231 | } |
232 | ||
05a4558a DJ |
233 | /* Fetch all WMMX registers of the process and store into |
234 | regcache. */ | |
235 | ||
236 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
237 | ||
238 | static void | |
56be3814 | 239 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
240 | { |
241 | char regbuf[IWMMXT_REGS_SIZE]; | |
242 | int ret, regno, tid; | |
243 | ||
244 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 245 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
05a4558a DJ |
246 | |
247 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
248 | if (ret < 0) | |
d86feca3 | 249 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
250 | |
251 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 252 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
253 | ®buf[regno * 8]); |
254 | ||
255 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 256 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
257 | ®buf[16 * 8 + regno * 4]); |
258 | ||
259 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 260 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
261 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
262 | } | |
263 | ||
264 | static void | |
56be3814 | 265 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
266 | { |
267 | char regbuf[IWMMXT_REGS_SIZE]; | |
268 | int ret, regno, tid; | |
269 | ||
270 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 271 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
05a4558a DJ |
272 | |
273 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
274 | if (ret < 0) | |
d86feca3 | 275 | perror_with_name (_("Unable to fetch WMMX registers.")); |
05a4558a DJ |
276 | |
277 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
278 | if (REG_VALID == regcache_register_status (regcache, |
279 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 280 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
281 | ®buf[regno * 8]); |
282 | ||
283 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
284 | if (REG_VALID == regcache_register_status (regcache, |
285 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 286 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
287 | ®buf[16 * 8 + regno * 4]); |
288 | ||
289 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
290 | if (REG_VALID == regcache_register_status (regcache, |
291 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 292 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
293 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
294 | ||
295 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
296 | ||
297 | if (ret < 0) | |
d86feca3 | 298 | perror_with_name (_("Unable to store WMMX registers.")); |
05a4558a DJ |
299 | } |
300 | ||
3b273a55 RE |
301 | static void |
302 | fetch_vfp_regs (struct regcache *regcache) | |
303 | { | |
f1b67888 | 304 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 305 | int ret, regno, tid; |
330c6ca9 YQ |
306 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
307 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
308 | |
309 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 310 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
3b273a55 | 311 | |
0bdb2f78 | 312 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
313 | { |
314 | struct iovec iov; | |
315 | ||
316 | iov.iov_base = regbuf; | |
317 | iov.iov_len = VFP_REGS_SIZE; | |
318 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
319 | } | |
320 | else | |
321 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
322 | ||
3b273a55 | 323 | if (ret < 0) |
d86feca3 | 324 | perror_with_name (_("Unable to fetch VFP registers.")); |
3b273a55 | 325 | |
f1b67888 YQ |
326 | aarch32_vfp_regcache_supply (regcache, regbuf, |
327 | tdep->vfp_register_count); | |
3b273a55 RE |
328 | } |
329 | ||
330 | static void | |
331 | store_vfp_regs (const struct regcache *regcache) | |
332 | { | |
f1b67888 | 333 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 334 | int ret, regno, tid; |
330c6ca9 YQ |
335 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
336 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
337 | |
338 | /* Get the thread id for the ptrace call. */ | |
4ac4bb6a | 339 | tid = ptid_get_lwp (regcache_get_ptid (regcache)); |
3b273a55 | 340 | |
0bdb2f78 | 341 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
342 | { |
343 | struct iovec iov; | |
344 | ||
345 | iov.iov_base = regbuf; | |
346 | iov.iov_len = VFP_REGS_SIZE; | |
347 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
348 | } | |
349 | else | |
350 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
351 | ||
3b273a55 | 352 | if (ret < 0) |
d86feca3 | 353 | perror_with_name (_("Unable to fetch VFP registers (for update).")); |
3b273a55 | 354 | |
f1b67888 YQ |
355 | aarch32_vfp_regcache_collect (regcache, regbuf, |
356 | tdep->vfp_register_count); | |
3b273a55 | 357 | |
0bdb2f78 | 358 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
359 | { |
360 | struct iovec iov; | |
361 | ||
362 | iov.iov_base = regbuf; | |
363 | iov.iov_len = VFP_REGS_SIZE; | |
364 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
365 | } | |
366 | else | |
367 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
368 | |
369 | if (ret < 0) | |
d86feca3 | 370 | perror_with_name (_("Unable to store VFP registers.")); |
3b273a55 RE |
371 | } |
372 | ||
ed9a39eb JM |
373 | /* Fetch registers from the child process. Fetch all registers if |
374 | regno == -1, otherwise fetch all general registers or all floating | |
375 | point registers depending upon the value of regno. */ | |
376 | ||
10d6c8cd | 377 | static void |
28439f5e PA |
378 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
379 | struct regcache *regcache, int regno) | |
ed9a39eb | 380 | { |
330c6ca9 YQ |
381 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
382 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
383 | ||
41c49b06 SB |
384 | if (-1 == regno) |
385 | { | |
56be3814 | 386 | fetch_regs (regcache); |
a56cc1ce | 387 | if (tdep->have_wmmx_registers) |
56be3814 | 388 | fetch_wmmx_regs (regcache); |
330c6ca9 | 389 | if (tdep->vfp_register_count > 0) |
3b273a55 | 390 | fetch_vfp_regs (regcache); |
4bd2e1b2 KC |
391 | if (tdep->have_fpa_registers) |
392 | fetch_fpregs (regcache); | |
41c49b06 | 393 | } |
4bd2e1b2 | 394 | else |
41c49b06 | 395 | { |
05a4558a | 396 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 397 | fetch_regs (regcache); |
05a4558a | 398 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 399 | fetch_fpregs (regcache); |
a56cc1ce | 400 | else if (tdep->have_wmmx_registers |
05a4558a | 401 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 402 | fetch_wmmx_regs (regcache); |
330c6ca9 | 403 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 404 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 405 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 406 | fetch_vfp_regs (regcache); |
41c49b06 | 407 | } |
ed9a39eb JM |
408 | } |
409 | ||
410 | /* Store registers back into the inferior. Store all registers if | |
411 | regno == -1, otherwise store all general registers or all floating | |
412 | point registers depending upon the value of regno. */ | |
413 | ||
10d6c8cd | 414 | static void |
28439f5e PA |
415 | arm_linux_store_inferior_registers (struct target_ops *ops, |
416 | struct regcache *regcache, int regno) | |
ed9a39eb | 417 | { |
330c6ca9 YQ |
418 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
419 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
420 | ||
41c49b06 SB |
421 | if (-1 == regno) |
422 | { | |
56be3814 | 423 | store_regs (regcache); |
a56cc1ce | 424 | if (tdep->have_wmmx_registers) |
56be3814 | 425 | store_wmmx_regs (regcache); |
330c6ca9 | 426 | if (tdep->vfp_register_count > 0) |
3b273a55 | 427 | store_vfp_regs (regcache); |
4bd2e1b2 KC |
428 | if (tdep->have_fpa_registers) |
429 | store_fpregs (regcache); | |
41c49b06 SB |
430 | } |
431 | else | |
432 | { | |
05a4558a | 433 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 434 | store_regs (regcache); |
05a4558a | 435 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 436 | store_fpregs (regcache); |
a56cc1ce | 437 | else if (tdep->have_wmmx_registers |
05a4558a | 438 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 439 | store_wmmx_regs (regcache); |
330c6ca9 | 440 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 441 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 442 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 443 | store_vfp_regs (regcache); |
41c49b06 | 444 | } |
ed9a39eb JM |
445 | } |
446 | ||
cb587d83 DJ |
447 | /* Wrapper functions for the standard regset handling, used by |
448 | thread debugging. */ | |
41c49b06 SB |
449 | |
450 | void | |
7f7fe91e UW |
451 | fill_gregset (const struct regcache *regcache, |
452 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 453 | { |
7f7fe91e | 454 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
455 | } |
456 | ||
41c49b06 | 457 | void |
7f7fe91e | 458 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 459 | { |
7f7fe91e | 460 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
461 | } |
462 | ||
41c49b06 | 463 | void |
7f7fe91e UW |
464 | fill_fpregset (const struct regcache *regcache, |
465 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 466 | { |
7f7fe91e | 467 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
468 | } |
469 | ||
470 | /* Fill GDB's register array with the floating-point register values | |
471 | in *fpregsetp. */ | |
472 | ||
473 | void | |
7f7fe91e | 474 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 475 | { |
7f7fe91e | 476 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
477 | } |
478 | ||
9308fc88 DJ |
479 | /* Fetch the thread-local storage pointer for libthread_db. */ |
480 | ||
481 | ps_err_e | |
754653a7 | 482 | ps_get_thread_area (struct ps_prochandle *ph, |
9308fc88 DJ |
483 | lwpid_t lwpid, int idx, void **base) |
484 | { | |
485 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
486 | return PS_ERR; | |
487 | ||
488 | /* IDX is the bias from the thread pointer to the beginning of the | |
489 | thread descriptor. It has to be subtracted due to implementation | |
490 | quirks in libthread_db. */ | |
491 | *base = (void *) ((char *)*base - idx); | |
492 | ||
493 | return PS_OK; | |
494 | } | |
495 | ||
81adfced DJ |
496 | static const struct target_desc * |
497 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 498 | { |
3b273a55 | 499 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 500 | |
0bdb2f78 | 501 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
502 | { |
503 | elf_gregset_t gpregs; | |
504 | struct iovec iov; | |
d89fa914 | 505 | int tid = ptid_get_lwp (inferior_ptid); |
7efe48d1 YQ |
506 | |
507 | iov.iov_base = &gpregs; | |
508 | iov.iov_len = sizeof (gpregs); | |
509 | ||
510 | /* Check if PTRACE_GETREGSET works. */ | |
511 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 512 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 513 | else |
0bdb2f78 | 514 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
515 | } |
516 | ||
3b273a55 RE |
517 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
518 | { | |
2117c711 | 519 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 520 | } |
81adfced | 521 | |
3b273a55 | 522 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 523 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
524 | |
525 | if (arm_hwcap & HWCAP_VFP) | |
526 | { | |
527 | int pid; | |
528 | char *buf; | |
529 | const struct target_desc * result = NULL; | |
530 | ||
531 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
532 | Neon with VFPv3-D32. */ | |
533 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 534 | result = tdesc_arm_with_neon; |
3b273a55 | 535 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 536 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 537 | else |
330c6ca9 | 538 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
539 | |
540 | /* Now make sure that the kernel supports reading these | |
541 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 542 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 | 543 | errno = 0; |
f844cf0e | 544 | buf = (char *) alloca (VFP_REGS_SIZE); |
3b273a55 RE |
545 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
546 | && errno == EIO) | |
547 | result = NULL; | |
548 | ||
549 | return result; | |
550 | } | |
551 | ||
2117c711 | 552 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
553 | } |
554 | ||
e3039479 UW |
555 | /* Information describing the hardware breakpoint capabilities. */ |
556 | struct arm_linux_hwbp_cap | |
557 | { | |
558 | gdb_byte arch; | |
559 | gdb_byte max_wp_length; | |
560 | gdb_byte wp_count; | |
561 | gdb_byte bp_count; | |
562 | }; | |
563 | ||
638c5f49 OJ |
564 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
565 | assume a maximum number of supported break-/watchpoints. */ | |
566 | #define MAX_BPTS 16 | |
567 | #define MAX_WPTS 16 | |
568 | ||
e3039479 UW |
569 | /* Get hold of the Hardware Breakpoint information for the target we are |
570 | attached to. Returns NULL if the kernel doesn't support Hardware | |
571 | breakpoints at all, or a pointer to the information structure. */ | |
572 | static const struct arm_linux_hwbp_cap * | |
573 | arm_linux_get_hwbp_cap (void) | |
574 | { | |
575 | /* The info structure we return. */ | |
576 | static struct arm_linux_hwbp_cap info; | |
577 | ||
578 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
579 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
580 | means INFO is in an initialized state. */ | |
581 | static int available = -1; | |
582 | ||
583 | if (available == -1) | |
584 | { | |
585 | int tid; | |
586 | unsigned int val; | |
587 | ||
d89fa914 | 588 | tid = ptid_get_lwp (inferior_ptid); |
e3039479 UW |
589 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
590 | available = 0; | |
591 | else | |
592 | { | |
593 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
594 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
595 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
596 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
597 | |
598 | if (info.wp_count > MAX_WPTS) | |
599 | { | |
600 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
601 | supports %d"), MAX_WPTS, info.wp_count); | |
602 | info.wp_count = MAX_WPTS; | |
603 | } | |
604 | ||
605 | if (info.bp_count > MAX_BPTS) | |
606 | { | |
607 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
608 | supports %d"), MAX_BPTS, info.bp_count); | |
609 | info.bp_count = MAX_BPTS; | |
610 | } | |
e3039479 UW |
611 | available = (info.arch != 0); |
612 | } | |
613 | } | |
614 | ||
615 | return available == 1 ? &info : NULL; | |
616 | } | |
617 | ||
618 | /* How many hardware breakpoints are available? */ | |
619 | static int | |
620 | arm_linux_get_hw_breakpoint_count (void) | |
621 | { | |
622 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
623 | return cap != NULL ? cap->bp_count : 0; | |
624 | } | |
625 | ||
626 | /* How many hardware watchpoints are available? */ | |
627 | static int | |
628 | arm_linux_get_hw_watchpoint_count (void) | |
629 | { | |
630 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
631 | return cap != NULL ? cap->wp_count : 0; | |
632 | } | |
633 | ||
634 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
635 | there is not an appropriate resource available, otherwise returns 1. */ | |
636 | static int | |
5461485a | 637 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
f486487f SM |
638 | enum bptype type, |
639 | int cnt, int ot) | |
e3039479 UW |
640 | { |
641 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
642 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
643 | { | |
dbbf180a YQ |
644 | int count = arm_linux_get_hw_watchpoint_count (); |
645 | ||
646 | if (count == 0) | |
647 | return 0; | |
648 | else if (cnt + ot > count) | |
e3039479 UW |
649 | return -1; |
650 | } | |
651 | else if (type == bp_hardware_breakpoint) | |
652 | { | |
dbbf180a YQ |
653 | int count = arm_linux_get_hw_breakpoint_count (); |
654 | ||
655 | if (count == 0) | |
656 | return 0; | |
657 | else if (cnt > count) | |
e3039479 UW |
658 | return -1; |
659 | } | |
660 | else | |
661 | gdb_assert (FALSE); | |
662 | ||
663 | return 1; | |
664 | } | |
665 | ||
666 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
667 | typedef enum | |
668 | { | |
669 | arm_hwbp_break = 0, | |
670 | arm_hwbp_load = 1, | |
671 | arm_hwbp_store = 2, | |
672 | arm_hwbp_access = 3 | |
673 | } arm_hwbp_type; | |
674 | ||
675 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
676 | typedef unsigned int arm_hwbp_control_t; | |
677 | ||
678 | /* Structure used to keep track of hardware break-/watch-points. */ | |
679 | struct arm_linux_hw_breakpoint | |
680 | { | |
681 | /* Address to break on, or being watched. */ | |
682 | unsigned int address; | |
683 | /* Control register for break-/watch- point. */ | |
684 | arm_hwbp_control_t control; | |
685 | }; | |
686 | ||
638c5f49 OJ |
687 | /* Structure containing arrays of per process hardware break-/watchpoints |
688 | for caching address and control information. | |
e3039479 UW |
689 | |
690 | The Linux ptrace interface to hardware break-/watch-points presents the | |
691 | values in a vector centred around 0 (which is used fo generic information). | |
692 | Positive indicies refer to breakpoint addresses/control registers, negative | |
693 | indices to watchpoint addresses/control registers. | |
694 | ||
695 | The Linux vector is indexed as follows: | |
696 | -((i << 1) + 2): Control register for watchpoint i. | |
697 | -((i << 1) + 1): Address register for watchpoint i. | |
698 | 0: Information register. | |
699 | ((i << 1) + 1): Address register for breakpoint i. | |
700 | ((i << 1) + 2): Control register for breakpoint i. | |
701 | ||
702 | This structure is used as a per-thread cache of the state stored by the | |
703 | kernel, so that we don't need to keep calling into the kernel to find a | |
704 | free breakpoint. | |
705 | ||
706 | We treat break-/watch-points with their enable bit clear as being deleted. | |
707 | */ | |
638c5f49 | 708 | struct arm_linux_debug_reg_state |
e3039479 | 709 | { |
638c5f49 OJ |
710 | /* Hardware breakpoints for this process. */ |
711 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
712 | /* Hardware watchpoints for this process. */ | |
713 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
714 | }; | |
715 | ||
716 | /* Per-process arch-specific data we want to keep. */ | |
717 | struct arm_linux_process_info | |
e3039479 | 718 | { |
638c5f49 OJ |
719 | /* Linked list. */ |
720 | struct arm_linux_process_info *next; | |
721 | /* The process identifier. */ | |
722 | pid_t pid; | |
723 | /* Hardware break-/watchpoints state information. */ | |
724 | struct arm_linux_debug_reg_state state; | |
e3039479 | 725 | |
638c5f49 OJ |
726 | }; |
727 | ||
728 | /* Per-thread arch-specific data we want to keep. */ | |
729 | struct arch_lwp_info | |
730 | { | |
731 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
732 | char bpts_changed[MAX_BPTS]; | |
733 | char wpts_changed[MAX_WPTS]; | |
734 | }; | |
735 | ||
736 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
737 | ||
738 | /* Find process data for process PID. */ | |
739 | ||
740 | static struct arm_linux_process_info * | |
741 | arm_linux_find_process_pid (pid_t pid) | |
742 | { | |
743 | struct arm_linux_process_info *proc; | |
744 | ||
745 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
746 | if (proc->pid == pid) | |
747 | return proc; | |
748 | ||
749 | return NULL; | |
750 | } | |
751 | ||
752 | /* Add process data for process PID. Returns newly allocated info | |
753 | object. */ | |
754 | ||
755 | static struct arm_linux_process_info * | |
756 | arm_linux_add_process (pid_t pid) | |
757 | { | |
758 | struct arm_linux_process_info *proc; | |
e3039479 | 759 | |
8d749320 | 760 | proc = XCNEW (struct arm_linux_process_info); |
638c5f49 | 761 | proc->pid = pid; |
e3039479 | 762 | |
638c5f49 OJ |
763 | proc->next = arm_linux_process_list; |
764 | arm_linux_process_list = proc; | |
765 | ||
766 | return proc; | |
767 | } | |
768 | ||
769 | /* Get data specific info for process PID, creating it if necessary. | |
770 | Never returns NULL. */ | |
771 | ||
772 | static struct arm_linux_process_info * | |
773 | arm_linux_process_info_get (pid_t pid) | |
774 | { | |
775 | struct arm_linux_process_info *proc; | |
776 | ||
777 | proc = arm_linux_find_process_pid (pid); | |
778 | if (proc == NULL) | |
779 | proc = arm_linux_add_process (pid); | |
780 | ||
781 | return proc; | |
782 | } | |
783 | ||
784 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
785 | data structures that keep track of debug register state. */ | |
786 | ||
787 | static void | |
788 | arm_linux_forget_process (pid_t pid) | |
789 | { | |
790 | struct arm_linux_process_info *proc, **proc_link; | |
791 | ||
792 | proc = arm_linux_process_list; | |
793 | proc_link = &arm_linux_process_list; | |
794 | ||
795 | while (proc != NULL) | |
796 | { | |
797 | if (proc->pid == pid) | |
e3039479 | 798 | { |
638c5f49 OJ |
799 | *proc_link = proc->next; |
800 | ||
801 | xfree (proc); | |
802 | return; | |
e3039479 UW |
803 | } |
804 | ||
638c5f49 OJ |
805 | proc_link = &proc->next; |
806 | proc = *proc_link; | |
807 | } | |
808 | } | |
809 | ||
810 | /* Get hardware break-/watchpoint state for process PID. */ | |
811 | ||
812 | static struct arm_linux_debug_reg_state * | |
813 | arm_linux_get_debug_reg_state (pid_t pid) | |
814 | { | |
815 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
816 | } |
817 | ||
818 | /* Initialize an ARM hardware break-/watch-point control register value. | |
819 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
820 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
821 | */ | |
822 | static arm_hwbp_control_t | |
823 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
824 | arm_hwbp_type hwbp_type, | |
825 | int enable) | |
826 | { | |
827 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
828 | gdb_assert (hwbp_type != arm_hwbp_break | |
829 | || ((byte_address_select & 0xfU) != 0)); | |
830 | ||
831 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
832 | } | |
833 | ||
834 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
835 | static int | |
836 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
837 | { | |
838 | return control & 0x1; | |
839 | } | |
840 | ||
841 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
842 | static arm_hwbp_control_t | |
843 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
844 | { | |
845 | return control & ~0x1; | |
846 | } | |
847 | ||
848 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
849 | enabled, and will point to the placed address of BP_TGT. */ | |
850 | static void | |
851 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
852 | struct bp_target_info *bp_tgt, | |
853 | struct arm_linux_hw_breakpoint *p) | |
854 | { | |
855 | unsigned mask; | |
0d5ed153 | 856 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
857 | |
858 | /* We have to create a mask for the control register which says which bits | |
859 | of the word pointed to by address to break on. */ | |
860 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
861 | { |
862 | mask = 0x3; | |
863 | address &= ~1; | |
864 | } | |
e3039479 | 865 | else |
fcf303ab UW |
866 | { |
867 | mask = 0xf; | |
868 | address &= ~3; | |
869 | } | |
e3039479 | 870 | |
fcf303ab | 871 | p->address = (unsigned int) address; |
e3039479 UW |
872 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
873 | } | |
874 | ||
8156fe7f | 875 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 876 | given when asked to set a watchpoint. */ |
e3039479 | 877 | static arm_hwbp_type |
f486487f | 878 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 879 | { |
8156fe7f | 880 | if (type == hw_read) |
e3039479 | 881 | return arm_hwbp_load; |
8156fe7f | 882 | else if (type == hw_write) |
e3039479 UW |
883 | return arm_hwbp_store; |
884 | else | |
885 | return arm_hwbp_access; | |
886 | } | |
887 | ||
888 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
889 | to LEN. The type of watchpoint is given in RW. */ | |
890 | static void | |
f486487f SM |
891 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
892 | enum target_hw_bp_type type, | |
e3039479 UW |
893 | struct arm_linux_hw_breakpoint *p) |
894 | { | |
895 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
896 | unsigned mask; | |
897 | ||
898 | gdb_assert (cap != NULL); | |
899 | gdb_assert (cap->max_wp_length != 0); | |
900 | ||
901 | mask = (1 << len) - 1; | |
902 | ||
903 | p->address = (unsigned int) addr; | |
904 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 905 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
906 | } |
907 | ||
908 | /* Are two break-/watch-points equal? */ | |
909 | static int | |
910 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
911 | const struct arm_linux_hw_breakpoint *p2) | |
912 | { | |
913 | return p1->address == p2->address && p1->control == p2->control; | |
914 | } | |
915 | ||
638c5f49 OJ |
916 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
917 | the current process. */ | |
918 | ||
919 | struct update_registers_data | |
920 | { | |
921 | int watch; | |
922 | int index; | |
923 | }; | |
924 | ||
925 | static int | |
926 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
927 | { | |
928 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
929 | ||
930 | if (lwp->arch_private == NULL) | |
931 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
932 | ||
933 | /* The actual update is done later just before resuming the lwp, | |
934 | we just mark that the registers need updating. */ | |
935 | if (data->watch) | |
936 | lwp->arch_private->wpts_changed[data->index] = 1; | |
937 | else | |
938 | lwp->arch_private->bpts_changed[data->index] = 1; | |
939 | ||
940 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
941 | we can update its breakpoint registers. */ | |
942 | if (!lwp->stopped) | |
943 | linux_stop_lwp (lwp); | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
e3039479 UW |
948 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
949 | =1) BPT for thread TID. */ | |
950 | static void | |
951 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 952 | int watchpoint) |
e3039479 | 953 | { |
638c5f49 OJ |
954 | int pid; |
955 | ptid_t pid_ptid; | |
e3039479 UW |
956 | gdb_byte count, i; |
957 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 958 | struct update_registers_data data; |
e3039479 | 959 | |
638c5f49 OJ |
960 | pid = ptid_get_pid (inferior_ptid); |
961 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
962 | |
963 | if (watchpoint) | |
964 | { | |
965 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 966 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
967 | } |
968 | else | |
969 | { | |
970 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 971 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
972 | } |
973 | ||
974 | for (i = 0; i < count; ++i) | |
975 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
976 | { | |
638c5f49 OJ |
977 | data.watch = watchpoint; |
978 | data.index = i; | |
979 | bpts[i] = *bpt; | |
980 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
981 | break; | |
e3039479 UW |
982 | } |
983 | ||
984 | gdb_assert (i != count); | |
985 | } | |
986 | ||
987 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
988 | (WATCHPOINT = 1) BPT for thread TID. */ | |
989 | static void | |
990 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 991 | int watchpoint) |
e3039479 | 992 | { |
638c5f49 | 993 | int pid; |
e3039479 | 994 | gdb_byte count, i; |
638c5f49 OJ |
995 | ptid_t pid_ptid; |
996 | struct arm_linux_hw_breakpoint* bpts; | |
997 | struct update_registers_data data; | |
e3039479 | 998 | |
638c5f49 OJ |
999 | pid = ptid_get_pid (inferior_ptid); |
1000 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1001 | |
1002 | if (watchpoint) | |
1003 | { | |
1004 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1005 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1006 | } |
1007 | else | |
1008 | { | |
1009 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1010 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1011 | } |
1012 | ||
1013 | for (i = 0; i < count; ++i) | |
1014 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1015 | { | |
638c5f49 OJ |
1016 | data.watch = watchpoint; |
1017 | data.index = i; | |
1018 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1019 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1020 | break; | |
e3039479 UW |
1021 | } |
1022 | ||
1023 | gdb_assert (i != count); | |
1024 | } | |
1025 | ||
1026 | /* Insert a Hardware breakpoint. */ | |
1027 | static int | |
23a26771 TT |
1028 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1029 | struct gdbarch *gdbarch, | |
e3039479 UW |
1030 | struct bp_target_info *bp_tgt) |
1031 | { | |
e3039479 UW |
1032 | struct lwp_info *lp; |
1033 | struct arm_linux_hw_breakpoint p; | |
1034 | ||
1035 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1036 | return -1; | |
1037 | ||
1038 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1039 | |
1040 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1041 | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | /* Remove a hardware breakpoint. */ | |
1046 | static int | |
a64dc96c TT |
1047 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1048 | struct gdbarch *gdbarch, | |
e3039479 UW |
1049 | struct bp_target_info *bp_tgt) |
1050 | { | |
e3039479 UW |
1051 | struct lwp_info *lp; |
1052 | struct arm_linux_hw_breakpoint p; | |
1053 | ||
1054 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1055 | return -1; | |
1056 | ||
1057 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1058 | |
1059 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1060 | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1065 | ADDR? */ | |
1066 | static int | |
31568a15 TT |
1067 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1068 | CORE_ADDR addr, int len) | |
e3039479 UW |
1069 | { |
1070 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1071 | CORE_ADDR max_wp_length, aligned_addr; | |
1072 | ||
1073 | /* Can not set watchpoints for zero or negative lengths. */ | |
1074 | if (len <= 0) | |
1075 | return 0; | |
1076 | ||
1077 | /* Need to be able to use the ptrace interface. */ | |
1078 | if (cap == NULL || cap->wp_count == 0) | |
1079 | return 0; | |
1080 | ||
1081 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1082 | range covered by a watchpoint. */ | |
1083 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1084 | aligned_addr = addr & ~(max_wp_length - 1); | |
1085 | ||
1086 | if (aligned_addr + max_wp_length < addr + len) | |
1087 | return 0; | |
1088 | ||
1089 | /* The current ptrace interface can only handle watchpoints that are a | |
1090 | power of 2. */ | |
1091 | if ((len & (len - 1)) != 0) | |
1092 | return 0; | |
1093 | ||
1094 | /* All tests passed so we must be able to set a watchpoint. */ | |
1095 | return 1; | |
1096 | } | |
1097 | ||
1098 | /* Insert a Hardware breakpoint. */ | |
1099 | static int | |
7bb99c53 | 1100 | arm_linux_insert_watchpoint (struct target_ops *self, |
f486487f SM |
1101 | CORE_ADDR addr, int len, |
1102 | enum target_hw_bp_type rw, | |
e3039479 UW |
1103 | struct expression *cond) |
1104 | { | |
e3039479 UW |
1105 | struct lwp_info *lp; |
1106 | struct arm_linux_hw_breakpoint p; | |
1107 | ||
1108 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1109 | return -1; | |
1110 | ||
1111 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1112 | |
1113 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1114 | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | /* Remove a hardware breakpoint. */ | |
1119 | static int | |
8156fe7f YQ |
1120 | arm_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr, |
1121 | int len, enum target_hw_bp_type rw, | |
e3039479 UW |
1122 | struct expression *cond) |
1123 | { | |
e3039479 UW |
1124 | struct lwp_info *lp; |
1125 | struct arm_linux_hw_breakpoint p; | |
1126 | ||
1127 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1128 | return -1; | |
1129 | ||
1130 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1131 | |
1132 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1133 | |
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | /* What was the data address the target was stopped on accessing. */ | |
1138 | static int | |
1139 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1140 | { | |
f865ee35 JK |
1141 | siginfo_t siginfo; |
1142 | int slot; | |
1143 | ||
1144 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1145 | return 0; | |
e3039479 UW |
1146 | |
1147 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1148 | if (siginfo.si_signo != SIGTRAP |
1149 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1150 | return 0; |
1151 | ||
1152 | /* We must be able to set hardware watchpoints. */ | |
1153 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1154 | return 0; | |
1155 | ||
f865ee35 JK |
1156 | slot = siginfo.si_errno; |
1157 | ||
e3039479 UW |
1158 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1159 | a watchpoint. */ | |
1160 | if (slot >= 0) | |
1161 | return 0; | |
1162 | ||
f865ee35 | 1163 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1164 | return 1; |
1165 | } | |
1166 | ||
1167 | /* Has the target been stopped by hitting a watchpoint? */ | |
1168 | static int | |
6a109b6b | 1169 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1170 | { |
1171 | CORE_ADDR addr; | |
6a109b6b | 1172 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1173 | } |
1174 | ||
1175 | static int | |
1176 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1177 | CORE_ADDR addr, | |
1178 | CORE_ADDR start, int length) | |
1179 | { | |
1180 | return start <= addr && start + length - 1 >= addr; | |
1181 | } | |
1182 | ||
1183 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1184 | in the parent thread to the child thread. */ | |
1185 | static void | |
7b50312a | 1186 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1187 | { |
638c5f49 OJ |
1188 | int i; |
1189 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1190 | ||
1191 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1192 | for this thread need to be initialized. */ | |
e3039479 | 1193 | |
638c5f49 | 1194 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1195 | { |
638c5f49 OJ |
1196 | info->bpts_changed[i] = 1; |
1197 | info->wpts_changed[i] = 1; | |
e3039479 | 1198 | } |
638c5f49 OJ |
1199 | |
1200 | lp->arch_private = info; | |
e3039479 UW |
1201 | } |
1202 | ||
638c5f49 OJ |
1203 | /* Called when resuming a thread. |
1204 | The hardware debug registers are updated when there is any change. */ | |
1205 | ||
e3039479 | 1206 | static void |
638c5f49 | 1207 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1208 | { |
638c5f49 OJ |
1209 | int pid, i; |
1210 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1211 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1212 | ||
1213 | pid = ptid_get_lwp (lwp->ptid); | |
1214 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1215 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1216 | ||
1217 | /* NULL means this is the main thread still going through the shell, | |
1218 | or, no watchpoint has been set yet. In that case, there's | |
1219 | nothing to do. */ | |
1220 | if (arm_lwp_info == NULL) | |
1221 | return; | |
e3039479 | 1222 | |
638c5f49 OJ |
1223 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1224 | if (arm_lwp_info->bpts_changed[i]) | |
1225 | { | |
1226 | errno = 0; | |
1227 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1228 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1229 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1230 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1231 | ||
1232 | if (bpts[i].control != 0) | |
1233 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1234 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1235 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1236 | ||
1237 | arm_lwp_info->bpts_changed[i] = 0; | |
1238 | } | |
e3039479 | 1239 | |
638c5f49 OJ |
1240 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1241 | if (arm_lwp_info->wpts_changed[i]) | |
1242 | { | |
1243 | errno = 0; | |
1244 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1245 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1246 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1247 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1248 | ||
1249 | if (wpts[i].control != 0) | |
1250 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1251 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1252 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1253 | ||
1254 | arm_lwp_info->wpts_changed[i] = 0; | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | /* linux_nat_new_fork hook. */ | |
1259 | ||
1260 | static void | |
1261 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1262 | { | |
1263 | pid_t parent_pid; | |
1264 | struct arm_linux_debug_reg_state *parent_state; | |
1265 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1266 | |
638c5f49 OJ |
1267 | /* NULL means no watchpoint has ever been set in the parent. In |
1268 | that case, there's nothing to do. */ | |
1269 | if (parent->arch_private == NULL) | |
1270 | return; | |
e3039479 | 1271 | |
638c5f49 OJ |
1272 | /* GDB core assumes the child inherits the watchpoints/hw |
1273 | breakpoints of the parent, and will remove them all from the | |
1274 | forked off process. Copy the debug registers mirrors into the | |
1275 | new process so that all breakpoints and watchpoints can be | |
1276 | removed together. */ | |
e3039479 | 1277 | |
638c5f49 OJ |
1278 | parent_pid = ptid_get_pid (parent->ptid); |
1279 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1280 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1281 | *child_state = *parent_state; | |
e3039479 UW |
1282 | } |
1283 | ||
10d6c8cd DJ |
1284 | void _initialize_arm_linux_nat (void); |
1285 | ||
ed9a39eb JM |
1286 | void |
1287 | _initialize_arm_linux_nat (void) | |
1288 | { | |
10d6c8cd DJ |
1289 | struct target_ops *t; |
1290 | ||
10d6c8cd DJ |
1291 | /* Fill in the generic GNU/Linux methods. */ |
1292 | t = linux_target (); | |
1293 | ||
1294 | /* Add our register access methods. */ | |
1295 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1296 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1297 | ||
e3039479 UW |
1298 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1299 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1300 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1301 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1302 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1303 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1304 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1305 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1306 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1307 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1308 | ||
81adfced | 1309 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1310 | |
10d6c8cd | 1311 | /* Register the target. */ |
f973ed9c | 1312 | linux_nat_add_target (t); |
e3039479 | 1313 | |
638c5f49 | 1314 | /* Handle thread creation and exit. */ |
e3039479 | 1315 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1316 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1317 | ||
1318 | /* Handle process creation and exit. */ | |
1319 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1320 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1321 | } |