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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
32d0add0 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
f1b67888 | 32 | #include "aarch32-linux-nat.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb JM |
35 | #include <sys/user.h> |
36 | #include <sys/ptrace.h> | |
37 | #include <sys/utsname.h> | |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
95855ca8 MS |
40 | #include "nat/linux-ptrace.h" |
41 | ||
0963b4bd | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
43 | #include "gregset.h" |
44 | ||
9308fc88 DJ |
45 | /* Defines ps_err_e, struct ps_prochandle. */ |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
05a4558a DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
3b273a55 RE |
57 | #ifndef PTRACE_GETVFPREGS |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
e3039479 UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
ed9a39eb JM |
67 | extern int arm_apcs_32; |
68 | ||
fdf39c9a | 69 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
41c49b06 | 70 | case we may be tracing more than one process at a time. In that |
39f77062 | 71 | case, inferior_ptid will contain the main process ID and the |
fdf39c9a RE |
72 | individual thread (process) ID. get_thread_id () is used to get |
73 | the thread id if it's available, and the process id otherwise. */ | |
41c49b06 | 74 | |
4e841acf | 75 | static int |
39f77062 | 76 | get_thread_id (ptid_t ptid) |
41c49b06 | 77 | { |
dfd4cc63 | 78 | int tid = ptid_get_lwp (ptid); |
39f77062 | 79 | if (0 == tid) |
dfd4cc63 | 80 | tid = ptid_get_pid (ptid); |
41c49b06 SB |
81 | return tid; |
82 | } | |
3b273a55 | 83 | |
05a4558a | 84 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) |
41c49b06 | 85 | |
41c49b06 | 86 | /* Get the whole floating point state of the process and store it |
c6b92abd | 87 | into regcache. */ |
ed9a39eb JM |
88 | |
89 | static void | |
56be3814 | 90 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 91 | { |
41c49b06 | 92 | int ret, regno, tid; |
cb587d83 | 93 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 94 | |
41c49b06 | 95 | /* Get the thread id for the ptrace call. */ |
39f77062 | 96 | tid = GET_THREAD_ID (inferior_ptid); |
df9d7ec9 | 97 | |
ed9a39eb | 98 | /* Read the floating point state. */ |
0bdb2f78 | 99 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
100 | { |
101 | struct iovec iov; | |
102 | ||
103 | iov.iov_base = &fp; | |
104 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
105 | ||
106 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
107 | } | |
108 | else | |
109 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
110 | ||
ed9a39eb JM |
111 | if (ret < 0) |
112 | { | |
edefbb7c | 113 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
114 | return; |
115 | } | |
116 | ||
117 | /* Fetch fpsr. */ | |
56be3814 | 118 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 119 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
120 | |
121 | /* Fetch the floating point registers. */ | |
34e8f22d | 122 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 123 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
124 | } |
125 | ||
126 | /* Save the whole floating point state of the process using | |
c6b92abd | 127 | the contents from regcache. */ |
ed9a39eb JM |
128 | |
129 | static void | |
56be3814 | 130 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 131 | { |
41c49b06 | 132 | int ret, regno, tid; |
cb587d83 | 133 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 134 | |
41c49b06 | 135 | /* Get the thread id for the ptrace call. */ |
39f77062 | 136 | tid = GET_THREAD_ID (inferior_ptid); |
df9d7ec9 | 137 | |
41c49b06 | 138 | /* Read the floating point state. */ |
0bdb2f78 | 139 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
140 | { |
141 | elf_fpregset_t fpregs; | |
142 | struct iovec iov; | |
143 | ||
144 | iov.iov_base = &fpregs; | |
145 | iov.iov_len = sizeof (fpregs); | |
146 | ||
147 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
148 | } | |
149 | else | |
150 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
151 | ||
41c49b06 SB |
152 | if (ret < 0) |
153 | { | |
edefbb7c | 154 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
155 | return; |
156 | } | |
157 | ||
ed9a39eb | 158 | /* Store fpsr. */ |
672c9795 | 159 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 160 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
161 | |
162 | /* Store the floating point registers. */ | |
34e8f22d | 163 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 164 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 165 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 166 | |
0bdb2f78 | 167 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
168 | { |
169 | struct iovec iov; | |
170 | ||
171 | iov.iov_base = &fp; | |
172 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
173 | ||
174 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
175 | } | |
176 | else | |
177 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
178 | ||
ed9a39eb JM |
179 | if (ret < 0) |
180 | { | |
edefbb7c | 181 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
182 | return; |
183 | } | |
184 | } | |
185 | ||
186 | /* Fetch all general registers of the process and store into | |
c6b92abd | 187 | regcache. */ |
ed9a39eb JM |
188 | |
189 | static void | |
56be3814 | 190 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 191 | { |
41c49b06 | 192 | int ret, regno, tid; |
c2152441 | 193 | elf_gregset_t regs; |
ed9a39eb | 194 | |
41c49b06 | 195 | /* Get the thread id for the ptrace call. */ |
39f77062 | 196 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 197 | |
0bdb2f78 | 198 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
199 | { |
200 | struct iovec iov; | |
201 | ||
202 | iov.iov_base = ®s; | |
203 | iov.iov_len = sizeof (regs); | |
204 | ||
205 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
206 | } | |
207 | else | |
208 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
209 | ||
ed9a39eb JM |
210 | if (ret < 0) |
211 | { | |
edefbb7c | 212 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
213 | return; |
214 | } | |
215 | ||
f1b67888 | 216 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
217 | } |
218 | ||
ed9a39eb | 219 | static void |
56be3814 | 220 | store_regs (const struct regcache *regcache) |
ed9a39eb | 221 | { |
41c49b06 | 222 | int ret, regno, tid; |
c2152441 | 223 | elf_gregset_t regs; |
ed9a39eb | 224 | |
41c49b06 | 225 | /* Get the thread id for the ptrace call. */ |
39f77062 | 226 | tid = GET_THREAD_ID (inferior_ptid); |
10766686 | 227 | |
41c49b06 | 228 | /* Fetch the general registers. */ |
0bdb2f78 | 229 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
230 | { |
231 | struct iovec iov; | |
232 | ||
233 | iov.iov_base = ®s; | |
234 | iov.iov_len = sizeof (regs); | |
235 | ||
236 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
237 | } | |
238 | else | |
239 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
240 | ||
ed9a39eb JM |
241 | if (ret < 0) |
242 | { | |
edefbb7c | 243 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
244 | return; |
245 | } | |
246 | ||
f1b67888 | 247 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 248 | |
0bdb2f78 | 249 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
250 | { |
251 | struct iovec iov; | |
252 | ||
253 | iov.iov_base = ®s; | |
254 | iov.iov_len = sizeof (regs); | |
255 | ||
256 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
257 | } | |
258 | else | |
259 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
260 | |
261 | if (ret < 0) | |
262 | { | |
edefbb7c | 263 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
264 | return; |
265 | } | |
266 | } | |
267 | ||
05a4558a DJ |
268 | /* Fetch all WMMX registers of the process and store into |
269 | regcache. */ | |
270 | ||
271 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
272 | ||
273 | static void | |
56be3814 | 274 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
275 | { |
276 | char regbuf[IWMMXT_REGS_SIZE]; | |
277 | int ret, regno, tid; | |
278 | ||
279 | /* Get the thread id for the ptrace call. */ | |
280 | tid = GET_THREAD_ID (inferior_ptid); | |
281 | ||
282 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
283 | if (ret < 0) | |
284 | { | |
285 | warning (_("Unable to fetch WMMX registers.")); | |
286 | return; | |
287 | } | |
288 | ||
289 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 290 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
291 | ®buf[regno * 8]); |
292 | ||
293 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 294 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
295 | ®buf[16 * 8 + regno * 4]); |
296 | ||
297 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 298 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
299 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
300 | } | |
301 | ||
302 | static void | |
56be3814 | 303 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
304 | { |
305 | char regbuf[IWMMXT_REGS_SIZE]; | |
306 | int ret, regno, tid; | |
307 | ||
308 | /* Get the thread id for the ptrace call. */ | |
309 | tid = GET_THREAD_ID (inferior_ptid); | |
310 | ||
311 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
312 | if (ret < 0) | |
313 | { | |
314 | warning (_("Unable to fetch WMMX registers.")); | |
315 | return; | |
316 | } | |
317 | ||
318 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
319 | if (REG_VALID == regcache_register_status (regcache, |
320 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 321 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
322 | ®buf[regno * 8]); |
323 | ||
324 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
325 | if (REG_VALID == regcache_register_status (regcache, |
326 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 327 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
328 | ®buf[16 * 8 + regno * 4]); |
329 | ||
330 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
331 | if (REG_VALID == regcache_register_status (regcache, |
332 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 333 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
334 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
335 | ||
336 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
337 | ||
338 | if (ret < 0) | |
339 | { | |
340 | warning (_("Unable to store WMMX registers.")); | |
341 | return; | |
342 | } | |
343 | } | |
344 | ||
3b273a55 RE |
345 | static void |
346 | fetch_vfp_regs (struct regcache *regcache) | |
347 | { | |
f1b67888 | 348 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 349 | int ret, regno, tid; |
330c6ca9 YQ |
350 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
351 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
352 | |
353 | /* Get the thread id for the ptrace call. */ | |
354 | tid = GET_THREAD_ID (inferior_ptid); | |
355 | ||
0bdb2f78 | 356 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
357 | { |
358 | struct iovec iov; | |
359 | ||
360 | iov.iov_base = regbuf; | |
361 | iov.iov_len = VFP_REGS_SIZE; | |
362 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
363 | } | |
364 | else | |
365 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
366 | ||
3b273a55 RE |
367 | if (ret < 0) |
368 | { | |
369 | warning (_("Unable to fetch VFP registers.")); | |
370 | return; | |
371 | } | |
372 | ||
f1b67888 YQ |
373 | aarch32_vfp_regcache_supply (regcache, regbuf, |
374 | tdep->vfp_register_count); | |
3b273a55 RE |
375 | } |
376 | ||
377 | static void | |
378 | store_vfp_regs (const struct regcache *regcache) | |
379 | { | |
f1b67888 | 380 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 381 | int ret, regno, tid; |
330c6ca9 YQ |
382 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
383 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
384 | |
385 | /* Get the thread id for the ptrace call. */ | |
386 | tid = GET_THREAD_ID (inferior_ptid); | |
387 | ||
0bdb2f78 | 388 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
389 | { |
390 | struct iovec iov; | |
391 | ||
392 | iov.iov_base = regbuf; | |
393 | iov.iov_len = VFP_REGS_SIZE; | |
394 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
395 | } | |
396 | else | |
397 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
398 | ||
3b273a55 RE |
399 | if (ret < 0) |
400 | { | |
401 | warning (_("Unable to fetch VFP registers (for update).")); | |
402 | return; | |
403 | } | |
404 | ||
f1b67888 YQ |
405 | aarch32_vfp_regcache_collect (regcache, regbuf, |
406 | tdep->vfp_register_count); | |
3b273a55 | 407 | |
0bdb2f78 | 408 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
409 | { |
410 | struct iovec iov; | |
411 | ||
412 | iov.iov_base = regbuf; | |
413 | iov.iov_len = VFP_REGS_SIZE; | |
414 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
415 | } | |
416 | else | |
417 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
418 | |
419 | if (ret < 0) | |
420 | { | |
421 | warning (_("Unable to store VFP registers.")); | |
422 | return; | |
423 | } | |
424 | } | |
425 | ||
ed9a39eb JM |
426 | /* Fetch registers from the child process. Fetch all registers if |
427 | regno == -1, otherwise fetch all general registers or all floating | |
428 | point registers depending upon the value of regno. */ | |
429 | ||
10d6c8cd | 430 | static void |
28439f5e PA |
431 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
432 | struct regcache *regcache, int regno) | |
ed9a39eb | 433 | { |
330c6ca9 YQ |
434 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
435 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
436 | ||
41c49b06 SB |
437 | if (-1 == regno) |
438 | { | |
56be3814 UW |
439 | fetch_regs (regcache); |
440 | fetch_fpregs (regcache); | |
a56cc1ce | 441 | if (tdep->have_wmmx_registers) |
56be3814 | 442 | fetch_wmmx_regs (regcache); |
330c6ca9 | 443 | if (tdep->vfp_register_count > 0) |
3b273a55 | 444 | fetch_vfp_regs (regcache); |
41c49b06 SB |
445 | } |
446 | else | |
447 | { | |
05a4558a | 448 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 449 | fetch_regs (regcache); |
05a4558a | 450 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 451 | fetch_fpregs (regcache); |
a56cc1ce | 452 | else if (tdep->have_wmmx_registers |
05a4558a | 453 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 454 | fetch_wmmx_regs (regcache); |
330c6ca9 | 455 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 456 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 457 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 458 | fetch_vfp_regs (regcache); |
41c49b06 | 459 | } |
ed9a39eb JM |
460 | } |
461 | ||
462 | /* Store registers back into the inferior. Store all registers if | |
463 | regno == -1, otherwise store all general registers or all floating | |
464 | point registers depending upon the value of regno. */ | |
465 | ||
10d6c8cd | 466 | static void |
28439f5e PA |
467 | arm_linux_store_inferior_registers (struct target_ops *ops, |
468 | struct regcache *regcache, int regno) | |
ed9a39eb | 469 | { |
330c6ca9 YQ |
470 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
471 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
472 | ||
41c49b06 SB |
473 | if (-1 == regno) |
474 | { | |
56be3814 UW |
475 | store_regs (regcache); |
476 | store_fpregs (regcache); | |
a56cc1ce | 477 | if (tdep->have_wmmx_registers) |
56be3814 | 478 | store_wmmx_regs (regcache); |
330c6ca9 | 479 | if (tdep->vfp_register_count > 0) |
3b273a55 | 480 | store_vfp_regs (regcache); |
41c49b06 SB |
481 | } |
482 | else | |
483 | { | |
05a4558a | 484 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 485 | store_regs (regcache); |
05a4558a | 486 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 487 | store_fpregs (regcache); |
a56cc1ce | 488 | else if (tdep->have_wmmx_registers |
05a4558a | 489 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 490 | store_wmmx_regs (regcache); |
330c6ca9 | 491 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 492 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 493 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 494 | store_vfp_regs (regcache); |
41c49b06 | 495 | } |
ed9a39eb JM |
496 | } |
497 | ||
cb587d83 DJ |
498 | /* Wrapper functions for the standard regset handling, used by |
499 | thread debugging. */ | |
41c49b06 SB |
500 | |
501 | void | |
7f7fe91e UW |
502 | fill_gregset (const struct regcache *regcache, |
503 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 504 | { |
7f7fe91e | 505 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
506 | } |
507 | ||
41c49b06 | 508 | void |
7f7fe91e | 509 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 510 | { |
7f7fe91e | 511 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
512 | } |
513 | ||
41c49b06 | 514 | void |
7f7fe91e UW |
515 | fill_fpregset (const struct regcache *regcache, |
516 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 517 | { |
7f7fe91e | 518 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
519 | } |
520 | ||
521 | /* Fill GDB's register array with the floating-point register values | |
522 | in *fpregsetp. */ | |
523 | ||
524 | void | |
7f7fe91e | 525 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 526 | { |
7f7fe91e | 527 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
528 | } |
529 | ||
9308fc88 DJ |
530 | /* Fetch the thread-local storage pointer for libthread_db. */ |
531 | ||
532 | ps_err_e | |
533 | ps_get_thread_area (const struct ps_prochandle *ph, | |
534 | lwpid_t lwpid, int idx, void **base) | |
535 | { | |
536 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
537 | return PS_ERR; | |
538 | ||
539 | /* IDX is the bias from the thread pointer to the beginning of the | |
540 | thread descriptor. It has to be subtracted due to implementation | |
541 | quirks in libthread_db. */ | |
542 | *base = (void *) ((char *)*base - idx); | |
543 | ||
544 | return PS_OK; | |
545 | } | |
546 | ||
81adfced DJ |
547 | static const struct target_desc * |
548 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 549 | { |
3b273a55 | 550 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 551 | |
0bdb2f78 | 552 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
553 | { |
554 | elf_gregset_t gpregs; | |
555 | struct iovec iov; | |
556 | int tid = GET_THREAD_ID (inferior_ptid); | |
557 | ||
558 | iov.iov_base = &gpregs; | |
559 | iov.iov_len = sizeof (gpregs); | |
560 | ||
561 | /* Check if PTRACE_GETREGSET works. */ | |
562 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 563 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 564 | else |
0bdb2f78 | 565 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
566 | } |
567 | ||
3b273a55 RE |
568 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
569 | { | |
2117c711 | 570 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 571 | } |
81adfced | 572 | |
3b273a55 | 573 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 574 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
575 | |
576 | if (arm_hwcap & HWCAP_VFP) | |
577 | { | |
578 | int pid; | |
579 | char *buf; | |
580 | const struct target_desc * result = NULL; | |
581 | ||
582 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
583 | Neon with VFPv3-D32. */ | |
584 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 585 | result = tdesc_arm_with_neon; |
3b273a55 | 586 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 587 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 588 | else |
330c6ca9 | 589 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
590 | |
591 | /* Now make sure that the kernel supports reading these | |
592 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 593 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
594 | errno = 0; |
595 | buf = alloca (VFP_REGS_SIZE); | |
596 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
597 | && errno == EIO) | |
598 | result = NULL; | |
599 | ||
600 | return result; | |
601 | } | |
602 | ||
2117c711 | 603 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
604 | } |
605 | ||
e3039479 UW |
606 | /* Information describing the hardware breakpoint capabilities. */ |
607 | struct arm_linux_hwbp_cap | |
608 | { | |
609 | gdb_byte arch; | |
610 | gdb_byte max_wp_length; | |
611 | gdb_byte wp_count; | |
612 | gdb_byte bp_count; | |
613 | }; | |
614 | ||
638c5f49 OJ |
615 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
616 | assume a maximum number of supported break-/watchpoints. */ | |
617 | #define MAX_BPTS 16 | |
618 | #define MAX_WPTS 16 | |
619 | ||
e3039479 UW |
620 | /* Get hold of the Hardware Breakpoint information for the target we are |
621 | attached to. Returns NULL if the kernel doesn't support Hardware | |
622 | breakpoints at all, or a pointer to the information structure. */ | |
623 | static const struct arm_linux_hwbp_cap * | |
624 | arm_linux_get_hwbp_cap (void) | |
625 | { | |
626 | /* The info structure we return. */ | |
627 | static struct arm_linux_hwbp_cap info; | |
628 | ||
629 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
630 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
631 | means INFO is in an initialized state. */ | |
632 | static int available = -1; | |
633 | ||
634 | if (available == -1) | |
635 | { | |
636 | int tid; | |
637 | unsigned int val; | |
638 | ||
639 | tid = GET_THREAD_ID (inferior_ptid); | |
640 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
641 | available = 0; | |
642 | else | |
643 | { | |
644 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
645 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
646 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
647 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
648 | |
649 | if (info.wp_count > MAX_WPTS) | |
650 | { | |
651 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
652 | supports %d"), MAX_WPTS, info.wp_count); | |
653 | info.wp_count = MAX_WPTS; | |
654 | } | |
655 | ||
656 | if (info.bp_count > MAX_BPTS) | |
657 | { | |
658 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
659 | supports %d"), MAX_BPTS, info.bp_count); | |
660 | info.bp_count = MAX_BPTS; | |
661 | } | |
e3039479 UW |
662 | available = (info.arch != 0); |
663 | } | |
664 | } | |
665 | ||
666 | return available == 1 ? &info : NULL; | |
667 | } | |
668 | ||
669 | /* How many hardware breakpoints are available? */ | |
670 | static int | |
671 | arm_linux_get_hw_breakpoint_count (void) | |
672 | { | |
673 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
674 | return cap != NULL ? cap->bp_count : 0; | |
675 | } | |
676 | ||
677 | /* How many hardware watchpoints are available? */ | |
678 | static int | |
679 | arm_linux_get_hw_watchpoint_count (void) | |
680 | { | |
681 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
682 | return cap != NULL ? cap->wp_count : 0; | |
683 | } | |
684 | ||
685 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
686 | there is not an appropriate resource available, otherwise returns 1. */ | |
687 | static int | |
5461485a TT |
688 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
689 | int type, int cnt, int ot) | |
e3039479 UW |
690 | { |
691 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
692 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
693 | { | |
dbbf180a YQ |
694 | int count = arm_linux_get_hw_watchpoint_count (); |
695 | ||
696 | if (count == 0) | |
697 | return 0; | |
698 | else if (cnt + ot > count) | |
e3039479 UW |
699 | return -1; |
700 | } | |
701 | else if (type == bp_hardware_breakpoint) | |
702 | { | |
dbbf180a YQ |
703 | int count = arm_linux_get_hw_breakpoint_count (); |
704 | ||
705 | if (count == 0) | |
706 | return 0; | |
707 | else if (cnt > count) | |
e3039479 UW |
708 | return -1; |
709 | } | |
710 | else | |
711 | gdb_assert (FALSE); | |
712 | ||
713 | return 1; | |
714 | } | |
715 | ||
716 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
717 | typedef enum | |
718 | { | |
719 | arm_hwbp_break = 0, | |
720 | arm_hwbp_load = 1, | |
721 | arm_hwbp_store = 2, | |
722 | arm_hwbp_access = 3 | |
723 | } arm_hwbp_type; | |
724 | ||
725 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
726 | typedef unsigned int arm_hwbp_control_t; | |
727 | ||
728 | /* Structure used to keep track of hardware break-/watch-points. */ | |
729 | struct arm_linux_hw_breakpoint | |
730 | { | |
731 | /* Address to break on, or being watched. */ | |
732 | unsigned int address; | |
733 | /* Control register for break-/watch- point. */ | |
734 | arm_hwbp_control_t control; | |
735 | }; | |
736 | ||
638c5f49 OJ |
737 | /* Structure containing arrays of per process hardware break-/watchpoints |
738 | for caching address and control information. | |
e3039479 UW |
739 | |
740 | The Linux ptrace interface to hardware break-/watch-points presents the | |
741 | values in a vector centred around 0 (which is used fo generic information). | |
742 | Positive indicies refer to breakpoint addresses/control registers, negative | |
743 | indices to watchpoint addresses/control registers. | |
744 | ||
745 | The Linux vector is indexed as follows: | |
746 | -((i << 1) + 2): Control register for watchpoint i. | |
747 | -((i << 1) + 1): Address register for watchpoint i. | |
748 | 0: Information register. | |
749 | ((i << 1) + 1): Address register for breakpoint i. | |
750 | ((i << 1) + 2): Control register for breakpoint i. | |
751 | ||
752 | This structure is used as a per-thread cache of the state stored by the | |
753 | kernel, so that we don't need to keep calling into the kernel to find a | |
754 | free breakpoint. | |
755 | ||
756 | We treat break-/watch-points with their enable bit clear as being deleted. | |
757 | */ | |
638c5f49 | 758 | struct arm_linux_debug_reg_state |
e3039479 | 759 | { |
638c5f49 OJ |
760 | /* Hardware breakpoints for this process. */ |
761 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
762 | /* Hardware watchpoints for this process. */ | |
763 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
764 | }; | |
765 | ||
766 | /* Per-process arch-specific data we want to keep. */ | |
767 | struct arm_linux_process_info | |
e3039479 | 768 | { |
638c5f49 OJ |
769 | /* Linked list. */ |
770 | struct arm_linux_process_info *next; | |
771 | /* The process identifier. */ | |
772 | pid_t pid; | |
773 | /* Hardware break-/watchpoints state information. */ | |
774 | struct arm_linux_debug_reg_state state; | |
e3039479 | 775 | |
638c5f49 OJ |
776 | }; |
777 | ||
778 | /* Per-thread arch-specific data we want to keep. */ | |
779 | struct arch_lwp_info | |
780 | { | |
781 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
782 | char bpts_changed[MAX_BPTS]; | |
783 | char wpts_changed[MAX_WPTS]; | |
784 | }; | |
785 | ||
786 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
787 | ||
788 | /* Find process data for process PID. */ | |
789 | ||
790 | static struct arm_linux_process_info * | |
791 | arm_linux_find_process_pid (pid_t pid) | |
792 | { | |
793 | struct arm_linux_process_info *proc; | |
794 | ||
795 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
796 | if (proc->pid == pid) | |
797 | return proc; | |
798 | ||
799 | return NULL; | |
800 | } | |
801 | ||
802 | /* Add process data for process PID. Returns newly allocated info | |
803 | object. */ | |
804 | ||
805 | static struct arm_linux_process_info * | |
806 | arm_linux_add_process (pid_t pid) | |
807 | { | |
808 | struct arm_linux_process_info *proc; | |
e3039479 | 809 | |
638c5f49 OJ |
810 | proc = xcalloc (1, sizeof (*proc)); |
811 | proc->pid = pid; | |
e3039479 | 812 | |
638c5f49 OJ |
813 | proc->next = arm_linux_process_list; |
814 | arm_linux_process_list = proc; | |
815 | ||
816 | return proc; | |
817 | } | |
818 | ||
819 | /* Get data specific info for process PID, creating it if necessary. | |
820 | Never returns NULL. */ | |
821 | ||
822 | static struct arm_linux_process_info * | |
823 | arm_linux_process_info_get (pid_t pid) | |
824 | { | |
825 | struct arm_linux_process_info *proc; | |
826 | ||
827 | proc = arm_linux_find_process_pid (pid); | |
828 | if (proc == NULL) | |
829 | proc = arm_linux_add_process (pid); | |
830 | ||
831 | return proc; | |
832 | } | |
833 | ||
834 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
835 | data structures that keep track of debug register state. */ | |
836 | ||
837 | static void | |
838 | arm_linux_forget_process (pid_t pid) | |
839 | { | |
840 | struct arm_linux_process_info *proc, **proc_link; | |
841 | ||
842 | proc = arm_linux_process_list; | |
843 | proc_link = &arm_linux_process_list; | |
844 | ||
845 | while (proc != NULL) | |
846 | { | |
847 | if (proc->pid == pid) | |
e3039479 | 848 | { |
638c5f49 OJ |
849 | *proc_link = proc->next; |
850 | ||
851 | xfree (proc); | |
852 | return; | |
e3039479 UW |
853 | } |
854 | ||
638c5f49 OJ |
855 | proc_link = &proc->next; |
856 | proc = *proc_link; | |
857 | } | |
858 | } | |
859 | ||
860 | /* Get hardware break-/watchpoint state for process PID. */ | |
861 | ||
862 | static struct arm_linux_debug_reg_state * | |
863 | arm_linux_get_debug_reg_state (pid_t pid) | |
864 | { | |
865 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
866 | } |
867 | ||
868 | /* Initialize an ARM hardware break-/watch-point control register value. | |
869 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
870 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
871 | */ | |
872 | static arm_hwbp_control_t | |
873 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
874 | arm_hwbp_type hwbp_type, | |
875 | int enable) | |
876 | { | |
877 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
878 | gdb_assert (hwbp_type != arm_hwbp_break | |
879 | || ((byte_address_select & 0xfU) != 0)); | |
880 | ||
881 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
882 | } | |
883 | ||
884 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
885 | static int | |
886 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
887 | { | |
888 | return control & 0x1; | |
889 | } | |
890 | ||
891 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
892 | static arm_hwbp_control_t | |
893 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
894 | { | |
895 | return control & ~0x1; | |
896 | } | |
897 | ||
898 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
899 | enabled, and will point to the placed address of BP_TGT. */ | |
900 | static void | |
901 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
902 | struct bp_target_info *bp_tgt, | |
903 | struct arm_linux_hw_breakpoint *p) | |
904 | { | |
905 | unsigned mask; | |
0d5ed153 | 906 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
907 | |
908 | /* We have to create a mask for the control register which says which bits | |
909 | of the word pointed to by address to break on. */ | |
910 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
911 | { |
912 | mask = 0x3; | |
913 | address &= ~1; | |
914 | } | |
e3039479 | 915 | else |
fcf303ab UW |
916 | { |
917 | mask = 0xf; | |
918 | address &= ~3; | |
919 | } | |
e3039479 | 920 | |
fcf303ab | 921 | p->address = (unsigned int) address; |
e3039479 UW |
922 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
923 | } | |
924 | ||
925 | /* Get the ARM hardware breakpoint type from the RW value we're given when | |
926 | asked to set a watchpoint. */ | |
927 | static arm_hwbp_type | |
928 | arm_linux_get_hwbp_type (int rw) | |
929 | { | |
930 | if (rw == hw_read) | |
931 | return arm_hwbp_load; | |
932 | else if (rw == hw_write) | |
933 | return arm_hwbp_store; | |
934 | else | |
935 | return arm_hwbp_access; | |
936 | } | |
937 | ||
938 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
939 | to LEN. The type of watchpoint is given in RW. */ | |
940 | static void | |
941 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, int rw, | |
942 | struct arm_linux_hw_breakpoint *p) | |
943 | { | |
944 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
945 | unsigned mask; | |
946 | ||
947 | gdb_assert (cap != NULL); | |
948 | gdb_assert (cap->max_wp_length != 0); | |
949 | ||
950 | mask = (1 << len) - 1; | |
951 | ||
952 | p->address = (unsigned int) addr; | |
953 | p->control = arm_hwbp_control_initialize (mask, | |
954 | arm_linux_get_hwbp_type (rw), 1); | |
955 | } | |
956 | ||
957 | /* Are two break-/watch-points equal? */ | |
958 | static int | |
959 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
960 | const struct arm_linux_hw_breakpoint *p2) | |
961 | { | |
962 | return p1->address == p2->address && p1->control == p2->control; | |
963 | } | |
964 | ||
638c5f49 OJ |
965 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
966 | the current process. */ | |
967 | ||
968 | struct update_registers_data | |
969 | { | |
970 | int watch; | |
971 | int index; | |
972 | }; | |
973 | ||
974 | static int | |
975 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
976 | { | |
977 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
978 | ||
979 | if (lwp->arch_private == NULL) | |
980 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
981 | ||
982 | /* The actual update is done later just before resuming the lwp, | |
983 | we just mark that the registers need updating. */ | |
984 | if (data->watch) | |
985 | lwp->arch_private->wpts_changed[data->index] = 1; | |
986 | else | |
987 | lwp->arch_private->bpts_changed[data->index] = 1; | |
988 | ||
989 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
990 | we can update its breakpoint registers. */ | |
991 | if (!lwp->stopped) | |
992 | linux_stop_lwp (lwp); | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
e3039479 UW |
997 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
998 | =1) BPT for thread TID. */ | |
999 | static void | |
1000 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 1001 | int watchpoint) |
e3039479 | 1002 | { |
638c5f49 OJ |
1003 | int pid; |
1004 | ptid_t pid_ptid; | |
e3039479 UW |
1005 | gdb_byte count, i; |
1006 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1007 | struct update_registers_data data; |
e3039479 | 1008 | |
638c5f49 OJ |
1009 | pid = ptid_get_pid (inferior_ptid); |
1010 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1011 | |
1012 | if (watchpoint) | |
1013 | { | |
1014 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1015 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1016 | } |
1017 | else | |
1018 | { | |
1019 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1020 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1021 | } |
1022 | ||
1023 | for (i = 0; i < count; ++i) | |
1024 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1025 | { | |
638c5f49 OJ |
1026 | data.watch = watchpoint; |
1027 | data.index = i; | |
1028 | bpts[i] = *bpt; | |
1029 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1030 | break; | |
e3039479 UW |
1031 | } |
1032 | ||
1033 | gdb_assert (i != count); | |
1034 | } | |
1035 | ||
1036 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1037 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1038 | static void | |
1039 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1040 | int watchpoint) |
e3039479 | 1041 | { |
638c5f49 | 1042 | int pid; |
e3039479 | 1043 | gdb_byte count, i; |
638c5f49 OJ |
1044 | ptid_t pid_ptid; |
1045 | struct arm_linux_hw_breakpoint* bpts; | |
1046 | struct update_registers_data data; | |
e3039479 | 1047 | |
638c5f49 OJ |
1048 | pid = ptid_get_pid (inferior_ptid); |
1049 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1050 | |
1051 | if (watchpoint) | |
1052 | { | |
1053 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1054 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1055 | } |
1056 | else | |
1057 | { | |
1058 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1059 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1060 | } |
1061 | ||
1062 | for (i = 0; i < count; ++i) | |
1063 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1064 | { | |
638c5f49 OJ |
1065 | data.watch = watchpoint; |
1066 | data.index = i; | |
1067 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1068 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1069 | break; | |
e3039479 UW |
1070 | } |
1071 | ||
1072 | gdb_assert (i != count); | |
1073 | } | |
1074 | ||
1075 | /* Insert a Hardware breakpoint. */ | |
1076 | static int | |
23a26771 TT |
1077 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1078 | struct gdbarch *gdbarch, | |
e3039479 UW |
1079 | struct bp_target_info *bp_tgt) |
1080 | { | |
e3039479 UW |
1081 | struct lwp_info *lp; |
1082 | struct arm_linux_hw_breakpoint p; | |
1083 | ||
1084 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1085 | return -1; | |
1086 | ||
1087 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1088 | |
1089 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1090 | |
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /* Remove a hardware breakpoint. */ | |
1095 | static int | |
a64dc96c TT |
1096 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1097 | struct gdbarch *gdbarch, | |
e3039479 UW |
1098 | struct bp_target_info *bp_tgt) |
1099 | { | |
e3039479 UW |
1100 | struct lwp_info *lp; |
1101 | struct arm_linux_hw_breakpoint p; | |
1102 | ||
1103 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1104 | return -1; | |
1105 | ||
1106 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1107 | |
1108 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1109 | |
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1114 | ADDR? */ | |
1115 | static int | |
31568a15 TT |
1116 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1117 | CORE_ADDR addr, int len) | |
e3039479 UW |
1118 | { |
1119 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1120 | CORE_ADDR max_wp_length, aligned_addr; | |
1121 | ||
1122 | /* Can not set watchpoints for zero or negative lengths. */ | |
1123 | if (len <= 0) | |
1124 | return 0; | |
1125 | ||
1126 | /* Need to be able to use the ptrace interface. */ | |
1127 | if (cap == NULL || cap->wp_count == 0) | |
1128 | return 0; | |
1129 | ||
1130 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1131 | range covered by a watchpoint. */ | |
1132 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1133 | aligned_addr = addr & ~(max_wp_length - 1); | |
1134 | ||
1135 | if (aligned_addr + max_wp_length < addr + len) | |
1136 | return 0; | |
1137 | ||
1138 | /* The current ptrace interface can only handle watchpoints that are a | |
1139 | power of 2. */ | |
1140 | if ((len & (len - 1)) != 0) | |
1141 | return 0; | |
1142 | ||
1143 | /* All tests passed so we must be able to set a watchpoint. */ | |
1144 | return 1; | |
1145 | } | |
1146 | ||
1147 | /* Insert a Hardware breakpoint. */ | |
1148 | static int | |
7bb99c53 TT |
1149 | arm_linux_insert_watchpoint (struct target_ops *self, |
1150 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1151 | struct expression *cond) |
1152 | { | |
e3039479 UW |
1153 | struct lwp_info *lp; |
1154 | struct arm_linux_hw_breakpoint p; | |
1155 | ||
1156 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1157 | return -1; | |
1158 | ||
1159 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1160 | |
1161 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1162 | |
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /* Remove a hardware breakpoint. */ | |
1167 | static int | |
11b5219a TT |
1168 | arm_linux_remove_watchpoint (struct target_ops *self, |
1169 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1170 | struct expression *cond) |
1171 | { | |
e3039479 UW |
1172 | struct lwp_info *lp; |
1173 | struct arm_linux_hw_breakpoint p; | |
1174 | ||
1175 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1176 | return -1; | |
1177 | ||
1178 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1179 | |
1180 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1181 | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | /* What was the data address the target was stopped on accessing. */ | |
1186 | static int | |
1187 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1188 | { | |
f865ee35 JK |
1189 | siginfo_t siginfo; |
1190 | int slot; | |
1191 | ||
1192 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1193 | return 0; | |
e3039479 UW |
1194 | |
1195 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1196 | if (siginfo.si_signo != SIGTRAP |
1197 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1198 | return 0; |
1199 | ||
1200 | /* We must be able to set hardware watchpoints. */ | |
1201 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1202 | return 0; | |
1203 | ||
f865ee35 JK |
1204 | slot = siginfo.si_errno; |
1205 | ||
e3039479 UW |
1206 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1207 | a watchpoint. */ | |
1208 | if (slot >= 0) | |
1209 | return 0; | |
1210 | ||
f865ee35 | 1211 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1212 | return 1; |
1213 | } | |
1214 | ||
1215 | /* Has the target been stopped by hitting a watchpoint? */ | |
1216 | static int | |
6a109b6b | 1217 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1218 | { |
1219 | CORE_ADDR addr; | |
6a109b6b | 1220 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1221 | } |
1222 | ||
1223 | static int | |
1224 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1225 | CORE_ADDR addr, | |
1226 | CORE_ADDR start, int length) | |
1227 | { | |
1228 | return start <= addr && start + length - 1 >= addr; | |
1229 | } | |
1230 | ||
1231 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1232 | in the parent thread to the child thread. */ | |
1233 | static void | |
7b50312a | 1234 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1235 | { |
638c5f49 OJ |
1236 | int i; |
1237 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1238 | ||
1239 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1240 | for this thread need to be initialized. */ | |
e3039479 | 1241 | |
638c5f49 | 1242 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1243 | { |
638c5f49 OJ |
1244 | info->bpts_changed[i] = 1; |
1245 | info->wpts_changed[i] = 1; | |
e3039479 | 1246 | } |
638c5f49 OJ |
1247 | |
1248 | lp->arch_private = info; | |
e3039479 UW |
1249 | } |
1250 | ||
638c5f49 OJ |
1251 | /* Called when resuming a thread. |
1252 | The hardware debug registers are updated when there is any change. */ | |
1253 | ||
e3039479 | 1254 | static void |
638c5f49 | 1255 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1256 | { |
638c5f49 OJ |
1257 | int pid, i; |
1258 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1259 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1260 | ||
1261 | pid = ptid_get_lwp (lwp->ptid); | |
1262 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1263 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1264 | ||
1265 | /* NULL means this is the main thread still going through the shell, | |
1266 | or, no watchpoint has been set yet. In that case, there's | |
1267 | nothing to do. */ | |
1268 | if (arm_lwp_info == NULL) | |
1269 | return; | |
e3039479 | 1270 | |
638c5f49 OJ |
1271 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1272 | if (arm_lwp_info->bpts_changed[i]) | |
1273 | { | |
1274 | errno = 0; | |
1275 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1276 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1277 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1278 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1279 | ||
1280 | if (bpts[i].control != 0) | |
1281 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1282 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1283 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1284 | ||
1285 | arm_lwp_info->bpts_changed[i] = 0; | |
1286 | } | |
e3039479 | 1287 | |
638c5f49 OJ |
1288 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1289 | if (arm_lwp_info->wpts_changed[i]) | |
1290 | { | |
1291 | errno = 0; | |
1292 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1293 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1294 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1295 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1296 | ||
1297 | if (wpts[i].control != 0) | |
1298 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1299 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1300 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1301 | ||
1302 | arm_lwp_info->wpts_changed[i] = 0; | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | /* linux_nat_new_fork hook. */ | |
1307 | ||
1308 | static void | |
1309 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1310 | { | |
1311 | pid_t parent_pid; | |
1312 | struct arm_linux_debug_reg_state *parent_state; | |
1313 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1314 | |
638c5f49 OJ |
1315 | /* NULL means no watchpoint has ever been set in the parent. In |
1316 | that case, there's nothing to do. */ | |
1317 | if (parent->arch_private == NULL) | |
1318 | return; | |
e3039479 | 1319 | |
638c5f49 OJ |
1320 | /* GDB core assumes the child inherits the watchpoints/hw |
1321 | breakpoints of the parent, and will remove them all from the | |
1322 | forked off process. Copy the debug registers mirrors into the | |
1323 | new process so that all breakpoints and watchpoints can be | |
1324 | removed together. */ | |
e3039479 | 1325 | |
638c5f49 OJ |
1326 | parent_pid = ptid_get_pid (parent->ptid); |
1327 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1328 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1329 | *child_state = *parent_state; | |
e3039479 UW |
1330 | } |
1331 | ||
10d6c8cd DJ |
1332 | void _initialize_arm_linux_nat (void); |
1333 | ||
ed9a39eb JM |
1334 | void |
1335 | _initialize_arm_linux_nat (void) | |
1336 | { | |
10d6c8cd DJ |
1337 | struct target_ops *t; |
1338 | ||
10d6c8cd DJ |
1339 | /* Fill in the generic GNU/Linux methods. */ |
1340 | t = linux_target (); | |
1341 | ||
1342 | /* Add our register access methods. */ | |
1343 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1344 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1345 | ||
e3039479 UW |
1346 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1347 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1348 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1349 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1350 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1351 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1352 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1353 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1354 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1355 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1356 | ||
81adfced | 1357 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1358 | |
10d6c8cd | 1359 | /* Register the target. */ |
f973ed9c | 1360 | linux_nat_add_target (t); |
e3039479 | 1361 | |
638c5f49 | 1362 | /* Handle thread creation and exit. */ |
e3039479 | 1363 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1364 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1365 | ||
1366 | /* Handle process creation and exit. */ | |
1367 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1368 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1369 | } |