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ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
32d0add0 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
f1b67888 | 32 | #include "aarch32-linux-nat.h" |
aeb98c60 | 33 | |
3b273a55 | 34 | #include <elf/common.h> |
ed9a39eb | 35 | #include <sys/user.h> |
5826e159 | 36 | #include "nat/gdb_ptrace.h" |
ed9a39eb | 37 | #include <sys/utsname.h> |
41c49b06 | 38 | #include <sys/procfs.h> |
ed9a39eb | 39 | |
95855ca8 MS |
40 | #include "nat/linux-ptrace.h" |
41 | ||
0963b4bd | 42 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
43 | #include "gregset.h" |
44 | ||
9308fc88 DJ |
45 | /* Defines ps_err_e, struct ps_prochandle. */ |
46 | #include "gdb_proc_service.h" | |
47 | ||
48 | #ifndef PTRACE_GET_THREAD_AREA | |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
05a4558a DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | #define PTRACE_GETWMMXREGS 18 | |
54 | #define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
3b273a55 RE |
57 | #ifndef PTRACE_GETVFPREGS |
58 | #define PTRACE_GETVFPREGS 27 | |
59 | #define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
e3039479 UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
ed9a39eb JM |
67 | extern int arm_apcs_32; |
68 | ||
41c49b06 | 69 | /* Get the whole floating point state of the process and store it |
c6b92abd | 70 | into regcache. */ |
ed9a39eb JM |
71 | |
72 | static void | |
56be3814 | 73 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 74 | { |
41c49b06 | 75 | int ret, regno, tid; |
cb587d83 | 76 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 77 | |
41c49b06 | 78 | /* Get the thread id for the ptrace call. */ |
d89fa914 | 79 | tid = ptid_get_lwp (inferior_ptid); |
df9d7ec9 | 80 | |
ed9a39eb | 81 | /* Read the floating point state. */ |
0bdb2f78 | 82 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
83 | { |
84 | struct iovec iov; | |
85 | ||
86 | iov.iov_base = &fp; | |
87 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
88 | ||
89 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
90 | } | |
91 | else | |
92 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
93 | ||
ed9a39eb JM |
94 | if (ret < 0) |
95 | { | |
edefbb7c | 96 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
97 | return; |
98 | } | |
99 | ||
100 | /* Fetch fpsr. */ | |
56be3814 | 101 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 102 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
103 | |
104 | /* Fetch the floating point registers. */ | |
34e8f22d | 105 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 106 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
107 | } |
108 | ||
109 | /* Save the whole floating point state of the process using | |
c6b92abd | 110 | the contents from regcache. */ |
ed9a39eb JM |
111 | |
112 | static void | |
56be3814 | 113 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 114 | { |
41c49b06 | 115 | int ret, regno, tid; |
cb587d83 | 116 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 117 | |
41c49b06 | 118 | /* Get the thread id for the ptrace call. */ |
d89fa914 | 119 | tid = ptid_get_lwp (inferior_ptid); |
df9d7ec9 | 120 | |
41c49b06 | 121 | /* Read the floating point state. */ |
0bdb2f78 | 122 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
123 | { |
124 | elf_fpregset_t fpregs; | |
125 | struct iovec iov; | |
126 | ||
127 | iov.iov_base = &fpregs; | |
128 | iov.iov_len = sizeof (fpregs); | |
129 | ||
130 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); | |
131 | } | |
132 | else | |
133 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); | |
134 | ||
41c49b06 SB |
135 | if (ret < 0) |
136 | { | |
edefbb7c | 137 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
138 | return; |
139 | } | |
140 | ||
ed9a39eb | 141 | /* Store fpsr. */ |
672c9795 | 142 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 143 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
144 | |
145 | /* Store the floating point registers. */ | |
34e8f22d | 146 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 147 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 148 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 149 | |
0bdb2f78 | 150 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
df9d7ec9 YQ |
151 | { |
152 | struct iovec iov; | |
153 | ||
154 | iov.iov_base = &fp; | |
155 | iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; | |
156 | ||
157 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); | |
158 | } | |
159 | else | |
160 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); | |
161 | ||
ed9a39eb JM |
162 | if (ret < 0) |
163 | { | |
edefbb7c | 164 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
165 | return; |
166 | } | |
167 | } | |
168 | ||
169 | /* Fetch all general registers of the process and store into | |
c6b92abd | 170 | regcache. */ |
ed9a39eb JM |
171 | |
172 | static void | |
56be3814 | 173 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 174 | { |
41c49b06 | 175 | int ret, regno, tid; |
c2152441 | 176 | elf_gregset_t regs; |
ed9a39eb | 177 | |
41c49b06 | 178 | /* Get the thread id for the ptrace call. */ |
d89fa914 | 179 | tid = ptid_get_lwp (inferior_ptid); |
10766686 | 180 | |
0bdb2f78 | 181 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
182 | { |
183 | struct iovec iov; | |
184 | ||
185 | iov.iov_base = ®s; | |
186 | iov.iov_len = sizeof (regs); | |
187 | ||
188 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
189 | } | |
190 | else | |
191 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
192 | ||
ed9a39eb JM |
193 | if (ret < 0) |
194 | { | |
edefbb7c | 195 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
196 | return; |
197 | } | |
198 | ||
f1b67888 | 199 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, arm_apcs_32); |
ed9a39eb JM |
200 | } |
201 | ||
ed9a39eb | 202 | static void |
56be3814 | 203 | store_regs (const struct regcache *regcache) |
ed9a39eb | 204 | { |
41c49b06 | 205 | int ret, regno, tid; |
c2152441 | 206 | elf_gregset_t regs; |
ed9a39eb | 207 | |
41c49b06 | 208 | /* Get the thread id for the ptrace call. */ |
d89fa914 | 209 | tid = ptid_get_lwp (inferior_ptid); |
10766686 | 210 | |
41c49b06 | 211 | /* Fetch the general registers. */ |
0bdb2f78 | 212 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
213 | { |
214 | struct iovec iov; | |
215 | ||
216 | iov.iov_base = ®s; | |
217 | iov.iov_len = sizeof (regs); | |
218 | ||
219 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); | |
220 | } | |
221 | else | |
222 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
223 | ||
ed9a39eb JM |
224 | if (ret < 0) |
225 | { | |
edefbb7c | 226 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
227 | return; |
228 | } | |
229 | ||
f1b67888 | 230 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); |
adb8a87c | 231 | |
0bdb2f78 | 232 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
10766686 YQ |
233 | { |
234 | struct iovec iov; | |
235 | ||
236 | iov.iov_base = ®s; | |
237 | iov.iov_len = sizeof (regs); | |
238 | ||
239 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); | |
240 | } | |
241 | else | |
242 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
ed9a39eb JM |
243 | |
244 | if (ret < 0) | |
245 | { | |
edefbb7c | 246 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
247 | return; |
248 | } | |
249 | } | |
250 | ||
05a4558a DJ |
251 | /* Fetch all WMMX registers of the process and store into |
252 | regcache. */ | |
253 | ||
254 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
255 | ||
256 | static void | |
56be3814 | 257 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
258 | { |
259 | char regbuf[IWMMXT_REGS_SIZE]; | |
260 | int ret, regno, tid; | |
261 | ||
262 | /* Get the thread id for the ptrace call. */ | |
d89fa914 | 263 | tid = ptid_get_lwp (inferior_ptid); |
05a4558a DJ |
264 | |
265 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
266 | if (ret < 0) | |
267 | { | |
268 | warning (_("Unable to fetch WMMX registers.")); | |
269 | return; | |
270 | } | |
271 | ||
272 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 273 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
274 | ®buf[regno * 8]); |
275 | ||
276 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 277 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
278 | ®buf[16 * 8 + regno * 4]); |
279 | ||
280 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 281 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
282 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
283 | } | |
284 | ||
285 | static void | |
56be3814 | 286 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
287 | { |
288 | char regbuf[IWMMXT_REGS_SIZE]; | |
289 | int ret, regno, tid; | |
290 | ||
291 | /* Get the thread id for the ptrace call. */ | |
d89fa914 | 292 | tid = ptid_get_lwp (inferior_ptid); |
05a4558a DJ |
293 | |
294 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
295 | if (ret < 0) | |
296 | { | |
297 | warning (_("Unable to fetch WMMX registers.")); | |
298 | return; | |
299 | } | |
300 | ||
301 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
302 | if (REG_VALID == regcache_register_status (regcache, |
303 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 304 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
305 | ®buf[regno * 8]); |
306 | ||
307 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
308 | if (REG_VALID == regcache_register_status (regcache, |
309 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 310 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
311 | ®buf[16 * 8 + regno * 4]); |
312 | ||
313 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
314 | if (REG_VALID == regcache_register_status (regcache, |
315 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 316 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
317 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
318 | ||
319 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
320 | ||
321 | if (ret < 0) | |
322 | { | |
323 | warning (_("Unable to store WMMX registers.")); | |
324 | return; | |
325 | } | |
326 | } | |
327 | ||
3b273a55 RE |
328 | static void |
329 | fetch_vfp_regs (struct regcache *regcache) | |
330 | { | |
f1b67888 | 331 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 332 | int ret, regno, tid; |
330c6ca9 YQ |
333 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
334 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
335 | |
336 | /* Get the thread id for the ptrace call. */ | |
d89fa914 | 337 | tid = ptid_get_lwp (inferior_ptid); |
3b273a55 | 338 | |
0bdb2f78 | 339 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
340 | { |
341 | struct iovec iov; | |
342 | ||
343 | iov.iov_base = regbuf; | |
344 | iov.iov_len = VFP_REGS_SIZE; | |
345 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
346 | } | |
347 | else | |
348 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
349 | ||
3b273a55 RE |
350 | if (ret < 0) |
351 | { | |
352 | warning (_("Unable to fetch VFP registers.")); | |
353 | return; | |
354 | } | |
355 | ||
f1b67888 YQ |
356 | aarch32_vfp_regcache_supply (regcache, regbuf, |
357 | tdep->vfp_register_count); | |
3b273a55 RE |
358 | } |
359 | ||
360 | static void | |
361 | store_vfp_regs (const struct regcache *regcache) | |
362 | { | |
f1b67888 | 363 | gdb_byte regbuf[VFP_REGS_SIZE]; |
3b273a55 | 364 | int ret, regno, tid; |
330c6ca9 YQ |
365 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
366 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
367 | |
368 | /* Get the thread id for the ptrace call. */ | |
d89fa914 | 369 | tid = ptid_get_lwp (inferior_ptid); |
3b273a55 | 370 | |
0bdb2f78 | 371 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
372 | { |
373 | struct iovec iov; | |
374 | ||
375 | iov.iov_base = regbuf; | |
376 | iov.iov_len = VFP_REGS_SIZE; | |
377 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); | |
378 | } | |
379 | else | |
380 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
381 | ||
3b273a55 RE |
382 | if (ret < 0) |
383 | { | |
384 | warning (_("Unable to fetch VFP registers (for update).")); | |
385 | return; | |
386 | } | |
387 | ||
f1b67888 YQ |
388 | aarch32_vfp_regcache_collect (regcache, regbuf, |
389 | tdep->vfp_register_count); | |
3b273a55 | 390 | |
0bdb2f78 | 391 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
bd16da51 YQ |
392 | { |
393 | struct iovec iov; | |
394 | ||
395 | iov.iov_base = regbuf; | |
396 | iov.iov_len = VFP_REGS_SIZE; | |
397 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); | |
398 | } | |
399 | else | |
400 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
3b273a55 RE |
401 | |
402 | if (ret < 0) | |
403 | { | |
404 | warning (_("Unable to store VFP registers.")); | |
405 | return; | |
406 | } | |
407 | } | |
408 | ||
ed9a39eb JM |
409 | /* Fetch registers from the child process. Fetch all registers if |
410 | regno == -1, otherwise fetch all general registers or all floating | |
411 | point registers depending upon the value of regno. */ | |
412 | ||
10d6c8cd | 413 | static void |
28439f5e PA |
414 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
415 | struct regcache *regcache, int regno) | |
ed9a39eb | 416 | { |
330c6ca9 YQ |
417 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
418 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
419 | ||
41c49b06 SB |
420 | if (-1 == regno) |
421 | { | |
56be3814 UW |
422 | fetch_regs (regcache); |
423 | fetch_fpregs (regcache); | |
a56cc1ce | 424 | if (tdep->have_wmmx_registers) |
56be3814 | 425 | fetch_wmmx_regs (regcache); |
330c6ca9 | 426 | if (tdep->vfp_register_count > 0) |
3b273a55 | 427 | fetch_vfp_regs (regcache); |
41c49b06 SB |
428 | } |
429 | else | |
430 | { | |
05a4558a | 431 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 432 | fetch_regs (regcache); |
05a4558a | 433 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
179bfe82 | 434 | fetch_fpregs (regcache); |
a56cc1ce | 435 | else if (tdep->have_wmmx_registers |
05a4558a | 436 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 437 | fetch_wmmx_regs (regcache); |
330c6ca9 | 438 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 439 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 440 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 441 | fetch_vfp_regs (regcache); |
41c49b06 | 442 | } |
ed9a39eb JM |
443 | } |
444 | ||
445 | /* Store registers back into the inferior. Store all registers if | |
446 | regno == -1, otherwise store all general registers or all floating | |
447 | point registers depending upon the value of regno. */ | |
448 | ||
10d6c8cd | 449 | static void |
28439f5e PA |
450 | arm_linux_store_inferior_registers (struct target_ops *ops, |
451 | struct regcache *regcache, int regno) | |
ed9a39eb | 452 | { |
330c6ca9 YQ |
453 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
454 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
455 | ||
41c49b06 SB |
456 | if (-1 == regno) |
457 | { | |
56be3814 UW |
458 | store_regs (regcache); |
459 | store_fpregs (regcache); | |
a56cc1ce | 460 | if (tdep->have_wmmx_registers) |
56be3814 | 461 | store_wmmx_regs (regcache); |
330c6ca9 | 462 | if (tdep->vfp_register_count > 0) |
3b273a55 | 463 | store_vfp_regs (regcache); |
41c49b06 SB |
464 | } |
465 | else | |
466 | { | |
05a4558a | 467 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
179bfe82 | 468 | store_regs (regcache); |
05a4558a | 469 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
179bfe82 | 470 | store_fpregs (regcache); |
a56cc1ce | 471 | else if (tdep->have_wmmx_registers |
05a4558a | 472 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 473 | store_wmmx_regs (regcache); |
330c6ca9 | 474 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 475 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 476 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 477 | store_vfp_regs (regcache); |
41c49b06 | 478 | } |
ed9a39eb JM |
479 | } |
480 | ||
cb587d83 DJ |
481 | /* Wrapper functions for the standard regset handling, used by |
482 | thread debugging. */ | |
41c49b06 SB |
483 | |
484 | void | |
7f7fe91e UW |
485 | fill_gregset (const struct regcache *regcache, |
486 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 487 | { |
7f7fe91e | 488 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
489 | } |
490 | ||
41c49b06 | 491 | void |
7f7fe91e | 492 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 493 | { |
7f7fe91e | 494 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
495 | } |
496 | ||
41c49b06 | 497 | void |
7f7fe91e UW |
498 | fill_fpregset (const struct regcache *regcache, |
499 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 500 | { |
7f7fe91e | 501 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
502 | } |
503 | ||
504 | /* Fill GDB's register array with the floating-point register values | |
505 | in *fpregsetp. */ | |
506 | ||
507 | void | |
7f7fe91e | 508 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 509 | { |
7f7fe91e | 510 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
511 | } |
512 | ||
9308fc88 DJ |
513 | /* Fetch the thread-local storage pointer for libthread_db. */ |
514 | ||
515 | ps_err_e | |
516 | ps_get_thread_area (const struct ps_prochandle *ph, | |
517 | lwpid_t lwpid, int idx, void **base) | |
518 | { | |
519 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
520 | return PS_ERR; | |
521 | ||
522 | /* IDX is the bias from the thread pointer to the beginning of the | |
523 | thread descriptor. It has to be subtracted due to implementation | |
524 | quirks in libthread_db. */ | |
525 | *base = (void *) ((char *)*base - idx); | |
526 | ||
527 | return PS_OK; | |
528 | } | |
529 | ||
81adfced DJ |
530 | static const struct target_desc * |
531 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 532 | { |
3b273a55 | 533 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 534 | |
0bdb2f78 | 535 | if (have_ptrace_getregset == TRIBOOL_UNKNOWN) |
7efe48d1 YQ |
536 | { |
537 | elf_gregset_t gpregs; | |
538 | struct iovec iov; | |
d89fa914 | 539 | int tid = ptid_get_lwp (inferior_ptid); |
7efe48d1 YQ |
540 | |
541 | iov.iov_base = &gpregs; | |
542 | iov.iov_len = sizeof (gpregs); | |
543 | ||
544 | /* Check if PTRACE_GETREGSET works. */ | |
545 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) < 0) | |
0bdb2f78 | 546 | have_ptrace_getregset = TRIBOOL_FALSE; |
7efe48d1 | 547 | else |
0bdb2f78 | 548 | have_ptrace_getregset = TRIBOOL_TRUE; |
7efe48d1 YQ |
549 | } |
550 | ||
3b273a55 RE |
551 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
552 | { | |
2117c711 | 553 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 554 | } |
81adfced | 555 | |
3b273a55 | 556 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 557 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
558 | |
559 | if (arm_hwcap & HWCAP_VFP) | |
560 | { | |
561 | int pid; | |
562 | char *buf; | |
563 | const struct target_desc * result = NULL; | |
564 | ||
565 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
566 | Neon with VFPv3-D32. */ | |
567 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 568 | result = tdesc_arm_with_neon; |
3b273a55 | 569 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 570 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 571 | else |
330c6ca9 | 572 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
573 | |
574 | /* Now make sure that the kernel supports reading these | |
575 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 576 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
577 | errno = 0; |
578 | buf = alloca (VFP_REGS_SIZE); | |
579 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
580 | && errno == EIO) | |
581 | result = NULL; | |
582 | ||
583 | return result; | |
584 | } | |
585 | ||
2117c711 | 586 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
587 | } |
588 | ||
e3039479 UW |
589 | /* Information describing the hardware breakpoint capabilities. */ |
590 | struct arm_linux_hwbp_cap | |
591 | { | |
592 | gdb_byte arch; | |
593 | gdb_byte max_wp_length; | |
594 | gdb_byte wp_count; | |
595 | gdb_byte bp_count; | |
596 | }; | |
597 | ||
638c5f49 OJ |
598 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
599 | assume a maximum number of supported break-/watchpoints. */ | |
600 | #define MAX_BPTS 16 | |
601 | #define MAX_WPTS 16 | |
602 | ||
e3039479 UW |
603 | /* Get hold of the Hardware Breakpoint information for the target we are |
604 | attached to. Returns NULL if the kernel doesn't support Hardware | |
605 | breakpoints at all, or a pointer to the information structure. */ | |
606 | static const struct arm_linux_hwbp_cap * | |
607 | arm_linux_get_hwbp_cap (void) | |
608 | { | |
609 | /* The info structure we return. */ | |
610 | static struct arm_linux_hwbp_cap info; | |
611 | ||
612 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
613 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
614 | means INFO is in an initialized state. */ | |
615 | static int available = -1; | |
616 | ||
617 | if (available == -1) | |
618 | { | |
619 | int tid; | |
620 | unsigned int val; | |
621 | ||
d89fa914 | 622 | tid = ptid_get_lwp (inferior_ptid); |
e3039479 UW |
623 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) |
624 | available = 0; | |
625 | else | |
626 | { | |
627 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
628 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
629 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
630 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
631 | |
632 | if (info.wp_count > MAX_WPTS) | |
633 | { | |
634 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
635 | supports %d"), MAX_WPTS, info.wp_count); | |
636 | info.wp_count = MAX_WPTS; | |
637 | } | |
638 | ||
639 | if (info.bp_count > MAX_BPTS) | |
640 | { | |
641 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
642 | supports %d"), MAX_BPTS, info.bp_count); | |
643 | info.bp_count = MAX_BPTS; | |
644 | } | |
e3039479 UW |
645 | available = (info.arch != 0); |
646 | } | |
647 | } | |
648 | ||
649 | return available == 1 ? &info : NULL; | |
650 | } | |
651 | ||
652 | /* How many hardware breakpoints are available? */ | |
653 | static int | |
654 | arm_linux_get_hw_breakpoint_count (void) | |
655 | { | |
656 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
657 | return cap != NULL ? cap->bp_count : 0; | |
658 | } | |
659 | ||
660 | /* How many hardware watchpoints are available? */ | |
661 | static int | |
662 | arm_linux_get_hw_watchpoint_count (void) | |
663 | { | |
664 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
665 | return cap != NULL ? cap->wp_count : 0; | |
666 | } | |
667 | ||
668 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
669 | there is not an appropriate resource available, otherwise returns 1. */ | |
670 | static int | |
5461485a | 671 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
f486487f SM |
672 | enum bptype type, |
673 | int cnt, int ot) | |
e3039479 UW |
674 | { |
675 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
676 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
677 | { | |
dbbf180a YQ |
678 | int count = arm_linux_get_hw_watchpoint_count (); |
679 | ||
680 | if (count == 0) | |
681 | return 0; | |
682 | else if (cnt + ot > count) | |
e3039479 UW |
683 | return -1; |
684 | } | |
685 | else if (type == bp_hardware_breakpoint) | |
686 | { | |
dbbf180a YQ |
687 | int count = arm_linux_get_hw_breakpoint_count (); |
688 | ||
689 | if (count == 0) | |
690 | return 0; | |
691 | else if (cnt > count) | |
e3039479 UW |
692 | return -1; |
693 | } | |
694 | else | |
695 | gdb_assert (FALSE); | |
696 | ||
697 | return 1; | |
698 | } | |
699 | ||
700 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
701 | typedef enum | |
702 | { | |
703 | arm_hwbp_break = 0, | |
704 | arm_hwbp_load = 1, | |
705 | arm_hwbp_store = 2, | |
706 | arm_hwbp_access = 3 | |
707 | } arm_hwbp_type; | |
708 | ||
709 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
710 | typedef unsigned int arm_hwbp_control_t; | |
711 | ||
712 | /* Structure used to keep track of hardware break-/watch-points. */ | |
713 | struct arm_linux_hw_breakpoint | |
714 | { | |
715 | /* Address to break on, or being watched. */ | |
716 | unsigned int address; | |
717 | /* Control register for break-/watch- point. */ | |
718 | arm_hwbp_control_t control; | |
719 | }; | |
720 | ||
638c5f49 OJ |
721 | /* Structure containing arrays of per process hardware break-/watchpoints |
722 | for caching address and control information. | |
e3039479 UW |
723 | |
724 | The Linux ptrace interface to hardware break-/watch-points presents the | |
725 | values in a vector centred around 0 (which is used fo generic information). | |
726 | Positive indicies refer to breakpoint addresses/control registers, negative | |
727 | indices to watchpoint addresses/control registers. | |
728 | ||
729 | The Linux vector is indexed as follows: | |
730 | -((i << 1) + 2): Control register for watchpoint i. | |
731 | -((i << 1) + 1): Address register for watchpoint i. | |
732 | 0: Information register. | |
733 | ((i << 1) + 1): Address register for breakpoint i. | |
734 | ((i << 1) + 2): Control register for breakpoint i. | |
735 | ||
736 | This structure is used as a per-thread cache of the state stored by the | |
737 | kernel, so that we don't need to keep calling into the kernel to find a | |
738 | free breakpoint. | |
739 | ||
740 | We treat break-/watch-points with their enable bit clear as being deleted. | |
741 | */ | |
638c5f49 | 742 | struct arm_linux_debug_reg_state |
e3039479 | 743 | { |
638c5f49 OJ |
744 | /* Hardware breakpoints for this process. */ |
745 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
746 | /* Hardware watchpoints for this process. */ | |
747 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
748 | }; | |
749 | ||
750 | /* Per-process arch-specific data we want to keep. */ | |
751 | struct arm_linux_process_info | |
e3039479 | 752 | { |
638c5f49 OJ |
753 | /* Linked list. */ |
754 | struct arm_linux_process_info *next; | |
755 | /* The process identifier. */ | |
756 | pid_t pid; | |
757 | /* Hardware break-/watchpoints state information. */ | |
758 | struct arm_linux_debug_reg_state state; | |
e3039479 | 759 | |
638c5f49 OJ |
760 | }; |
761 | ||
762 | /* Per-thread arch-specific data we want to keep. */ | |
763 | struct arch_lwp_info | |
764 | { | |
765 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
766 | char bpts_changed[MAX_BPTS]; | |
767 | char wpts_changed[MAX_WPTS]; | |
768 | }; | |
769 | ||
770 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
771 | ||
772 | /* Find process data for process PID. */ | |
773 | ||
774 | static struct arm_linux_process_info * | |
775 | arm_linux_find_process_pid (pid_t pid) | |
776 | { | |
777 | struct arm_linux_process_info *proc; | |
778 | ||
779 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
780 | if (proc->pid == pid) | |
781 | return proc; | |
782 | ||
783 | return NULL; | |
784 | } | |
785 | ||
786 | /* Add process data for process PID. Returns newly allocated info | |
787 | object. */ | |
788 | ||
789 | static struct arm_linux_process_info * | |
790 | arm_linux_add_process (pid_t pid) | |
791 | { | |
792 | struct arm_linux_process_info *proc; | |
e3039479 | 793 | |
638c5f49 OJ |
794 | proc = xcalloc (1, sizeof (*proc)); |
795 | proc->pid = pid; | |
e3039479 | 796 | |
638c5f49 OJ |
797 | proc->next = arm_linux_process_list; |
798 | arm_linux_process_list = proc; | |
799 | ||
800 | return proc; | |
801 | } | |
802 | ||
803 | /* Get data specific info for process PID, creating it if necessary. | |
804 | Never returns NULL. */ | |
805 | ||
806 | static struct arm_linux_process_info * | |
807 | arm_linux_process_info_get (pid_t pid) | |
808 | { | |
809 | struct arm_linux_process_info *proc; | |
810 | ||
811 | proc = arm_linux_find_process_pid (pid); | |
812 | if (proc == NULL) | |
813 | proc = arm_linux_add_process (pid); | |
814 | ||
815 | return proc; | |
816 | } | |
817 | ||
818 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
819 | data structures that keep track of debug register state. */ | |
820 | ||
821 | static void | |
822 | arm_linux_forget_process (pid_t pid) | |
823 | { | |
824 | struct arm_linux_process_info *proc, **proc_link; | |
825 | ||
826 | proc = arm_linux_process_list; | |
827 | proc_link = &arm_linux_process_list; | |
828 | ||
829 | while (proc != NULL) | |
830 | { | |
831 | if (proc->pid == pid) | |
e3039479 | 832 | { |
638c5f49 OJ |
833 | *proc_link = proc->next; |
834 | ||
835 | xfree (proc); | |
836 | return; | |
e3039479 UW |
837 | } |
838 | ||
638c5f49 OJ |
839 | proc_link = &proc->next; |
840 | proc = *proc_link; | |
841 | } | |
842 | } | |
843 | ||
844 | /* Get hardware break-/watchpoint state for process PID. */ | |
845 | ||
846 | static struct arm_linux_debug_reg_state * | |
847 | arm_linux_get_debug_reg_state (pid_t pid) | |
848 | { | |
849 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
850 | } |
851 | ||
852 | /* Initialize an ARM hardware break-/watch-point control register value. | |
853 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
854 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
855 | */ | |
856 | static arm_hwbp_control_t | |
857 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
858 | arm_hwbp_type hwbp_type, | |
859 | int enable) | |
860 | { | |
861 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
862 | gdb_assert (hwbp_type != arm_hwbp_break | |
863 | || ((byte_address_select & 0xfU) != 0)); | |
864 | ||
865 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
866 | } | |
867 | ||
868 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
869 | static int | |
870 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
871 | { | |
872 | return control & 0x1; | |
873 | } | |
874 | ||
875 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
876 | static arm_hwbp_control_t | |
877 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
878 | { | |
879 | return control & ~0x1; | |
880 | } | |
881 | ||
882 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
883 | enabled, and will point to the placed address of BP_TGT. */ | |
884 | static void | |
885 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
886 | struct bp_target_info *bp_tgt, | |
887 | struct arm_linux_hw_breakpoint *p) | |
888 | { | |
889 | unsigned mask; | |
0d5ed153 | 890 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
891 | |
892 | /* We have to create a mask for the control register which says which bits | |
893 | of the word pointed to by address to break on. */ | |
894 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
895 | { |
896 | mask = 0x3; | |
897 | address &= ~1; | |
898 | } | |
e3039479 | 899 | else |
fcf303ab UW |
900 | { |
901 | mask = 0xf; | |
902 | address &= ~3; | |
903 | } | |
e3039479 | 904 | |
fcf303ab | 905 | p->address = (unsigned int) address; |
e3039479 UW |
906 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
907 | } | |
908 | ||
8156fe7f | 909 | /* Get the ARM hardware breakpoint type from the TYPE value we're |
f486487f | 910 | given when asked to set a watchpoint. */ |
e3039479 | 911 | static arm_hwbp_type |
f486487f | 912 | arm_linux_get_hwbp_type (enum target_hw_bp_type type) |
e3039479 | 913 | { |
8156fe7f | 914 | if (type == hw_read) |
e3039479 | 915 | return arm_hwbp_load; |
8156fe7f | 916 | else if (type == hw_write) |
e3039479 UW |
917 | return arm_hwbp_store; |
918 | else | |
919 | return arm_hwbp_access; | |
920 | } | |
921 | ||
922 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
923 | to LEN. The type of watchpoint is given in RW. */ | |
924 | static void | |
f486487f SM |
925 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, |
926 | enum target_hw_bp_type type, | |
e3039479 UW |
927 | struct arm_linux_hw_breakpoint *p) |
928 | { | |
929 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
930 | unsigned mask; | |
931 | ||
932 | gdb_assert (cap != NULL); | |
933 | gdb_assert (cap->max_wp_length != 0); | |
934 | ||
935 | mask = (1 << len) - 1; | |
936 | ||
937 | p->address = (unsigned int) addr; | |
938 | p->control = arm_hwbp_control_initialize (mask, | |
f486487f | 939 | arm_linux_get_hwbp_type (type), 1); |
e3039479 UW |
940 | } |
941 | ||
942 | /* Are two break-/watch-points equal? */ | |
943 | static int | |
944 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
945 | const struct arm_linux_hw_breakpoint *p2) | |
946 | { | |
947 | return p1->address == p2->address && p1->control == p2->control; | |
948 | } | |
949 | ||
638c5f49 OJ |
950 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
951 | the current process. */ | |
952 | ||
953 | struct update_registers_data | |
954 | { | |
955 | int watch; | |
956 | int index; | |
957 | }; | |
958 | ||
959 | static int | |
960 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
961 | { | |
962 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
963 | ||
964 | if (lwp->arch_private == NULL) | |
965 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
966 | ||
967 | /* The actual update is done later just before resuming the lwp, | |
968 | we just mark that the registers need updating. */ | |
969 | if (data->watch) | |
970 | lwp->arch_private->wpts_changed[data->index] = 1; | |
971 | else | |
972 | lwp->arch_private->bpts_changed[data->index] = 1; | |
973 | ||
974 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
975 | we can update its breakpoint registers. */ | |
976 | if (!lwp->stopped) | |
977 | linux_stop_lwp (lwp); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
e3039479 UW |
982 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
983 | =1) BPT for thread TID. */ | |
984 | static void | |
985 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 986 | int watchpoint) |
e3039479 | 987 | { |
638c5f49 OJ |
988 | int pid; |
989 | ptid_t pid_ptid; | |
e3039479 UW |
990 | gdb_byte count, i; |
991 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 992 | struct update_registers_data data; |
e3039479 | 993 | |
638c5f49 OJ |
994 | pid = ptid_get_pid (inferior_ptid); |
995 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
996 | |
997 | if (watchpoint) | |
998 | { | |
999 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1000 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1001 | } |
1002 | else | |
1003 | { | |
1004 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1005 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1006 | } |
1007 | ||
1008 | for (i = 0; i < count; ++i) | |
1009 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1010 | { | |
638c5f49 OJ |
1011 | data.watch = watchpoint; |
1012 | data.index = i; | |
1013 | bpts[i] = *bpt; | |
1014 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1015 | break; | |
e3039479 UW |
1016 | } |
1017 | ||
1018 | gdb_assert (i != count); | |
1019 | } | |
1020 | ||
1021 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1022 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1023 | static void | |
1024 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1025 | int watchpoint) |
e3039479 | 1026 | { |
638c5f49 | 1027 | int pid; |
e3039479 | 1028 | gdb_byte count, i; |
638c5f49 OJ |
1029 | ptid_t pid_ptid; |
1030 | struct arm_linux_hw_breakpoint* bpts; | |
1031 | struct update_registers_data data; | |
e3039479 | 1032 | |
638c5f49 OJ |
1033 | pid = ptid_get_pid (inferior_ptid); |
1034 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1035 | |
1036 | if (watchpoint) | |
1037 | { | |
1038 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1039 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1040 | } |
1041 | else | |
1042 | { | |
1043 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1044 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1045 | } |
1046 | ||
1047 | for (i = 0; i < count; ++i) | |
1048 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1049 | { | |
638c5f49 OJ |
1050 | data.watch = watchpoint; |
1051 | data.index = i; | |
1052 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1053 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1054 | break; | |
e3039479 UW |
1055 | } |
1056 | ||
1057 | gdb_assert (i != count); | |
1058 | } | |
1059 | ||
1060 | /* Insert a Hardware breakpoint. */ | |
1061 | static int | |
23a26771 TT |
1062 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1063 | struct gdbarch *gdbarch, | |
e3039479 UW |
1064 | struct bp_target_info *bp_tgt) |
1065 | { | |
e3039479 UW |
1066 | struct lwp_info *lp; |
1067 | struct arm_linux_hw_breakpoint p; | |
1068 | ||
1069 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1070 | return -1; | |
1071 | ||
1072 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1073 | |
1074 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | /* Remove a hardware breakpoint. */ | |
1080 | static int | |
a64dc96c TT |
1081 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1082 | struct gdbarch *gdbarch, | |
e3039479 UW |
1083 | struct bp_target_info *bp_tgt) |
1084 | { | |
e3039479 UW |
1085 | struct lwp_info *lp; |
1086 | struct arm_linux_hw_breakpoint p; | |
1087 | ||
1088 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1089 | return -1; | |
1090 | ||
1091 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1092 | |
1093 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1094 | |
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1099 | ADDR? */ | |
1100 | static int | |
31568a15 TT |
1101 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1102 | CORE_ADDR addr, int len) | |
e3039479 UW |
1103 | { |
1104 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1105 | CORE_ADDR max_wp_length, aligned_addr; | |
1106 | ||
1107 | /* Can not set watchpoints for zero or negative lengths. */ | |
1108 | if (len <= 0) | |
1109 | return 0; | |
1110 | ||
1111 | /* Need to be able to use the ptrace interface. */ | |
1112 | if (cap == NULL || cap->wp_count == 0) | |
1113 | return 0; | |
1114 | ||
1115 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1116 | range covered by a watchpoint. */ | |
1117 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1118 | aligned_addr = addr & ~(max_wp_length - 1); | |
1119 | ||
1120 | if (aligned_addr + max_wp_length < addr + len) | |
1121 | return 0; | |
1122 | ||
1123 | /* The current ptrace interface can only handle watchpoints that are a | |
1124 | power of 2. */ | |
1125 | if ((len & (len - 1)) != 0) | |
1126 | return 0; | |
1127 | ||
1128 | /* All tests passed so we must be able to set a watchpoint. */ | |
1129 | return 1; | |
1130 | } | |
1131 | ||
1132 | /* Insert a Hardware breakpoint. */ | |
1133 | static int | |
7bb99c53 | 1134 | arm_linux_insert_watchpoint (struct target_ops *self, |
f486487f SM |
1135 | CORE_ADDR addr, int len, |
1136 | enum target_hw_bp_type rw, | |
e3039479 UW |
1137 | struct expression *cond) |
1138 | { | |
e3039479 UW |
1139 | struct lwp_info *lp; |
1140 | struct arm_linux_hw_breakpoint p; | |
1141 | ||
1142 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1143 | return -1; | |
1144 | ||
1145 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1146 | |
1147 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1148 | |
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | /* Remove a hardware breakpoint. */ | |
1153 | static int | |
8156fe7f YQ |
1154 | arm_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr, |
1155 | int len, enum target_hw_bp_type rw, | |
e3039479 UW |
1156 | struct expression *cond) |
1157 | { | |
e3039479 UW |
1158 | struct lwp_info *lp; |
1159 | struct arm_linux_hw_breakpoint p; | |
1160 | ||
1161 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1162 | return -1; | |
1163 | ||
1164 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1165 | |
1166 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1167 | |
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | /* What was the data address the target was stopped on accessing. */ | |
1172 | static int | |
1173 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1174 | { | |
f865ee35 JK |
1175 | siginfo_t siginfo; |
1176 | int slot; | |
1177 | ||
1178 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1179 | return 0; | |
e3039479 UW |
1180 | |
1181 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1182 | if (siginfo.si_signo != SIGTRAP |
1183 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1184 | return 0; |
1185 | ||
1186 | /* We must be able to set hardware watchpoints. */ | |
1187 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1188 | return 0; | |
1189 | ||
f865ee35 JK |
1190 | slot = siginfo.si_errno; |
1191 | ||
e3039479 UW |
1192 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1193 | a watchpoint. */ | |
1194 | if (slot >= 0) | |
1195 | return 0; | |
1196 | ||
f865ee35 | 1197 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1198 | return 1; |
1199 | } | |
1200 | ||
1201 | /* Has the target been stopped by hitting a watchpoint? */ | |
1202 | static int | |
6a109b6b | 1203 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1204 | { |
1205 | CORE_ADDR addr; | |
6a109b6b | 1206 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1207 | } |
1208 | ||
1209 | static int | |
1210 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1211 | CORE_ADDR addr, | |
1212 | CORE_ADDR start, int length) | |
1213 | { | |
1214 | return start <= addr && start + length - 1 >= addr; | |
1215 | } | |
1216 | ||
1217 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1218 | in the parent thread to the child thread. */ | |
1219 | static void | |
7b50312a | 1220 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1221 | { |
638c5f49 OJ |
1222 | int i; |
1223 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1224 | ||
1225 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1226 | for this thread need to be initialized. */ | |
e3039479 | 1227 | |
638c5f49 | 1228 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1229 | { |
638c5f49 OJ |
1230 | info->bpts_changed[i] = 1; |
1231 | info->wpts_changed[i] = 1; | |
e3039479 | 1232 | } |
638c5f49 OJ |
1233 | |
1234 | lp->arch_private = info; | |
e3039479 UW |
1235 | } |
1236 | ||
638c5f49 OJ |
1237 | /* Called when resuming a thread. |
1238 | The hardware debug registers are updated when there is any change. */ | |
1239 | ||
e3039479 | 1240 | static void |
638c5f49 | 1241 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1242 | { |
638c5f49 OJ |
1243 | int pid, i; |
1244 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1245 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1246 | ||
1247 | pid = ptid_get_lwp (lwp->ptid); | |
1248 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1249 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1250 | ||
1251 | /* NULL means this is the main thread still going through the shell, | |
1252 | or, no watchpoint has been set yet. In that case, there's | |
1253 | nothing to do. */ | |
1254 | if (arm_lwp_info == NULL) | |
1255 | return; | |
e3039479 | 1256 | |
638c5f49 OJ |
1257 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1258 | if (arm_lwp_info->bpts_changed[i]) | |
1259 | { | |
1260 | errno = 0; | |
1261 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1262 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1263 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1264 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1265 | ||
1266 | if (bpts[i].control != 0) | |
1267 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1268 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1269 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1270 | ||
1271 | arm_lwp_info->bpts_changed[i] = 0; | |
1272 | } | |
e3039479 | 1273 | |
638c5f49 OJ |
1274 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1275 | if (arm_lwp_info->wpts_changed[i]) | |
1276 | { | |
1277 | errno = 0; | |
1278 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1279 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1280 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1281 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1282 | ||
1283 | if (wpts[i].control != 0) | |
1284 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1285 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1286 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1287 | ||
1288 | arm_lwp_info->wpts_changed[i] = 0; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | /* linux_nat_new_fork hook. */ | |
1293 | ||
1294 | static void | |
1295 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1296 | { | |
1297 | pid_t parent_pid; | |
1298 | struct arm_linux_debug_reg_state *parent_state; | |
1299 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1300 | |
638c5f49 OJ |
1301 | /* NULL means no watchpoint has ever been set in the parent. In |
1302 | that case, there's nothing to do. */ | |
1303 | if (parent->arch_private == NULL) | |
1304 | return; | |
e3039479 | 1305 | |
638c5f49 OJ |
1306 | /* GDB core assumes the child inherits the watchpoints/hw |
1307 | breakpoints of the parent, and will remove them all from the | |
1308 | forked off process. Copy the debug registers mirrors into the | |
1309 | new process so that all breakpoints and watchpoints can be | |
1310 | removed together. */ | |
e3039479 | 1311 | |
638c5f49 OJ |
1312 | parent_pid = ptid_get_pid (parent->ptid); |
1313 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1314 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1315 | *child_state = *parent_state; | |
e3039479 UW |
1316 | } |
1317 | ||
10d6c8cd DJ |
1318 | void _initialize_arm_linux_nat (void); |
1319 | ||
ed9a39eb JM |
1320 | void |
1321 | _initialize_arm_linux_nat (void) | |
1322 | { | |
10d6c8cd DJ |
1323 | struct target_ops *t; |
1324 | ||
10d6c8cd DJ |
1325 | /* Fill in the generic GNU/Linux methods. */ |
1326 | t = linux_target (); | |
1327 | ||
1328 | /* Add our register access methods. */ | |
1329 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1330 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1331 | ||
e3039479 UW |
1332 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1333 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1334 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1335 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1336 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1337 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1338 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1339 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1340 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1341 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1342 | ||
81adfced | 1343 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1344 | |
10d6c8cd | 1345 | /* Register the target. */ |
f973ed9c | 1346 | linux_nat_add_target (t); |
e3039479 | 1347 | |
638c5f49 | 1348 | /* Handle thread creation and exit. */ |
e3039479 | 1349 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1350 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1351 | ||
1352 | /* Handle process creation and exit. */ | |
1353 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1354 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1355 | } |