Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
34e8f22d RE |
37 | |
38 | #include "arm-tdep.h" | |
39 | ||
082fc60d RE |
40 | #include "elf-bfd.h" |
41 | #include "coff/internal.h" | |
97e03143 | 42 | #include "elf/arm.h" |
c906108c | 43 | |
2a451106 KB |
44 | /* Each OS has a different mechanism for accessing the various |
45 | registers stored in the sigcontext structure. | |
46 | ||
47 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
48 | function pointer) which may be used to determine the addresses | |
49 | of the various saved registers in the sigcontext structure. | |
50 | ||
51 | For the ARM target, there are three parameters to this function. | |
52 | The first is the pc value of the frame under consideration, the | |
53 | second the stack pointer of this frame, and the last is the | |
54 | register number to fetch. | |
55 | ||
56 | If the tm.h file does not define this macro, then it's assumed that | |
57 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
58 | be 0. | |
59 | ||
60 | When it comes time to multi-arching this code, see the identically | |
61 | named machinery in ia64-tdep.c for an example of how it could be | |
62 | done. It should not be necessary to modify the code below where | |
63 | this macro is used. */ | |
64 | ||
3bb04bdd AC |
65 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
66 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
67 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
68 | #endif | |
69 | #else | |
70 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
71 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
72 | #endif |
73 | ||
082fc60d RE |
74 | /* Macros for setting and testing a bit in a minimal symbol that marks |
75 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
76 | is used for this purpose. This field is already being used to store | |
77 | the symbol size, so the assumption is that the symbol size cannot | |
78 | exceed 2^31. | |
79 | ||
80 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
81 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
82 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
83 | i.e. the "info" field with the "special" bit | |
84 | masked out. */ | |
85 | ||
86 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
87 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
88 | | 0x80000000) | |
89 | ||
90 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
91 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
92 | ||
93 | #define MSYMBOL_SIZE(msym) \ | |
94 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 95 | |
94c30b78 | 96 | /* Number of different reg name sets (options). */ |
bc90b915 FN |
97 | static int num_flavor_options; |
98 | ||
99 | /* We have more registers than the disassembler as gdb can print the value | |
100 | of special registers as well. | |
101 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 102 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 103 | |
94c30b78 | 104 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 105 | static char * arm_register_name_strings[] = |
da59e081 JM |
106 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
107 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
108 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
109 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
110 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
111 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 112 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 113 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 114 | |
bc90b915 | 115 | /* Valid register name flavors. */ |
53904c9e | 116 | static const char **valid_flavors; |
ed9a39eb | 117 | |
94c30b78 | 118 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 119 | static const char *disassembly_flavor; |
94c30b78 | 120 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 121 | static int current_option; |
96baa820 | 122 | |
ed9a39eb JM |
123 | /* This is used to keep the bfd arch_info in sync with the disassembly |
124 | flavor. */ | |
125 | static void set_disassembly_flavor_sfunc(char *, int, | |
126 | struct cmd_list_element *); | |
127 | static void set_disassembly_flavor (void); | |
128 | ||
129 | static void convert_from_extended (void *ptr, void *dbl); | |
130 | ||
131 | /* Define other aspects of the stack frame. We keep the offsets of | |
132 | all saved registers, 'cause we need 'em a lot! We also keep the | |
133 | current size of the stack frame, and the offset of the frame | |
134 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 135 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
136 | |
137 | struct frame_extra_info | |
c3b4394c RE |
138 | { |
139 | int framesize; | |
140 | int frameoffset; | |
141 | int framereg; | |
142 | }; | |
ed9a39eb | 143 | |
bc90b915 FN |
144 | /* Addresses for calling Thumb functions have the bit 0 set. |
145 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
146 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
147 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
148 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
149 | ||
39bbf761 | 150 | static int |
ed9a39eb | 151 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 152 | { |
c906108c SS |
153 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
154 | } | |
155 | ||
94c30b78 | 156 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
157 | |
158 | int arm_apcs_32 = 1; | |
159 | ||
ed9a39eb JM |
160 | /* Flag set by arm_fix_call_dummy that tells whether the target |
161 | function is a Thumb function. This flag is checked by | |
162 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
163 | its use in valops.c) to pass the function address as an additional | |
164 | parameter. */ | |
c906108c SS |
165 | |
166 | static int target_is_thumb; | |
167 | ||
ed9a39eb JM |
168 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
169 | function is a Thumb function. This flag is checked by | |
170 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
171 | |
172 | static int caller_is_thumb; | |
173 | ||
ed9a39eb JM |
174 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
175 | function. */ | |
c906108c | 176 | |
34e8f22d | 177 | int |
2a451106 | 178 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 179 | { |
c5aa993b | 180 | struct minimal_symbol *sym; |
c906108c | 181 | |
ed9a39eb | 182 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
183 | if (IS_THUMB_ADDR (memaddr)) |
184 | return 1; | |
185 | ||
ed9a39eb | 186 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
187 | sym = lookup_minimal_symbol_by_pc (memaddr); |
188 | if (sym) | |
189 | { | |
c5aa993b | 190 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
191 | } |
192 | else | |
ed9a39eb JM |
193 | { |
194 | return 0; | |
195 | } | |
c906108c SS |
196 | } |
197 | ||
ed9a39eb JM |
198 | /* Determine if the program counter specified in MEMADDR is in a call |
199 | dummy being called from a Thumb function. */ | |
c906108c | 200 | |
34e8f22d | 201 | int |
2a451106 | 202 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 203 | { |
c5aa993b | 204 | CORE_ADDR sp = read_sp (); |
c906108c | 205 | |
dfcd3bfb JM |
206 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
207 | is the best we can do. We are trying to determine if the pc is on | |
208 | the stack, which (hopefully) will only happen in a call dummy. | |
209 | We hope the current stack pointer is not so far alway from the dummy | |
210 | frame location (true if we have not pushed large data structures or | |
211 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 212 | code regions as part of the stack (true for most practical purposes). */ |
dfcd3bfb | 213 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
214 | return caller_is_thumb; |
215 | else | |
216 | return 0; | |
217 | } | |
218 | ||
181c1381 | 219 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 220 | static CORE_ADDR |
ed9a39eb | 221 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
222 | { |
223 | if (arm_pc_is_thumb (val)) | |
224 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
225 | else | |
226 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
227 | } | |
228 | ||
181c1381 RE |
229 | /* When reading symbols, we need to zap the low bit of the address, |
230 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 231 | static CORE_ADDR |
181c1381 RE |
232 | arm_smash_text_address (CORE_ADDR val) |
233 | { | |
234 | return val & ~1; | |
235 | } | |
236 | ||
34e8f22d RE |
237 | /* Immediately after a function call, return the saved pc. Can't |
238 | always go through the frames for this because on some machines the | |
239 | new frame is not set up until the new function executes some | |
240 | instructions. */ | |
241 | ||
242 | static CORE_ADDR | |
ed9a39eb | 243 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 244 | { |
34e8f22d | 245 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
246 | } |
247 | ||
0defa245 RE |
248 | /* Determine whether the function invocation represented by FI has a |
249 | frame on the stack associated with it. If it does return zero, | |
250 | otherwise return 1. */ | |
251 | ||
148754e5 | 252 | static int |
ed9a39eb | 253 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 254 | { |
392a587b | 255 | CORE_ADDR func_start, after_prologue; |
96baa820 | 256 | int frameless; |
ed9a39eb | 257 | |
0defa245 RE |
258 | /* Sometimes we have functions that do a little setup (like saving the |
259 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
260 | The symbol table will report this as a prologue. However, it is | |
261 | important not to try to parse these partial frames as frames, or we | |
262 | will get really confused. | |
263 | ||
264 | So I will demand 3 instructions between the start & end of the | |
265 | prologue before I call it a real prologue, i.e. at least | |
266 | mov ip, sp, | |
267 | stmdb sp!, {} | |
268 | sub sp, ip, #4. */ | |
269 | ||
392a587b | 270 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 271 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 272 | |
96baa820 | 273 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 274 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 275 | be func_start + 8. */ |
ed9a39eb | 276 | |
96baa820 | 277 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
278 | return frameless; |
279 | } | |
280 | ||
0defa245 | 281 | /* The address of the arguments in the frame. */ |
148754e5 | 282 | static CORE_ADDR |
0defa245 RE |
283 | arm_frame_args_address (struct frame_info *fi) |
284 | { | |
285 | return fi->frame; | |
286 | } | |
287 | ||
288 | /* The address of the local variables in the frame. */ | |
148754e5 | 289 | static CORE_ADDR |
0defa245 RE |
290 | arm_frame_locals_address (struct frame_info *fi) |
291 | { | |
292 | return fi->frame; | |
293 | } | |
294 | ||
295 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 296 | static int |
0defa245 RE |
297 | arm_frame_num_args (struct frame_info *fi) |
298 | { | |
299 | /* We have no way of knowing. */ | |
300 | return -1; | |
301 | } | |
302 | ||
c906108c | 303 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
304 | push {r7, lr} |
305 | add sp, sp, #-28 | |
306 | add r7, sp, #12 | |
c906108c | 307 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
308 | mov r7, sp |
309 | ||
310 | or like this: | |
311 | push {r7, lr} | |
312 | mov r7, sp | |
313 | sub sp, #12 | |
314 | ||
315 | or, on tpcs, like this: | |
316 | sub sp,#16 | |
317 | push {r7, lr} | |
318 | (many instructions) | |
319 | mov r7, sp | |
320 | sub sp, #12 | |
321 | ||
322 | There is always one instruction of three classes: | |
323 | 1 - push | |
324 | 2 - setting of r7 | |
325 | 3 - adjusting of sp | |
326 | ||
327 | When we have found at least one of each class we are done with the prolog. | |
328 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 329 | */ |
c906108c SS |
330 | |
331 | static CORE_ADDR | |
c7885828 | 332 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
333 | { |
334 | CORE_ADDR current_pc; | |
da3c6d4a MS |
335 | /* findmask: |
336 | bit 0 - push { rlist } | |
337 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
338 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
339 | */ | |
340 | int findmask = 0; | |
341 | ||
94c30b78 MS |
342 | for (current_pc = pc; |
343 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 344 | current_pc += 2) |
c906108c SS |
345 | { |
346 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
347 | ||
94c30b78 | 348 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 349 | { |
94c30b78 | 350 | findmask |= 1; /* push found */ |
da59e081 | 351 | } |
da3c6d4a MS |
352 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
353 | sub sp, #simm */ | |
da59e081 | 354 | { |
94c30b78 | 355 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
356 | continue; |
357 | else | |
94c30b78 | 358 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
359 | } |
360 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
361 | { | |
94c30b78 | 362 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
363 | } |
364 | else if (insn == 0x466f) /* mov r7, sp */ | |
365 | { | |
94c30b78 | 366 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 367 | } |
3d74b771 FF |
368 | else if (findmask == (4+2+1)) |
369 | { | |
da3c6d4a MS |
370 | /* We have found one of each type of prologue instruction */ |
371 | break; | |
3d74b771 | 372 | } |
da59e081 | 373 | else |
94c30b78 | 374 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 375 | instruction from outside the prolog scheduled here for |
94c30b78 | 376 | optimization. */ |
da3c6d4a | 377 | continue; |
c906108c SS |
378 | } |
379 | ||
380 | return current_pc; | |
381 | } | |
382 | ||
da3c6d4a MS |
383 | /* Advance the PC across any function entry prologue instructions to |
384 | reach some "real" code. | |
34e8f22d RE |
385 | |
386 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 387 | prologue: |
c906108c | 388 | |
c5aa993b JM |
389 | mov ip, sp |
390 | [stmfd sp!, {a1,a2,a3,a4}] | |
391 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
392 | [stfe f7, [sp, #-12]!] |
393 | [stfe f6, [sp, #-12]!] | |
394 | [stfe f5, [sp, #-12]!] | |
395 | [stfe f4, [sp, #-12]!] | |
396 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 397 | |
34e8f22d | 398 | static CORE_ADDR |
ed9a39eb | 399 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
400 | { |
401 | unsigned long inst; | |
402 | CORE_ADDR skip_pc; | |
b8d5e71d | 403 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 404 | char *func_name; |
c906108c SS |
405 | struct symtab_and_line sal; |
406 | ||
848cfffb AC |
407 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
408 | if (USE_GENERIC_DUMMY_FRAMES | |
409 | && PC_IN_CALL_DUMMY (pc, 0, 0)) | |
410 | return pc; | |
411 | ||
96baa820 | 412 | /* See what the symbol table says. */ |
ed9a39eb | 413 | |
50f6fb4b | 414 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 415 | { |
50f6fb4b CV |
416 | struct symbol *sym; |
417 | ||
418 | /* Found a function. */ | |
419 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
420 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
421 | { | |
94c30b78 | 422 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
423 | sal = find_pc_line (func_addr, 0); |
424 | if ((sal.line != 0) && (sal.end < func_end)) | |
425 | return sal.end; | |
426 | } | |
c906108c SS |
427 | } |
428 | ||
429 | /* Check if this is Thumb code. */ | |
430 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 431 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
432 | |
433 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 434 | by disassembling the instructions. */ |
c906108c | 435 | |
b8d5e71d MS |
436 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
437 | if (func_end == 0 || func_end > pc + 64) | |
438 | func_end = pc + 64; | |
c906108c | 439 | |
b8d5e71d | 440 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 441 | { |
f43845b3 | 442 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 443 | |
b8d5e71d MS |
444 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
445 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
446 | continue; | |
c906108c | 447 | |
b8d5e71d MS |
448 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
449 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
450 | continue; | |
c906108c | 451 | |
b8d5e71d MS |
452 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
453 | continue; | |
c906108c | 454 | |
b8d5e71d MS |
455 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
456 | continue; | |
11d3b27d | 457 | |
b8d5e71d MS |
458 | /* Any insns after this point may float into the code, if it makes |
459 | for better instruction scheduling, so we skip them only if we | |
460 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 461 | |
b8d5e71d MS |
462 | /* We may have either one sfmfd instruction here, or several stfe |
463 | insns, depending on the version of floating point code we | |
464 | support. */ | |
465 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
466 | continue; | |
467 | ||
468 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
469 | continue; | |
470 | ||
471 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
472 | continue; | |
473 | ||
474 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
475 | continue; | |
476 | ||
477 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
478 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
479 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
480 | continue; | |
481 | ||
482 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
483 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
484 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
485 | continue; | |
486 | ||
487 | /* Un-recognized instruction; stop scanning. */ | |
488 | break; | |
f43845b3 | 489 | } |
c906108c | 490 | |
b8d5e71d | 491 | return skip_pc; /* End of prologue */ |
c906108c | 492 | } |
94c30b78 | 493 | |
c5aa993b | 494 | /* *INDENT-OFF* */ |
c906108c SS |
495 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
496 | This function decodes a Thumb function prologue to determine: | |
497 | 1) the size of the stack frame | |
498 | 2) which registers are saved on it | |
499 | 3) the offsets of saved regs | |
500 | 4) the offset from the stack pointer to the frame pointer | |
501 | This information is stored in the "extra" fields of the frame_info. | |
502 | ||
da59e081 JM |
503 | A typical Thumb function prologue would create this stack frame |
504 | (offsets relative to FP) | |
c906108c SS |
505 | old SP -> 24 stack parameters |
506 | 20 LR | |
507 | 16 R7 | |
508 | R7 -> 0 local variables (16 bytes) | |
509 | SP -> -12 additional stack space (12 bytes) | |
510 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
511 | 12 bytes. The frame register is R7. |
512 | ||
da3c6d4a MS |
513 | The comments for thumb_skip_prolog() describe the algorithm we use |
514 | to detect the end of the prolog. */ | |
c5aa993b JM |
515 | /* *INDENT-ON* */ |
516 | ||
c906108c | 517 | static void |
ed9a39eb | 518 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
519 | { |
520 | CORE_ADDR prologue_start; | |
521 | CORE_ADDR prologue_end; | |
522 | CORE_ADDR current_pc; | |
94c30b78 | 523 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
524 | int saved_reg[16]; |
525 | /* findmask: | |
526 | bit 0 - push { rlist } | |
527 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
528 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
529 | */ | |
530 | int findmask = 0; | |
c5aa993b | 531 | int i; |
c906108c | 532 | |
848cfffb AC |
533 | /* Don't try to scan dummy frames. */ |
534 | if (USE_GENERIC_DUMMY_FRAMES | |
535 | && fi != NULL | |
536 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
537 | return; | |
538 | ||
c5aa993b | 539 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
540 | { |
541 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
542 | ||
94c30b78 | 543 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
544 | prologue_end = fi->pc; |
545 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
94c30b78 | 546 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
547 | } |
548 | else | |
da3c6d4a MS |
549 | /* We're in the boondocks: allow for |
550 | 16 pushes, an add, and "mv fp,sp". */ | |
551 | prologue_end = prologue_start + 40; | |
c906108c SS |
552 | |
553 | prologue_end = min (prologue_end, fi->pc); | |
554 | ||
555 | /* Initialize the saved register map. When register H is copied to | |
556 | register L, we will put H in saved_reg[L]. */ | |
557 | for (i = 0; i < 16; i++) | |
558 | saved_reg[i] = i; | |
559 | ||
560 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
561 | frame pointer, adjust the stack pointer, and save registers. |
562 | Do this until all basic prolog instructions are found. */ | |
c906108c | 563 | |
c3b4394c | 564 | fi->extra_info->framesize = 0; |
da59e081 JM |
565 | for (current_pc = prologue_start; |
566 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
567 | current_pc += 2) | |
c906108c SS |
568 | { |
569 | unsigned short insn; | |
570 | int regno; | |
571 | int offset; | |
572 | ||
573 | insn = read_memory_unsigned_integer (current_pc, 2); | |
574 | ||
c5aa993b | 575 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 576 | { |
da59e081 | 577 | int mask; |
94c30b78 | 578 | findmask |= 1; /* push found */ |
c906108c SS |
579 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
580 | whether to save LR (R14). */ | |
da59e081 | 581 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 582 | |
b8d5e71d | 583 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 584 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 585 | if (mask & (1 << regno)) |
c5aa993b | 586 | { |
c3b4394c RE |
587 | fi->extra_info->framesize += 4; |
588 | fi->saved_regs[saved_reg[regno]] = | |
589 | -(fi->extra_info->framesize); | |
da3c6d4a MS |
590 | /* Reset saved register map. */ |
591 | saved_reg[regno] = regno; | |
c906108c SS |
592 | } |
593 | } | |
da3c6d4a MS |
594 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
595 | sub sp, #simm */ | |
c906108c | 596 | { |
b8d5e71d | 597 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
598 | continue; |
599 | else | |
94c30b78 | 600 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 601 | |
94c30b78 MS |
602 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
603 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 604 | { |
c3b4394c | 605 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
606 | offset = -offset; |
607 | } | |
c3b4394c | 608 | fi->extra_info->framesize -= offset; |
c906108c SS |
609 | } |
610 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
611 | { | |
94c30b78 | 612 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
613 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
614 | /* get scaled offset */ | |
615 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 616 | } |
da59e081 | 617 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 618 | { |
94c30b78 | 619 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
620 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
621 | fi->extra_info->frameoffset = 0; | |
34e8f22d | 622 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
623 | } |
624 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
625 | { | |
da3c6d4a | 626 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 627 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 628 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
629 | } |
630 | else | |
da3c6d4a MS |
631 | /* Something in the prolog that we don't care about or some |
632 | instruction from outside the prolog scheduled here for | |
633 | optimization. */ | |
634 | continue; | |
c906108c SS |
635 | } |
636 | } | |
637 | ||
ed9a39eb JM |
638 | /* Check if prologue for this frame's PC has already been scanned. If |
639 | it has, copy the relevant information about that prologue and | |
c906108c SS |
640 | return non-zero. Otherwise do not copy anything and return zero. |
641 | ||
642 | The information saved in the cache includes: | |
c5aa993b JM |
643 | * the frame register number; |
644 | * the size of the stack frame; | |
645 | * the offsets of saved regs (relative to the old SP); and | |
646 | * the offset from the stack pointer to the frame pointer | |
c906108c | 647 | |
ed9a39eb JM |
648 | The cache contains only one entry, since this is adequate for the |
649 | typical sequence of prologue scan requests we get. When performing | |
650 | a backtrace, GDB will usually ask to scan the same function twice | |
651 | in a row (once to get the frame chain, and once to fill in the | |
652 | extra frame information). */ | |
c906108c SS |
653 | |
654 | static struct frame_info prologue_cache; | |
655 | ||
656 | static int | |
ed9a39eb | 657 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
658 | { |
659 | int i; | |
660 | ||
661 | if (fi->pc == prologue_cache.pc) | |
662 | { | |
c3b4394c RE |
663 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
664 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
665 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
666 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
667 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
668 | return 1; |
669 | } | |
670 | else | |
671 | return 0; | |
672 | } | |
673 | ||
674 | ||
ed9a39eb | 675 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
676 | |
677 | static void | |
ed9a39eb | 678 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
679 | { |
680 | int i; | |
681 | ||
c5aa993b | 682 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
683 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
684 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
685 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 686 | |
c3b4394c RE |
687 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
688 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
689 | } |
690 | ||
691 | ||
ed9a39eb | 692 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
693 | 1) the size of the stack frame |
694 | 2) which registers are saved on it | |
695 | 3) the offsets of saved regs | |
696 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
697 | This information is stored in the "extra" fields of the frame_info. |
698 | ||
96baa820 JM |
699 | There are two basic forms for the ARM prologue. The fixed argument |
700 | function call will look like: | |
ed9a39eb JM |
701 | |
702 | mov ip, sp | |
703 | stmfd sp!, {fp, ip, lr, pc} | |
704 | sub fp, ip, #4 | |
705 | [sub sp, sp, #4] | |
96baa820 | 706 | |
c906108c | 707 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
708 | IP -> 4 (caller's stack) |
709 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
710 | -4 LR (return address in caller) | |
711 | -8 IP (copy of caller's SP) | |
712 | -12 FP (caller's FP) | |
713 | SP -> -28 Local variables | |
714 | ||
c906108c | 715 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
716 | 28 bytes. The stmfd call can also save any of the vN registers it |
717 | plans to use, which increases the frame size accordingly. | |
718 | ||
719 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
720 | because the ARM Store instructions always store PC + 8 when you read | |
721 | the PC register. | |
ed9a39eb | 722 | |
96baa820 JM |
723 | A variable argument function call will look like: |
724 | ||
ed9a39eb JM |
725 | mov ip, sp |
726 | stmfd sp!, {a1, a2, a3, a4} | |
727 | stmfd sp!, {fp, ip, lr, pc} | |
728 | sub fp, ip, #20 | |
729 | ||
96baa820 | 730 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
731 | IP -> 20 (caller's stack) |
732 | 16 A4 | |
733 | 12 A3 | |
734 | 8 A2 | |
735 | 4 A1 | |
736 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
737 | -4 LR (return address in caller) | |
738 | -8 IP (copy of caller's SP) | |
739 | -12 FP (caller's FP) | |
740 | SP -> -28 Local variables | |
96baa820 JM |
741 | |
742 | The frame size would thus be 48 bytes, and the frame offset would be | |
743 | 28 bytes. | |
744 | ||
745 | There is another potential complication, which is that the optimizer | |
746 | will try to separate the store of fp in the "stmfd" instruction from | |
747 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
748 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
749 | ||
750 | Also, note, the original version of the ARM toolchain claimed that there | |
751 | should be an | |
752 | ||
753 | instruction at the end of the prologue. I have never seen GCC produce | |
754 | this, and the ARM docs don't mention it. We still test for it below in | |
755 | case it happens... | |
ed9a39eb JM |
756 | |
757 | */ | |
c906108c SS |
758 | |
759 | static void | |
ed9a39eb | 760 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
761 | { |
762 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 763 | LONGEST return_value; |
c906108c SS |
764 | CORE_ADDR prologue_start, prologue_end, current_pc; |
765 | ||
94c30b78 | 766 | /* Check if this function is already in the cache of frame information. */ |
c906108c SS |
767 | if (check_prologue_cache (fi)) |
768 | return; | |
769 | ||
770 | /* Assume there is no frame until proven otherwise. */ | |
34e8f22d | 771 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
772 | fi->extra_info->framesize = 0; |
773 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
774 | |
775 | /* Check for Thumb prologue. */ | |
776 | if (arm_pc_is_thumb (fi->pc)) | |
777 | { | |
778 | thumb_scan_prologue (fi); | |
779 | save_prologue_cache (fi); | |
780 | return; | |
781 | } | |
782 | ||
783 | /* Find the function prologue. If we can't find the function in | |
784 | the symbol table, peek in the stack frame to find the PC. */ | |
785 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
786 | { | |
2a451106 KB |
787 | /* One way to find the end of the prologue (which works well |
788 | for unoptimized code) is to do the following: | |
789 | ||
790 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
791 | ||
792 | if (sal.line == 0) | |
793 | prologue_end = fi->pc; | |
794 | else if (sal.end < prologue_end) | |
795 | prologue_end = sal.end; | |
796 | ||
797 | This mechanism is very accurate so long as the optimizer | |
798 | doesn't move any instructions from the function body into the | |
799 | prologue. If this happens, sal.end will be the last | |
800 | instruction in the first hunk of prologue code just before | |
801 | the first instruction that the scheduler has moved from | |
802 | the body to the prologue. | |
803 | ||
804 | In order to make sure that we scan all of the prologue | |
805 | instructions, we use a slightly less accurate mechanism which | |
806 | may scan more than necessary. To help compensate for this | |
807 | lack of accuracy, the prologue scanning loop below contains | |
808 | several clauses which'll cause the loop to terminate early if | |
809 | an implausible prologue instruction is encountered. | |
810 | ||
811 | The expression | |
812 | ||
813 | prologue_start + 64 | |
814 | ||
815 | is a suitable endpoint since it accounts for the largest | |
816 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 817 | the scheduler. */ |
2a451106 KB |
818 | |
819 | if (prologue_end > prologue_start + 64) | |
820 | { | |
94c30b78 | 821 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 822 | } |
c906108c SS |
823 | } |
824 | else | |
825 | { | |
94c30b78 MS |
826 | /* Get address of the stmfd in the prologue of the callee; |
827 | the saved PC is the address of the stmfd + 8. */ | |
16a0f3e7 EZ |
828 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
829 | return; | |
830 | else | |
831 | { | |
832 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 833 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 834 | } |
c906108c SS |
835 | } |
836 | ||
837 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 838 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 839 | |
96baa820 JM |
840 | Be careful, however, and if it doesn't look like a prologue, |
841 | don't try to scan it. If, for instance, a frameless function | |
842 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 843 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
844 | and other operations that rely on a knowledge of the stack |
845 | traceback. | |
846 | ||
847 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 848 | if we don't see this as the first insn, we will stop. |
c906108c | 849 | |
f43845b3 MS |
850 | [Note: This doesn't seem to be true any longer, so it's now an |
851 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 852 | |
f43845b3 MS |
853 | [Note further: The "mov ip,sp" only seems to be missing in |
854 | frameless functions at optimization level "-O2" or above, | |
855 | in which case it is often (but not always) replaced by | |
b8d5e71d | 856 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 857 | |
f43845b3 MS |
858 | sp_offset = fp_offset = 0; |
859 | ||
94c30b78 MS |
860 | for (current_pc = prologue_start; |
861 | current_pc < prologue_end; | |
f43845b3 | 862 | current_pc += 4) |
96baa820 | 863 | { |
d4473757 KB |
864 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
865 | ||
94c30b78 | 866 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
867 | { |
868 | continue; | |
869 | } | |
94c30b78 | 870 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
871 | { |
872 | /* Function is frameless: extra_info defaults OK? */ | |
873 | continue; | |
874 | } | |
875 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
876 | /* stmfd sp!, {..., fp, ip, lr, pc} |
877 | or | |
878 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 879 | { |
d4473757 | 880 | int mask = insn & 0xffff; |
ed9a39eb | 881 | |
94c30b78 | 882 | /* Calculate offsets of saved registers. */ |
34e8f22d | 883 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
884 | if (mask & (1 << regno)) |
885 | { | |
886 | sp_offset -= 4; | |
c3b4394c | 887 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
888 | } |
889 | } | |
b8d5e71d MS |
890 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
891 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
892 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
893 | { | |
894 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
895 | continue; | |
896 | } | |
897 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
898 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
899 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
900 | { |
901 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
902 | continue; | |
903 | } | |
d4473757 KB |
904 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
905 | { | |
94c30b78 MS |
906 | unsigned imm = insn & 0xff; /* immediate value */ |
907 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
908 | imm = (imm >> rot) | (imm << (32 - rot)); |
909 | fp_offset = -imm; | |
34e8f22d | 910 | fi->extra_info->framereg = ARM_FP_REGNUM; |
d4473757 KB |
911 | } |
912 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
913 | { | |
94c30b78 MS |
914 | unsigned imm = insn & 0xff; /* immediate value */ |
915 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
916 | imm = (imm >> rot) | (imm << (32 - rot)); |
917 | sp_offset -= imm; | |
918 | } | |
919 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
920 | { | |
921 | sp_offset -= 12; | |
34e8f22d | 922 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
c3b4394c | 923 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
924 | } |
925 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
926 | { | |
927 | int n_saved_fp_regs; | |
928 | unsigned int fp_start_reg, fp_bound_reg; | |
929 | ||
94c30b78 | 930 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 931 | { |
d4473757 KB |
932 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
933 | n_saved_fp_regs = 3; | |
934 | else | |
935 | n_saved_fp_regs = 1; | |
96baa820 | 936 | } |
d4473757 | 937 | else |
96baa820 | 938 | { |
d4473757 KB |
939 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
940 | n_saved_fp_regs = 2; | |
941 | else | |
942 | n_saved_fp_regs = 4; | |
96baa820 | 943 | } |
d4473757 | 944 | |
34e8f22d | 945 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
946 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
947 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
948 | { |
949 | sp_offset -= 12; | |
c3b4394c | 950 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 951 | } |
c906108c | 952 | } |
d4473757 | 953 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 954 | break; /* Condition not true, exit early */ |
b8d5e71d | 955 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 956 | break; /* Don't scan past a block load */ |
d4473757 KB |
957 | else |
958 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 959 | so we just skip what we don't recognize. */ |
d4473757 | 960 | continue; |
c906108c SS |
961 | } |
962 | ||
94c30b78 MS |
963 | /* The frame size is just the negative of the offset (from the |
964 | original SP) of the last thing thing we pushed on the stack. | |
965 | The frame offset is [new FP] - [new SP]. */ | |
c3b4394c | 966 | fi->extra_info->framesize = -sp_offset; |
34e8f22d | 967 | if (fi->extra_info->framereg == ARM_FP_REGNUM) |
c3b4394c | 968 | fi->extra_info->frameoffset = fp_offset - sp_offset; |
d4473757 | 969 | else |
c3b4394c | 970 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 971 | |
c906108c SS |
972 | save_prologue_cache (fi); |
973 | } | |
974 | ||
ed9a39eb JM |
975 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
976 | One thing we might want to do here is to check REGNUM against the | |
977 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
978 | the stack somewhere. This would provide a graceful failure mode | |
979 | when trying to get the value of caller-saves registers for an inner | |
980 | frame. */ | |
c906108c SS |
981 | |
982 | static CORE_ADDR | |
ed9a39eb | 983 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 984 | { |
848cfffb AC |
985 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
986 | needed. Instead the (still being written) register unwind | |
987 | function could be called directly. */ | |
c906108c | 988 | for (; fi; fi = fi->next) |
848cfffb AC |
989 | { |
990 | if (USE_GENERIC_DUMMY_FRAMES | |
991 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
992 | { | |
993 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
994 | } | |
995 | else if (fi->saved_regs[regnum] != 0) | |
996 | { | |
997 | /* NOTE: cagney/2002-05-03: This would normally need to | |
998 | handle ARM_SP_REGNUM as a special case as, according to | |
999 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
1000 | SP value not its address. It appears that the ARM isn't | |
1001 | doing this though. */ | |
1002 | return read_memory_integer (fi->saved_regs[regnum], | |
1003 | REGISTER_RAW_SIZE (regnum)); | |
1004 | } | |
1005 | } | |
c906108c SS |
1006 | return read_register (regnum); |
1007 | } | |
148754e5 RE |
1008 | /* Function: frame_chain Given a GDB frame, determine the address of |
1009 | the calling function's frame. This will be used to create a new | |
1010 | GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC | |
1011 | will be called for the new frame. For ARM, we save the frame size | |
1012 | when we initialize the frame_info. */ | |
c5aa993b | 1013 | |
148754e5 | 1014 | static CORE_ADDR |
ed9a39eb | 1015 | arm_frame_chain (struct frame_info *fi) |
c906108c | 1016 | { |
848cfffb | 1017 | CORE_ADDR caller_pc; |
c3b4394c | 1018 | int framereg = fi->extra_info->framereg; |
c906108c | 1019 | |
848cfffb AC |
1020 | if (USE_GENERIC_DUMMY_FRAMES |
1021 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
1022 | /* A generic call dummy's frame is the same as caller's. */ | |
1023 | return fi->frame; | |
1024 | ||
c906108c SS |
1025 | if (fi->pc < LOWEST_PC) |
1026 | return 0; | |
1027 | ||
1028 | /* If the caller is the startup code, we're at the end of the chain. */ | |
1029 | caller_pc = FRAME_SAVED_PC (fi); | |
c906108c SS |
1030 | |
1031 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1032 | the frame register of the caller is different from ours. | |
1033 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 1034 | frame register number. */ |
c3b4394c RE |
1035 | /* XXX Fixme, we should try to do this without creating a temporary |
1036 | caller_fi. */ | |
c906108c SS |
1037 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1038 | { | |
c3b4394c RE |
1039 | struct frame_info caller_fi; |
1040 | struct cleanup *old_chain; | |
1041 | ||
1042 | /* Create a temporary frame suitable for scanning the caller's | |
1043 | prologue. (Ugh.) */ | |
c5aa993b | 1044 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1045 | caller_fi.extra_info = (struct frame_extra_info *) |
1046 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1047 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1048 | caller_fi.saved_regs = (CORE_ADDR *) | |
1049 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1050 | make_cleanup (xfree, caller_fi.saved_regs); | |
1051 | ||
1052 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1053 | caller_fi.pc = caller_pc; |
c5aa993b | 1054 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1055 | framereg = caller_fi.extra_info->framereg; |
1056 | ||
1057 | /* Deallocate the storage associated with the temporary frame | |
1058 | created above. */ | |
1059 | do_cleanups (old_chain); | |
c906108c SS |
1060 | } |
1061 | ||
1062 | /* If the caller used a frame register, return its value. | |
1063 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1064 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1065 | return arm_find_callers_reg (fi, framereg); |
1066 | else | |
c3b4394c | 1067 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1068 | } |
1069 | ||
ed9a39eb JM |
1070 | /* This function actually figures out the frame address for a given pc |
1071 | and sp. This is tricky because we sometimes don't use an explicit | |
1072 | frame pointer, and the previous stack pointer isn't necessarily | |
1073 | recorded on the stack. The only reliable way to get this info is | |
1074 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1075 | this is the next frame up the chain AFTER a frameless function. If | |
1076 | this is true, then the frame value for this frame is still in the | |
1077 | fp register. */ | |
c906108c | 1078 | |
148754e5 | 1079 | static void |
ed9a39eb | 1080 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1081 | { |
1082 | int reg; | |
f079148d | 1083 | CORE_ADDR sp; |
c906108c | 1084 | |
c3b4394c RE |
1085 | if (fi->saved_regs == NULL) |
1086 | frame_saved_regs_zalloc (fi); | |
1087 | ||
1088 | fi->extra_info = (struct frame_extra_info *) | |
1089 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1090 | ||
1091 | fi->extra_info->framesize = 0; | |
1092 | fi->extra_info->frameoffset = 0; | |
1093 | fi->extra_info->framereg = 0; | |
1094 | ||
c906108c SS |
1095 | if (fi->next) |
1096 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1097 | ||
c3b4394c | 1098 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1099 | |
da3c6d4a MS |
1100 | /* Compute stack pointer for this frame. We use this value for both |
1101 | the sigtramp and call dummy cases. */ | |
f079148d KB |
1102 | if (!fi->next) |
1103 | sp = read_sp(); | |
848cfffb AC |
1104 | else if (USE_GENERIC_DUMMY_FRAMES |
1105 | && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) | |
1106 | /* For generic dummy frames, pull the value direct from the frame. | |
1107 | Having an unwind function to do this would be nice. */ | |
1108 | sp = generic_read_register_dummy (fi->next->pc, fi->next->frame, | |
1109 | ARM_SP_REGNUM); | |
f079148d | 1110 | else |
c3b4394c RE |
1111 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1112 | + fi->next->extra_info->framesize); | |
f079148d | 1113 | |
d7bd68ca | 1114 | /* Determine whether or not we're in a sigtramp frame. |
2a451106 KB |
1115 | Unfortunately, it isn't sufficient to test |
1116 | fi->signal_handler_caller because this value is sometimes set | |
1117 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
d7bd68ca AC |
1118 | fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we |
1119 | need to use the sigcontext addresses for the saved registers. | |
2a451106 | 1120 | |
d7bd68ca AC |
1121 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1122 | against the name of the function, the code below will have to be | |
1123 | changed to first fetch the name of the function and then pass | |
1124 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1125 | |
3bb04bdd | 1126 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
d7bd68ca | 1127 | && (fi->signal_handler_caller || PC_IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1128 | { |
2a451106 | 1129 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1130 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 | 1131 | |
94c30b78 | 1132 | /* FIXME: What about thumb mode? */ |
34e8f22d | 1133 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
1134 | fi->frame = |
1135 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1136 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1137 | fi->extra_info->framesize = 0; | |
1138 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1139 | |
1140 | } | |
f079148d KB |
1141 | else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame)) |
1142 | { | |
1143 | CORE_ADDR rp; | |
1144 | CORE_ADDR callers_sp; | |
1145 | ||
1146 | /* Set rp point at the high end of the saved registers. */ | |
1147 | rp = fi->frame - REGISTER_SIZE; | |
1148 | ||
1149 | /* Fill in addresses of saved registers. */ | |
34e8f22d RE |
1150 | fi->saved_regs[ARM_PS_REGNUM] = rp; |
1151 | rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM); | |
1152 | for (reg = ARM_PC_REGNUM; reg >= 0; reg--) | |
f079148d | 1153 | { |
c3b4394c | 1154 | fi->saved_regs[reg] = rp; |
f079148d KB |
1155 | rp -= REGISTER_RAW_SIZE (reg); |
1156 | } | |
1157 | ||
34e8f22d RE |
1158 | callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM], |
1159 | REGISTER_RAW_SIZE (ARM_SP_REGNUM)); | |
1160 | fi->extra_info->framereg = ARM_FP_REGNUM; | |
c3b4394c RE |
1161 | fi->extra_info->framesize = callers_sp - sp; |
1162 | fi->extra_info->frameoffset = fi->frame - sp; | |
f079148d | 1163 | } |
2a451106 | 1164 | else |
c906108c SS |
1165 | { |
1166 | arm_scan_prologue (fi); | |
1167 | ||
104c1213 | 1168 | if (!fi->next) |
94c30b78 | 1169 | /* This is the innermost frame? */ |
c3b4394c | 1170 | fi->frame = read_register (fi->extra_info->framereg); |
848cfffb AC |
1171 | else if (USE_GENERIC_DUMMY_FRAMES |
1172 | && PC_IN_CALL_DUMMY (fi->next->pc, 0, 0)) | |
1173 | /* Next inner most frame is a dummy, just grab its frame. | |
1174 | Dummy frames always have the same FP as their caller. */ | |
1175 | fi->frame = fi->next->frame; | |
34e8f22d | 1176 | else if (fi->extra_info->framereg == ARM_FP_REGNUM |
c3b4394c | 1177 | || fi->extra_info->framereg == THUMB_FP_REGNUM) |
ed9a39eb JM |
1178 | { |
1179 | /* not the innermost frame */ | |
94c30b78 | 1180 | /* If we have an FP, the callee saved it. */ |
c3b4394c | 1181 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1182 | fi->frame = |
c3b4394c RE |
1183 | read_memory_integer (fi->next |
1184 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1185 | else if (fromleaf) |
1186 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1187 | still in the frame pointer register on the board... */ |
ed9a39eb JM |
1188 | fi->frame = read_fp (); |
1189 | } | |
c906108c | 1190 | |
ed9a39eb JM |
1191 | /* Calculate actual addresses of saved registers using offsets |
1192 | determined by arm_scan_prologue. */ | |
c906108c | 1193 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1194 | if (fi->saved_regs[reg] != 0) |
1195 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1196 | - fi->extra_info->frameoffset); | |
c906108c SS |
1197 | } |
1198 | } | |
1199 | ||
1200 | ||
34e8f22d | 1201 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1202 | is saved in the stack anywhere, otherwise we get it from the |
1203 | registers. | |
c906108c SS |
1204 | |
1205 | The old definition of this function was a macro: | |
c5aa993b | 1206 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1207 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1208 | |
148754e5 | 1209 | static CORE_ADDR |
ed9a39eb | 1210 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1211 | { |
848cfffb AC |
1212 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
1213 | if (USE_GENERIC_DUMMY_FRAMES | |
1214 | && PC_IN_CALL_DUMMY (fi->pc, 0, 0)) | |
34e8f22d | 1215 | return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM); |
848cfffb | 1216 | |
c3b4394c RE |
1217 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
1218 | fi->frame)) | |
f079148d | 1219 | { |
34e8f22d RE |
1220 | return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM], |
1221 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); | |
f079148d KB |
1222 | } |
1223 | else | |
c906108c | 1224 | { |
34e8f22d | 1225 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1226 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1227 | } | |
1228 | } | |
1229 | ||
c906108c SS |
1230 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1231 | Examine the Program Status Register to decide which state we're in. */ | |
1232 | ||
148754e5 RE |
1233 | static CORE_ADDR |
1234 | arm_read_fp (void) | |
c906108c | 1235 | { |
34e8f22d | 1236 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1237 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1238 | else | |
34e8f22d | 1239 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1240 | } |
1241 | ||
148754e5 RE |
1242 | /* Store into a struct frame_saved_regs the addresses of the saved |
1243 | registers of frame described by FRAME_INFO. This includes special | |
1244 | registers such as PC and FP saved in special ways in the stack | |
1245 | frame. SP is even more special: the address we return for it IS | |
1246 | the sp for the next frame. */ | |
c906108c | 1247 | |
148754e5 | 1248 | static void |
c3b4394c | 1249 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1250 | { |
c3b4394c RE |
1251 | |
1252 | if (fip->saved_regs) | |
1253 | return; | |
1254 | ||
1255 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1256 | } |
1257 | ||
848cfffb AC |
1258 | /* Set the return address for a generic dummy frame. ARM uses the |
1259 | entry point. */ | |
1260 | ||
1261 | static CORE_ADDR | |
1262 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1263 | { | |
1264 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1265 | return sp; | |
1266 | } | |
1267 | ||
148754e5 RE |
1268 | /* Push an empty stack frame, to record the current PC, etc. */ |
1269 | ||
1270 | static void | |
ed9a39eb | 1271 | arm_push_dummy_frame (void) |
c906108c | 1272 | { |
34e8f22d | 1273 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1274 | CORE_ADDR sp = old_sp; |
1275 | CORE_ADDR fp, prologue_start; | |
1276 | int regnum; | |
1277 | ||
1278 | /* Push the two dummy prologue instructions in reverse order, | |
1279 | so that they'll be in the correct low-to-high order in memory. */ | |
1280 | /* sub fp, ip, #4 */ | |
1281 | sp = push_word (sp, 0xe24cb004); | |
1282 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1283 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1284 | ||
ed9a39eb JM |
1285 | /* Push a pointer to the dummy prologue + 12, because when stm |
1286 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1287 | instruction itself plus 12. */ |
1288 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1289 | |
f079148d | 1290 | /* Push the processor status. */ |
34e8f22d | 1291 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1292 | |
1293 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1294 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1295 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1296 | |
f079148d | 1297 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1298 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1299 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1300 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1301 | } |
1302 | ||
6eb69eab RE |
1303 | /* CALL_DUMMY_WORDS: |
1304 | This sequence of words is the instructions | |
1305 | ||
1306 | mov lr,pc | |
1307 | mov pc,r4 | |
1308 | illegal | |
1309 | ||
1310 | Note this is 12 bytes. */ | |
1311 | ||
34e8f22d | 1312 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1313 | { |
1314 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1315 | }; | |
1316 | ||
3fb4b924 RE |
1317 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1318 | breakpoint to the proper address in the call dummy, so that | |
1319 | `finish' after a stop in a call dummy works. | |
1320 | ||
d7b486e7 RE |
1321 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1322 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1323 | followed by a call to run_stack_dummy, which is the only function | |
1324 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1325 | |
1326 | ||
1327 | static void | |
1328 | arm_set_call_dummy_breakpoint_offset (void) | |
1329 | { | |
1330 | if (caller_is_thumb) | |
1331 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1332 | else | |
1333 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1334 | } | |
1335 | ||
c906108c | 1336 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1337 | in Thumb or ARM mode, and whether the target function is Thumb or |
1338 | ARM. There are three different situations requiring three | |
c906108c SS |
1339 | different dummies: |
1340 | ||
1341 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1342 | been copied into the dummy parameter to this function. |
c906108c | 1343 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1344 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1345 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1346 | works for calling both ARM and Thumb functions. |
c906108c | 1347 | |
ed9a39eb JM |
1348 | All three call dummies expect to receive the target function |
1349 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1350 | |
34e8f22d | 1351 | static void |
ed9a39eb | 1352 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1353 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1354 | { |
1355 | static short thumb_dummy[4] = | |
1356 | { | |
c5aa993b JM |
1357 | 0xf000, 0xf801, /* bl label */ |
1358 | 0xdf18, /* swi 24 */ | |
1359 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1360 | }; |
1361 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1362 | ||
94c30b78 | 1363 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1364 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1365 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1366 | |
ed9a39eb JM |
1367 | /* If the target function is Thumb, set the low bit of the function |
1368 | address. And if the CPU is currently in ARM mode, patch the | |
1369 | second instruction of call dummy to use a BX instruction to | |
1370 | switch to Thumb mode. */ | |
c906108c SS |
1371 | target_is_thumb = arm_pc_is_thumb (fun); |
1372 | if (target_is_thumb) | |
1373 | { | |
1374 | fun |= 1; | |
1375 | if (!caller_is_thumb) | |
1376 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1377 | } | |
1378 | ||
1379 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1380 | instead of the ARM one that's already been copied. This will | |
1381 | work for both Thumb and ARM target functions. */ | |
1382 | if (caller_is_thumb) | |
1383 | { | |
1384 | int i; | |
1385 | char *p = dummy; | |
1386 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1387 | ||
1388 | for (i = 0; i < len; i++) | |
1389 | { | |
1390 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1391 | p += sizeof (thumb_dummy[0]); | |
1392 | } | |
1393 | } | |
1394 | ||
ed9a39eb | 1395 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1396 | the PC. */ |
c906108c SS |
1397 | write_register (4, fun); |
1398 | } | |
1399 | ||
ed9a39eb JM |
1400 | /* Note: ScottB |
1401 | ||
1402 | This function does not support passing parameters using the FPA | |
1403 | variant of the APCS. It passes any floating point arguments in the | |
1404 | general registers and/or on the stack. */ | |
c906108c | 1405 | |
39bbf761 | 1406 | static CORE_ADDR |
ea7c478f | 1407 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1408 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1409 | { |
ed9a39eb JM |
1410 | char *fp; |
1411 | int argnum, argreg, nstack_size; | |
1412 | ||
1413 | /* Walk through the list of args and determine how large a temporary | |
1414 | stack is required. Need to take care here as structs may be | |
1415 | passed on the stack, and we have to to push them. */ | |
1416 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
94c30b78 | 1417 | if (struct_return) /* The struct address goes in A1. */ |
ed9a39eb JM |
1418 | nstack_size += REGISTER_SIZE; |
1419 | ||
1420 | /* Walk through the arguments and add their size to nstack_size. */ | |
1421 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1422 | { |
c906108c | 1423 | int len; |
ed9a39eb JM |
1424 | struct type *arg_type; |
1425 | ||
1426 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1427 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1428 | |
6b230f1b | 1429 | nstack_size += len; |
ed9a39eb | 1430 | } |
c906108c | 1431 | |
ed9a39eb JM |
1432 | /* Allocate room on the stack, and initialize our stack frame |
1433 | pointer. */ | |
1434 | fp = NULL; | |
1435 | if (nstack_size > 0) | |
1436 | { | |
1437 | sp -= nstack_size; | |
1438 | fp = (char *) sp; | |
1439 | } | |
1440 | ||
1441 | /* Initialize the integer argument register pointer. */ | |
34e8f22d | 1442 | argreg = ARM_A1_REGNUM; |
c906108c | 1443 | |
ed9a39eb JM |
1444 | /* The struct_return pointer occupies the first parameter passing |
1445 | register. */ | |
c906108c | 1446 | if (struct_return) |
c5aa993b | 1447 | write_register (argreg++, struct_addr); |
c906108c | 1448 | |
ed9a39eb JM |
1449 | /* Process arguments from left to right. Store as many as allowed |
1450 | in the parameter passing registers (A1-A4), and save the rest on | |
1451 | the temporary stack. */ | |
c5aa993b | 1452 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1453 | { |
ed9a39eb | 1454 | int len; |
c5aa993b | 1455 | char *val; |
c5aa993b | 1456 | CORE_ADDR regval; |
ed9a39eb JM |
1457 | enum type_code typecode; |
1458 | struct type *arg_type, *target_type; | |
1459 | ||
1460 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1461 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1462 | len = TYPE_LENGTH (arg_type); | |
1463 | typecode = TYPE_CODE (arg_type); | |
1464 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1465 | ||
da59e081 JM |
1466 | #if 1 |
1467 | /* I don't know why this code was disable. The only logical use | |
1468 | for a function pointer is to call that function, so setting | |
94c30b78 | 1469 | the mode bit is perfectly fine. FN */ |
ed9a39eb | 1470 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1471 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1472 | if (TYPE_CODE_PTR == typecode |
1473 | && NULL != target_type | |
1474 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1475 | { |
ed9a39eb | 1476 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1477 | if (arm_pc_is_thumb (regval)) |
1478 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1479 | } | |
c906108c | 1480 | #endif |
ed9a39eb JM |
1481 | /* Copy the argument to general registers or the stack in |
1482 | register-sized pieces. Large arguments are split between | |
1483 | registers and stack. */ | |
1484 | while (len > 0) | |
c906108c | 1485 | { |
ed9a39eb JM |
1486 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1487 | ||
1488 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1489 | { |
ed9a39eb JM |
1490 | /* It's an argument being passed in a general register. */ |
1491 | regval = extract_address (val, partial_len); | |
1492 | write_register (argreg++, regval); | |
c906108c | 1493 | } |
ed9a39eb JM |
1494 | else |
1495 | { | |
1496 | /* Push the arguments onto the stack. */ | |
1497 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1498 | fp += REGISTER_SIZE; | |
1499 | } | |
1500 | ||
1501 | len -= partial_len; | |
1502 | val += partial_len; | |
c906108c SS |
1503 | } |
1504 | } | |
c906108c SS |
1505 | |
1506 | /* Return adjusted stack pointer. */ | |
1507 | return sp; | |
1508 | } | |
1509 | ||
da3c6d4a MS |
1510 | /* Pop the current frame. So long as the frame info has been |
1511 | initialized properly (see arm_init_extra_frame_info), this code | |
1512 | works for dummy frames as well as regular frames. I.e, there's no | |
1513 | need to have a special case for dummy frames. */ | |
148754e5 | 1514 | static void |
ed9a39eb | 1515 | arm_pop_frame (void) |
c906108c | 1516 | { |
c906108c | 1517 | int regnum; |
8b93c638 | 1518 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1519 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1520 | + frame->extra_info->framesize); | |
c906108c | 1521 | |
848cfffb AC |
1522 | if (USE_GENERIC_DUMMY_FRAMES |
1523 | && PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
1524 | { | |
1525 | generic_pop_dummy_frame (); | |
1526 | flush_cached_frames (); | |
1527 | return; | |
1528 | } | |
1529 | ||
f079148d | 1530 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1531 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1532 | write_register (regnum, |
c3b4394c | 1533 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1534 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1535 | |
34e8f22d RE |
1536 | write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame)); |
1537 | write_register (ARM_SP_REGNUM, old_SP); | |
c906108c SS |
1538 | |
1539 | flush_cached_frames (); | |
1540 | } | |
1541 | ||
1542 | static void | |
ed9a39eb | 1543 | print_fpu_flags (int flags) |
c906108c | 1544 | { |
c5aa993b JM |
1545 | if (flags & (1 << 0)) |
1546 | fputs ("IVO ", stdout); | |
1547 | if (flags & (1 << 1)) | |
1548 | fputs ("DVZ ", stdout); | |
1549 | if (flags & (1 << 2)) | |
1550 | fputs ("OFL ", stdout); | |
1551 | if (flags & (1 << 3)) | |
1552 | fputs ("UFL ", stdout); | |
1553 | if (flags & (1 << 4)) | |
1554 | fputs ("INX ", stdout); | |
1555 | putchar ('\n'); | |
c906108c SS |
1556 | } |
1557 | ||
5e74b15c RE |
1558 | /* Print interesting information about the floating point processor |
1559 | (if present) or emulator. */ | |
34e8f22d | 1560 | static void |
5e74b15c | 1561 | arm_print_float_info (void) |
c906108c | 1562 | { |
34e8f22d | 1563 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1564 | int type; |
1565 | ||
1566 | type = (status >> 24) & 127; | |
1567 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1568 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1569 | type); |
1570 | fputs ("mask: ", stdout); | |
1571 | print_fpu_flags (status >> 16); | |
1572 | fputs ("flags: ", stdout); | |
1573 | print_fpu_flags (status); | |
c906108c SS |
1574 | } |
1575 | ||
34e8f22d RE |
1576 | /* Return the GDB type object for the "standard" data type of data in |
1577 | register N. */ | |
1578 | ||
1579 | static struct type * | |
032758dc AC |
1580 | arm_register_type (int regnum) |
1581 | { | |
34e8f22d | 1582 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1583 | { |
d7449b42 | 1584 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1585 | return builtin_type_arm_ext_big; |
1586 | else | |
1587 | return builtin_type_arm_ext_littlebyte_bigword; | |
1588 | } | |
1589 | else | |
1590 | return builtin_type_int32; | |
1591 | } | |
1592 | ||
34e8f22d RE |
1593 | /* Index within `registers' of the first byte of the space for |
1594 | register N. */ | |
1595 | ||
1596 | static int | |
1597 | arm_register_byte (int regnum) | |
1598 | { | |
1599 | if (regnum < ARM_F0_REGNUM) | |
1600 | return regnum * INT_REGISTER_RAW_SIZE; | |
1601 | else if (regnum < ARM_PS_REGNUM) | |
1602 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1603 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1604 | else | |
1605 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1606 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1607 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1608 | } | |
1609 | ||
1610 | /* Number of bytes of storage in the actual machine representation for | |
1611 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1612 | 12 bytes in length. */ | |
1613 | ||
1614 | static int | |
1615 | arm_register_raw_size (int regnum) | |
1616 | { | |
1617 | if (regnum < ARM_F0_REGNUM) | |
1618 | return INT_REGISTER_RAW_SIZE; | |
1619 | else if (regnum < ARM_FPS_REGNUM) | |
1620 | return FP_REGISTER_RAW_SIZE; | |
1621 | else | |
1622 | return STATUS_REGISTER_SIZE; | |
1623 | } | |
1624 | ||
1625 | /* Number of bytes of storage in a program's representation | |
1626 | for register N. */ | |
1627 | static int | |
1628 | arm_register_virtual_size (int regnum) | |
1629 | { | |
1630 | if (regnum < ARM_F0_REGNUM) | |
1631 | return INT_REGISTER_VIRTUAL_SIZE; | |
1632 | else if (regnum < ARM_FPS_REGNUM) | |
1633 | return FP_REGISTER_VIRTUAL_SIZE; | |
1634 | else | |
1635 | return STATUS_REGISTER_SIZE; | |
1636 | } | |
1637 | ||
1638 | ||
a37b3cc0 AC |
1639 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1640 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1641 | It is thought that this is is the floating-point register format on | |
1642 | little-endian systems. */ | |
c906108c | 1643 | |
ed9a39eb JM |
1644 | static void |
1645 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1646 | { |
a37b3cc0 | 1647 | DOUBLEST d; |
d7449b42 | 1648 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1649 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1650 | else | |
1651 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1652 | ptr, &d); | |
1653 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1654 | } |
1655 | ||
34e8f22d | 1656 | static void |
ed9a39eb | 1657 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1658 | { |
a37b3cc0 AC |
1659 | DOUBLEST d; |
1660 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1661 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1662 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1663 | else | |
1664 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1665 | &d, dbl); | |
c906108c | 1666 | } |
ed9a39eb | 1667 | |
c906108c | 1668 | static int |
ed9a39eb | 1669 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1670 | { |
1671 | if (cond == INST_AL || cond == INST_NV) | |
1672 | return 1; | |
1673 | ||
1674 | switch (cond) | |
1675 | { | |
1676 | case INST_EQ: | |
1677 | return ((status_reg & FLAG_Z) != 0); | |
1678 | case INST_NE: | |
1679 | return ((status_reg & FLAG_Z) == 0); | |
1680 | case INST_CS: | |
1681 | return ((status_reg & FLAG_C) != 0); | |
1682 | case INST_CC: | |
1683 | return ((status_reg & FLAG_C) == 0); | |
1684 | case INST_MI: | |
1685 | return ((status_reg & FLAG_N) != 0); | |
1686 | case INST_PL: | |
1687 | return ((status_reg & FLAG_N) == 0); | |
1688 | case INST_VS: | |
1689 | return ((status_reg & FLAG_V) != 0); | |
1690 | case INST_VC: | |
1691 | return ((status_reg & FLAG_V) == 0); | |
1692 | case INST_HI: | |
1693 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1694 | case INST_LS: | |
1695 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1696 | case INST_GE: | |
1697 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1698 | case INST_LT: | |
1699 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1700 | case INST_GT: | |
1701 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1702 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1703 | case INST_LE: |
1704 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1705 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1706 | } |
1707 | return 1; | |
1708 | } | |
1709 | ||
9512d7fd | 1710 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1711 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1712 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1713 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1714 | #define sbits(obj,st,fn) \ | |
1715 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1716 | #define BranchDest(addr,instr) \ | |
1717 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1718 | #define ARM_PC_32 1 | |
1719 | ||
1720 | static unsigned long | |
ed9a39eb JM |
1721 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1722 | unsigned long status_reg) | |
c906108c SS |
1723 | { |
1724 | unsigned long res, shift; | |
1725 | int rm = bits (inst, 0, 3); | |
1726 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1727 | |
1728 | if (bit (inst, 4)) | |
c906108c SS |
1729 | { |
1730 | int rs = bits (inst, 8, 11); | |
1731 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1732 | } | |
1733 | else | |
1734 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1735 | |
1736 | res = (rm == 15 | |
c906108c | 1737 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1738 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1739 | : read_register (rm)); |
1740 | ||
1741 | switch (shifttype) | |
1742 | { | |
c5aa993b | 1743 | case 0: /* LSL */ |
c906108c SS |
1744 | res = shift >= 32 ? 0 : res << shift; |
1745 | break; | |
c5aa993b JM |
1746 | |
1747 | case 1: /* LSR */ | |
c906108c SS |
1748 | res = shift >= 32 ? 0 : res >> shift; |
1749 | break; | |
1750 | ||
c5aa993b JM |
1751 | case 2: /* ASR */ |
1752 | if (shift >= 32) | |
1753 | shift = 31; | |
c906108c SS |
1754 | res = ((res & 0x80000000L) |
1755 | ? ~((~res) >> shift) : res >> shift); | |
1756 | break; | |
1757 | ||
c5aa993b | 1758 | case 3: /* ROR/RRX */ |
c906108c SS |
1759 | shift &= 31; |
1760 | if (shift == 0) | |
1761 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1762 | else | |
c5aa993b | 1763 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1764 | break; |
1765 | } | |
1766 | ||
1767 | return res & 0xffffffff; | |
1768 | } | |
1769 | ||
c906108c SS |
1770 | /* Return number of 1-bits in VAL. */ |
1771 | ||
1772 | static int | |
ed9a39eb | 1773 | bitcount (unsigned long val) |
c906108c SS |
1774 | { |
1775 | int nbits; | |
1776 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1777 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1778 | return nbits; |
1779 | } | |
1780 | ||
34e8f22d | 1781 | CORE_ADDR |
ed9a39eb | 1782 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1783 | { |
c5aa993b | 1784 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1785 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1786 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1787 | unsigned long offset; |
1788 | ||
1789 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1790 | { | |
1791 | CORE_ADDR sp; | |
1792 | ||
1793 | /* Fetch the saved PC from the stack. It's stored above | |
1794 | all of the other registers. */ | |
1795 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1796 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1797 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1798 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1799 | if (nextpc == pc) | |
1800 | error ("Infinite loop detected"); | |
1801 | } | |
1802 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1803 | { | |
34e8f22d | 1804 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1805 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1806 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1807 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1808 | } | |
1809 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1810 | { | |
1811 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1812 | } | |
1813 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1814 | { | |
1815 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1816 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1817 | nextpc = pc_val + offset; |
1818 | } | |
1819 | ||
1820 | return nextpc; | |
1821 | } | |
1822 | ||
34e8f22d | 1823 | CORE_ADDR |
ed9a39eb | 1824 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1825 | { |
1826 | unsigned long pc_val; | |
1827 | unsigned long this_instr; | |
1828 | unsigned long status; | |
1829 | CORE_ADDR nextpc; | |
1830 | ||
1831 | if (arm_pc_is_thumb (pc)) | |
1832 | return thumb_get_next_pc (pc); | |
1833 | ||
1834 | pc_val = (unsigned long) pc; | |
1835 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1836 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1837 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1838 | |
1839 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1840 | { | |
1841 | switch (bits (this_instr, 24, 27)) | |
1842 | { | |
c5aa993b | 1843 | case 0x0: |
94c30b78 | 1844 | case 0x1: /* data processing */ |
c5aa993b JM |
1845 | case 0x2: |
1846 | case 0x3: | |
c906108c SS |
1847 | { |
1848 | unsigned long operand1, operand2, result = 0; | |
1849 | unsigned long rn; | |
1850 | int c; | |
c5aa993b | 1851 | |
c906108c SS |
1852 | if (bits (this_instr, 12, 15) != 15) |
1853 | break; | |
1854 | ||
1855 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1856 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1857 | error ("Illegal update to pc in instruction"); |
1858 | ||
1859 | /* Multiply into PC */ | |
1860 | c = (status & FLAG_C) ? 1 : 0; | |
1861 | rn = bits (this_instr, 16, 19); | |
1862 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1863 | |
c906108c SS |
1864 | if (bit (this_instr, 25)) |
1865 | { | |
1866 | unsigned long immval = bits (this_instr, 0, 7); | |
1867 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1868 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1869 | & 0xffffffff; | |
c906108c | 1870 | } |
c5aa993b | 1871 | else /* operand 2 is a shifted register */ |
c906108c | 1872 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1873 | |
c906108c SS |
1874 | switch (bits (this_instr, 21, 24)) |
1875 | { | |
c5aa993b | 1876 | case 0x0: /*and */ |
c906108c SS |
1877 | result = operand1 & operand2; |
1878 | break; | |
1879 | ||
c5aa993b | 1880 | case 0x1: /*eor */ |
c906108c SS |
1881 | result = operand1 ^ operand2; |
1882 | break; | |
1883 | ||
c5aa993b | 1884 | case 0x2: /*sub */ |
c906108c SS |
1885 | result = operand1 - operand2; |
1886 | break; | |
1887 | ||
c5aa993b | 1888 | case 0x3: /*rsb */ |
c906108c SS |
1889 | result = operand2 - operand1; |
1890 | break; | |
1891 | ||
c5aa993b | 1892 | case 0x4: /*add */ |
c906108c SS |
1893 | result = operand1 + operand2; |
1894 | break; | |
1895 | ||
c5aa993b | 1896 | case 0x5: /*adc */ |
c906108c SS |
1897 | result = operand1 + operand2 + c; |
1898 | break; | |
1899 | ||
c5aa993b | 1900 | case 0x6: /*sbc */ |
c906108c SS |
1901 | result = operand1 - operand2 + c; |
1902 | break; | |
1903 | ||
c5aa993b | 1904 | case 0x7: /*rsc */ |
c906108c SS |
1905 | result = operand2 - operand1 + c; |
1906 | break; | |
1907 | ||
c5aa993b JM |
1908 | case 0x8: |
1909 | case 0x9: | |
1910 | case 0xa: | |
1911 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1912 | result = (unsigned long) nextpc; |
1913 | break; | |
1914 | ||
c5aa993b | 1915 | case 0xc: /*orr */ |
c906108c SS |
1916 | result = operand1 | operand2; |
1917 | break; | |
1918 | ||
c5aa993b | 1919 | case 0xd: /*mov */ |
c906108c SS |
1920 | /* Always step into a function. */ |
1921 | result = operand2; | |
c5aa993b | 1922 | break; |
c906108c | 1923 | |
c5aa993b | 1924 | case 0xe: /*bic */ |
c906108c SS |
1925 | result = operand1 & ~operand2; |
1926 | break; | |
1927 | ||
c5aa993b | 1928 | case 0xf: /*mvn */ |
c906108c SS |
1929 | result = ~operand2; |
1930 | break; | |
1931 | } | |
1932 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1933 | ||
1934 | if (nextpc == pc) | |
1935 | error ("Infinite loop detected"); | |
1936 | break; | |
1937 | } | |
c5aa993b JM |
1938 | |
1939 | case 0x4: | |
1940 | case 0x5: /* data transfer */ | |
1941 | case 0x6: | |
1942 | case 0x7: | |
c906108c SS |
1943 | if (bit (this_instr, 20)) |
1944 | { | |
1945 | /* load */ | |
1946 | if (bits (this_instr, 12, 15) == 15) | |
1947 | { | |
1948 | /* rd == pc */ | |
c5aa993b | 1949 | unsigned long rn; |
c906108c | 1950 | unsigned long base; |
c5aa993b | 1951 | |
c906108c SS |
1952 | if (bit (this_instr, 22)) |
1953 | error ("Illegal update to pc in instruction"); | |
1954 | ||
1955 | /* byte write to PC */ | |
1956 | rn = bits (this_instr, 16, 19); | |
1957 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1958 | if (bit (this_instr, 24)) | |
1959 | { | |
1960 | /* pre-indexed */ | |
1961 | int c = (status & FLAG_C) ? 1 : 0; | |
1962 | unsigned long offset = | |
c5aa993b | 1963 | (bit (this_instr, 25) |
ed9a39eb | 1964 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1965 | : bits (this_instr, 0, 11)); |
c906108c SS |
1966 | |
1967 | if (bit (this_instr, 23)) | |
1968 | base += offset; | |
1969 | else | |
1970 | base -= offset; | |
1971 | } | |
c5aa993b | 1972 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1973 | 4); |
c5aa993b | 1974 | |
c906108c SS |
1975 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1976 | ||
1977 | if (nextpc == pc) | |
1978 | error ("Infinite loop detected"); | |
1979 | } | |
1980 | } | |
1981 | break; | |
c5aa993b JM |
1982 | |
1983 | case 0x8: | |
1984 | case 0x9: /* block transfer */ | |
c906108c SS |
1985 | if (bit (this_instr, 20)) |
1986 | { | |
1987 | /* LDM */ | |
1988 | if (bit (this_instr, 15)) | |
1989 | { | |
1990 | /* loading pc */ | |
1991 | int offset = 0; | |
1992 | ||
1993 | if (bit (this_instr, 23)) | |
1994 | { | |
1995 | /* up */ | |
1996 | unsigned long reglist = bits (this_instr, 0, 14); | |
1997 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1998 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1999 | offset += 4; |
2000 | } | |
2001 | else if (bit (this_instr, 24)) | |
2002 | offset = -4; | |
c5aa993b | 2003 | |
c906108c | 2004 | { |
c5aa993b JM |
2005 | unsigned long rn_val = |
2006 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
2007 | nextpc = |
2008 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2009 | + offset), |
c906108c SS |
2010 | 4); |
2011 | } | |
2012 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2013 | if (nextpc == pc) | |
2014 | error ("Infinite loop detected"); | |
2015 | } | |
2016 | } | |
2017 | break; | |
c5aa993b JM |
2018 | |
2019 | case 0xb: /* branch & link */ | |
2020 | case 0xa: /* branch */ | |
c906108c SS |
2021 | { |
2022 | nextpc = BranchDest (pc, this_instr); | |
2023 | ||
2024 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
2025 | if (nextpc == pc) | |
2026 | error ("Infinite loop detected"); | |
2027 | break; | |
2028 | } | |
c5aa993b JM |
2029 | |
2030 | case 0xc: | |
2031 | case 0xd: | |
2032 | case 0xe: /* coproc ops */ | |
2033 | case 0xf: /* SWI */ | |
c906108c SS |
2034 | break; |
2035 | ||
2036 | default: | |
97e03143 | 2037 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2038 | return (pc); |
2039 | } | |
2040 | } | |
2041 | ||
2042 | return nextpc; | |
2043 | } | |
2044 | ||
9512d7fd FN |
2045 | /* single_step() is called just before we want to resume the inferior, |
2046 | if we want to single-step it but there is no hardware or kernel | |
2047 | single-step support. We find the target of the coming instruction | |
2048 | and breakpoint it. | |
2049 | ||
94c30b78 MS |
2050 | single_step() is also called just after the inferior stops. If we |
2051 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2052 | |
34e8f22d RE |
2053 | static void |
2054 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2055 | { |
b8d5e71d | 2056 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2057 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2058 | ||
2059 | if (insert_bpt) | |
2060 | { | |
34e8f22d | 2061 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2062 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2063 | } |
2064 | else | |
80fcf3f0 | 2065 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2066 | } |
9512d7fd | 2067 | |
c906108c SS |
2068 | #include "bfd-in2.h" |
2069 | #include "libcoff.h" | |
2070 | ||
2071 | static int | |
ed9a39eb | 2072 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2073 | { |
2074 | if (arm_pc_is_thumb (memaddr)) | |
2075 | { | |
c5aa993b JM |
2076 | static asymbol *asym; |
2077 | static combined_entry_type ce; | |
2078 | static struct coff_symbol_struct csym; | |
2079 | static struct _bfd fake_bfd; | |
2080 | static bfd_target fake_target; | |
c906108c SS |
2081 | |
2082 | if (csym.native == NULL) | |
2083 | { | |
da3c6d4a MS |
2084 | /* Create a fake symbol vector containing a Thumb symbol. |
2085 | This is solely so that the code in print_insn_little_arm() | |
2086 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2087 | the presence of a Thumb symbol and switch to decoding | |
2088 | Thumb instructions. */ | |
c5aa993b JM |
2089 | |
2090 | fake_target.flavour = bfd_target_coff_flavour; | |
2091 | fake_bfd.xvec = &fake_target; | |
c906108c | 2092 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2093 | csym.native = &ce; |
2094 | csym.symbol.the_bfd = &fake_bfd; | |
2095 | csym.symbol.name = "fake"; | |
2096 | asym = (asymbol *) & csym; | |
c906108c | 2097 | } |
c5aa993b | 2098 | |
c906108c | 2099 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2100 | info->symbols = &asym; |
c906108c SS |
2101 | } |
2102 | else | |
2103 | info->symbols = NULL; | |
c5aa993b | 2104 | |
d7449b42 | 2105 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2106 | return print_insn_big_arm (memaddr, info); |
2107 | else | |
2108 | return print_insn_little_arm (memaddr, info); | |
2109 | } | |
2110 | ||
66e810cd RE |
2111 | /* The following define instruction sequences that will cause ARM |
2112 | cpu's to take an undefined instruction trap. These are used to | |
2113 | signal a breakpoint to GDB. | |
2114 | ||
2115 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2116 | modes. A different instruction is required for each mode. The ARM | |
2117 | cpu's can also be big or little endian. Thus four different | |
2118 | instructions are needed to support all cases. | |
2119 | ||
2120 | Note: ARMv4 defines several new instructions that will take the | |
2121 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2122 | not in fact add the new instructions. The new undefined | |
2123 | instructions in ARMv4 are all instructions that had no defined | |
2124 | behaviour in earlier chips. There is no guarantee that they will | |
2125 | raise an exception, but may be treated as NOP's. In practice, it | |
2126 | may only safe to rely on instructions matching: | |
2127 | ||
2128 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2129 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2130 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2131 | ||
2132 | Even this may only true if the condition predicate is true. The | |
2133 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2134 | ||
2135 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2136 | and NetBSD all use a software interrupt rather than an undefined | |
2137 | instruction to force a trap. This can be handled by by the | |
2138 | abi-specific code during establishment of the gdbarch vector. */ | |
2139 | ||
2140 | ||
d7b486e7 RE |
2141 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2142 | override these definitions. */ | |
66e810cd RE |
2143 | #ifndef ARM_LE_BREAKPOINT |
2144 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2145 | #endif | |
2146 | #ifndef ARM_BE_BREAKPOINT | |
2147 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2148 | #endif | |
2149 | #ifndef THUMB_LE_BREAKPOINT | |
2150 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2151 | #endif | |
2152 | #ifndef THUMB_BE_BREAKPOINT | |
2153 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2154 | #endif | |
2155 | ||
2156 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2157 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2158 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2159 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2160 | ||
34e8f22d RE |
2161 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2162 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2163 | breakpoint should be used. It returns a pointer to a string of |
2164 | bytes that encode a breakpoint instruction, stores the length of | |
2165 | the string to *lenptr, and adjusts the program counter (if | |
2166 | necessary) to point to the actual memory location where the | |
c906108c SS |
2167 | breakpoint should be inserted. */ |
2168 | ||
34e8f22d RE |
2169 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2170 | breakpoints and storing their handles instread of what was in | |
2171 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2172 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2173 | |
ab89facf | 2174 | static const unsigned char * |
ed9a39eb | 2175 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2176 | { |
66e810cd RE |
2177 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2178 | ||
c906108c SS |
2179 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2180 | { | |
66e810cd RE |
2181 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2182 | *lenptr = tdep->thumb_breakpoint_size; | |
2183 | return tdep->thumb_breakpoint; | |
c906108c SS |
2184 | } |
2185 | else | |
2186 | { | |
66e810cd RE |
2187 | *lenptr = tdep->arm_breakpoint_size; |
2188 | return tdep->arm_breakpoint; | |
c906108c SS |
2189 | } |
2190 | } | |
ed9a39eb JM |
2191 | |
2192 | /* Extract from an array REGBUF containing the (raw) register state a | |
2193 | function return value of type TYPE, and copy that, in virtual | |
2194 | format, into VALBUF. */ | |
2195 | ||
34e8f22d | 2196 | static void |
ed9a39eb JM |
2197 | arm_extract_return_value (struct type *type, |
2198 | char regbuf[REGISTER_BYTES], | |
2199 | char *valbuf) | |
2200 | { | |
2201 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 RE |
2202 | { |
2203 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2204 | ||
2205 | switch (tdep->fp_model) | |
2206 | { | |
2207 | case ARM_FLOAT_FPA: | |
2208 | convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)], | |
2209 | valbuf); | |
2210 | break; | |
2211 | ||
2212 | case ARM_FLOAT_SOFT: | |
2213 | case ARM_FLOAT_SOFT_VFP: | |
2214 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], | |
2215 | TYPE_LENGTH (type)); | |
2216 | break; | |
2217 | ||
2218 | default: | |
2219 | internal_error | |
2220 | (__FILE__, __LINE__, | |
2221 | "arm_extract_return_value: Floating point model not supported"); | |
2222 | break; | |
2223 | } | |
2224 | } | |
ed9a39eb | 2225 | else |
34e8f22d RE |
2226 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], |
2227 | TYPE_LENGTH (type)); | |
2228 | } | |
2229 | ||
67255d04 RE |
2230 | /* Extract from an array REGBUF containing the (raw) register state |
2231 | the address in which a function should return its structure value. */ | |
2232 | ||
2233 | static CORE_ADDR | |
2234 | arm_extract_struct_value_address (char *regbuf) | |
2235 | { | |
2236 | return extract_address (regbuf, REGISTER_RAW_SIZE(ARM_A1_REGNUM)); | |
2237 | } | |
2238 | ||
2239 | /* Will a function return an aggregate type in memory or in a | |
2240 | register? Return 0 if an aggregate type can be returned in a | |
2241 | register, 1 if it must be returned in memory. */ | |
2242 | ||
2243 | static int | |
2244 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2245 | { | |
2246 | int nRc; | |
2247 | register enum type_code code; | |
2248 | ||
2249 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2250 | registers. For an aggregate type to be integer like, its size | |
2251 | must be less than or equal to REGISTER_SIZE and the offset of | |
2252 | each addressable subfield must be zero. Note that bit fields are | |
2253 | not addressable, and all addressable subfields of unions always | |
2254 | start at offset zero. | |
2255 | ||
2256 | This function is based on the behaviour of GCC 2.95.1. | |
2257 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2258 | ||
2259 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2260 | parameters correctly for a function returning the following | |
2261 | structure: struct { float f;}; This should be returned in memory, | |
2262 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2263 | know of any way to detect if a function like the above has been | |
2264 | compiled with the correct calling convention. */ | |
2265 | ||
2266 | /* All aggregate types that won't fit in a register must be returned | |
2267 | in memory. */ | |
2268 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2269 | { | |
2270 | return 1; | |
2271 | } | |
2272 | ||
2273 | /* The only aggregate types that can be returned in a register are | |
2274 | structs and unions. Arrays must be returned in memory. */ | |
2275 | code = TYPE_CODE (type); | |
2276 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2277 | { | |
2278 | return 1; | |
2279 | } | |
2280 | ||
2281 | /* Assume all other aggregate types can be returned in a register. | |
2282 | Run a check for structures, unions and arrays. */ | |
2283 | nRc = 0; | |
2284 | ||
2285 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2286 | { | |
2287 | int i; | |
2288 | /* Need to check if this struct/union is "integer" like. For | |
2289 | this to be true, its size must be less than or equal to | |
2290 | REGISTER_SIZE and the offset of each addressable subfield | |
2291 | must be zero. Note that bit fields are not addressable, and | |
2292 | unions always start at offset zero. If any of the subfields | |
2293 | is a floating point type, the struct/union cannot be an | |
2294 | integer type. */ | |
2295 | ||
2296 | /* For each field in the object, check: | |
2297 | 1) Is it FP? --> yes, nRc = 1; | |
2298 | 2) Is it addressable (bitpos != 0) and | |
2299 | not packed (bitsize == 0)? | |
2300 | --> yes, nRc = 1 | |
2301 | */ | |
2302 | ||
2303 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2304 | { | |
2305 | enum type_code field_type_code; | |
2306 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2307 | ||
2308 | /* Is it a floating point type field? */ | |
2309 | if (field_type_code == TYPE_CODE_FLT) | |
2310 | { | |
2311 | nRc = 1; | |
2312 | break; | |
2313 | } | |
2314 | ||
2315 | /* If bitpos != 0, then we have to care about it. */ | |
2316 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2317 | { | |
2318 | /* Bitfields are not addressable. If the field bitsize is | |
2319 | zero, then the field is not packed. Hence it cannot be | |
2320 | a bitfield or any other packed type. */ | |
2321 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2322 | { | |
2323 | nRc = 1; | |
2324 | break; | |
2325 | } | |
2326 | } | |
2327 | } | |
2328 | } | |
2329 | ||
2330 | return nRc; | |
2331 | } | |
2332 | ||
34e8f22d RE |
2333 | /* Write into appropriate registers a function return value of type |
2334 | TYPE, given in virtual format. */ | |
2335 | ||
2336 | static void | |
2337 | arm_store_return_value (struct type *type, char *valbuf) | |
2338 | { | |
2339 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2340 | { | |
08216dd7 | 2341 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2342 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2343 | |
08216dd7 RE |
2344 | switch (tdep->fp_model) |
2345 | { | |
2346 | case ARM_FLOAT_FPA: | |
2347 | ||
2348 | convert_to_extended (valbuf, buf); | |
2349 | write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf, | |
7bbcf283 | 2350 | FP_REGISTER_RAW_SIZE); |
08216dd7 RE |
2351 | break; |
2352 | ||
2353 | case ARM_FLOAT_SOFT: | |
2354 | case ARM_FLOAT_SOFT_VFP: | |
2355 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); | |
2356 | break; | |
2357 | ||
2358 | default: | |
2359 | internal_error | |
2360 | (__FILE__, __LINE__, | |
2361 | "arm_store_return_value: Floating point model not supported"); | |
2362 | break; | |
2363 | } | |
34e8f22d RE |
2364 | } |
2365 | else | |
08216dd7 | 2366 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); |
34e8f22d RE |
2367 | } |
2368 | ||
2369 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2370 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2371 | |
2372 | static void | |
2373 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2374 | { | |
2375 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2376 | } |
2377 | ||
9df628e0 RE |
2378 | static int |
2379 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2380 | { | |
2381 | CORE_ADDR jb_addr; | |
2382 | char buf[INT_REGISTER_RAW_SIZE]; | |
2383 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2384 | ||
2385 | jb_addr = read_register (ARM_A1_REGNUM); | |
2386 | ||
2387 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2388 | INT_REGISTER_RAW_SIZE)) | |
2389 | return 0; | |
2390 | ||
2391 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2392 | return 1; | |
2393 | } | |
2394 | ||
ed9a39eb | 2395 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2396 | |
2397 | int | |
ed9a39eb | 2398 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2399 | { |
2400 | CORE_ADDR start_addr; | |
2401 | ||
ed9a39eb JM |
2402 | /* Find the starting address of the function containing the PC. If |
2403 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2404 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2405 | &start_addr, NULL)) | |
c906108c SS |
2406 | return 0; |
2407 | ||
2408 | return strncmp (name, "_call_via_r", 11) == 0; | |
2409 | } | |
2410 | ||
ed9a39eb JM |
2411 | /* If PC is in a Thumb call or return stub, return the address of the |
2412 | target PC, which is in a register. The thunk functions are called | |
2413 | _called_via_xx, where x is the register name. The possible names | |
2414 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2415 | |
2416 | CORE_ADDR | |
ed9a39eb | 2417 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2418 | { |
c5aa993b | 2419 | char *name; |
c906108c SS |
2420 | CORE_ADDR start_addr; |
2421 | ||
2422 | /* Find the starting address and name of the function containing the PC. */ | |
2423 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2424 | return 0; | |
2425 | ||
2426 | /* Call thunks always start with "_call_via_". */ | |
2427 | if (strncmp (name, "_call_via_", 10) == 0) | |
2428 | { | |
ed9a39eb JM |
2429 | /* Use the name suffix to determine which register contains the |
2430 | target PC. */ | |
c5aa993b JM |
2431 | static char *table[15] = |
2432 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2433 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2434 | }; | |
c906108c SS |
2435 | int regno; |
2436 | ||
2437 | for (regno = 0; regno <= 14; regno++) | |
2438 | if (strcmp (&name[10], table[regno]) == 0) | |
2439 | return read_register (regno); | |
2440 | } | |
ed9a39eb | 2441 | |
c5aa993b | 2442 | return 0; /* not a stub */ |
c906108c SS |
2443 | } |
2444 | ||
da3c6d4a MS |
2445 | /* If the user changes the register disassembly flavor used for info |
2446 | register and other commands, we have to also switch the flavor used | |
2447 | in opcodes for disassembly output. This function is run in the set | |
94c30b78 | 2448 | disassembly_flavor command, and does that. */ |
bc90b915 FN |
2449 | |
2450 | static void | |
2451 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2452 | struct cmd_list_element *c) | |
2453 | { | |
2454 | set_disassembly_flavor (); | |
2455 | } | |
2456 | \f | |
966fbf70 | 2457 | /* Return the ARM register name corresponding to register I. */ |
34e8f22d RE |
2458 | static char * |
2459 | arm_register_name (int i) | |
966fbf70 RE |
2460 | { |
2461 | return arm_register_names[i]; | |
2462 | } | |
2463 | ||
bc90b915 FN |
2464 | static void |
2465 | set_disassembly_flavor (void) | |
2466 | { | |
2467 | const char *setname, *setdesc, **regnames; | |
2468 | int numregs, j; | |
2469 | ||
94c30b78 | 2470 | /* Find the flavor that the user wants in the opcodes table. */ |
bc90b915 FN |
2471 | int current = 0; |
2472 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2473 | while ((disassembly_flavor != setname) | |
2474 | && (current < num_flavor_options)) | |
2475 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2476 | current_option = current; | |
2477 | ||
94c30b78 | 2478 | /* Fill our copy. */ |
bc90b915 FN |
2479 | for (j = 0; j < numregs; j++) |
2480 | arm_register_names[j] = (char *) regnames[j]; | |
2481 | ||
94c30b78 | 2482 | /* Adjust case. */ |
34e8f22d | 2483 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2484 | { |
34e8f22d RE |
2485 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2486 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2487 | } |
2488 | else | |
2489 | { | |
34e8f22d RE |
2490 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2491 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2492 | } |
2493 | ||
94c30b78 | 2494 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2495 | set_arm_regname_option (current); |
2496 | } | |
2497 | ||
2498 | /* arm_othernames implements the "othernames" command. This is kind | |
2499 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2500 | also used for the x86 gdb. I will keep this around, however, in | |
94c30b78 | 2501 | case anyone is actually using it. */ |
bc90b915 FN |
2502 | |
2503 | static void | |
2504 | arm_othernames (char *names, int n) | |
2505 | { | |
94c30b78 | 2506 | /* Circle through the various flavors. */ |
bc90b915 FN |
2507 | current_option = (current_option + 1) % num_flavor_options; |
2508 | ||
2509 | disassembly_flavor = valid_flavors[current_option]; | |
94c30b78 | 2510 | set_disassembly_flavor (); |
bc90b915 FN |
2511 | } |
2512 | ||
a42dd537 KB |
2513 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2514 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2515 | Note, however, that link.h is not actually referred to in this file. | |
2516 | Instead, the relevant structs offsets were obtained from examining | |
2517 | link.h. (We can't refer to link.h from this file because the host | |
2518 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2519 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2520 | |
2521 | struct link_map_offsets * | |
2522 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2523 | { | |
2524 | static struct link_map_offsets lmo; | |
2525 | static struct link_map_offsets *lmp = 0; | |
2526 | ||
2527 | if (lmp == 0) | |
2528 | { | |
2529 | lmp = &lmo; | |
2530 | ||
2531 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2532 | need. */ |
a42dd537 KB |
2533 | |
2534 | lmo.r_map_offset = 4; | |
2535 | lmo.r_map_size = 4; | |
2536 | ||
2537 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2538 | need. */ |
a42dd537 KB |
2539 | |
2540 | lmo.l_addr_offset = 0; | |
2541 | lmo.l_addr_size = 4; | |
2542 | ||
2543 | lmo.l_name_offset = 4; | |
2544 | lmo.l_name_size = 4; | |
2545 | ||
2546 | lmo.l_next_offset = 12; | |
2547 | lmo.l_next_size = 4; | |
2548 | ||
2549 | lmo.l_prev_offset = 16; | |
2550 | lmo.l_prev_size = 4; | |
2551 | } | |
2552 | ||
2553 | return lmp; | |
2554 | } | |
2555 | ||
082fc60d RE |
2556 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2557 | function. */ | |
2558 | ||
2559 | static int | |
2560 | coff_sym_is_thumb (int val) | |
2561 | { | |
2562 | return (val == C_THUMBEXT || | |
2563 | val == C_THUMBSTAT || | |
2564 | val == C_THUMBEXTFUNC || | |
2565 | val == C_THUMBSTATFUNC || | |
2566 | val == C_THUMBLABEL); | |
2567 | } | |
2568 | ||
2569 | /* arm_coff_make_msymbol_special() | |
2570 | arm_elf_make_msymbol_special() | |
2571 | ||
2572 | These functions test whether the COFF or ELF symbol corresponds to | |
2573 | an address in thumb code, and set a "special" bit in a minimal | |
2574 | symbol to indicate that it does. */ | |
2575 | ||
34e8f22d | 2576 | static void |
082fc60d RE |
2577 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2578 | { | |
2579 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2580 | STT_ARM_TFUNC). */ | |
2581 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2582 | == STT_LOPROC) | |
2583 | MSYMBOL_SET_SPECIAL (msym); | |
2584 | } | |
2585 | ||
34e8f22d | 2586 | static void |
082fc60d RE |
2587 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2588 | { | |
2589 | if (coff_sym_is_thumb (val)) | |
2590 | MSYMBOL_SET_SPECIAL (msym); | |
2591 | } | |
2592 | ||
97e03143 | 2593 | \f |
70f80edf JT |
2594 | static enum gdb_osabi |
2595 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2596 | { |
70f80edf JT |
2597 | unsigned int elfosabi, eflags; |
2598 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2599 | |
70f80edf | 2600 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2601 | |
70f80edf | 2602 | switch (elfosabi) |
97e03143 | 2603 | { |
70f80edf JT |
2604 | case ELFOSABI_NONE: |
2605 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2606 | file are conforming to the base specification for that machine | |
2607 | (there are no OS-specific extensions). In order to determine the | |
2608 | real OS in use we must look for OS notes that have been added. */ | |
2609 | bfd_map_over_sections (abfd, | |
2610 | generic_elf_osabi_sniff_abi_tag_sections, | |
2611 | &osabi); | |
2612 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2613 | { |
70f80edf JT |
2614 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2615 | field for more information. */ | |
2616 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2617 | switch (eflags) | |
97e03143 | 2618 | { |
70f80edf JT |
2619 | case EF_ARM_EABI_VER1: |
2620 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2621 | break; |
2622 | ||
70f80edf JT |
2623 | case EF_ARM_EABI_VER2: |
2624 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2625 | break; |
2626 | ||
70f80edf JT |
2627 | case EF_ARM_EABI_UNKNOWN: |
2628 | /* Assume GNU tools. */ | |
2629 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2630 | break; |
2631 | ||
70f80edf JT |
2632 | default: |
2633 | internal_error (__FILE__, __LINE__, | |
2634 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2635 | "version 0x%x", eflags); | |
97e03143 RE |
2636 | } |
2637 | } | |
70f80edf | 2638 | break; |
97e03143 | 2639 | |
70f80edf JT |
2640 | case ELFOSABI_ARM: |
2641 | /* GNU tools use this value. Check note sections in this case, | |
2642 | as well. */ | |
97e03143 | 2643 | bfd_map_over_sections (abfd, |
70f80edf JT |
2644 | generic_elf_osabi_sniff_abi_tag_sections, |
2645 | &osabi); | |
2646 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2647 | { |
70f80edf JT |
2648 | /* Assume APCS ABI. */ |
2649 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2650 | } |
2651 | break; | |
2652 | ||
97e03143 | 2653 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2654 | osabi = GDB_OSABI_FREEBSD_ELF; |
2655 | break; | |
97e03143 | 2656 | |
70f80edf JT |
2657 | case ELFOSABI_NETBSD: |
2658 | osabi = GDB_OSABI_NETBSD_ELF; | |
2659 | break; | |
97e03143 | 2660 | |
70f80edf JT |
2661 | case ELFOSABI_LINUX: |
2662 | osabi = GDB_OSABI_LINUX; | |
2663 | break; | |
97e03143 RE |
2664 | } |
2665 | ||
70f80edf | 2666 | return osabi; |
97e03143 RE |
2667 | } |
2668 | ||
70f80edf | 2669 | \f |
da3c6d4a MS |
2670 | /* Initialize the current architecture based on INFO. If possible, |
2671 | re-use an architecture from ARCHES, which is a list of | |
2672 | architectures already created during this debugging session. | |
97e03143 | 2673 | |
da3c6d4a MS |
2674 | Called e.g. at program startup, when reading a core file, and when |
2675 | reading a binary file. */ | |
97e03143 | 2676 | |
39bbf761 RE |
2677 | static struct gdbarch * |
2678 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2679 | { | |
97e03143 | 2680 | struct gdbarch_tdep *tdep; |
39bbf761 | 2681 | struct gdbarch *gdbarch; |
70f80edf | 2682 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
39bbf761 | 2683 | |
97e03143 | 2684 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2685 | |
97e03143 RE |
2686 | if (info.abfd != NULL) |
2687 | { | |
70f80edf JT |
2688 | osabi = gdbarch_lookup_osabi (info.abfd); |
2689 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2690 | { |
70f80edf JT |
2691 | switch (bfd_get_flavour (info.abfd)) |
2692 | { | |
2693 | case bfd_target_aout_flavour: | |
2694 | /* Assume it's an old APCS-style ABI. */ | |
2695 | osabi = GDB_OSABI_ARM_APCS; | |
2696 | break; | |
97e03143 | 2697 | |
70f80edf JT |
2698 | case bfd_target_coff_flavour: |
2699 | /* Assume it's an old APCS-style ABI. */ | |
2700 | /* XXX WinCE? */ | |
2701 | osabi = GDB_OSABI_ARM_APCS; | |
2702 | break; | |
97e03143 | 2703 | |
70f80edf JT |
2704 | default: |
2705 | /* Leave it as "unknown". */ | |
2706 | } | |
97e03143 RE |
2707 | } |
2708 | } | |
2709 | ||
d7afb4c9 | 2710 | /* Find a candidate among extant architectures. */ |
97e03143 RE |
2711 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2712 | arches != NULL; | |
2713 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2714 | { | |
2715 | /* Make sure the ABI selection matches. */ | |
2716 | tdep = gdbarch_tdep (arches->gdbarch); | |
70f80edf | 2717 | if (tdep && tdep->osabi == osabi) |
97e03143 RE |
2718 | return arches->gdbarch; |
2719 | } | |
2720 | ||
2721 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2722 | gdbarch = gdbarch_alloc (&info, tdep); | |
2723 | ||
70f80edf | 2724 | tdep->osabi = osabi; |
39bbf761 | 2725 | |
08216dd7 RE |
2726 | /* This is the way it has always defaulted. */ |
2727 | tdep->fp_model = ARM_FLOAT_FPA; | |
2728 | ||
2729 | /* Breakpoints. */ | |
67255d04 RE |
2730 | switch (info.byte_order) |
2731 | { | |
2732 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2733 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2734 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2735 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2736 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2737 | ||
67255d04 RE |
2738 | break; |
2739 | ||
2740 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2741 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2742 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2743 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2744 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2745 | ||
67255d04 RE |
2746 | break; |
2747 | ||
2748 | default: | |
2749 | internal_error (__FILE__, __LINE__, | |
2750 | "arm_gdbarch_init: bad byte order for float format"); | |
2751 | } | |
2752 | ||
d7b486e7 RE |
2753 | /* On ARM targets char defaults to unsigned. */ |
2754 | set_gdbarch_char_signed (gdbarch, 0); | |
2755 | ||
9df628e0 | 2756 | /* This should be low enough for everything. */ |
97e03143 | 2757 | tdep->lowest_pc = 0x20; |
94c30b78 | 2758 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2759 | |
848cfffb AC |
2760 | #if OLD_STYLE_ARM_DUMMY_FRAMES |
2761 | /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM | |
2762 | specific (non-generic) dummy frame code. Might be useful if | |
2763 | there appears to be a problem with the generic dummy frame | |
2764 | mechanism that replaced it. */ | |
39bbf761 RE |
2765 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
2766 | ||
2767 | /* Call dummy code. */ | |
2768 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2769 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
3fb4b924 RE |
2770 | /* We have to give this a value now, even though we will re-set it |
2771 | during each call to arm_fix_call_dummy. */ | |
2772 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8); | |
39bbf761 RE |
2773 | set_gdbarch_call_dummy_p (gdbarch, 1); |
2774 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2775 | ||
34e8f22d RE |
2776 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); |
2777 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words)); | |
2778 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
d7b486e7 | 2779 | set_gdbarch_call_dummy_length (gdbarch, 0); |
34e8f22d RE |
2780 | |
2781 | set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy); | |
2782 | ||
39bbf761 | 2783 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
848cfffb AC |
2784 | #else |
2785 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
2786 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
2787 | ||
2788 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
2789 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2790 | ||
2791 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2792 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2793 | ||
2794 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2795 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2796 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2797 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2798 | ||
2799 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
2800 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
2801 | ||
2802 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2803 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
2804 | #endif | |
39bbf761 RE |
2805 | |
2806 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
2807 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); | |
d7afb4c9 RE |
2808 | set_gdbarch_coerce_float_to_double (gdbarch, |
2809 | standard_coerce_float_to_double); | |
39bbf761 | 2810 | |
148754e5 | 2811 | /* Frame handling. */ |
39bbf761 | 2812 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
148754e5 RE |
2813 | set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
2814 | set_gdbarch_read_fp (gdbarch, arm_read_fp); | |
2815 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2816 | set_gdbarch_frameless_function_invocation | |
2817 | (gdbarch, arm_frameless_function_invocation); | |
2818 | set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc); | |
2819 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); | |
2820 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2821 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2822 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2823 | set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); | |
848cfffb AC |
2824 | #if OLD_STYLE_ARM_DUMMY_FRAMES |
2825 | /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM | |
2826 | specific (non-generic) dummy frame code. Might be useful if | |
2827 | there appears to be a problem with the generic dummy frame | |
2828 | mechanism that replaced it. */ | |
148754e5 | 2829 | set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame); |
848cfffb AC |
2830 | #else |
2831 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
2832 | #endif | |
148754e5 RE |
2833 | set_gdbarch_pop_frame (gdbarch, arm_pop_frame); |
2834 | ||
34e8f22d RE |
2835 | /* Address manipulation. */ |
2836 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2837 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2838 | ||
2839 | /* Offset from address of function to start of its code. */ | |
2840 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2841 | ||
2842 | /* Advance PC across function entry code. */ | |
2843 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2844 | ||
2845 | /* Get the PC when a frame might not be available. */ | |
2846 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2847 | ||
2848 | /* The stack grows downward. */ | |
2849 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2850 | ||
2851 | /* Breakpoint manipulation. */ | |
2852 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2853 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2854 | ||
2855 | /* Information about registers, etc. */ | |
2856 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 2857 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2858 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2859 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2860 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2861 | set_gdbarch_register_bytes (gdbarch, | |
2862 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2863 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2864 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2865 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2866 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2867 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
2868 | set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); | |
2869 | set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
2870 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); | |
2871 | ||
2872 | /* Integer registers are 4 bytes. */ | |
2873 | set_gdbarch_register_size (gdbarch, 4); | |
2874 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2875 | ||
2876 | /* Returning results. */ | |
2877 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); | |
2878 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
2879 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); | |
67255d04 RE |
2880 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
2881 | set_gdbarch_extract_struct_value_address (gdbarch, | |
2882 | arm_extract_struct_value_address); | |
34e8f22d RE |
2883 | |
2884 | /* Single stepping. */ | |
2885 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2886 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2887 | ||
2888 | /* Minsymbol frobbing. */ | |
2889 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2890 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2891 | arm_coff_make_msymbol_special); | |
2892 | ||
97e03143 | 2893 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
70f80edf | 2894 | gdbarch_init_osabi (info, gdbarch, osabi); |
97e03143 RE |
2895 | |
2896 | /* Now we have tuned the configuration, set a few final things, | |
2897 | based on what the OS ABI has told us. */ | |
2898 | ||
9df628e0 RE |
2899 | if (tdep->jb_pc >= 0) |
2900 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2901 | ||
08216dd7 RE |
2902 | /* Floating point sizes and format. */ |
2903 | switch (info.byte_order) | |
2904 | { | |
2905 | case BFD_ENDIAN_BIG: | |
2906 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2907 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2908 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2909 | ||
2910 | break; | |
2911 | ||
2912 | case BFD_ENDIAN_LITTLE: | |
2913 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
2914 | if (tdep->fp_model == ARM_FLOAT_VFP | |
2915 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
2916 | { | |
2917 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2918 | set_gdbarch_long_double_format (gdbarch, | |
2919 | &floatformat_ieee_double_little); | |
2920 | } | |
2921 | else | |
2922 | { | |
2923 | set_gdbarch_double_format | |
2924 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2925 | set_gdbarch_long_double_format | |
2926 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2927 | } | |
2928 | break; | |
2929 | ||
2930 | default: | |
2931 | internal_error (__FILE__, __LINE__, | |
2932 | "arm_gdbarch_init: bad byte order for float format"); | |
2933 | } | |
2934 | ||
97e03143 | 2935 | /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still |
34e8f22d RE |
2936 | references the old architecture vector, not the one we are |
2937 | building here. */ | |
2938 | if (prologue_cache.saved_regs != NULL) | |
2939 | xfree (prologue_cache.saved_regs); | |
2940 | ||
a0abec03 AC |
2941 | /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still |
2942 | references the old architecture vector, not the one we are | |
2943 | building here. */ | |
34e8f22d RE |
2944 | prologue_cache.saved_regs = (CORE_ADDR *) |
2945 | xcalloc (1, (sizeof (CORE_ADDR) | |
29673b29 AC |
2946 | * (gdbarch_num_regs (gdbarch) |
2947 | + gdbarch_num_pseudo_regs (gdbarch)))); | |
39bbf761 RE |
2948 | |
2949 | return gdbarch; | |
2950 | } | |
2951 | ||
97e03143 RE |
2952 | static void |
2953 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2954 | { | |
2955 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2956 | ||
2957 | if (tdep == NULL) | |
2958 | return; | |
2959 | ||
70f80edf JT |
2960 | fprintf_unfiltered (file, "arm_dump_tdep: OS ABI = %s\n", |
2961 | gdbarch_osabi_name (tdep->osabi)); | |
97e03143 RE |
2962 | |
2963 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", | |
2964 | (unsigned long) tdep->lowest_pc); | |
2965 | } | |
2966 | ||
2967 | static void | |
2968 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2969 | struct gdbarch *gdbarch) | |
2970 | { | |
2971 | /* Place-holder. */ | |
2972 | } | |
2973 | ||
2974 | static void | |
2975 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2976 | struct gdbarch *gdbarch) | |
2977 | { | |
2978 | /* Place-holder. */ | |
2979 | } | |
2980 | ||
2981 | static void | |
2982 | arm_init_abi_apcs (struct gdbarch_info info, | |
2983 | struct gdbarch *gdbarch) | |
2984 | { | |
2985 | /* Place-holder. */ | |
2986 | } | |
2987 | ||
c906108c | 2988 | void |
ed9a39eb | 2989 | _initialize_arm_tdep (void) |
c906108c | 2990 | { |
bc90b915 FN |
2991 | struct ui_file *stb; |
2992 | long length; | |
96baa820 | 2993 | struct cmd_list_element *new_cmd; |
53904c9e AC |
2994 | const char *setname; |
2995 | const char *setdesc; | |
2996 | const char **regnames; | |
bc90b915 FN |
2997 | int numregs, i, j; |
2998 | static char *helptext; | |
085dd6e6 | 2999 | |
39bbf761 | 3000 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3001 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3002 | ||
70f80edf JT |
3003 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3004 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3005 | bfd_target_elf_flavour, | |
3006 | arm_elf_osabi_sniffer); | |
3007 | ||
97e03143 | 3008 | /* Register some ABI variants for embedded systems. */ |
70f80edf JT |
3009 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V1, |
3010 | arm_init_abi_eabi_v1); | |
3011 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_EABI_V2, | |
3012 | arm_init_abi_eabi_v2); | |
3013 | gdbarch_register_osabi (bfd_arch_arm, GDB_OSABI_ARM_APCS, | |
3014 | arm_init_abi_apcs); | |
39bbf761 | 3015 | |
c906108c | 3016 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3017 | |
94c30b78 | 3018 | /* Get the number of possible sets of register names defined in opcodes. */ |
bc90b915 FN |
3019 | num_flavor_options = get_arm_regname_num_options (); |
3020 | ||
94c30b78 | 3021 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3022 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3023 | |
94c30b78 | 3024 | /* Begin creating the help text. */ |
bc90b915 FN |
3025 | stb = mem_fileopen (); |
3026 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3027 | The valid values are:\n"); | |
ed9a39eb | 3028 | |
94c30b78 | 3029 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
bc90b915 FN |
3030 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
3031 | for (i = 0; i < num_flavor_options; i++) | |
3032 | { | |
3033 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3034 | valid_flavors[i] = setname; |
bc90b915 FN |
3035 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3036 | setdesc); | |
94c30b78 | 3037 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3038 | if (!strcmp (setname, "std")) |
3039 | { | |
53904c9e | 3040 | disassembly_flavor = setname; |
bc90b915 FN |
3041 | current_option = i; |
3042 | for (j = 0; j < numregs; j++) | |
3043 | arm_register_names[j] = (char *) regnames[j]; | |
3044 | set_arm_regname_option (i); | |
3045 | } | |
3046 | } | |
94c30b78 | 3047 | /* Mark the end of valid options. */ |
bc90b915 | 3048 | valid_flavors[num_flavor_options] = NULL; |
c906108c | 3049 | |
94c30b78 | 3050 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3051 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3052 | helptext = ui_file_xstrdup (stb, &length); | |
3053 | ui_file_delete (stb); | |
ed9a39eb | 3054 | |
94c30b78 | 3055 | /* Add the disassembly-flavor command. */ |
96baa820 | 3056 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3057 | valid_flavors, |
1ed2a135 | 3058 | &disassembly_flavor, |
bc90b915 | 3059 | helptext, |
ed9a39eb | 3060 | &setlist); |
9f60d481 | 3061 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3062 | add_show_from_set (new_cmd, &showlist); |
3063 | ||
c906108c SS |
3064 | /* ??? Maybe this should be a boolean. */ |
3065 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3066 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3067 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3068 | &showlist); |
c906108c | 3069 | |
94c30b78 | 3070 | /* Add the deprecated "othernames" command. */ |
bc90b915 FN |
3071 | |
3072 | add_com ("othernames", class_obscure, arm_othernames, | |
3073 | "Switch to the next set of register names."); | |
c3b4394c RE |
3074 | |
3075 | /* Fill in the prologue_cache fields. */ | |
34e8f22d | 3076 | prologue_cache.saved_regs = NULL; |
c3b4394c RE |
3077 | prologue_cache.extra_info = (struct frame_extra_info *) |
3078 | xcalloc (1, sizeof (struct frame_extra_info)); | |
c906108c | 3079 | } |