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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "gdb_string.h" | |
29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
e8b09175 | 30 | #include "dis-asm.h" /* For register flavors. */ |
30f6df08 | 31 | #include <ctype.h> /* for isupper () */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
a42dd537 | 35 | #include "solib-svr4.h" |
c906108c | 36 | |
2a451106 KB |
37 | /* Each OS has a different mechanism for accessing the various |
38 | registers stored in the sigcontext structure. | |
39 | ||
40 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
41 | function pointer) which may be used to determine the addresses | |
42 | of the various saved registers in the sigcontext structure. | |
43 | ||
44 | For the ARM target, there are three parameters to this function. | |
45 | The first is the pc value of the frame under consideration, the | |
46 | second the stack pointer of this frame, and the last is the | |
47 | register number to fetch. | |
48 | ||
49 | If the tm.h file does not define this macro, then it's assumed that | |
50 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
51 | be 0. | |
52 | ||
53 | When it comes time to multi-arching this code, see the identically | |
54 | named machinery in ia64-tdep.c for an example of how it could be | |
55 | done. It should not be necessary to modify the code below where | |
56 | this macro is used. */ | |
57 | ||
3bb04bdd AC |
58 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
59 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
60 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
61 | #endif | |
62 | #else | |
63 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
64 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
65 | #endif |
66 | ||
ed9a39eb JM |
67 | extern void _initialize_arm_tdep (void); |
68 | ||
bc90b915 FN |
69 | /* Number of different reg name sets (options). */ |
70 | static int num_flavor_options; | |
71 | ||
72 | /* We have more registers than the disassembler as gdb can print the value | |
73 | of special registers as well. | |
74 | The general register names are overwritten by whatever is being used by | |
75 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ | |
76 | ||
77 | /* Initial value: Register names used in ARM's ISA documentation. */ | |
78 | static char * arm_register_name_strings[] = | |
da59e081 JM |
79 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
80 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
81 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
82 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
83 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
84 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
bc90b915 | 85 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 86 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 87 | |
bc90b915 | 88 | /* Valid register name flavors. */ |
53904c9e | 89 | static const char **valid_flavors; |
ed9a39eb | 90 | |
bc90b915 | 91 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 92 | static const char *disassembly_flavor; |
bc90b915 | 93 | static int current_option; /* Index to that option in the opcodes table. */ |
96baa820 | 94 | |
ed9a39eb JM |
95 | /* This is used to keep the bfd arch_info in sync with the disassembly |
96 | flavor. */ | |
97 | static void set_disassembly_flavor_sfunc(char *, int, | |
98 | struct cmd_list_element *); | |
99 | static void set_disassembly_flavor (void); | |
100 | ||
101 | static void convert_from_extended (void *ptr, void *dbl); | |
102 | ||
103 | /* Define other aspects of the stack frame. We keep the offsets of | |
104 | all saved registers, 'cause we need 'em a lot! We also keep the | |
105 | current size of the stack frame, and the offset of the frame | |
106 | pointer from the stack pointer (for frameless functions, and when | |
107 | we're still in the prologue of a function with a frame) */ | |
108 | ||
109 | struct frame_extra_info | |
c3b4394c RE |
110 | { |
111 | int framesize; | |
112 | int frameoffset; | |
113 | int framereg; | |
114 | }; | |
ed9a39eb | 115 | |
bc90b915 FN |
116 | /* Addresses for calling Thumb functions have the bit 0 set. |
117 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
118 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
119 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
120 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
121 | ||
ed9a39eb JM |
122 | /* Will a function return an aggregate type in memory or in a |
123 | register? Return 0 if an aggregate type can be returned in a | |
124 | register, 1 if it must be returned in memory. */ | |
085dd6e6 | 125 | |
c906108c | 126 | int |
ed9a39eb | 127 | arm_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 128 | { |
ed9a39eb JM |
129 | int nRc; |
130 | register enum type_code code; | |
131 | ||
132 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
133 | registers. For an aggregate type to be integer like, its size | |
134 | must be less than or equal to REGISTER_SIZE and the offset of | |
135 | each addressable subfield must be zero. Note that bit fields are | |
136 | not addressable, and all addressable subfields of unions always | |
137 | start at offset zero. | |
138 | ||
139 | This function is based on the behaviour of GCC 2.95.1. | |
140 | See: gcc/arm.c: arm_return_in_memory() for details. | |
141 | ||
142 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
143 | parameters correctly for a function returning the following | |
144 | structure: struct { float f;}; This should be returned in memory, | |
145 | not a register. Richard Earnshaw sent me a patch, but I do not | |
146 | know of any way to detect if a function like the above has been | |
147 | compiled with the correct calling convention. */ | |
148 | ||
149 | /* All aggregate types that won't fit in a register must be returned | |
150 | in memory. */ | |
151 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
152 | { | |
153 | return 1; | |
154 | } | |
155 | ||
156 | /* The only aggregate types that can be returned in a register are | |
157 | structs and unions. Arrays must be returned in memory. */ | |
158 | code = TYPE_CODE (type); | |
159 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
160 | { | |
161 | return 1; | |
162 | } | |
163 | ||
164 | /* Assume all other aggregate types can be returned in a register. | |
165 | Run a check for structures, unions and arrays. */ | |
166 | nRc = 0; | |
167 | ||
168 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
169 | { | |
170 | int i; | |
171 | /* Need to check if this struct/union is "integer" like. For | |
172 | this to be true, its size must be less than or equal to | |
173 | REGISTER_SIZE and the offset of each addressable subfield | |
174 | must be zero. Note that bit fields are not addressable, and | |
175 | unions always start at offset zero. If any of the subfields | |
176 | is a floating point type, the struct/union cannot be an | |
177 | integer type. */ | |
178 | ||
179 | /* For each field in the object, check: | |
180 | 1) Is it FP? --> yes, nRc = 1; | |
181 | 2) Is it addressable (bitpos != 0) and | |
182 | not packed (bitsize == 0)? | |
183 | --> yes, nRc = 1 | |
184 | */ | |
185 | ||
186 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
187 | { | |
188 | enum type_code field_type_code; | |
189 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
190 | ||
191 | /* Is it a floating point type field? */ | |
192 | if (field_type_code == TYPE_CODE_FLT) | |
193 | { | |
194 | nRc = 1; | |
195 | break; | |
196 | } | |
197 | ||
198 | /* If bitpos != 0, then we have to care about it. */ | |
199 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
200 | { | |
201 | /* Bitfields are not addressable. If the field bitsize is | |
202 | zero, then the field is not packed. Hence it cannot be | |
203 | a bitfield or any other packed type. */ | |
204 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
205 | { | |
206 | nRc = 1; | |
207 | break; | |
208 | } | |
209 | } | |
210 | } | |
211 | } | |
212 | ||
213 | return nRc; | |
c906108c SS |
214 | } |
215 | ||
216 | int | |
ed9a39eb | 217 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 218 | { |
c906108c SS |
219 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
220 | } | |
221 | ||
222 | /* Set to true if the 32-bit mode is in use. */ | |
223 | ||
224 | int arm_apcs_32 = 1; | |
225 | ||
ed9a39eb JM |
226 | /* Flag set by arm_fix_call_dummy that tells whether the target |
227 | function is a Thumb function. This flag is checked by | |
228 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
229 | its use in valops.c) to pass the function address as an additional | |
230 | parameter. */ | |
c906108c SS |
231 | |
232 | static int target_is_thumb; | |
233 | ||
ed9a39eb JM |
234 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
235 | function is a Thumb function. This flag is checked by | |
236 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
237 | |
238 | static int caller_is_thumb; | |
239 | ||
ed9a39eb JM |
240 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
241 | function. */ | |
c906108c SS |
242 | |
243 | int | |
2a451106 | 244 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 245 | { |
c5aa993b | 246 | struct minimal_symbol *sym; |
c906108c | 247 | |
ed9a39eb | 248 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
249 | if (IS_THUMB_ADDR (memaddr)) |
250 | return 1; | |
251 | ||
ed9a39eb | 252 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
253 | sym = lookup_minimal_symbol_by_pc (memaddr); |
254 | if (sym) | |
255 | { | |
c5aa993b | 256 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
257 | } |
258 | else | |
ed9a39eb JM |
259 | { |
260 | return 0; | |
261 | } | |
c906108c SS |
262 | } |
263 | ||
ed9a39eb JM |
264 | /* Determine if the program counter specified in MEMADDR is in a call |
265 | dummy being called from a Thumb function. */ | |
c906108c SS |
266 | |
267 | int | |
2a451106 | 268 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 269 | { |
c5aa993b | 270 | CORE_ADDR sp = read_sp (); |
c906108c | 271 | |
dfcd3bfb JM |
272 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
273 | is the best we can do. We are trying to determine if the pc is on | |
274 | the stack, which (hopefully) will only happen in a call dummy. | |
275 | We hope the current stack pointer is not so far alway from the dummy | |
276 | frame location (true if we have not pushed large data structures or | |
277 | gone too many levels deep) and that our 1024 is not enough to consider | |
278 | code regions as part of the stack (true for most practical purposes) */ | |
279 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) | |
c906108c SS |
280 | return caller_is_thumb; |
281 | else | |
282 | return 0; | |
283 | } | |
284 | ||
285 | CORE_ADDR | |
ed9a39eb | 286 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
287 | { |
288 | if (arm_pc_is_thumb (val)) | |
289 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
290 | else | |
291 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
292 | } | |
293 | ||
294 | CORE_ADDR | |
ed9a39eb | 295 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
296 | { |
297 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
298 | } | |
299 | ||
392a587b | 300 | int |
ed9a39eb | 301 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 302 | { |
392a587b | 303 | CORE_ADDR func_start, after_prologue; |
96baa820 | 304 | int frameless; |
ed9a39eb | 305 | |
392a587b | 306 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 307 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 308 | |
96baa820 | 309 | /* There are some frameless functions whose first two instructions |
ed9a39eb JM |
310 | follow the standard APCS form, in which case after_prologue will |
311 | be func_start + 8. */ | |
312 | ||
96baa820 | 313 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
314 | return frameless; |
315 | } | |
316 | ||
c906108c | 317 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
318 | push {r7, lr} |
319 | add sp, sp, #-28 | |
320 | add r7, sp, #12 | |
c906108c | 321 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
322 | mov r7, sp |
323 | ||
324 | or like this: | |
325 | push {r7, lr} | |
326 | mov r7, sp | |
327 | sub sp, #12 | |
328 | ||
329 | or, on tpcs, like this: | |
330 | sub sp,#16 | |
331 | push {r7, lr} | |
332 | (many instructions) | |
333 | mov r7, sp | |
334 | sub sp, #12 | |
335 | ||
336 | There is always one instruction of three classes: | |
337 | 1 - push | |
338 | 2 - setting of r7 | |
339 | 3 - adjusting of sp | |
340 | ||
341 | When we have found at least one of each class we are done with the prolog. | |
342 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 343 | */ |
c906108c SS |
344 | |
345 | static CORE_ADDR | |
c7885828 | 346 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
347 | { |
348 | CORE_ADDR current_pc; | |
da59e081 JM |
349 | int findmask = 0; /* findmask: |
350 | bit 0 - push { rlist } | |
351 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
352 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
353 | */ | |
c906108c | 354 | |
c7885828 | 355 | for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2) |
c906108c SS |
356 | { |
357 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
358 | ||
da59e081 JM |
359 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
360 | { | |
361 | findmask |= 1; /* push found */ | |
362 | } | |
363 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ | |
364 | { | |
365 | if ((findmask & 1) == 0) /* before push ? */ | |
366 | continue; | |
367 | else | |
368 | findmask |= 4; /* add/sub sp found */ | |
369 | } | |
370 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
371 | { | |
372 | findmask |= 2; /* setting of r7 found */ | |
373 | } | |
374 | else if (insn == 0x466f) /* mov r7, sp */ | |
375 | { | |
376 | findmask |= 2; /* setting of r7 found */ | |
377 | } | |
3d74b771 FF |
378 | else if (findmask == (4+2+1)) |
379 | { | |
380 | break; /* We have found one of each type of prologue instruction */ | |
381 | } | |
da59e081 JM |
382 | else |
383 | continue; /* something in the prolog that we don't care about or some | |
384 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
385 | } |
386 | ||
387 | return current_pc; | |
388 | } | |
389 | ||
ed9a39eb JM |
390 | /* The APCS (ARM Procedure Call Standard) defines the following |
391 | prologue: | |
c906108c | 392 | |
c5aa993b JM |
393 | mov ip, sp |
394 | [stmfd sp!, {a1,a2,a3,a4}] | |
395 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
396 | [stfe f7, [sp, #-12]!] |
397 | [stfe f6, [sp, #-12]!] | |
398 | [stfe f5, [sp, #-12]!] | |
399 | [stfe f4, [sp, #-12]!] | |
400 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c SS |
401 | |
402 | CORE_ADDR | |
ed9a39eb | 403 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
404 | { |
405 | unsigned long inst; | |
406 | CORE_ADDR skip_pc; | |
407 | CORE_ADDR func_addr, func_end; | |
50f6fb4b | 408 | char *func_name; |
c906108c SS |
409 | struct symtab_and_line sal; |
410 | ||
96baa820 | 411 | /* See what the symbol table says. */ |
ed9a39eb | 412 | |
50f6fb4b | 413 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 414 | { |
50f6fb4b CV |
415 | struct symbol *sym; |
416 | ||
417 | /* Found a function. */ | |
418 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
419 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
420 | { | |
421 | /* Don't use this trick for assembly source files. */ | |
422 | sal = find_pc_line (func_addr, 0); | |
423 | if ((sal.line != 0) && (sal.end < func_end)) | |
424 | return sal.end; | |
425 | } | |
c906108c SS |
426 | } |
427 | ||
428 | /* Check if this is Thumb code. */ | |
429 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 430 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
431 | |
432 | /* Can't find the prologue end in the symbol table, try it the hard way | |
433 | by disassembling the instructions. */ | |
434 | skip_pc = pc; | |
435 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 436 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
437 | return pc; |
438 | ||
439 | skip_pc += 4; | |
440 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 441 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
442 | { |
443 | skip_pc += 4; | |
444 | inst = read_memory_integer (skip_pc, 4); | |
445 | } | |
446 | ||
c5aa993b | 447 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
448 | return pc; |
449 | ||
450 | skip_pc += 4; | |
451 | inst = read_memory_integer (skip_pc, 4); | |
452 | ||
453 | /* Any insns after this point may float into the code, if it makes | |
ed9a39eb JM |
454 | for better instruction scheduling, so we skip them only if we |
455 | find them, but still consdier the function to be frame-ful. */ | |
c906108c | 456 | |
ed9a39eb JM |
457 | /* We may have either one sfmfd instruction here, or several stfe |
458 | insns, depending on the version of floating point code we | |
459 | support. */ | |
c5aa993b | 460 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
461 | { |
462 | skip_pc += 4; | |
463 | inst = read_memory_integer (skip_pc, 4); | |
464 | } | |
465 | else | |
466 | { | |
c5aa993b JM |
467 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
468 | { | |
469 | skip_pc += 4; | |
470 | inst = read_memory_integer (skip_pc, 4); | |
471 | } | |
c906108c SS |
472 | } |
473 | ||
c5aa993b | 474 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
475 | skip_pc += 4; |
476 | ||
477 | return skip_pc; | |
478 | } | |
c5aa993b | 479 | /* *INDENT-OFF* */ |
c906108c SS |
480 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
481 | This function decodes a Thumb function prologue to determine: | |
482 | 1) the size of the stack frame | |
483 | 2) which registers are saved on it | |
484 | 3) the offsets of saved regs | |
485 | 4) the offset from the stack pointer to the frame pointer | |
486 | This information is stored in the "extra" fields of the frame_info. | |
487 | ||
da59e081 JM |
488 | A typical Thumb function prologue would create this stack frame |
489 | (offsets relative to FP) | |
c906108c SS |
490 | old SP -> 24 stack parameters |
491 | 20 LR | |
492 | 16 R7 | |
493 | R7 -> 0 local variables (16 bytes) | |
494 | SP -> -12 additional stack space (12 bytes) | |
495 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
496 | 12 bytes. The frame register is R7. |
497 | ||
498 | The comments for thumb_skip_prolog() describe the algorithm we use to detect | |
499 | the end of the prolog */ | |
c5aa993b JM |
500 | /* *INDENT-ON* */ |
501 | ||
c906108c | 502 | static void |
ed9a39eb | 503 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
504 | { |
505 | CORE_ADDR prologue_start; | |
506 | CORE_ADDR prologue_end; | |
507 | CORE_ADDR current_pc; | |
c5aa993b | 508 | int saved_reg[16]; /* which register has been copied to register n? */ |
da59e081 JM |
509 | int findmask = 0; /* findmask: |
510 | bit 0 - push { rlist } | |
511 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
512 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
513 | */ | |
c5aa993b | 514 | int i; |
c906108c | 515 | |
c5aa993b | 516 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
517 | { |
518 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
519 | ||
c5aa993b | 520 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
521 | prologue_end = fi->pc; |
522 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 523 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
524 | } |
525 | else | |
c5aa993b JM |
526 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
527 | /* 16 pushes, an add, and "mv fp,sp" */ | |
c906108c SS |
528 | |
529 | prologue_end = min (prologue_end, fi->pc); | |
530 | ||
531 | /* Initialize the saved register map. When register H is copied to | |
532 | register L, we will put H in saved_reg[L]. */ | |
533 | for (i = 0; i < 16; i++) | |
534 | saved_reg[i] = i; | |
535 | ||
536 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
537 | frame pointer, adjust the stack pointer, and save registers. |
538 | Do this until all basic prolog instructions are found. */ | |
c906108c | 539 | |
c3b4394c | 540 | fi->extra_info->framesize = 0; |
da59e081 JM |
541 | for (current_pc = prologue_start; |
542 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
543 | current_pc += 2) | |
c906108c SS |
544 | { |
545 | unsigned short insn; | |
546 | int regno; | |
547 | int offset; | |
548 | ||
549 | insn = read_memory_unsigned_integer (current_pc, 2); | |
550 | ||
c5aa993b | 551 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 552 | { |
da59e081 JM |
553 | int mask; |
554 | findmask |= 1; /* push found */ | |
c906108c SS |
555 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
556 | whether to save LR (R14). */ | |
da59e081 | 557 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c SS |
558 | |
559 | /* Calculate offsets of saved R0-R7 and LR. */ | |
560 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
561 | if (mask & (1 << regno)) | |
c5aa993b | 562 | { |
c3b4394c RE |
563 | fi->extra_info->framesize += 4; |
564 | fi->saved_regs[saved_reg[regno]] = | |
565 | -(fi->extra_info->framesize); | |
c906108c SS |
566 | saved_reg[regno] = regno; /* reset saved register map */ |
567 | } | |
568 | } | |
da59e081 | 569 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ |
c906108c | 570 | { |
da59e081 JM |
571 | if ((findmask & 1) == 0) /* before push ? */ |
572 | continue; | |
573 | else | |
574 | findmask |= 4; /* add/sub sp found */ | |
575 | ||
c5aa993b | 576 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
da59e081 JM |
577 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
578 | { | |
c3b4394c | 579 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
580 | offset = -offset; |
581 | } | |
c3b4394c | 582 | fi->extra_info->framesize -= offset; |
c906108c SS |
583 | } |
584 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
585 | { | |
da59e081 | 586 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
587 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
588 | /* get scaled offset */ | |
589 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 590 | } |
da59e081 | 591 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 592 | { |
da59e081 | 593 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
594 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
595 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
596 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; |
597 | } | |
598 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
599 | { | |
c5aa993b | 600 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 601 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 602 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
603 | } |
604 | else | |
da59e081 JM |
605 | continue; /* something in the prolog that we don't care about or some |
606 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
607 | } |
608 | } | |
609 | ||
ed9a39eb JM |
610 | /* Check if prologue for this frame's PC has already been scanned. If |
611 | it has, copy the relevant information about that prologue and | |
c906108c SS |
612 | return non-zero. Otherwise do not copy anything and return zero. |
613 | ||
614 | The information saved in the cache includes: | |
c5aa993b JM |
615 | * the frame register number; |
616 | * the size of the stack frame; | |
617 | * the offsets of saved regs (relative to the old SP); and | |
618 | * the offset from the stack pointer to the frame pointer | |
c906108c | 619 | |
ed9a39eb JM |
620 | The cache contains only one entry, since this is adequate for the |
621 | typical sequence of prologue scan requests we get. When performing | |
622 | a backtrace, GDB will usually ask to scan the same function twice | |
623 | in a row (once to get the frame chain, and once to fill in the | |
624 | extra frame information). */ | |
c906108c SS |
625 | |
626 | static struct frame_info prologue_cache; | |
627 | ||
628 | static int | |
ed9a39eb | 629 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
630 | { |
631 | int i; | |
632 | ||
633 | if (fi->pc == prologue_cache.pc) | |
634 | { | |
c3b4394c RE |
635 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
636 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
637 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
638 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
639 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
640 | return 1; |
641 | } | |
642 | else | |
643 | return 0; | |
644 | } | |
645 | ||
646 | ||
ed9a39eb | 647 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
648 | |
649 | static void | |
ed9a39eb | 650 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
651 | { |
652 | int i; | |
653 | ||
c5aa993b | 654 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
655 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
656 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
657 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 658 | |
c3b4394c RE |
659 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
660 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
661 | } |
662 | ||
663 | ||
ed9a39eb | 664 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
665 | 1) the size of the stack frame |
666 | 2) which registers are saved on it | |
667 | 3) the offsets of saved regs | |
668 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
669 | This information is stored in the "extra" fields of the frame_info. |
670 | ||
96baa820 JM |
671 | There are two basic forms for the ARM prologue. The fixed argument |
672 | function call will look like: | |
ed9a39eb JM |
673 | |
674 | mov ip, sp | |
675 | stmfd sp!, {fp, ip, lr, pc} | |
676 | sub fp, ip, #4 | |
677 | [sub sp, sp, #4] | |
96baa820 | 678 | |
c906108c | 679 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
680 | IP -> 4 (caller's stack) |
681 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
682 | -4 LR (return address in caller) | |
683 | -8 IP (copy of caller's SP) | |
684 | -12 FP (caller's FP) | |
685 | SP -> -28 Local variables | |
686 | ||
c906108c | 687 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
688 | 28 bytes. The stmfd call can also save any of the vN registers it |
689 | plans to use, which increases the frame size accordingly. | |
690 | ||
691 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
692 | because the ARM Store instructions always store PC + 8 when you read | |
693 | the PC register. | |
ed9a39eb | 694 | |
96baa820 JM |
695 | A variable argument function call will look like: |
696 | ||
ed9a39eb JM |
697 | mov ip, sp |
698 | stmfd sp!, {a1, a2, a3, a4} | |
699 | stmfd sp!, {fp, ip, lr, pc} | |
700 | sub fp, ip, #20 | |
701 | ||
96baa820 | 702 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
703 | IP -> 20 (caller's stack) |
704 | 16 A4 | |
705 | 12 A3 | |
706 | 8 A2 | |
707 | 4 A1 | |
708 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
709 | -4 LR (return address in caller) | |
710 | -8 IP (copy of caller's SP) | |
711 | -12 FP (caller's FP) | |
712 | SP -> -28 Local variables | |
96baa820 JM |
713 | |
714 | The frame size would thus be 48 bytes, and the frame offset would be | |
715 | 28 bytes. | |
716 | ||
717 | There is another potential complication, which is that the optimizer | |
718 | will try to separate the store of fp in the "stmfd" instruction from | |
719 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
720 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
721 | ||
722 | Also, note, the original version of the ARM toolchain claimed that there | |
723 | should be an | |
724 | ||
725 | instruction at the end of the prologue. I have never seen GCC produce | |
726 | this, and the ARM docs don't mention it. We still test for it below in | |
727 | case it happens... | |
ed9a39eb JM |
728 | |
729 | */ | |
c906108c SS |
730 | |
731 | static void | |
ed9a39eb | 732 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
733 | { |
734 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 735 | LONGEST return_value; |
c906108c SS |
736 | CORE_ADDR prologue_start, prologue_end, current_pc; |
737 | ||
738 | /* Check if this function is already in the cache of frame information. */ | |
739 | if (check_prologue_cache (fi)) | |
740 | return; | |
741 | ||
742 | /* Assume there is no frame until proven otherwise. */ | |
c3b4394c RE |
743 | fi->extra_info->framereg = SP_REGNUM; |
744 | fi->extra_info->framesize = 0; | |
745 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
746 | |
747 | /* Check for Thumb prologue. */ | |
748 | if (arm_pc_is_thumb (fi->pc)) | |
749 | { | |
750 | thumb_scan_prologue (fi); | |
751 | save_prologue_cache (fi); | |
752 | return; | |
753 | } | |
754 | ||
755 | /* Find the function prologue. If we can't find the function in | |
756 | the symbol table, peek in the stack frame to find the PC. */ | |
757 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
758 | { | |
2a451106 KB |
759 | /* One way to find the end of the prologue (which works well |
760 | for unoptimized code) is to do the following: | |
761 | ||
762 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
763 | ||
764 | if (sal.line == 0) | |
765 | prologue_end = fi->pc; | |
766 | else if (sal.end < prologue_end) | |
767 | prologue_end = sal.end; | |
768 | ||
769 | This mechanism is very accurate so long as the optimizer | |
770 | doesn't move any instructions from the function body into the | |
771 | prologue. If this happens, sal.end will be the last | |
772 | instruction in the first hunk of prologue code just before | |
773 | the first instruction that the scheduler has moved from | |
774 | the body to the prologue. | |
775 | ||
776 | In order to make sure that we scan all of the prologue | |
777 | instructions, we use a slightly less accurate mechanism which | |
778 | may scan more than necessary. To help compensate for this | |
779 | lack of accuracy, the prologue scanning loop below contains | |
780 | several clauses which'll cause the loop to terminate early if | |
781 | an implausible prologue instruction is encountered. | |
782 | ||
783 | The expression | |
784 | ||
785 | prologue_start + 64 | |
786 | ||
787 | is a suitable endpoint since it accounts for the largest | |
788 | possible prologue plus up to five instructions inserted by | |
789 | the scheduler. */ | |
790 | ||
791 | if (prologue_end > prologue_start + 64) | |
792 | { | |
793 | prologue_end = prologue_start + 64; /* See above. */ | |
794 | } | |
c906108c SS |
795 | } |
796 | else | |
797 | { | |
798 | /* Get address of the stmfd in the prologue of the callee; the saved | |
96baa820 | 799 | PC is the address of the stmfd + 8. */ |
16a0f3e7 EZ |
800 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
801 | return; | |
802 | else | |
803 | { | |
804 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
805 | prologue_end = prologue_start + 64; /* See above. */ | |
806 | } | |
c906108c SS |
807 | } |
808 | ||
809 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 810 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 811 | |
96baa820 JM |
812 | Be careful, however, and if it doesn't look like a prologue, |
813 | don't try to scan it. If, for instance, a frameless function | |
814 | begins with stmfd sp!, then we will tell ourselves there is | |
815 | a frame, which will confuse stack traceback, as well ad"finish" | |
816 | and other operations that rely on a knowledge of the stack | |
817 | traceback. | |
818 | ||
819 | In the APCS, the prologue should start with "mov ip, sp" so | |
d4473757 KB |
820 | if we don't see this as the first insn, we will stop. [Note: |
821 | This doesn't seem to be true any longer, so it's now an optional | |
822 | part of the prologue. - Kevin Buettner, 2001-11-20] */ | |
c906108c SS |
823 | |
824 | sp_offset = fp_offset = 0; | |
c906108c | 825 | |
ed9a39eb JM |
826 | if (read_memory_unsigned_integer (prologue_start, 4) |
827 | == 0xe1a0c00d) /* mov ip, sp */ | |
d4473757 KB |
828 | current_pc = prologue_start + 4; |
829 | else | |
830 | current_pc = prologue_start; | |
831 | ||
832 | for (; current_pc < prologue_end; current_pc += 4) | |
96baa820 | 833 | { |
d4473757 KB |
834 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
835 | ||
836 | if ((insn & 0xffff0000) == 0xe92d0000) | |
837 | /* stmfd sp!, {..., fp, ip, lr, pc} | |
838 | or | |
839 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 840 | { |
d4473757 | 841 | int mask = insn & 0xffff; |
ed9a39eb | 842 | |
d4473757 KB |
843 | /* Calculate offsets of saved registers. */ |
844 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
845 | if (mask & (1 << regno)) | |
846 | { | |
847 | sp_offset -= 4; | |
c3b4394c | 848 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
849 | } |
850 | } | |
851 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
852 | { | |
853 | unsigned imm = insn & 0xff; /* immediate value */ | |
854 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
855 | imm = (imm >> rot) | (imm << (32 - rot)); | |
856 | fp_offset = -imm; | |
c3b4394c | 857 | fi->extra_info->framereg = FP_REGNUM; |
d4473757 KB |
858 | } |
859 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
860 | { | |
861 | unsigned imm = insn & 0xff; /* immediate value */ | |
862 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
863 | imm = (imm >> rot) | (imm << (32 - rot)); | |
864 | sp_offset -= imm; | |
865 | } | |
866 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
867 | { | |
868 | sp_offset -= 12; | |
869 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
c3b4394c | 870 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
871 | } |
872 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
873 | { | |
874 | int n_saved_fp_regs; | |
875 | unsigned int fp_start_reg, fp_bound_reg; | |
876 | ||
877 | if ((insn & 0x800) == 0x800) /* N0 is set */ | |
96baa820 | 878 | { |
d4473757 KB |
879 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
880 | n_saved_fp_regs = 3; | |
881 | else | |
882 | n_saved_fp_regs = 1; | |
96baa820 | 883 | } |
d4473757 | 884 | else |
96baa820 | 885 | { |
d4473757 KB |
886 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
887 | n_saved_fp_regs = 2; | |
888 | else | |
889 | n_saved_fp_regs = 4; | |
96baa820 | 890 | } |
d4473757 KB |
891 | |
892 | fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); | |
893 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; | |
894 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
895 | { |
896 | sp_offset -= 12; | |
c3b4394c | 897 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 898 | } |
c906108c | 899 | } |
d4473757 KB |
900 | else if ((insn & 0xf0000000) != 0xe0000000) |
901 | break; /* Condition not true, exit early */ | |
902 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ | |
903 | break; /* Don't scan past a block load */ | |
904 | else | |
905 | /* The optimizer might shove anything into the prologue, | |
906 | so we just skip what we don't recognize. */ | |
907 | continue; | |
c906108c SS |
908 | } |
909 | ||
910 | /* The frame size is just the negative of the offset (from the original SP) | |
911 | of the last thing thing we pushed on the stack. The frame offset is | |
912 | [new FP] - [new SP]. */ | |
c3b4394c RE |
913 | fi->extra_info->framesize = -sp_offset; |
914 | if (fi->extra_info->framereg == FP_REGNUM) | |
915 | fi->extra_info->frameoffset = fp_offset - sp_offset; | |
d4473757 | 916 | else |
c3b4394c | 917 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 918 | |
c906108c SS |
919 | save_prologue_cache (fi); |
920 | } | |
921 | ||
ed9a39eb JM |
922 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
923 | One thing we might want to do here is to check REGNUM against the | |
924 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
925 | the stack somewhere. This would provide a graceful failure mode | |
926 | when trying to get the value of caller-saves registers for an inner | |
927 | frame. */ | |
c906108c SS |
928 | |
929 | static CORE_ADDR | |
ed9a39eb | 930 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c SS |
931 | { |
932 | for (; fi; fi = fi->next) | |
c5aa993b JM |
933 | |
934 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
c906108c SS |
935 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
936 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
937 | else | |
938 | #endif | |
c3b4394c RE |
939 | if (fi->saved_regs[regnum] != 0) |
940 | return read_memory_integer (fi->saved_regs[regnum], | |
c5aa993b | 941 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
942 | return read_register (regnum); |
943 | } | |
c5aa993b | 944 | /* *INDENT-OFF* */ |
c906108c SS |
945 | /* Function: frame_chain |
946 | Given a GDB frame, determine the address of the calling function's frame. | |
947 | This will be used to create a new GDB frame struct, and then | |
948 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
949 | For ARM, we save the frame size when we initialize the frame_info. | |
950 | ||
951 | The original definition of this function was a macro in tm-arm.h: | |
952 | { In the case of the ARM, the frame's nominal address is the FP value, | |
953 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
954 | ||
955 | #define FRAME_CHAIN(thisframe) \ | |
956 | ((thisframe)->pc >= LOWEST_PC ? \ | |
957 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
958 | 0) | |
959 | */ | |
c5aa993b JM |
960 | /* *INDENT-ON* */ |
961 | ||
c906108c | 962 | CORE_ADDR |
ed9a39eb | 963 | arm_frame_chain (struct frame_info *fi) |
c906108c | 964 | { |
c5aa993b | 965 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
966 | CORE_ADDR fn_start, callers_pc, fp; |
967 | ||
968 | /* is this a dummy frame? */ | |
969 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 970 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
971 | |
972 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 973 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
c906108c | 974 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
c5aa993b JM |
975 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
976 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
977 | |
978 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
979 | if (fn_start == entry_point_address ()) | |
c5aa993b | 980 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
981 | #endif |
982 | CORE_ADDR caller_pc, fn_start; | |
c3b4394c | 983 | int framereg = fi->extra_info->framereg; |
c906108c SS |
984 | |
985 | if (fi->pc < LOWEST_PC) | |
986 | return 0; | |
987 | ||
988 | /* If the caller is the startup code, we're at the end of the chain. */ | |
989 | caller_pc = FRAME_SAVED_PC (fi); | |
990 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
991 | if (fn_start == entry_point_address ()) | |
992 | return 0; | |
993 | ||
994 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
995 | the frame register of the caller is different from ours. | |
996 | So we must scan the prologue of the caller to determine its | |
997 | frame register number. */ | |
c3b4394c RE |
998 | /* XXX Fixme, we should try to do this without creating a temporary |
999 | caller_fi. */ | |
c906108c SS |
1000 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1001 | { | |
c3b4394c RE |
1002 | struct frame_info caller_fi; |
1003 | struct cleanup *old_chain; | |
1004 | ||
1005 | /* Create a temporary frame suitable for scanning the caller's | |
1006 | prologue. (Ugh.) */ | |
c5aa993b | 1007 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1008 | caller_fi.extra_info = (struct frame_extra_info *) |
1009 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1010 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1011 | caller_fi.saved_regs = (CORE_ADDR *) | |
1012 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1013 | make_cleanup (xfree, caller_fi.saved_regs); | |
1014 | ||
1015 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1016 | caller_fi.pc = caller_pc; |
c5aa993b | 1017 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1018 | framereg = caller_fi.extra_info->framereg; |
1019 | ||
1020 | /* Deallocate the storage associated with the temporary frame | |
1021 | created above. */ | |
1022 | do_cleanups (old_chain); | |
c906108c SS |
1023 | } |
1024 | ||
1025 | /* If the caller used a frame register, return its value. | |
1026 | Otherwise, return the caller's stack pointer. */ | |
1027 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
1028 | return arm_find_callers_reg (fi, framereg); | |
1029 | else | |
c3b4394c | 1030 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1031 | } |
1032 | ||
ed9a39eb JM |
1033 | /* This function actually figures out the frame address for a given pc |
1034 | and sp. This is tricky because we sometimes don't use an explicit | |
1035 | frame pointer, and the previous stack pointer isn't necessarily | |
1036 | recorded on the stack. The only reliable way to get this info is | |
1037 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1038 | this is the next frame up the chain AFTER a frameless function. If | |
1039 | this is true, then the frame value for this frame is still in the | |
1040 | fp register. */ | |
c906108c SS |
1041 | |
1042 | void | |
ed9a39eb | 1043 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1044 | { |
1045 | int reg; | |
f079148d | 1046 | CORE_ADDR sp; |
c906108c | 1047 | |
c3b4394c RE |
1048 | if (fi->saved_regs == NULL) |
1049 | frame_saved_regs_zalloc (fi); | |
1050 | ||
1051 | fi->extra_info = (struct frame_extra_info *) | |
1052 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1053 | ||
1054 | fi->extra_info->framesize = 0; | |
1055 | fi->extra_info->frameoffset = 0; | |
1056 | fi->extra_info->framereg = 0; | |
1057 | ||
c906108c SS |
1058 | if (fi->next) |
1059 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1060 | ||
c3b4394c | 1061 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1062 | |
c5aa993b | 1063 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1064 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1065 | { | |
1066 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
1067 | by assuming it's always FP. */ |
1068 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
c3b4394c RE |
1069 | fi->extra_info->framesize = 0; |
1070 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
1071 | return; |
1072 | } | |
c5aa993b | 1073 | else |
c906108c | 1074 | #endif |
2a451106 | 1075 | |
f079148d KB |
1076 | /* Compute stack pointer for this frame. We use this value for both the |
1077 | sigtramp and call dummy cases. */ | |
1078 | if (!fi->next) | |
1079 | sp = read_sp(); | |
1080 | else | |
c3b4394c RE |
1081 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1082 | + fi->next->extra_info->framesize); | |
f079148d | 1083 | |
2a451106 KB |
1084 | /* Determine whether or not we're in a sigtramp frame. |
1085 | Unfortunately, it isn't sufficient to test | |
1086 | fi->signal_handler_caller because this value is sometimes set | |
1087 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1088 | fi->signal_handler_caller and IN_SIGTRAMP to determine if we need | |
1089 | to use the sigcontext addresses for the saved registers. | |
1090 | ||
1091 | Note: If an ARM IN_SIGTRAMP method ever needs to compare against | |
1092 | the name of the function, the code below will have to be changed | |
1093 | to first fetch the name of the function and then pass this name | |
f079148d | 1094 | to IN_SIGTRAMP. */ |
2a451106 | 1095 | |
3bb04bdd | 1096 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
dd96c05b | 1097 | && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1098 | { |
2a451106 | 1099 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1100 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 KB |
1101 | |
1102 | /* FIXME: What about thumb mode? */ | |
c3b4394c RE |
1103 | fi->extra_info->framereg = SP_REGNUM; |
1104 | fi->frame = | |
1105 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1106 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1107 | fi->extra_info->framesize = 0; | |
1108 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1109 | |
1110 | } | |
f079148d KB |
1111 | else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame)) |
1112 | { | |
1113 | CORE_ADDR rp; | |
1114 | CORE_ADDR callers_sp; | |
1115 | ||
1116 | /* Set rp point at the high end of the saved registers. */ | |
1117 | rp = fi->frame - REGISTER_SIZE; | |
1118 | ||
1119 | /* Fill in addresses of saved registers. */ | |
c3b4394c | 1120 | fi->saved_regs[PS_REGNUM] = rp; |
f079148d KB |
1121 | rp -= REGISTER_RAW_SIZE (PS_REGNUM); |
1122 | for (reg = PC_REGNUM; reg >= 0; reg--) | |
1123 | { | |
c3b4394c | 1124 | fi->saved_regs[reg] = rp; |
f079148d KB |
1125 | rp -= REGISTER_RAW_SIZE (reg); |
1126 | } | |
1127 | ||
c3b4394c | 1128 | callers_sp = read_memory_integer (fi->saved_regs[SP_REGNUM], |
f079148d | 1129 | REGISTER_RAW_SIZE (SP_REGNUM)); |
c3b4394c RE |
1130 | fi->extra_info->framereg = FP_REGNUM; |
1131 | fi->extra_info->framesize = callers_sp - sp; | |
1132 | fi->extra_info->frameoffset = fi->frame - sp; | |
f079148d | 1133 | } |
2a451106 | 1134 | else |
c906108c SS |
1135 | { |
1136 | arm_scan_prologue (fi); | |
1137 | ||
104c1213 JM |
1138 | if (!fi->next) |
1139 | /* this is the innermost frame? */ | |
c3b4394c RE |
1140 | fi->frame = read_register (fi->extra_info->framereg); |
1141 | else if (fi->extra_info->framereg == FP_REGNUM | |
1142 | || fi->extra_info->framereg == THUMB_FP_REGNUM) | |
ed9a39eb JM |
1143 | { |
1144 | /* not the innermost frame */ | |
1145 | /* If we have an FP, the callee saved it. */ | |
c3b4394c | 1146 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1147 | fi->frame = |
c3b4394c RE |
1148 | read_memory_integer (fi->next |
1149 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1150 | else if (fromleaf) |
1151 | /* If we were called by a frameless fn. then our frame is | |
1152 | still in the frame pointer register on the board... */ | |
1153 | fi->frame = read_fp (); | |
1154 | } | |
c906108c | 1155 | |
ed9a39eb JM |
1156 | /* Calculate actual addresses of saved registers using offsets |
1157 | determined by arm_scan_prologue. */ | |
c906108c | 1158 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1159 | if (fi->saved_regs[reg] != 0) |
1160 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1161 | - fi->extra_info->frameoffset); | |
c906108c SS |
1162 | } |
1163 | } | |
1164 | ||
1165 | ||
ed9a39eb JM |
1166 | /* Find the caller of this frame. We do this by seeing if LR_REGNUM |
1167 | is saved in the stack anywhere, otherwise we get it from the | |
1168 | registers. | |
c906108c SS |
1169 | |
1170 | The old definition of this function was a macro: | |
c5aa993b | 1171 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1172 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c SS |
1173 | |
1174 | CORE_ADDR | |
ed9a39eb | 1175 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1176 | { |
c5aa993b | 1177 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1178 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1179 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
1180 | else | |
1181 | #endif | |
c3b4394c RE |
1182 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
1183 | fi->frame)) | |
f079148d | 1184 | { |
c3b4394c RE |
1185 | return read_memory_integer (fi->saved_regs[PC_REGNUM], |
1186 | REGISTER_RAW_SIZE (PC_REGNUM)); | |
f079148d KB |
1187 | } |
1188 | else | |
c906108c SS |
1189 | { |
1190 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
1191 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1192 | } | |
1193 | } | |
1194 | ||
c906108c SS |
1195 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1196 | Examine the Program Status Register to decide which state we're in. */ | |
1197 | ||
1198 | CORE_ADDR | |
ed9a39eb | 1199 | arm_target_read_fp (void) |
c906108c SS |
1200 | { |
1201 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
1202 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
1203 | else | |
c5aa993b | 1204 | return read_register (FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1205 | } |
1206 | ||
ed9a39eb | 1207 | /* Calculate the frame offsets of the saved registers (ARM version). */ |
c906108c | 1208 | |
c906108c | 1209 | void |
c3b4394c | 1210 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1211 | { |
c3b4394c RE |
1212 | |
1213 | if (fip->saved_regs) | |
1214 | return; | |
1215 | ||
1216 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1217 | } |
1218 | ||
c906108c | 1219 | void |
ed9a39eb | 1220 | arm_push_dummy_frame (void) |
c906108c SS |
1221 | { |
1222 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
1223 | CORE_ADDR sp = old_sp; | |
1224 | CORE_ADDR fp, prologue_start; | |
1225 | int regnum; | |
1226 | ||
1227 | /* Push the two dummy prologue instructions in reverse order, | |
1228 | so that they'll be in the correct low-to-high order in memory. */ | |
1229 | /* sub fp, ip, #4 */ | |
1230 | sp = push_word (sp, 0xe24cb004); | |
1231 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1232 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1233 | ||
ed9a39eb JM |
1234 | /* Push a pointer to the dummy prologue + 12, because when stm |
1235 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1236 | instruction itself plus 12. */ |
1237 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1238 | |
f079148d KB |
1239 | /* Push the processor status. */ |
1240 | sp = push_word (sp, read_register (PS_REGNUM)); | |
1241 | ||
1242 | /* Push all 16 registers starting with r15. */ | |
1243 | for (regnum = PC_REGNUM; regnum >= 0; regnum--) | |
c906108c | 1244 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1245 | |
f079148d | 1246 | /* Update fp (for both Thumb and ARM) and sp. */ |
c906108c SS |
1247 | write_register (FP_REGNUM, fp); |
1248 | write_register (THUMB_FP_REGNUM, fp); | |
1249 | write_register (SP_REGNUM, sp); | |
1250 | } | |
1251 | ||
1252 | /* Fix up the call dummy, based on whether the processor is currently | |
ed9a39eb JM |
1253 | in Thumb or ARM mode, and whether the target function is Thumb or |
1254 | ARM. There are three different situations requiring three | |
c906108c SS |
1255 | different dummies: |
1256 | ||
1257 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1258 | been copied into the dummy parameter to this function. |
c906108c | 1259 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1260 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1261 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1262 | works for calling both ARM and Thumb functions. |
c906108c | 1263 | |
ed9a39eb JM |
1264 | All three call dummies expect to receive the target function |
1265 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c SS |
1266 | |
1267 | void | |
ed9a39eb | 1268 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1269 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1270 | { |
1271 | static short thumb_dummy[4] = | |
1272 | { | |
c5aa993b JM |
1273 | 0xf000, 0xf801, /* bl label */ |
1274 | 0xdf18, /* swi 24 */ | |
1275 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1276 | }; |
1277 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1278 | ||
1279 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 1280 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
c906108c | 1281 | |
ed9a39eb JM |
1282 | /* If the target function is Thumb, set the low bit of the function |
1283 | address. And if the CPU is currently in ARM mode, patch the | |
1284 | second instruction of call dummy to use a BX instruction to | |
1285 | switch to Thumb mode. */ | |
c906108c SS |
1286 | target_is_thumb = arm_pc_is_thumb (fun); |
1287 | if (target_is_thumb) | |
1288 | { | |
1289 | fun |= 1; | |
1290 | if (!caller_is_thumb) | |
1291 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1292 | } | |
1293 | ||
1294 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1295 | instead of the ARM one that's already been copied. This will | |
1296 | work for both Thumb and ARM target functions. */ | |
1297 | if (caller_is_thumb) | |
1298 | { | |
1299 | int i; | |
1300 | char *p = dummy; | |
1301 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1302 | ||
1303 | for (i = 0; i < len; i++) | |
1304 | { | |
1305 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1306 | p += sizeof (thumb_dummy[0]); | |
1307 | } | |
1308 | } | |
1309 | ||
ed9a39eb JM |
1310 | /* Put the target address in r4; the call dummy will copy this to |
1311 | the PC. */ | |
c906108c SS |
1312 | write_register (4, fun); |
1313 | } | |
1314 | ||
c906108c | 1315 | /* Return the offset in the call dummy of the instruction that needs |
ed9a39eb JM |
1316 | to have a breakpoint placed on it. This is the offset of the 'swi |
1317 | 24' instruction, which is no longer actually used, but simply acts | |
c906108c SS |
1318 | as a place-holder now. |
1319 | ||
ed9a39eb | 1320 | This implements the CALL_DUMMY_BREAK_OFFSET macro. */ |
c906108c SS |
1321 | |
1322 | int | |
ed9a39eb | 1323 | arm_call_dummy_breakpoint_offset (void) |
c906108c SS |
1324 | { |
1325 | if (caller_is_thumb) | |
1326 | return 4; | |
1327 | else | |
1328 | return 8; | |
1329 | } | |
1330 | ||
ed9a39eb JM |
1331 | /* Note: ScottB |
1332 | ||
1333 | This function does not support passing parameters using the FPA | |
1334 | variant of the APCS. It passes any floating point arguments in the | |
1335 | general registers and/or on the stack. */ | |
c906108c SS |
1336 | |
1337 | CORE_ADDR | |
ea7c478f | 1338 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1339 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1340 | { |
ed9a39eb JM |
1341 | char *fp; |
1342 | int argnum, argreg, nstack_size; | |
1343 | ||
1344 | /* Walk through the list of args and determine how large a temporary | |
1345 | stack is required. Need to take care here as structs may be | |
1346 | passed on the stack, and we have to to push them. */ | |
1347 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
1348 | if (struct_return) /* The struct address goes in A1. */ | |
1349 | nstack_size += REGISTER_SIZE; | |
1350 | ||
1351 | /* Walk through the arguments and add their size to nstack_size. */ | |
1352 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1353 | { |
c906108c | 1354 | int len; |
ed9a39eb JM |
1355 | struct type *arg_type; |
1356 | ||
1357 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1358 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1359 | |
ed9a39eb JM |
1360 | /* ANSI C code passes float arguments as integers, K&R code |
1361 | passes float arguments as doubles. Correct for this here. */ | |
1362 | if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) | |
1363 | nstack_size += FP_REGISTER_VIRTUAL_SIZE; | |
1364 | else | |
1365 | nstack_size += len; | |
1366 | } | |
c906108c | 1367 | |
ed9a39eb JM |
1368 | /* Allocate room on the stack, and initialize our stack frame |
1369 | pointer. */ | |
1370 | fp = NULL; | |
1371 | if (nstack_size > 0) | |
1372 | { | |
1373 | sp -= nstack_size; | |
1374 | fp = (char *) sp; | |
1375 | } | |
1376 | ||
1377 | /* Initialize the integer argument register pointer. */ | |
c906108c | 1378 | argreg = A1_REGNUM; |
c906108c | 1379 | |
ed9a39eb JM |
1380 | /* The struct_return pointer occupies the first parameter passing |
1381 | register. */ | |
c906108c | 1382 | if (struct_return) |
c5aa993b | 1383 | write_register (argreg++, struct_addr); |
c906108c | 1384 | |
ed9a39eb JM |
1385 | /* Process arguments from left to right. Store as many as allowed |
1386 | in the parameter passing registers (A1-A4), and save the rest on | |
1387 | the temporary stack. */ | |
c5aa993b | 1388 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1389 | { |
ed9a39eb | 1390 | int len; |
c5aa993b | 1391 | char *val; |
c5aa993b | 1392 | CORE_ADDR regval; |
ed9a39eb JM |
1393 | enum type_code typecode; |
1394 | struct type *arg_type, *target_type; | |
1395 | ||
1396 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1397 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1398 | len = TYPE_LENGTH (arg_type); | |
1399 | typecode = TYPE_CODE (arg_type); | |
1400 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1401 | ||
1402 | /* ANSI C code passes float arguments as integers, K&R code | |
1403 | passes float arguments as doubles. The .stabs record for | |
1404 | for ANSI prototype floating point arguments records the | |
1405 | type as FP_INTEGER, while a K&R style (no prototype) | |
1406 | .stabs records the type as FP_FLOAT. In this latter case | |
1407 | the compiler converts the float arguments to double before | |
1408 | calling the function. */ | |
1409 | if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) | |
1410 | { | |
a37b3cc0 AC |
1411 | DOUBLEST dblval; |
1412 | dblval = extract_floating (val, len); | |
1413 | len = TARGET_DOUBLE_BIT / TARGET_CHAR_BIT; | |
1414 | val = alloca (len); | |
1415 | store_floating (val, len, dblval); | |
ed9a39eb | 1416 | } |
da59e081 JM |
1417 | #if 1 |
1418 | /* I don't know why this code was disable. The only logical use | |
1419 | for a function pointer is to call that function, so setting | |
1420 | the mode bit is perfectly fine. FN */ | |
ed9a39eb | 1421 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1422 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1423 | if (TYPE_CODE_PTR == typecode |
1424 | && NULL != target_type | |
1425 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1426 | { |
ed9a39eb | 1427 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1428 | if (arm_pc_is_thumb (regval)) |
1429 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1430 | } | |
c906108c | 1431 | #endif |
ed9a39eb JM |
1432 | /* Copy the argument to general registers or the stack in |
1433 | register-sized pieces. Large arguments are split between | |
1434 | registers and stack. */ | |
1435 | while (len > 0) | |
c906108c | 1436 | { |
ed9a39eb JM |
1437 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1438 | ||
1439 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1440 | { |
ed9a39eb JM |
1441 | /* It's an argument being passed in a general register. */ |
1442 | regval = extract_address (val, partial_len); | |
1443 | write_register (argreg++, regval); | |
c906108c | 1444 | } |
ed9a39eb JM |
1445 | else |
1446 | { | |
1447 | /* Push the arguments onto the stack. */ | |
1448 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1449 | fp += REGISTER_SIZE; | |
1450 | } | |
1451 | ||
1452 | len -= partial_len; | |
1453 | val += partial_len; | |
c906108c SS |
1454 | } |
1455 | } | |
c906108c SS |
1456 | |
1457 | /* Return adjusted stack pointer. */ | |
1458 | return sp; | |
1459 | } | |
1460 | ||
f079148d KB |
1461 | /* Pop the current frame. So long as the frame info has been initialized |
1462 | properly (see arm_init_extra_frame_info), this code works for dummy frames | |
1463 | as well as regular frames. I.e, there's no need to have a special case | |
1464 | for dummy frames. */ | |
c906108c | 1465 | void |
ed9a39eb | 1466 | arm_pop_frame (void) |
c906108c | 1467 | { |
c906108c | 1468 | int regnum; |
8b93c638 | 1469 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1470 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1471 | + frame->extra_info->framesize); | |
c906108c | 1472 | |
f079148d | 1473 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1474 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1475 | write_register (regnum, |
c3b4394c | 1476 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1477 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1478 | |
f079148d KB |
1479 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
1480 | write_register (SP_REGNUM, old_SP); | |
c906108c SS |
1481 | |
1482 | flush_cached_frames (); | |
1483 | } | |
1484 | ||
1485 | static void | |
ed9a39eb | 1486 | print_fpu_flags (int flags) |
c906108c | 1487 | { |
c5aa993b JM |
1488 | if (flags & (1 << 0)) |
1489 | fputs ("IVO ", stdout); | |
1490 | if (flags & (1 << 1)) | |
1491 | fputs ("DVZ ", stdout); | |
1492 | if (flags & (1 << 2)) | |
1493 | fputs ("OFL ", stdout); | |
1494 | if (flags & (1 << 3)) | |
1495 | fputs ("UFL ", stdout); | |
1496 | if (flags & (1 << 4)) | |
1497 | fputs ("INX ", stdout); | |
1498 | putchar ('\n'); | |
c906108c SS |
1499 | } |
1500 | ||
1501 | void | |
ed9a39eb | 1502 | arm_float_info (void) |
c906108c | 1503 | { |
c5aa993b JM |
1504 | register unsigned long status = read_register (FPS_REGNUM); |
1505 | int type; | |
1506 | ||
1507 | type = (status >> 24) & 127; | |
1508 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1509 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1510 | type); |
1511 | fputs ("mask: ", stdout); | |
1512 | print_fpu_flags (status >> 16); | |
1513 | fputs ("flags: ", stdout); | |
1514 | print_fpu_flags (status); | |
c906108c SS |
1515 | } |
1516 | ||
032758dc AC |
1517 | struct type * |
1518 | arm_register_type (int regnum) | |
1519 | { | |
1520 | if (regnum >= F0_REGNUM && regnum < F0_REGNUM + NUM_FREGS) | |
1521 | { | |
d7449b42 | 1522 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1523 | return builtin_type_arm_ext_big; |
1524 | else | |
1525 | return builtin_type_arm_ext_littlebyte_bigword; | |
1526 | } | |
1527 | else | |
1528 | return builtin_type_int32; | |
1529 | } | |
1530 | ||
a37b3cc0 AC |
1531 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1532 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1533 | It is thought that this is is the floating-point register format on | |
1534 | little-endian systems. */ | |
c906108c | 1535 | |
ed9a39eb JM |
1536 | static void |
1537 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1538 | { |
a37b3cc0 | 1539 | DOUBLEST d; |
d7449b42 | 1540 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1541 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1542 | else | |
1543 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1544 | ptr, &d); | |
1545 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1546 | } |
1547 | ||
c5aa993b | 1548 | void |
ed9a39eb | 1549 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1550 | { |
a37b3cc0 AC |
1551 | DOUBLEST d; |
1552 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1553 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1554 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1555 | else | |
1556 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1557 | &d, dbl); | |
c906108c | 1558 | } |
ed9a39eb | 1559 | |
c906108c | 1560 | static int |
ed9a39eb | 1561 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1562 | { |
1563 | if (cond == INST_AL || cond == INST_NV) | |
1564 | return 1; | |
1565 | ||
1566 | switch (cond) | |
1567 | { | |
1568 | case INST_EQ: | |
1569 | return ((status_reg & FLAG_Z) != 0); | |
1570 | case INST_NE: | |
1571 | return ((status_reg & FLAG_Z) == 0); | |
1572 | case INST_CS: | |
1573 | return ((status_reg & FLAG_C) != 0); | |
1574 | case INST_CC: | |
1575 | return ((status_reg & FLAG_C) == 0); | |
1576 | case INST_MI: | |
1577 | return ((status_reg & FLAG_N) != 0); | |
1578 | case INST_PL: | |
1579 | return ((status_reg & FLAG_N) == 0); | |
1580 | case INST_VS: | |
1581 | return ((status_reg & FLAG_V) != 0); | |
1582 | case INST_VC: | |
1583 | return ((status_reg & FLAG_V) == 0); | |
1584 | case INST_HI: | |
1585 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1586 | case INST_LS: | |
1587 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1588 | case INST_GE: | |
1589 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1590 | case INST_LT: | |
1591 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1592 | case INST_GT: | |
1593 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1594 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1595 | case INST_LE: |
1596 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1597 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1598 | } |
1599 | return 1; | |
1600 | } | |
1601 | ||
9512d7fd | 1602 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1603 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1604 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1605 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1606 | #define sbits(obj,st,fn) \ | |
1607 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1608 | #define BranchDest(addr,instr) \ | |
1609 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1610 | #define ARM_PC_32 1 | |
1611 | ||
1612 | static unsigned long | |
ed9a39eb JM |
1613 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1614 | unsigned long status_reg) | |
c906108c SS |
1615 | { |
1616 | unsigned long res, shift; | |
1617 | int rm = bits (inst, 0, 3); | |
1618 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1619 | |
1620 | if (bit (inst, 4)) | |
c906108c SS |
1621 | { |
1622 | int rs = bits (inst, 8, 11); | |
1623 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1624 | } | |
1625 | else | |
1626 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1627 | |
1628 | res = (rm == 15 | |
c906108c | 1629 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1630 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1631 | : read_register (rm)); |
1632 | ||
1633 | switch (shifttype) | |
1634 | { | |
c5aa993b | 1635 | case 0: /* LSL */ |
c906108c SS |
1636 | res = shift >= 32 ? 0 : res << shift; |
1637 | break; | |
c5aa993b JM |
1638 | |
1639 | case 1: /* LSR */ | |
c906108c SS |
1640 | res = shift >= 32 ? 0 : res >> shift; |
1641 | break; | |
1642 | ||
c5aa993b JM |
1643 | case 2: /* ASR */ |
1644 | if (shift >= 32) | |
1645 | shift = 31; | |
c906108c SS |
1646 | res = ((res & 0x80000000L) |
1647 | ? ~((~res) >> shift) : res >> shift); | |
1648 | break; | |
1649 | ||
c5aa993b | 1650 | case 3: /* ROR/RRX */ |
c906108c SS |
1651 | shift &= 31; |
1652 | if (shift == 0) | |
1653 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1654 | else | |
c5aa993b | 1655 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1656 | break; |
1657 | } | |
1658 | ||
1659 | return res & 0xffffffff; | |
1660 | } | |
1661 | ||
c906108c SS |
1662 | /* Return number of 1-bits in VAL. */ |
1663 | ||
1664 | static int | |
ed9a39eb | 1665 | bitcount (unsigned long val) |
c906108c SS |
1666 | { |
1667 | int nbits; | |
1668 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1669 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1670 | return nbits; |
1671 | } | |
1672 | ||
c906108c | 1673 | static CORE_ADDR |
ed9a39eb | 1674 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1675 | { |
c5aa993b | 1676 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1677 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1678 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1679 | unsigned long offset; |
1680 | ||
1681 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1682 | { | |
1683 | CORE_ADDR sp; | |
1684 | ||
1685 | /* Fetch the saved PC from the stack. It's stored above | |
1686 | all of the other registers. */ | |
1687 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1688 | sp = read_register (SP_REGNUM); | |
1689 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1690 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1691 | if (nextpc == pc) | |
1692 | error ("Infinite loop detected"); | |
1693 | } | |
1694 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1695 | { | |
1696 | unsigned long status = read_register (PS_REGNUM); | |
c5aa993b | 1697 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1698 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1699 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1700 | } | |
1701 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1702 | { | |
1703 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1704 | } | |
1705 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1706 | { | |
1707 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1708 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1709 | nextpc = pc_val + offset; |
1710 | } | |
1711 | ||
1712 | return nextpc; | |
1713 | } | |
1714 | ||
c906108c | 1715 | CORE_ADDR |
ed9a39eb | 1716 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1717 | { |
1718 | unsigned long pc_val; | |
1719 | unsigned long this_instr; | |
1720 | unsigned long status; | |
1721 | CORE_ADDR nextpc; | |
1722 | ||
1723 | if (arm_pc_is_thumb (pc)) | |
1724 | return thumb_get_next_pc (pc); | |
1725 | ||
1726 | pc_val = (unsigned long) pc; | |
1727 | this_instr = read_memory_integer (pc, 4); | |
1728 | status = read_register (PS_REGNUM); | |
c5aa993b | 1729 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1730 | |
1731 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1732 | { | |
1733 | switch (bits (this_instr, 24, 27)) | |
1734 | { | |
c5aa993b JM |
1735 | case 0x0: |
1736 | case 0x1: /* data processing */ | |
1737 | case 0x2: | |
1738 | case 0x3: | |
c906108c SS |
1739 | { |
1740 | unsigned long operand1, operand2, result = 0; | |
1741 | unsigned long rn; | |
1742 | int c; | |
c5aa993b | 1743 | |
c906108c SS |
1744 | if (bits (this_instr, 12, 15) != 15) |
1745 | break; | |
1746 | ||
1747 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1748 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1749 | error ("Illegal update to pc in instruction"); |
1750 | ||
1751 | /* Multiply into PC */ | |
1752 | c = (status & FLAG_C) ? 1 : 0; | |
1753 | rn = bits (this_instr, 16, 19); | |
1754 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1755 | |
c906108c SS |
1756 | if (bit (this_instr, 25)) |
1757 | { | |
1758 | unsigned long immval = bits (this_instr, 0, 7); | |
1759 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1760 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1761 | & 0xffffffff; | |
c906108c | 1762 | } |
c5aa993b | 1763 | else /* operand 2 is a shifted register */ |
c906108c | 1764 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1765 | |
c906108c SS |
1766 | switch (bits (this_instr, 21, 24)) |
1767 | { | |
c5aa993b | 1768 | case 0x0: /*and */ |
c906108c SS |
1769 | result = operand1 & operand2; |
1770 | break; | |
1771 | ||
c5aa993b | 1772 | case 0x1: /*eor */ |
c906108c SS |
1773 | result = operand1 ^ operand2; |
1774 | break; | |
1775 | ||
c5aa993b | 1776 | case 0x2: /*sub */ |
c906108c SS |
1777 | result = operand1 - operand2; |
1778 | break; | |
1779 | ||
c5aa993b | 1780 | case 0x3: /*rsb */ |
c906108c SS |
1781 | result = operand2 - operand1; |
1782 | break; | |
1783 | ||
c5aa993b | 1784 | case 0x4: /*add */ |
c906108c SS |
1785 | result = operand1 + operand2; |
1786 | break; | |
1787 | ||
c5aa993b | 1788 | case 0x5: /*adc */ |
c906108c SS |
1789 | result = operand1 + operand2 + c; |
1790 | break; | |
1791 | ||
c5aa993b | 1792 | case 0x6: /*sbc */ |
c906108c SS |
1793 | result = operand1 - operand2 + c; |
1794 | break; | |
1795 | ||
c5aa993b | 1796 | case 0x7: /*rsc */ |
c906108c SS |
1797 | result = operand2 - operand1 + c; |
1798 | break; | |
1799 | ||
c5aa993b JM |
1800 | case 0x8: |
1801 | case 0x9: | |
1802 | case 0xa: | |
1803 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1804 | result = (unsigned long) nextpc; |
1805 | break; | |
1806 | ||
c5aa993b | 1807 | case 0xc: /*orr */ |
c906108c SS |
1808 | result = operand1 | operand2; |
1809 | break; | |
1810 | ||
c5aa993b | 1811 | case 0xd: /*mov */ |
c906108c SS |
1812 | /* Always step into a function. */ |
1813 | result = operand2; | |
c5aa993b | 1814 | break; |
c906108c | 1815 | |
c5aa993b | 1816 | case 0xe: /*bic */ |
c906108c SS |
1817 | result = operand1 & ~operand2; |
1818 | break; | |
1819 | ||
c5aa993b | 1820 | case 0xf: /*mvn */ |
c906108c SS |
1821 | result = ~operand2; |
1822 | break; | |
1823 | } | |
1824 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1825 | ||
1826 | if (nextpc == pc) | |
1827 | error ("Infinite loop detected"); | |
1828 | break; | |
1829 | } | |
c5aa993b JM |
1830 | |
1831 | case 0x4: | |
1832 | case 0x5: /* data transfer */ | |
1833 | case 0x6: | |
1834 | case 0x7: | |
c906108c SS |
1835 | if (bit (this_instr, 20)) |
1836 | { | |
1837 | /* load */ | |
1838 | if (bits (this_instr, 12, 15) == 15) | |
1839 | { | |
1840 | /* rd == pc */ | |
c5aa993b | 1841 | unsigned long rn; |
c906108c | 1842 | unsigned long base; |
c5aa993b | 1843 | |
c906108c SS |
1844 | if (bit (this_instr, 22)) |
1845 | error ("Illegal update to pc in instruction"); | |
1846 | ||
1847 | /* byte write to PC */ | |
1848 | rn = bits (this_instr, 16, 19); | |
1849 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1850 | if (bit (this_instr, 24)) | |
1851 | { | |
1852 | /* pre-indexed */ | |
1853 | int c = (status & FLAG_C) ? 1 : 0; | |
1854 | unsigned long offset = | |
c5aa993b | 1855 | (bit (this_instr, 25) |
ed9a39eb | 1856 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1857 | : bits (this_instr, 0, 11)); |
c906108c SS |
1858 | |
1859 | if (bit (this_instr, 23)) | |
1860 | base += offset; | |
1861 | else | |
1862 | base -= offset; | |
1863 | } | |
c5aa993b | 1864 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1865 | 4); |
c5aa993b | 1866 | |
c906108c SS |
1867 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1868 | ||
1869 | if (nextpc == pc) | |
1870 | error ("Infinite loop detected"); | |
1871 | } | |
1872 | } | |
1873 | break; | |
c5aa993b JM |
1874 | |
1875 | case 0x8: | |
1876 | case 0x9: /* block transfer */ | |
c906108c SS |
1877 | if (bit (this_instr, 20)) |
1878 | { | |
1879 | /* LDM */ | |
1880 | if (bit (this_instr, 15)) | |
1881 | { | |
1882 | /* loading pc */ | |
1883 | int offset = 0; | |
1884 | ||
1885 | if (bit (this_instr, 23)) | |
1886 | { | |
1887 | /* up */ | |
1888 | unsigned long reglist = bits (this_instr, 0, 14); | |
1889 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1890 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1891 | offset += 4; |
1892 | } | |
1893 | else if (bit (this_instr, 24)) | |
1894 | offset = -4; | |
c5aa993b | 1895 | |
c906108c | 1896 | { |
c5aa993b JM |
1897 | unsigned long rn_val = |
1898 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1899 | nextpc = |
1900 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1901 | + offset), |
c906108c SS |
1902 | 4); |
1903 | } | |
1904 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1905 | if (nextpc == pc) | |
1906 | error ("Infinite loop detected"); | |
1907 | } | |
1908 | } | |
1909 | break; | |
c5aa993b JM |
1910 | |
1911 | case 0xb: /* branch & link */ | |
1912 | case 0xa: /* branch */ | |
c906108c SS |
1913 | { |
1914 | nextpc = BranchDest (pc, this_instr); | |
1915 | ||
1916 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1917 | if (nextpc == pc) | |
1918 | error ("Infinite loop detected"); | |
1919 | break; | |
1920 | } | |
c5aa993b JM |
1921 | |
1922 | case 0xc: | |
1923 | case 0xd: | |
1924 | case 0xe: /* coproc ops */ | |
1925 | case 0xf: /* SWI */ | |
c906108c SS |
1926 | break; |
1927 | ||
1928 | default: | |
1929 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1930 | return (pc); | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | return nextpc; | |
1935 | } | |
1936 | ||
9512d7fd FN |
1937 | /* single_step() is called just before we want to resume the inferior, |
1938 | if we want to single-step it but there is no hardware or kernel | |
1939 | single-step support. We find the target of the coming instruction | |
1940 | and breakpoint it. | |
1941 | ||
1942 | single_step is also called just after the inferior stops. If we had | |
1943 | set up a simulated single-step, we undo our damage. */ | |
1944 | ||
1945 | void | |
1946 | arm_software_single_step (ignore, insert_bpt) | |
1947 | int ignore; /* Signal, not needed */ | |
1948 | int insert_bpt; | |
1949 | { | |
1950 | static int next_pc; /* State between setting and unsetting. */ | |
1951 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ | |
1952 | ||
1953 | if (insert_bpt) | |
1954 | { | |
1955 | next_pc = arm_get_next_pc (read_register (PC_REGNUM)); | |
80fcf3f0 | 1956 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
1957 | } |
1958 | else | |
80fcf3f0 | 1959 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 1960 | } |
9512d7fd | 1961 | |
c906108c SS |
1962 | #include "bfd-in2.h" |
1963 | #include "libcoff.h" | |
1964 | ||
1965 | static int | |
ed9a39eb | 1966 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1967 | { |
1968 | if (arm_pc_is_thumb (memaddr)) | |
1969 | { | |
c5aa993b JM |
1970 | static asymbol *asym; |
1971 | static combined_entry_type ce; | |
1972 | static struct coff_symbol_struct csym; | |
1973 | static struct _bfd fake_bfd; | |
1974 | static bfd_target fake_target; | |
c906108c SS |
1975 | |
1976 | if (csym.native == NULL) | |
1977 | { | |
1978 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1979 | solely so that the code in print_insn_little_arm() and | |
1980 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1981 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
c5aa993b JM |
1982 | |
1983 | fake_target.flavour = bfd_target_coff_flavour; | |
1984 | fake_bfd.xvec = &fake_target; | |
c906108c | 1985 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1986 | csym.native = &ce; |
1987 | csym.symbol.the_bfd = &fake_bfd; | |
1988 | csym.symbol.name = "fake"; | |
1989 | asym = (asymbol *) & csym; | |
c906108c | 1990 | } |
c5aa993b | 1991 | |
c906108c | 1992 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1993 | info->symbols = &asym; |
c906108c SS |
1994 | } |
1995 | else | |
1996 | info->symbols = NULL; | |
c5aa993b | 1997 | |
d7449b42 | 1998 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1999 | return print_insn_big_arm (memaddr, info); |
2000 | else | |
2001 | return print_insn_little_arm (memaddr, info); | |
2002 | } | |
2003 | ||
ed9a39eb JM |
2004 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the |
2005 | program counter value to determine whether a 16-bit or 32-bit | |
2006 | breakpoint should be used. It returns a pointer to a string of | |
2007 | bytes that encode a breakpoint instruction, stores the length of | |
2008 | the string to *lenptr, and adjusts the program counter (if | |
2009 | necessary) to point to the actual memory location where the | |
c906108c SS |
2010 | breakpoint should be inserted. */ |
2011 | ||
2012 | unsigned char * | |
ed9a39eb | 2013 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c SS |
2014 | { |
2015 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
2016 | { | |
d7449b42 | 2017 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c5aa993b JM |
2018 | { |
2019 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2020 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
2021 | *lenptr = sizeof (thumb_breakpoint); | |
2022 | return thumb_breakpoint; | |
2023 | } | |
c906108c | 2024 | else |
c5aa993b JM |
2025 | { |
2026 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2027 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
2028 | *lenptr = sizeof (thumb_breakpoint); | |
2029 | return thumb_breakpoint; | |
2030 | } | |
c906108c SS |
2031 | } |
2032 | else | |
2033 | { | |
d7449b42 | 2034 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c5aa993b JM |
2035 | { |
2036 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
2037 | *lenptr = sizeof (arm_breakpoint); | |
2038 | return arm_breakpoint; | |
2039 | } | |
c906108c | 2040 | else |
c5aa993b JM |
2041 | { |
2042 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
2043 | *lenptr = sizeof (arm_breakpoint); | |
2044 | return arm_breakpoint; | |
2045 | } | |
c906108c SS |
2046 | } |
2047 | } | |
ed9a39eb JM |
2048 | |
2049 | /* Extract from an array REGBUF containing the (raw) register state a | |
2050 | function return value of type TYPE, and copy that, in virtual | |
2051 | format, into VALBUF. */ | |
2052 | ||
2053 | void | |
2054 | arm_extract_return_value (struct type *type, | |
2055 | char regbuf[REGISTER_BYTES], | |
2056 | char *valbuf) | |
2057 | { | |
2058 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
2059 | convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); | |
2060 | else | |
2061 | memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); | |
2062 | } | |
2063 | ||
2064 | /* Return non-zero if the PC is inside a thumb call thunk. */ | |
c906108c SS |
2065 | |
2066 | int | |
ed9a39eb | 2067 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2068 | { |
2069 | CORE_ADDR start_addr; | |
2070 | ||
ed9a39eb JM |
2071 | /* Find the starting address of the function containing the PC. If |
2072 | the caller didn't give us a name, look it up at the same time. */ | |
c906108c SS |
2073 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
2074 | return 0; | |
2075 | ||
2076 | return strncmp (name, "_call_via_r", 11) == 0; | |
2077 | } | |
2078 | ||
ed9a39eb JM |
2079 | /* If PC is in a Thumb call or return stub, return the address of the |
2080 | target PC, which is in a register. The thunk functions are called | |
2081 | _called_via_xx, where x is the register name. The possible names | |
2082 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2083 | |
2084 | CORE_ADDR | |
ed9a39eb | 2085 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2086 | { |
c5aa993b | 2087 | char *name; |
c906108c SS |
2088 | CORE_ADDR start_addr; |
2089 | ||
2090 | /* Find the starting address and name of the function containing the PC. */ | |
2091 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2092 | return 0; | |
2093 | ||
2094 | /* Call thunks always start with "_call_via_". */ | |
2095 | if (strncmp (name, "_call_via_", 10) == 0) | |
2096 | { | |
ed9a39eb JM |
2097 | /* Use the name suffix to determine which register contains the |
2098 | target PC. */ | |
c5aa993b JM |
2099 | static char *table[15] = |
2100 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2101 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2102 | }; | |
c906108c SS |
2103 | int regno; |
2104 | ||
2105 | for (regno = 0; regno <= 14; regno++) | |
2106 | if (strcmp (&name[10], table[regno]) == 0) | |
2107 | return read_register (regno); | |
2108 | } | |
ed9a39eb | 2109 | |
c5aa993b | 2110 | return 0; /* not a stub */ |
c906108c SS |
2111 | } |
2112 | ||
bc90b915 FN |
2113 | /* If the user changes the register disassembly flavor used for info register |
2114 | and other commands, we have to also switch the flavor used in opcodes | |
2115 | for disassembly output. | |
2116 | This function is run in the set disassembly_flavor command, and does that. */ | |
2117 | ||
2118 | static void | |
2119 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2120 | struct cmd_list_element *c) | |
2121 | { | |
2122 | set_disassembly_flavor (); | |
2123 | } | |
2124 | \f | |
966fbf70 RE |
2125 | /* Return the ARM register name corresponding to register I. */ |
2126 | char * | |
2127 | arm_register_name(int i) | |
2128 | { | |
2129 | return arm_register_names[i]; | |
2130 | } | |
2131 | ||
bc90b915 FN |
2132 | static void |
2133 | set_disassembly_flavor (void) | |
2134 | { | |
2135 | const char *setname, *setdesc, **regnames; | |
2136 | int numregs, j; | |
2137 | ||
2138 | /* Find the flavor that the user wants in the opcodes table. */ | |
2139 | int current = 0; | |
2140 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2141 | while ((disassembly_flavor != setname) | |
2142 | && (current < num_flavor_options)) | |
2143 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2144 | current_option = current; | |
2145 | ||
2146 | /* Fill our copy. */ | |
2147 | for (j = 0; j < numregs; j++) | |
2148 | arm_register_names[j] = (char *) regnames[j]; | |
2149 | ||
2150 | /* Adjust case. */ | |
2151 | if (isupper (*regnames[PC_REGNUM])) | |
2152 | { | |
2153 | arm_register_names[FPS_REGNUM] = "FPS"; | |
2154 | arm_register_names[PS_REGNUM] = "CPSR"; | |
2155 | } | |
2156 | else | |
2157 | { | |
2158 | arm_register_names[FPS_REGNUM] = "fps"; | |
2159 | arm_register_names[PS_REGNUM] = "cpsr"; | |
2160 | } | |
2161 | ||
2162 | /* Synchronize the disassembler. */ | |
2163 | set_arm_regname_option (current); | |
2164 | } | |
2165 | ||
2166 | /* arm_othernames implements the "othernames" command. This is kind | |
2167 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2168 | also used for the x86 gdb. I will keep this around, however, in | |
2169 | case anyone is actually using it. */ | |
2170 | ||
2171 | static void | |
2172 | arm_othernames (char *names, int n) | |
2173 | { | |
2174 | /* Circle through the various flavors. */ | |
2175 | current_option = (current_option + 1) % num_flavor_options; | |
2176 | ||
2177 | disassembly_flavor = valid_flavors[current_option]; | |
2178 | set_disassembly_flavor (); | |
2179 | } | |
2180 | ||
a42dd537 KB |
2181 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2182 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2183 | Note, however, that link.h is not actually referred to in this file. | |
2184 | Instead, the relevant structs offsets were obtained from examining | |
2185 | link.h. (We can't refer to link.h from this file because the host | |
2186 | system won't necessarily have it, or if it does, the structs which | |
2187 | it defines will refer to the host system, not the target.) */ | |
2188 | ||
2189 | struct link_map_offsets * | |
2190 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2191 | { | |
2192 | static struct link_map_offsets lmo; | |
2193 | static struct link_map_offsets *lmp = 0; | |
2194 | ||
2195 | if (lmp == 0) | |
2196 | { | |
2197 | lmp = &lmo; | |
2198 | ||
2199 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
2200 | need. */ | |
2201 | ||
2202 | lmo.r_map_offset = 4; | |
2203 | lmo.r_map_size = 4; | |
2204 | ||
2205 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
2206 | need. */ | |
2207 | ||
2208 | lmo.l_addr_offset = 0; | |
2209 | lmo.l_addr_size = 4; | |
2210 | ||
2211 | lmo.l_name_offset = 4; | |
2212 | lmo.l_name_size = 4; | |
2213 | ||
2214 | lmo.l_next_offset = 12; | |
2215 | lmo.l_next_size = 4; | |
2216 | ||
2217 | lmo.l_prev_offset = 16; | |
2218 | lmo.l_prev_size = 4; | |
2219 | } | |
2220 | ||
2221 | return lmp; | |
2222 | } | |
2223 | ||
c906108c | 2224 | void |
ed9a39eb | 2225 | _initialize_arm_tdep (void) |
c906108c | 2226 | { |
bc90b915 FN |
2227 | struct ui_file *stb; |
2228 | long length; | |
96baa820 | 2229 | struct cmd_list_element *new_cmd; |
53904c9e AC |
2230 | const char *setname; |
2231 | const char *setdesc; | |
2232 | const char **regnames; | |
bc90b915 FN |
2233 | int numregs, i, j; |
2234 | static char *helptext; | |
085dd6e6 | 2235 | |
c906108c | 2236 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 2237 | |
bc90b915 FN |
2238 | /* Get the number of possible sets of register names defined in opcodes. */ |
2239 | num_flavor_options = get_arm_regname_num_options (); | |
2240 | ||
085dd6e6 | 2241 | /* Sync the opcode insn printer with our register viewer: */ |
bc90b915 | 2242 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2243 | |
bc90b915 FN |
2244 | /* Begin creating the help text. */ |
2245 | stb = mem_fileopen (); | |
2246 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
2247 | The valid values are:\n"); | |
ed9a39eb | 2248 | |
bc90b915 FN |
2249 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
2250 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); | |
2251 | for (i = 0; i < num_flavor_options; i++) | |
2252 | { | |
2253 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 2254 | valid_flavors[i] = setname; |
bc90b915 FN |
2255 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
2256 | setdesc); | |
2257 | /* Copy the default names (if found) and synchronize disassembler. */ | |
2258 | if (!strcmp (setname, "std")) | |
2259 | { | |
53904c9e | 2260 | disassembly_flavor = setname; |
bc90b915 FN |
2261 | current_option = i; |
2262 | for (j = 0; j < numregs; j++) | |
2263 | arm_register_names[j] = (char *) regnames[j]; | |
2264 | set_arm_regname_option (i); | |
2265 | } | |
2266 | } | |
2267 | /* Mark the end of valid options. */ | |
2268 | valid_flavors[num_flavor_options] = NULL; | |
c906108c | 2269 | |
bc90b915 FN |
2270 | /* Finish the creation of the help text. */ |
2271 | fprintf_unfiltered (stb, "The default is \"std\"."); | |
2272 | helptext = ui_file_xstrdup (stb, &length); | |
2273 | ui_file_delete (stb); | |
ed9a39eb | 2274 | |
bc90b915 | 2275 | /* Add the disassembly-flavor command */ |
96baa820 | 2276 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 2277 | valid_flavors, |
1ed2a135 | 2278 | &disassembly_flavor, |
bc90b915 | 2279 | helptext, |
ed9a39eb | 2280 | &setlist); |
96baa820 | 2281 | new_cmd->function.sfunc = set_disassembly_flavor_sfunc; |
ed9a39eb JM |
2282 | add_show_from_set (new_cmd, &showlist); |
2283 | ||
c906108c SS |
2284 | /* ??? Maybe this should be a boolean. */ |
2285 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 2286 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 2287 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 2288 | &showlist); |
c906108c | 2289 | |
bc90b915 FN |
2290 | /* Add the deprecated "othernames" command */ |
2291 | ||
2292 | add_com ("othernames", class_obscure, arm_othernames, | |
2293 | "Switch to the next set of register names."); | |
c3b4394c RE |
2294 | |
2295 | /* Fill in the prologue_cache fields. */ | |
2296 | prologue_cache.extra_info = (struct frame_extra_info *) | |
2297 | xcalloc (1, sizeof (struct frame_extra_info)); | |
2298 | prologue_cache.saved_regs = (CORE_ADDR *) | |
2299 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
c906108c SS |
2300 | } |
2301 | ||
ed9a39eb JM |
2302 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2303 | function. */ | |
2304 | ||
c906108c | 2305 | int |
c5aa993b | 2306 | coff_sym_is_thumb (int val) |
c906108c | 2307 | { |
c5aa993b JM |
2308 | return (val == C_THUMBEXT || |
2309 | val == C_THUMBSTAT || | |
2310 | val == C_THUMBEXTFUNC || | |
2311 | val == C_THUMBSTATFUNC || | |
2312 | val == C_THUMBLABEL); | |
c906108c | 2313 | } |